| commit | 8a3cb560f4aa8b2606a5fdc137338b3a65a75dc7 | [log] [tgz] |
|---|---|---|
| author | Aamir Bohra <aamir.bohra@intel.com> | Thu Mar 30 14:42:21 2017 |
| committer | chrome-bot <chrome-bot@chromium.org> | Wed Apr 12 18:35:29 2017 |
| tree | 23f80df1eeed6a83744949e94dec645aeb9368c0 | |
| parent | 42bbbaca046877feaaba71899fb2c9b3c79aa73c [diff] |
UPSTREAM: soc/intel/common/block: Add Intel common UART code Create Intel Common UART driver code. This code does below UART configuration for bootblock phase. * Program BAR * Configure reset register * Configure clock register BUG=none BRANCH=none TEST=none Change-Id: Iba752e0a751c1eb37f68a401d237de21d0327dcd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01d75f4172e73fbcdc08ce0a13eaa0efb400ff12 Original-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Original-Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Original-Reviewed-on: https://review.coreboot.org/18952 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/475715