diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c
index 73dacef..2c98be7 100644
--- a/src/soc/mediatek/common/dsi.c
+++ b/src/soc/mediatek/common/dsi.c
@@ -155,8 +155,11 @@
 		break;
 	}
 
-	tmp_reg |= (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
-	tmp_reg |= (mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
+	if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
+		tmp_reg |= NON_CONTINUOUS_CLK;
+
+	if (!(mode_flags & MIPI_DSI_MODE_EOT_PACKET))
+		tmp_reg |= EOTP_DISABLE;
 
 	write32(&dsi0->dsi_txrx_ctrl, tmp_reg);
 }
@@ -203,6 +206,10 @@
 			  phy_timing->da_hs_zero + phy_timing->da_hs_exit + 3;
 
 	u32 delta = 12;
+
+	if (mode_flags & MIPI_DSI_MODE_EOT_PACKET)
+		delta += 2;
+
 	if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
 		delta += 6;
 
diff --git a/src/soc/mediatek/common/include/soc/dsi_common.h b/src/soc/mediatek/common/include/soc/dsi_common.h
index 7bacec1..aebe62a 100644
--- a/src/soc/mediatek/common/include/soc/dsi_common.h
+++ b/src/soc/mediatek/common/include/soc/dsi_common.h
@@ -118,6 +118,12 @@
 	MIX_MODE = BIT(17)
 };
 
+/* DSI_TXRX_CTRL */
+enum {
+	EOTP_DISABLE = BIT(6),
+	NON_CONTINUOUS_CLK = BIT(16),
+};
+
 /* DSI_PSCTRL */
 enum {
 	DSI_PS_WC = 0x3fff,