Google Git
Sign in
chromium / chromiumos / third_party / coreboot / refs/heads/firmware-brya-14505.71.B
commitfa0a959e6e463457706dc61e082038e54014fcb1[log] [tgz]
authorSubrata Banik <subratabanik@google.com>Mon Apr 11 12:28:22 2022
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>Mon Apr 18 16:47:06 2022
tree80599d2ad2a8d126bc5045e9eec3c4870aff31c8
parent289ab3ce859f632b008f4a9d4cb659d5e160a7d5 [diff]
FROMLIST: mb/google/brya: Reset XHCI controller while preparing for S5

This patch calls into `xhci_host_reset()` function to perform XHCI
controller reset.

Without this patch the PMC IPC timeout issue is seen while sending the
USB-C (0xA7) command during poweron from S5 (S5->S4->S3->S0).

On Brya variants, poweron from S5 state results in PMC error while
sending PMC IPC (0xA7) to USB-C active ports, log here:

localhost ~ # cbmem -c | grep ERROR

[ERROR]  PMC IPC timeout after 1000 ms
[ERROR]  PMC IPC command 0x200a7 failed
[ERROR]  pmc_send_ipc_cmd failed
[ERROR]  Failed to setup port:0 to initial state
[ERROR]  PMC IPC timeout after 1000 ms
[ERROR]  PMC IPC command 0x200a7 failed
[ERROR]  pmc_send_ipc_cmd failed
[ERROR]  Failed to setup port:1 to initial state
[ERROR]  PMC IPC timeout after 1000 ms
[ERROR]  PMC IPC command 0x20a0 failed

This problem is not seen while powering on from G3 (G3->S5->S4->S3->S0).

During poweron the state of USB ports are not the same between S5 and G3
and it appears that the active USB port still is in U3 (suspend) while
PMC tries to send the IPC command, which results in a timeout.

This patch utilises the S5 SMI handler to reset the XHCI controller
using `xhci_host_reset()` prior entering into the S5, it helps to
restore the port state to active hence, no PMC timeout is seen with
this code change.

BUG=b:227289581
TEST=No PMC timeout is observed while sending USB-C PMC command (0xA7)
during resume from S5.

Total Time: 1,045,855
localhost ~ # cbmem -c | grep ERROR

No PMC timeout error is observed with this CL.

Signed-off-by: Subrata Banik <subratabanik@google.com>
(am from https://review.coreboot.org/c/coreboot/+/63552)
Change-Id: Ifc47847a9b7b193a6c776ea7de28cd82a3ff3d6a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3583293
Auto-Submit: Subrata Banik <subratabanik@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
1 file changed
tree: 80599d2ad2a8d126bc5045e9eec3c4870aff31c8
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. OWNERS
  22. PRESUBMIT.cfg
  23. README.md
  24. toolchain.inc
  25. unblocked_terms.txt
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.