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chromium / chromiumos / third_party / coreboot / refs/heads/firmware-cherry-14454.B
commit54df674e7a49d37ee13d28c01c6fe0a598f6bcb1[log] [tgz]
authorYu-Ping Wu <yupingso@chromium.org>Tue Aug 09 07:54:05 2022
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>Thu Sep 29 10:37:32 2022
treea7f6b510b6462308c84da1099215b2792434d9c4
parentdaa4a0abe30455aeccef726093b1b0f2f3eb50ce [diff]
UPSTREAM: mb/google/cherry: Initialize PCIe by SKU encoding

All cherry boards (tomato, dojo) share the same SKU ID encoding, in the
sense that a device has NVMe storage if and only if the BIT(1) of SKU ID
is set (otherwise eMMC). Therefore, instead of hard coding the list of
NVMe (PCIe) SKU IDs, we check the BIT(1) to decide whether to initialize
PCIe.

In addition, in preparation for UFS devices coming in the future,
reserve BIT(3) (which is unset for all of current SKUs) for them.

BUG=b:237953117, b:233327674
TEST=emerge-cherry coreboot
BRANCH=cherry

(cherry picked from commit 514277f7462e338c41c27e37198725923128d039)

Original-Change-Id: I9b30338645a87f29f96a249808b90f1ec16f82df
Original-Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/66580
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Yidi Lin <yidilin@google.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
GitOrigin-RevId: 514277f7462e338c41c27e37198725923128d039
Change-Id: I132bd516a4fc0aafc0ece1eeda4c3b89cdf62629
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3913281
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
(cherry picked from commit e8a326e6da1550781e795b99bcadb3e0f8947ca6)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3928488
Tested-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Auto-Submit: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
1 file changed
tree: a7f6b510b6462308c84da1099215b2792434d9c4
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. AUTHORS
  16. COPYING
  17. gnat.adc
  18. MAINTAINERS
  19. Makefile
  20. Makefile.inc
  21. OWNERS
  22. PRESUBMIT.cfg
  23. README.md
  24. toolchain.inc
  25. unblocked_terms.txt
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.