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chromium / chromiumos / third_party / coreboot / refs/heads/firmware-guybrush-14500.B
commitbb32b28674def00d79e337d05248503ac5a68934[log] [tgz]
authorJasonNien <finaljason@gmail.com>Tue Jan 30 00:11:02 2024
committerChromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com>Wed Mar 13 19:38:42 2024
treecd56e145354378f0ef68be286fbf62b09e4b47f6
parenta8569f6fed741a0b17ddc6730debd082fda9d62e [diff]
UPSTREAM: mb/google/guybrush: turn off SD ASPM L1.1/L1.2

Turn off SD ASPM L1.1/L1.2 as w/a for wlan DMA resume failure

We completed 4 runs for each of the 2 tests - power_idle and power_VideoCall. Here are the averages for both the tests:

L1ss disabled SD plugged power idle test: 735.3875
L1ss enabled SD plugged power idle test: 737.2335

L1ss disabled SD plugged power video test: 333.29325
L1ss enabled SD plugged power video test: 333.442

BUG=b:254382832
TEST=test pass over 10k cycles

(cherry picked from commit f3ae0f0cfb56aae82ff877ee74b9c8e83aee9ab9)

Original-Signed-off-by: Jason Nien <finaljason@gmail.com>
Original-Change-Id: I4d903f0f6333ffa18069e42be3c932aeae8013d9
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/80237
Original-Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Original-Reviewed-by: Tim Van Patten <timvp@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GitOrigin-RevId: f3ae0f0cfb56aae82ff877ee74b9c8e83aee9ab9
Change-Id: I016106ee7dfcb4349f2dd182c3a1f793544c4f5e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5346067
Reviewed-by: Brett Brotherton <bbrotherton@google.com>
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Commit-Queue: Brett Brotherton <bbrotherton@google.com>
(cherry picked from commit 650cf3ffa25f5282e9821b278a84801fb5b54eb1)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5360959
Tested-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Commit-Queue: Tim Van Patten <timvp@google.com>
1 file changed
tree: cd56e145354378f0ef68be286fbf62b09e4b47f6
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. .mailmap
  16. AUTHORS
  17. COPYING
  18. gnat.adc
  19. MAINTAINERS
  20. Makefile
  21. Makefile.inc
  22. OWNERS
  23. PRESUBMIT.cfg
  24. README.md
  25. toolchain.inc
  26. unblocked_terms.txt
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.