UPSTREAM: mb/google/hatch/var/jinlon: Increase reset deassert delay to 4 ms

With 1ms delay, reset is de-asserted too soon, before power is fully
up, causing a glitch to the reset signal. The issue is resolved with
4ms delay.

TEST=tested on google/jinlon device and observed the issue is resolved.
BUG=b:260253945

(cherry picked from commit 83e9f048024ab3a527d886d4591b29513c628f79)

Original-Signed-off-by: Eran Mitrani <mitrani@google.com>
Original-Change-Id: I4efe916824cc193a7c2db7599b37f0d4de40bfce
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/79474
Original-Reviewed-by: Subrata Banik <subratabanik@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Original-Reviewed-by: Shelley Chen <shchen@google.com>
GitOrigin-RevId: 83e9f048024ab3a527d886d4591b29513c628f79
Change-Id: Ie05cb247ada9e06cc5024eaeb37661136f86709f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5133391
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Reviewed-by: Kapil Porwal <kapilporwal@chromium.org>
Commit-Queue: Kapil Porwal <kapilporwal@chromium.org>
(cherry picked from commit 363c1aae7be7b1a240e2f8b018c430fc75d4f65e)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5146768
Commit-Queue: Eran Mitrani <mitrani@google.com>
Reviewed-by: Shelley Chen <shchen@chromium.org>
Tested-by: Eran Mitrani <mitrani@google.com>
Auto-Submit: Eran Mitrani <mitrani@google.com>
1 file changed
tree: fe58d9277d00fc556e05d508b02ef3f61282feaf
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. src/
  6. util/
  7. .checkpatch.conf
  8. .clang-format
  9. .editorconfig
  10. .gitignore
  11. .gitmodules
  12. .gitreview
  13. AUTHORS
  14. COMMIT-QUEUE.ini
  15. COPYING
  16. gnat.adc
  17. MAINTAINERS
  18. Makefile
  19. Makefile.inc
  20. PRESUBMIT.cfg
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.