commit | d09e161f7538a2f57b3e94f514c730893ca9eaf0 | [log] [tgz] |
---|---|---|
author | Vijay Navnath Kamble <vkambl@codeaurora.org> | Thu Feb 27 07:05:08 2020 |
committer | Commit Bot <commit-bot@chromium.org> | Tue Jun 16 07:34:49 2020 |
tree | c5b910200df883ce1820af88968bdceb8ec8cf47 | |
parent | 9dfc2210e35714bf34c5671149a811e18d8d8175 [diff] |
qclib: Update qclib DDR Training data section The DDR bitflips,corruption issues seen with 739 MHz DDR Freq are not seen with DDR Freq 672 MHz. Next release of coreboot will have DDR freq set to 672 MHz. But with change in DDR freq, there is a need of DDR Training Data update. Currently "RO_DDR_TRAINING" section is used for DDR Training data. But we can not use this section as its Factory locked and can not be updated. So we need to use other section for DDR Training data update which is "RW_DDR_TRAINING". BUG=b:141614863 BRANCH=mistral TEST=firmware autoupdate Change-Id: I63e9751fc99a22b31b8d247de75f55b8adb30bb5 Signed-off-by: Vijay Navnath Kamble <vkambl@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2077257 Reviewed-by: nsekar nsekar <nsekar1@qualcomm.corp-partner.google.com> Reviewed-by: Yuji Sasaki <sasakiy@google.com> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Yuji Sasaki <sasakiy@google.com> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.