UPSTREAM: mb/google/nissa/var/joxer: Disable GPIOs for SD card reader

the board won’t have a SD card reader, so disable it.

BUG=b:285477026
TEST=USE="project_joxer emerge-nissa coreboot"

(cherry picked from commit 4c6171397e93d959983414388b8a4895903d4bfd)

Original-Change-Id: I6a55058b453771d264700a1364ef538f831148e4
Original-Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/75914
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Original-Reviewed-by: Derek Huang <derekhuang@google.com>
GitOrigin-RevId: 4c6171397e93d959983414388b8a4895903d4bfd
Change-Id: I47a4dc4c5c0dc36fd6dc857200f0ccb17cd7ec47
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/4640282
Commit-Queue: Subrata Banik <subratabanik@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@chromium.org>
Tested-by: CopyBot Service Account <copybot.service@gmail.com>
Tested-by: Subrata Banik <subratabanik@chromium.org>
(cherry picked from commit 4210afe5ff6e07c89bf94cac562473e24a10d8e6)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/4643424
Reviewed-by: Ivan Chen <yulunchen@google.com>
Tested-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Commit-Queue: Ivan Chen <yulunchen@google.com>
1 file changed
tree: f4ee0e025eba16e7642e58d39338d2199fbffbe8
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. spd/
  6. src/
  7. tests/
  8. util/
  9. .checkpatch.conf
  10. .clang-format
  11. .editorconfig
  12. .gitignore
  13. .gitmodules
  14. .gitreview
  15. .mailmap
  16. AUTHORS
  17. COPYING
  18. gnat.adc
  19. MAINTAINERS
  20. Makefile
  21. Makefile.inc
  22. OWNERS
  23. PRESUBMIT.cfg
  24. README.md
  25. toolchain.inc
  26. unblocked_terms.txt
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.