UPSTREAM: soc/intel/tigerlake: Enable end of post support in FSP

Send end of post message to CSME in FSP, by selecting EndOfPost
message in PEI phase. In API mode which coreboot currently uses,
sending EndOfPost message in DXE phase is not applicable.

BUG=b:180755397
TEST=Extract and copy MEInfo tool from CSME Fit Kit to voxel, execute
  ./MEInfo | grep "BIOS Boot State"
and confirm response shows BIOS Boot State to be "Post Boot".

Change-Id: I98a424cffec6a45ed7d493265dc1650e78d41e58
Signed-off-by:  <>
Original-Commit-Id: 202b1899dc0f7701b03a7839bccd3bf0438f1ac7
Original-Change-Id: I1ad0d7cc06e79b2fe1e53d49c8e838f4d91af736
Original-Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/51012
Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2713188
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Commit-Queue: Nick Vaccaro <nvaccaro@google.com>
Tested-by: Nick Vaccaro <nvaccaro@google.com>
(cherry picked from commit e211bc6bbd4f3b5bd81605c00ba98c763018dea5)
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2718205
Reviewed-by: Alex Levin <levinale@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: YH Lin <yueherngl@chromium.org>
Tested-by: YH Lin <yueherngl@chromium.org>
1 file changed
tree: 0034e9d4ed9e704cf27516087337939e45566884
  1. configs/
  2. Documentation/
  3. LICENSES/
  4. payloads/
  5. src/
  6. tests/
  7. util/
  8. .checkpatch.conf
  9. .clang-format
  10. .editorconfig
  11. .gitignore
  12. .gitmodules
  13. .gitreview
  14. AUTHORS
  15. COPYING
  16. gnat.adc
  17. MAINTAINERS
  18. Makefile
  19. Makefile.inc
  20. PRESUBMIT.cfg
  21. README.md
  22. toolchain.inc
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.