commit | b3f67a364f3bf1e02090a137794059b282096fda | [log] [tgz] |
---|---|---|
author | Sen Chu <sen.chu@mediatek.corp-partner.google.com> | Mon Sep 05 11:19:48 2022 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Mon Sep 12 17:49:53 2022 |
tree | 97df3ed33b19bb8822a77229cf1c35ca9ff73da8 | |
parent | 33d420314bbb81fce2266b5d205a05ebe56994bc [diff] |
UPSTREAM: soc/mediatek/mt8186: Enable CPU power hardware tracking for PMIC MT6366 1. There are two power sources for CPU: - Logic power (VPROC). - SRAM power (VSRAM_PROC). 2. There is a constraint between VPROC and VSRAM_PROC: - 0mV <= VSRAM_PROC - VPROC <= 250mV. With software control, the constraint might not always hold. Therefore, we enable hardware tracking from PMIC MT6366 to ensure the constraint is met automatically. BUG=b:236353282, b:241615706 TEST=meet the constrain correctly when adjusting the voltage. (cherry picked from commit a292f41faef437555c675d50090dc107bfff375e) Original-Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Original-Change-Id: I6012c57e60c009f1d599b57aab1c2526ee789208 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/67436 Original-Reviewed-by: Yidi Lin <yidilin@google.com> Original-Reviewed-by: Yu-Ping Wu <yupingso@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> GitOrigin-RevId: a292f41faef437555c675d50090dc107bfff375e Change-Id: Ib55659a24dd72d327fb116a5459c5edbbeda4a90 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3888806 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Yu-Ping Wu <yupingso@chromium.org> Tested-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-by: Hsin-Yi Wang <hsinyi@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.