| commit | 3d715efb13d215fdee13b5b5acf7075f66867923 | [log] [tgz] |
|---|---|---|
| author | Subrata Banik <subrata.banik@intel.com> | Thu Apr 11 11:04:44 2019 |
| committer | chrome-bot <chrome-bot@chromium.org> | Fri Apr 19 02:50:16 2019 |
| tree | dc2d465f544e769d233735dce8718ade37c0595c | |
| parent | b3924ace48b141a351e0d094f65296468ac82b41 [diff] |
UPSTREAM: soc/intel/common/timer: Calculate TSC frequency based on CPUID 0x15 This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to calculate nominal TSC frequency. As per SDM recommendation: For any processor in which CPUID.15H is enumerated and MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is available, a more accurate frequency can be obtained by using CPUID.15H This patch also adds header file to capture Intel processor model number. BUG=b:129839774 TEST=Boot ICL platform and calculate TSC frequency using below methods 1. TSC freq calculated based on MSR 0xCE tsc: Detected 1600.000 MHz processor 2. TSC freq calculated based on CPUID 0x15 tsc: Detected 1612.800 MHz TSC Method 2 actually reduce ~25ms of boot performance time. Note: Method 2 is recommended from gen 6 processor onwards. Change-Id: I032e096a8859bb935508414c4ae9f12d6946ae7d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0a9be33a8aa8e41663c58e0f2f1641f44c7cf5de Original-Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Original-Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1572282
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig and make nconfig)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.