commit | 56779abd67462f3f2c234038e37a80dc4343c14a | [log] [tgz] |
---|---|---|
author | Nick Vaccaro <nvaccaro@google.com> | Tue May 11 23:41:37 2021 |
committer | Commit Bot <commit-bot@chromium.org> | Sat May 15 03:09:59 2021 |
tree | 296f0981eec806697eedbeb176efcb2c3d4fdaf7 | |
parent | c15bd7832f4c3a1e9edb636931f0787c325d3211 [diff] |
UPSTREAM: mb/google/volteer: Configure TCSS OC pins TCSS OC pins have not been correctly configured for volteer. This patch fills the value from devicetree to correct the OC pins mapping. BUG=b:184660529 BRANCH=None TEST="emerge-volteer coreboot chromeos-bootimage", flash volteer2 and verify CpuUsb3OverCurrentPin UPDs get set correctly. Change-Id: Ic32f615b65297d5c47728b84029c86a1fe254f62 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Original-Commit-Id: 97b608feed7fddf40a586ca3600b35bc877aa341 Original-Change-Id: I12da755a1d3b9ec3ed0a2dbfb0782313dd49c7e9 Original-Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/54076 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Zhuohao Lee <zhuohao@google.com> Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2898064
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.