commit | c74d7e003d5ff8df15aa00c7e8dd21900d4e8f14 | [log] [tgz] |
---|---|---|
author | Bora Guvendik <bora.guvendik@intel.com> | Wed Jul 13 00:19:42 2022 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Wed Jul 20 22:09:44 2022 |
tree | a909bc9128df72c2a96cf9e6c6a7cabf2ecace08 | |
parent | 8c5e329410e65ef8a87a12aa3c1474ece27a6608 [diff] |
UPSTREAM: vendorcode/intel/fsp: Add Raptor Lake FSP headers for FSP v3257_00_40 The headers added are generated as per FSP v3257_00_40. In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake fsp headers can be deleted and Raptor Lake soc will also use headers from alderlake/ folder. BUG=b:238791453 BRANCH=firmware-brya-14505.B TEST=none (cherry picked from commit 9f45f06e0ecb2740dc69f35daaf6c7fb90af0eba) Original-Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Original-Change-Id: If8fd6700f0afed7e2bd5d73a95407dbfd3e88abd Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/65803 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nick Vaccaro <nvaccaro@google.com> GitOrigin-RevId: 9f45f06e0ecb2740dc69f35daaf6c7fb90af0eba Change-Id: I0bda45baeb3e1d26d1aedbe1f564b313cfa09664 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3776901 Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Tested-by: CopyBot Service Account <copybot.service@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.