commit | 28654b970211ef4669b50ac5cac55029587d410a | [log] [tgz] |
---|---|---|
author | Raihow Shi <raihow_shi@wistron.corp-partner.google.com> | Tue Aug 02 13:50:18 2022 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Wed Aug 17 19:20:51 2022 |
tree | 4caf008ed029182c731db319e92364db1895bb31 | |
parent | bf3a7abb525aa08c39af688a71ac4a9520f506b0 [diff] |
UPSTREAM: mb/google/brask/variants/moli: use specific gpio table by board_ver EN_PP3300_EMMC will change to GPP_A21 to meet DP++ function and it based on Moli GPIO Table_20220803.xlsx. But it will let current eMMC skus can't boot into OS, so use the board_ver to decide which gpio table return and set override_gpio_table_id2 and early_gpio_table_id2 based on Moli GPIO Table_20220803.xlsx 1. set GPP_A21 to EN_PP3300_EMMC 2. set GPP_A22 to NC 3. set GPP_E20 to DDIC_DP_CTRCLK 4. set GPP_E21 to DDIC_DP_CTRLDATA BUG=b:241370405 TEST=emerge-brask coreboot (cherry picked from commit e173f2bd5468439e5a37daf211f4ea7920650f4c) Original-Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com> Original-Change-Id: I0a2c8684d140738f43658cd6075ed083eee44e65 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/66371 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Original-Reviewed-by: Zhuohao Lee <zhuohao@google.com> GitOrigin-RevId: e173f2bd5468439e5a37daf211f4ea7920650f4c Change-Id: I55d42bb31236edb55826fc50cf7488ffb61af99d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/3834632 Reviewed-by: Rob Barnes <robbarnes@google.com> Commit-Queue: Rob Barnes <robbarnes@google.com> Tested-by: CopyBot Service Account <copybot.service@gmail.com>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.