Skylake: During RO mode after FSP reset CB lose original state
CB used to clear recovery status towards romstage end after FSP
memory init. Later inside FSP silicon init due to HSIO CRC mismatch
it will request for an additional reset.On next boot system resume
in dev mode rather than recovery because lost its original state
due to FSP silicon init reset.
Hence an additional 1 reset require to identify original state.
With this patch, we will get future platform reset info during romstage
and restore back recovery request flag so, in next boot CB can maintain
its original status and avoid 1 extra reboot.
BUG=chrome-os-partner:43517
BRANCH=none
TEST= build and booted Kunimitsu and tested RO mode
Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/302257
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
6 files changed
