ichspi: Update 100-series PCH conventions
Currently code intended to support Sunrise Point / 100-series PCH
hardware sequencing is somewhat vague in its naming, claiming the
pch_ prefix. To make things more confusing the code used 16-bit
reads/writes for hardware sequencing control/status register reads
to look like previous generation ICH chipsets.
This patch is the first in what will likely be a short series of
patches to disambiguate the current ICH/PCH hardware sequencing
support. For now we start by updating conventions to make 100-series
PCH support more explicit and use 32-bit register access where
appropriate. This at least makes the code make more sense when reading
the datasheet.
This was reverted in commit ce3334b4, but with new follow-on
patches, should be good to submit again.
BUG=none
BRANCH=none
TEST=firmware read/write on Reef (APL) and Lars (SKL) still works
Original-Change-Id: I1ba7f71d4101815fa5e306a5ae474eb9b11a0cb0
Original-Reviewed-on: https://chromium-review.googlesource.com/424048
Original-Commit-Ready: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Icdeaa52e25e043fbb733c8ae5ea93da322a102a9
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/448165
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
1 file changed
