Turn off power detect in board init
Tegra core power rail has leakage voltage around 0.2V while system in
suspend mode. The source of the leakage should be coming from PMC power detect
logic for IO rails power detection.
That can be disabled by writing a '0' to PWR_DET_LATCH followed by writing '0'
to PWR_DET (APBDEV_PMC_PWR_DET_0).
BUG=None
TEST=Suspend seaboard by "echo mem > /sys/power/state",
Probe C80 or C81 on seaboard to confirm that voltage is nearly zero.
Change-Id: I755f4915120a2b4aa2a6ce71b1ebd8958fc474bb
Signed-off-by: Wei Ni <wni@nvidia.com>
Reviewed-on: http://gerrit.chromium.org/gerrit/741
Reviewed-by: Bill Huang <bilhuang@nvidia.com>
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Anton Staaf <robotboy@chromium.org>
2 files changed
