x86/insns.dat: Enable contracted forms for a few EVEX vcvt* instructions Most instructions support contracted forms, but those had been overlooked. Signed-off-by: Henrik Gramner <henrik@gramner.com> [ hpa: manual merge ] Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
diff --git a/x86/insns.dat b/x86/insns.dat index 5afaf5d..e6bc2d4 100644 --- a/x86/insns.dat +++ b/x86/insns.dat
@@ -3583,14 +3583,14 @@ VCVTQQ2PS ymmreg|mask|z,zmmrm512|b64|er [rm:fv: evex.512.0f.w1 5b /r ] AVX512DQ VCVTSD2SI reg32,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w0 2d /r ] AVX512 VCVTSD2SI reg64,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w1 2d /r ] AVX512 -VCVTSD2SS xmmreg|mask|z,xmmreg,xmmrm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 5a /r ] AVX512 +VCVTSD2SS xmmreg|mask|z,xmmreg*,xmmrm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 5a /r ] AVX512 VCVTSD2USI reg32,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w0 79 /r ] AVX512 VCVTSD2USI reg64,xmmrm64|er [rm:t1f64: evex.128.f2.0f.w1 79 /r ] AVX512 -VCVTSI2SD xmmreg,xmmreg,rm32 [rvm:t1s: evex.nds.lig.f2.0f.w0 2a /r ] AVX512 -VCVTSI2SD xmmreg,xmmreg,rm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 2a /r ] AVX512 -VCVTSI2SS xmmreg,xmmreg,rm32|er [rvm:t1s: evex.nds.lig.f3.0f.w0 2a /r ] AVX512 -VCVTSI2SS xmmreg,xmmreg,rm64|er [rvm:t1s: evex.nds.lig.f3.0f.w1 2a /r ] AVX512 -VCVTSS2SD xmmreg|mask|z,xmmreg,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 5a /r ] AVX512 +VCVTSI2SD xmmreg,xmmreg*,rm32 [rvm:t1s: evex.nds.lig.f2.0f.w0 2a /r ] AVX512 +VCVTSI2SD xmmreg,xmmreg*,rm64|er [rvm:t1s: evex.nds.lig.f2.0f.w1 2a /r ] AVX512 +VCVTSI2SS xmmreg,xmmreg*,rm32|er [rvm:t1s: evex.nds.lig.f3.0f.w0 2a /r ] AVX512 +VCVTSI2SS xmmreg,xmmreg*,rm64|er [rvm:t1s: evex.nds.lig.f3.0f.w1 2a /r ] AVX512 +VCVTSS2SD xmmreg|mask|z,xmmreg*,xmmrm32|sae [rvm:t1s: evex.nds.lig.f3.0f.w0 5a /r ] AVX512 VCVTSS2SI reg32,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w0 2d /r ] AVX512 VCVTSS2SI reg64,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w1 2d /r ] AVX512 VCVTSS2USI reg32,xmmrm32|er [rm:t1f32: evex.128.f3.0f.w0 79 /r ] AVX512