blob: 5ae0a9f20a7787b35ad4323fafa0b4d0d48bf759 [file] [log] [blame]
/* Generated by gen_x86_insn.py rHEAD, do not edit */
static const x86_info_operand insn_operands[] = {
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEXImmSrc, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Mem, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_MemXMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_MemXMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_XMM0, OPS_128, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_MemXMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_MemYMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_MemYMMIndex, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_MemYMMIndex, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_VEX, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_SpareEA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_SImm, OPAP_SImm8},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
{OPT_Reg, OPS_80, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
{OPT_ST0, OPS_80, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDRM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_MemOffs, OPS_8, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_16, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_32, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_64, 1, 1, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_MemOffs, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_MemOffs, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_ShortMov},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_8, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Imm, OPS_64, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Imm, OPS_64, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm32Avail},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_CR4, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_CRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_DRReg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
{OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
{OPT_Creg, OPS_64, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_Short, OPA_JmpRel, OPAP_None},
{OPT_Creg, OPS_16, 0, 0, OPTM_None, OPA_AdSizeR, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Areg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Dreg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_EAVEX, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_EAVEX, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_MemrAX, OPS_Any, 0, 0, OPTM_None, OPA_AdSizeEA, OPAP_None},
{OPT_Creg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_Any, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_8, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Creg, OPS_8, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm1, OPS_8, 1, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_RM, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_8, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_256, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Reg, OPS_16, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_256, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Mem, OPS_80, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SegReg, OPS_16, 1, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_64, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Areg, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Areg, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Areg, OPS_64, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Imm, OPS_32, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_Mem, OPS_128, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_8, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_SIMDRM, OPS_128, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_SIMDReg, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_256, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 1, 0, OPTM_None, OPA_EA, OPAP_A16},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_Imm, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Spare, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SIMDReg, OPS_128, 0, 0, OPTM_None, OPA_SpareVEX, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_16, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Mem, OPS_32, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_MemEAX, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Mem, OPS_80, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Reg, OPS_BITS, 0, 0, OPTM_None, OPA_Op0Add, OPAP_None},
{OPT_RM, OPS_BITS, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_SS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_SS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_DS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_DS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_DS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_ES, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_ES, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_ES, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_FS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_FS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_FS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_GS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_GS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_GS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_Mem, OPS_Any, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_ImmNotSegOff, OPS_Any, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_ImmNotSegOff, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_ImmNotSegOff, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_16, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_Near, OPA_JmpRel, OPAP_None},
{OPT_Reg, OPS_BITS, 0, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_RM, OPS_16, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
{OPT_RM, OPS_32, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
{OPT_RM, OPS_64, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
{OPT_Mem, OPS_Any, 0, 0, OPTM_Near, OPA_EA, OPAP_None},
{OPT_Mem, OPS_16, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
{OPT_Mem, OPS_32, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
{OPT_Mem, OPS_64, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
{OPT_Mem, OPS_Any, 0, 0, OPTM_Far, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_Far, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Imm, OPS_Any, 0, 0, OPTM_None, OPA_JmpFar, OPAP_None},
{OPT_Reg, OPS_80, 0, 0, OPTM_To, OPA_Op1Add, OPAP_None},
{OPT_Reg, OPS_32, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
{OPT_Reg, OPS_64, 0, 0, OPTM_None, OPA_Op1Add, OPAP_None},
{OPT_Mem, OPS_BITS, 1, 0, OPTM_None, OPA_EA, OPAP_None},
{OPT_Imm, OPS_16, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_JmpRel, OPAP_None},
{OPT_Imm, OPS_8, 1, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_Imm, OPS_BITS, 1, 0, OPTM_None, OPA_Imm, OPAP_SImm8},
{OPT_Imm, OPS_32, 0, 0, OPTM_None, OPA_SImm, OPAP_None},
{OPT_CS, OPS_Any, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_CS, OPS_16, 0, 0, OPTM_None, OPA_None, OPAP_None},
{OPT_CS, OPS_32, 0, 0, OPTM_None, OPA_None, OPAP_None}
};
static const x86_insn_info empty_insn[] = {
{ SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info not64_insn[] = {
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info onebyte_insn[] = {
{ SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_OpSizeR, MOD_DOpS64R}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info onebyte_prefix_insn[] = {
{ SUF_Z, 0, 0, 0, 0, {MOD_PreAdd, MOD_Op0Add, 0}, 0, 0, 0x00, 1, {0x00, 0, 0}, 0, 0, 0 }
};
static const x86_insn_info twobyte_insn[] = {
{ SUF_L|SUF_Q|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, 0}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 0, 0 }
};
static const x86_insn_info threebyte_insn[] = {
{ SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, MOD_Op1Add, MOD_Op2Add}, 0, 0, 0, 3, {0x00, 0x00, 0x00}, 0, 0, 0 }
};
static const x86_insn_info onebytemem_insn[] = {
{ SUF_L|SUF_Q|SUF_S|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 1, 668 }
};
static const x86_insn_info twobytemem_insn[] = {
{ SUF_L|SUF_Q|SUF_S|SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, MOD_Op0Add, MOD_Op1Add}, 0, 0, 0, 2, {0x00, 0x00, 0}, 0, 1, 526 }
};
static const x86_insn_info mov_insn[] = {
{ SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 359 },
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 361 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 363 },
{ SUF_B|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 365 },
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 367 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 369 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 335 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 337 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 339 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 341 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 343 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 345 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 347 },
{ SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 349 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0xA2, 0}, 0, 2, 371 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 373 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 375 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0xA3, 0}, 0, 2, 377 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x88, 0, 0}, 0, 2, 317 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x89, 0, 0}, 0, 2, 254 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x89, 0, 0}, 0, 2, 260 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x89, 0, 0}, 0, 2, 266 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0xA0, 0}, 0, 2, 379 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 381 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 383 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0xA1, 0}, 0, 2, 385 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8A, 0, 0}, 0, 2, 319 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 98 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 101 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8B, 0, 0}, 0, 2, 104 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 387 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 389 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 391 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8C, 0, 0}, 0, 2, 393 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 395 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 390 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x8E, 0, 0}, 0, 2, 392 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xB0, 0, 0}, 0, 2, 397 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 399 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 401 },
{ GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 403 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0xC7, 0}, 0, 2, 405 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 407 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 409 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 411 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 413 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xC6, 0, 0}, 0, 2, 415 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 417 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 419 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xC7, 0, 0}, 0, 2, 421 },
{ SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 423 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 425 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x22, 0}, 0, 2, 427 },
{ SUF_L|SUF_Z, NOT_64, CPU_586, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 429 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 424 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x20, 0}, 0, 2, 431 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 433 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x23, 0}, 0, 2, 435 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, CPU_Priv, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 434 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_Priv, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x21, 0}, 0, 2, 437 },
{ GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x6F, 0}, 0, 2, 140 },
{ GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x6E, 0}, 0, 2, 289 },
{ GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_MMX, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0x7F, 0}, 0, 2, 325 },
{ GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_MMX, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0x7E, 0}, 0, 2, 291 },
{ GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 64 },
{ GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0xF3, 2, {0x0F, 0x7E, 0}, 0, 2, 327 },
{ GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x6E, 0}, 0, 2, 295 },
{ GAS_ONLY|SUF_Q|SUF_Z, 0, CPU_SSE2, 0, 0, {0, 0, 0}, 0, 0, 0x66, 2, {0x0F, 0xD6, 0}, 0, 2, 329 },
{ GAS_ONLY|SUF_Q|SUF_Z, ONLY_64, CPU_SSE2, 0, 0, {0, 0, 0}, 64, 0, 0x66, 2, {0x0F, 0x7E, 0}, 0, 2, 182 }
};
static const x86_insn_info movabs_insn[] = {
{ SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA0, 0, 0}, 0, 2, 335 },
{ SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 337 },
{ SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 339 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA1, 0, 0}, 0, 2, 341 },
{ SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA2, 0, 0}, 0, 2, 343 },
{ SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 345 },
{ SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 347 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA3, 0, 0}, 0, 2, 349 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xB8, 0, 0}, 0, 2, 351 }
};
static const x86_insn_info movszx_insn[] = {
{ SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 599 },
{ SUF_B|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 531 },
{ SUF_B|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 535 },
{ SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 533 },
{ SUF_W|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x01, 0}, 0, 2, 601 }
};
static const x86_insn_info movsxd_insn[] = {
{ SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x63, 0, 0}, 0, 2, 641 }
};
static const x86_insn_info push_insn[] = {
{ SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 651 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x50, 0, 0}, 0, 1, 399 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x50, 0, 0}, 0, 1, 401 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x50, 0, 0}, 0, 1, 351 },
{ SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 652 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 281 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 6, 1, 277 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0xFF, 0, 0}, 6, 1, 280 },
{ GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 100 },
{ GAS_ONLY|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x6A, 0, 0}, 0, 1, 696 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 112 },
{ GAS_ILLEGAL|SUF_Z, NOT_64, CPU_186, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 697 },
{ SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x6A, 0x68, 0}, 0, 1, 570 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6A, 0x68, 0}, 0, 1, 572 },
{ GAS_ILLEGAL|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x68, 0, 0}, 0, 1, 410 },
{ GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x68, 0, 0}, 0, 1, 412 },
{ GAS_ILLEGAL|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 64, 0, 1, {0x68, 0, 0}, 0, 1, 698 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 699 },
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 700 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x0E, 0, 0}, 0, 1, 701 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x16, 0, 0}, 0, 1, 653 },
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x16, 0, 0}, 0, 1, 654 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x16, 0, 0}, 0, 1, 655 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 656 },
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 657 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1E, 0, 0}, 0, 1, 658 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x06, 0, 0}, 0, 1, 659 },
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x06, 0, 0}, 0, 1, 660 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x06, 0, 0}, 0, 1, 661 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 662 },
{ SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 663 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA0, 0}, 0, 1, 664 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 665 },
{ SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 666 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA8, 0}, 0, 1, 667 }
};
static const x86_insn_info pop_insn[] = {
{ SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 651 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x58, 0, 0}, 0, 1, 399 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x58, 0, 0}, 0, 1, 401 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x58, 0, 0}, 0, 1, 351 },
{ SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 652 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 281 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8F, 0, 0}, 0, 1, 277 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 64, 0, 1, {0x8F, 0, 0}, 0, 1, 280 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x17, 0, 0}, 0, 1, 653 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x17, 0, 0}, 0, 1, 654 },
{ SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x17, 0, 0}, 0, 1, 655 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 656 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 657 },
{ SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x1F, 0, 0}, 0, 1, 658 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x07, 0, 0}, 0, 1, 659 },
{ SUF_Z, NOT_64, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x07, 0, 0}, 0, 1, 660 },
{ SUF_Z, NOT_64, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x07, 0, 0}, 0, 1, 661 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 662 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 663 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA1, 0}, 0, 1, 664 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 0, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 665 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 666 },
{ SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xA9, 0}, 0, 1, 667 }
};
static const x86_insn_info xchg_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 317 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x86, 0, 0}, 0, 2, 319 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 511 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x90, 0, 0}, 0, 2, 513 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 254 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x87, 0, 0}, 0, 2, 98 },
{ SUF_L|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 515 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 517 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x90, 0, 0}, 0, 2, 519 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 260 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x87, 0, 0}, 0, 2, 101 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x90, 0, 0}, 0, 2, 521 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 350 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x90, 0, 0}, 0, 2, 523 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 266 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x87, 0, 0}, 0, 2, 104 }
};
static const x86_insn_info in_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 2, 492 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 494 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 2, 613 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 2, 498 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 2, 500 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 2, 496 },
{ GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE4, 0, 0}, 0, 1, 3 },
{ GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
{ GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE5, 0, 0}, 0, 1, 3 },
{ GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEC, 0, 0}, 0, 1, 497 },
{ GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xED, 0, 0}, 0, 1, 497 },
{ GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xED, 0, 0}, 0, 1, 497 }
};
static const x86_insn_info out_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 2, 491 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 493 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 2, 495 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 2, 497 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 499 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 2, 501 },
{ GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xE6, 0, 0}, 0, 1, 3 },
{ GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
{ GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xE7, 0, 0}, 0, 1, 3 },
{ GAS_ONLY|SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xEE, 0, 0}, 0, 1, 497 },
{ GAS_ONLY|SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 497 },
{ GAS_ONLY|SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xEF, 0, 0}, 0, 1, 497 }
};
static const x86_insn_info lea_insn[] = {
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 525 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 527 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x8D, 0, 0}, 0, 2, 529 }
};
static const x86_insn_info ldes_insn[] = {
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 2, 525 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 2, 527 }
};
static const x86_insn_info lfgss_insn[] = {
{ SUF_W|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 16, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 525 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 32, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 527 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {MOD_Op1Add, 0, 0}, 64, 0, 0, 2, {0x0F, 0x00, 0}, 0, 2, 529 }
};
static const x86_insn_info arith_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x04, 0, 0}, 0, 2, 492 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 16, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 569 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 32, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 571 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op2Add, MOD_Op1AddSp, 0}, 64, 0, 0, 2, {0x83, 0xC0, 0x05}, 0, 2, 573 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 415 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0x80, 0, 0}, 0, 2, 407 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0, 0}, 0, 2, 575 },
{ GAS_ILLEGAL|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 577 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 579 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0, 0}, 0, 2, 581 },
{ GAS_ILLEGAL|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 583 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 585 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0, 0}, 0, 2, 587 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0x83, 0x81, 0}, 0, 2, 589 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x00, 0, 0}, 0, 2, 317 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x01, 0, 0}, 0, 2, 254 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x01, 0, 0}, 0, 2, 260 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x01, 0, 0}, 0, 2, 266 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0x02, 0, 0}, 0, 2, 319 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x03, 0, 0}, 0, 2, 98 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x03, 0, 0}, 0, 2, 101 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 64, 0, 0, 1, {0x03, 0, 0}, 0, 2, 104 }
};
static const x86_insn_info incdec_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 0, 0, 0, 1, {0xFE, 0, 0}, 0, 1, 415 },
{ SUF_W|SUF_Z, NOT_64, 0, 0, 0, {MOD_Op0Add, 0, 0}, 16, 0, 0, 1, {0x00, 0, 0}, 0, 1, 399 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 16, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 281 },
{ SUF_L|SUF_Z, NOT_64, CPU_386, 0, 0, {MOD_Op0Add, 0, 0}, 32, 0, 0, 1, {0x00, 0, 0}, 0, 1, 401 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 32, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 277 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_Gap, MOD_SpAdd, 0}, 64, 0, 0, 1, {0xFF, 0, 0}, 0, 1, 280 }
};
static const x86_insn_info f6_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 415 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 281 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 277 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 280 }
};
static const x86_insn_info div_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 1, 415 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 281 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 277 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 1, 280 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 465 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 467 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {MOD_SpAdd, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 469 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {MOD_SpAdd, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 471 }
};
static const x86_insn_info test_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xA8, 0, 0}, 0, 2, 492 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 619 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 621 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xA9, 0, 0}, 0, 2, 623 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 415 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 0, 2, 407 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 417 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 409 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 419 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 411 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 421 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 0, 2, 413 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 317 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 254 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 260 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 266 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0x84, 0, 0}, 0, 2, 319 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x85, 0, 0}, 0, 2, 98 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x85, 0, 0}, 0, 2, 101 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x85, 0, 0}, 0, 2, 104 }
};
static const x86_insn_info aadm_insn[] = {
{ SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 2, {0xD4, 0x0A, 0}, 0, 0, 0 },
{ SUF_Z, 0, 0, 0, 0, {MOD_Op0Add, 0, 0}, 0, 0, 0, 1, {0xD4, 0, 0}, 0, 1, 3 }
};
static const x86_insn_info imul_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 0, 0, 0, 1, {0xF6, 0, 0}, 5, 1, 415 },
{ SUF_W|SUF_Z, 0, 0, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 281 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 277 },
{ SUF_Q|SUF_Z, ONLY_64, 0, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0xF7, 0, 0}, 5, 1, 280 },
{ SUF_W|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 16, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 98 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 101 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_386, 0, 0, {0, 0, 0}, 64, 0, 0, 2, {0x0F, 0xAF, 0}, 0, 2, 104 },
{ SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 98 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 101 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 3, 104 },
{ SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 297 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 299 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0, 0}, 0, 2, 301 },
{ SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 107 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 110 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 3, 113 },
{ SUF_W|SUF_Z, 0, CPU_186, 0, 0, {0, 0, 0}, 16, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 303 },
{ SUF_L|SUF_Z, 0, CPU_386, 0, 0, {0, 0, 0}, 32, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 305 },
{ SUF_Q|SUF_Z, ONLY_64, CPU_186, 0, 0, {0, 0, 0}, 64, 0, 0, 1, {0x6B, 0x69, 0}, 0, 2, 307 }
};
static const x86_insn_info shift_insn[] = {
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0, 0, 1, {0xD2, 0, 0}, 0, 2, 545 },
{ SUF_B|SUF_Z, 0, 0, 0, 0, {MOD_SpAdd, 0, 0}, 0, 0,