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| <project groups="minilayout,project_sdk,buildtools" name="external/swarming.client" path="chromite/third_party/swarming.client" revision="0ec868bc7a6a72ca40e3cb508898e4e07f109ae1"/> |
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| <pending_commit branch="master" change_id="Ie433b07860cb1b04c12b2609c6fa39025fc0e515" commit="7412a4379e7d276c53d2f1b00a67a7d765699bca" commit_message="Cr50: Disable customized RO image by default A previous commit caused ToT to use a not-yet-working bootloader. This disables that bootloader by default so that the rest of us can continue to work. ;-) A configuration option is added to be able to address this issue in the future with other boards as well. BRANCH=None BUG=chrome-os-partner:43025, chromium:551151 TEST=make buildall -j Also verified that both normal and customized cr50 RO images build and work as expected. Change-Id: Ie433b07860cb1b04c12b2609c6fa39025fc0e515 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310978 " fail_count="0" gerrit_number="310978" owner_email="wfrichar@chromium.org" pass_count="0" patch_number="3" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/78/310978/3" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ia8a064758f71f86771729437ae3e81226fd55789" commit="6c547fcc0f4b4ae34a22b8b038b1a53250cc7611" commit_message="Cr50: Update to the "final" FPGA image 20151104_041733@78962 In fact this provides support for three FPGA images: 20151104_011218 - full crypto, no USB 20151104_041733 - tiny crypto, full USB 20151104_065845 - full crypto, full USB (only for hard-to-get boards) We can tell these FPGA images apart at run-time by looking at some SWDP registers: register crypto usb full GREG32(SWDP, BUILD_TIME) 0x2bd2 0xa305 0x10135 GREG32(SWDP, FPGA_CONFIG) 0x1 0x2 0x3 This CL includes a run-time check for the USB features so that it's safe to build the firmware with CONFIG_USB and run it on a non-USB FPGA image. Here are the differences I could find in the top-level image header files: All three FPGA images define different (apparently arbitrary) default values for the PMU_PWRDN_SCRATCHn registers, but other than that, the usb and full images differ only in the BUILD_TIME and FPGA_CONFIG register values. I'm not sure why, but function uart_init() in file chip/g/polling_uart.c writes to one of the PMU_PWRDN_SCRATCHn registers, but nothing seems to read it again. The crypto image defines these values which don't appear in the other images: #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51 #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52 #define PINMUX_USB0_EXT_RX_DMI_SEL 0x53 #define PINMUX_USB0_EXT_RX_DPI_SEL 0x54 #define PINMUX_USB0_EXT_RX_RCV_SEL 0x55 #define PINMUX_USB0_EXT_SUSPENDB_SEL 0x56 #define PINMUX_USB0_EXT_TX_DMO_SEL 0x57 #define PINMUX_USB0_EXT_TX_DPO_SEL 0x58 #define PINMUX_USB0_EXT_TX_OEB_SEL 0x59 #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230 #define PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234 #define PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238 #define PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c #define PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x240 #define PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x244 #define PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x248 #define PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x24c #define PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x250 #define PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x254 #define PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0 #define PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x258 #define PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0 The crypto image also differs in this: #define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c instead of this: #define PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230 The rest of the differences between the crypto and usb versions are in these values, which I don't think we care about. At least, I can't find any place where they're used. PINMUX_EXITEDGE0_DIOAn_OFFSET PINMUX_EXITEDGE0_DIOBn_OFFSET PINMUX_EXITEDGE0_DIOMn_OFFSET PINMUX_EXITEDGE0_VIOn_OFFSET PINMUX_EXITEDGE0_OFFSET PINMUX_EXITEN0_DIOAn_OFFSET PINMUX_EXITEN0_DIOBn_OFFSET PINMUX_EXITEN0_DIOMn_OFFSET PINMUX_EXITEN0_VIOn_OFFSET PINMUX_EXITEN0_OFFSET PINMUX_EXITINV0_DIOAn_OFFSET PINMUX_EXITINV0_DIOBn_OFFSET PINMUX_EXITINV0_DIOMn_OFFSET PINMUX_EXITINV0_VIOn_OFFSET PINMUX_EXITINV0_OFFSET PINMUX_HOLD_OFFSET PINMUX_SEL_COUNT PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET PINMUX_XO0_TESTBUSn_SEL PINMUX_XO0_TESTBUSn_SEL_OFFSET I used the header from the usb image to update chip/g/cr50_fpga_regdefs.h BRANCH=none BUG=chrome-os-partner:43791 CQ-DEPEND=CL:310978 TEST=make buildall I also built a single Cr50 firmware and tried it on both the crypto and usb FPGA images. Both worked as expected. Change-Id: Ia8a064758f71f86771729437ae3e81226fd55789 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311211 " fail_count="0" gerrit_number="311211" owner_email="wfrichar@chromium.org" pass_count="0" patch_number="3" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/11/311211/3" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Id321f81b82bc25f271ccd54a40bc8a8cb8961fd8" commit="82670a0b2275d142f61685dc22fcc32db94feb3b" commit_message="Disble firmware_FwScreenPressPower for DUT without power button. BUG=chromium-os-partner:44099 TEST=Execute on Mickey Change-Id: Id321f81b82bc25f271ccd54a40bc8a8cb8961fd8 Reviewed-on: https://chromium-review.googlesource.com/310888 Commit-Ready: danny chan <dchan@chromium.org> Tested-by: danny chan <dchan@chromium.org> Reviewed-by: Wai-Hong Tam <waihong@chromium.org> " fail_count="0" gerrit_number="310888" owner_email="dchan@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/88/310888/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="Ic3af01ddc0639b75f4685b1c1d287c858b944494" commit="1d3adda448cd2cce085dd4eed75bc29407d8225f" commit_message="stateful_update retry once on downloading error. Sometimes wget may fail to get the full contents of stateful.tgz and then tar will exit with code 2. This CL retries wget and tar once to make it more robust on dealing with network flake. TEST=Run a trybot. Manually ran the script, force the branch to trigger. BUG=chromium:485197;chromium:546630 Change-Id: Ic3af01ddc0639b75f4685b1c1d287c858b944494 Reviewed-on: https://chromium-review.googlesource.com/310922 Commit-Ready: Fang Deng <fdeng@chromium.org> Tested-by: Fang Deng <fdeng@chromium.org> Reviewed-by: Richard Barnette <jrbarnette@chromium.org> Reviewed-by: Chris Sosa <sosa@chromium.org> " fail_count="0" gerrit_number="310922" owner_email="fdeng@chromium.org" pass_count="0" patch_number="6" project="chromiumos/platform/dev-util" project_url="https://chromium-review.googlesource.com/chromiumos/platform/dev-util" ref="refs/changes/22/310922/6" remote="cros" total_fail_count="0"/><lkgm version="7615.0.0-rc1"/></manifest> |
