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| <pending_commit branch="chromeos-2016.02" change_id="Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019" commit="d789d79223986e2ffcd70f11d182c1d8c4b4bc33" commit_message="soc/qualcomm/ipq40xx: Add support for BLSP QUP I2C Able to talk to the TPM device and the commands seem to succeed. BUG=chrome-os-partner:49249 chrome-os-partner:49250 TEST=All commands to the TPM succeed BRANCH=none Change-Id: Ie8c3c1ab1290cd8d7e6ddd1ae22f765c7be81019 Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/333314 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> " fail_count="0" gerrit_number="333314" owner_email="varada@codeaurora.org" pass_count="0" patch_number="11" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/14/333314/11" remote="cros" total_fail_count="3"/><pending_commit branch="chromeos-2016.02" change_id="If809b0fdf7d6c9405db6fd3747a3774c00ea9870" commit="a9c3c328c3c8e701d9f3a1e2f4c5c8094b49421e" commit_message="soc/qualcomm/ipq40xx: Add support for BLSP QUP SPI - Enable BLSP SPI driver for ipq40xx - supports only FIFO mode BUG=chrome-os-partner:49249 TEST=None. Initial code not sure if it will even compile BRANCH=none Change-Id: If809b0fdf7d6c9405db6fd3747a3774c00ea9870 Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/333303 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> " fail_count="0" gerrit_number="333303" owner_email="varada@codeaurora.org" pass_count="0" patch_number="12" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/03/333303/12" remote="cros" total_fail_count="2"/><pending_commit branch="chromeos-2016.02" change_id="Id6e09516209f47c3ea8fa3d8d90440789b395660" commit="87898952190526996159f2d6c35ca4a126bfeeb9" commit_message="soc/qualcomm/ipq40xx: Enable crashdump handling Clear the crash dump cookie set by SBL to indicate that it is a normal reset. Inform DDR image of the entrypoint for SDI image to be preserved in OCIMEM which will be needed during watchdog resets. BUG=chrome-os-partner:49249 TEST=DDR image is able to fetch the entry point address BRANCH=none Change-Id: Id6e09516209f47c3ea8fa3d8d90440789b395660 Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Reviewed-on: https://chromium-review.googlesource.com/333321 Commit-Ready: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> " fail_count="0" gerrit_number="333321" owner_email="varada@codeaurora.org" pass_count="0" patch_number="12" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/21/333321/12" remote="cros" total_fail_count="4"/><lkgm version="8223.0.0-rc1"/></manifest> |
