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| <pending_commit branch="master" change_id="I33371e7dcee9905c2f1453743e88bdbcfff88e75" commit="0c7f081b7a6ac830769e6e68348591c46a6773b8" commit_message="Un-fork Minijail. Also fix one erroneous tab char. BUG=b:32206741 TEST=None, but this is a piecemeal-revert of https://chromium-review.googlesource.com/343290. Change-Id: I33371e7dcee9905c2f1453743e88bdbcfff88e75 Reviewed-on: https://chromium-review.googlesource.com/400478 Commit-Ready: Jorge Lucangeli Obes <jorgelo@chromium.org> Tested-by: Jorge Lucangeli Obes <jorgelo@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="400478" owner_email="jorgelo@chromium.org" pass_count="0" patch_number="2" project="chromiumos/manifest" project_url="https://chromium-review.googlesource.com/chromiumos/manifest" ref="refs/changes/78/400478/2" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I277cc9ae22cd33f2cd9ded808960349d09e8670d" commit="2fca8628fb07f530d7601916d951fb42453763b0" commit_message="UPSTREAM: riscv and power8: Convert printk/while(1) to die BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: I277cc9ae22cd33f2cd9ded808960349d09e8670d Reviewed-on: https://chromium-review.googlesource.com/400101 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400101" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/01/400101/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1789bad8bbab964c3f2f0480de8d97588c68ceaf" commit="c2b4963877975bc24fdd884d654bb82b19e3a491" commit_message="UPSTREAM: riscv: Clean up {qemu,spike}_util spike_util.h: - (LOG_)REGBYTES and STORE are already defined in arch/riscv/include/bits.h. - TOHOST_CMD, FROMHOST_* are helper macros for the deprecated Host-Target Interface (HTIF). qemu_util.c: - mcall_query_memory now uses mprv_write_ulong instead of first translating the address and then accessing it normally. Thus, translate_address isn't used anymore. - Several functions used the deprecated HTIF CSRs mtohost/mfromhost. They have mostly been replaced by stub implementations. - htif_interrupt and testPrint were unused and have been deleted. spike_util.c: - translate_address and testPrint were unused and have been deleted. After this commit, spike_util.c and qemu_util.c are exactly the same and can be moved to a common location. BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16985 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: I1789bad8bbab964c3f2f0480de8d97588c68ceaf Reviewed-on: https://chromium-review.googlesource.com/400102 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400102" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/02/400102/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id30463d1809d0a31c9d3825642dce66f3ab2750d" commit="e720fc4f9e8dda14718065073b9faa090405c81e" commit_message="UPSTREAM: arch/riscv: Remove unused bootblock_simple.c BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16986 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Id30463d1809d0a31c9d3825642dce66f3ab2750d Reviewed-on: https://chromium-review.googlesource.com/400103 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400103" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/03/400103/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id173643a3571962406f9191db248b206235dca35" commit="9c056feb6829ebcd0d79f260f24c7eb490532a7b" commit_message="UPSTREAM: riscv: Use the generic src/lib/bootblock.c TEST=Compiled for and ran on spike; it booted as before. BUG=None BRANCH=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16995 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: Id173643a3571962406f9191db248b206235dca35 Reviewed-on: https://chromium-review.googlesource.com/400104 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400104" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/04/400104/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia1de545325a53607f62d08e76b2f61b25edbe6ef" commit="199f30d4bf22e1cc5af790f961689fa2c0a4c829" commit_message="UPSTREAM: [WIP] console/Kconfig: Calculate COM port base addresses only on x86 On other architectures, the serial ports aren't mapped at 0x3f8. WIP: I'm not sure how exactly the dependency should be encoded in Kconfig. BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16982 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ia1de545325a53607f62d08e76b2f61b25edbe6ef Reviewed-on: https://chromium-review.googlesource.com/400105 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400105" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/05/400105/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a" commit="ade8d187b523aba8d6f40d0dc2312bd6cffe2644" commit_message="UPSTREAM: arch/riscv: Visually align trap frame information The pointers printed on unaligned memory accesses are now aligned to those printed at the end of print_trap_information. BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16983 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Change-Id: Ifec1cb639036ce61b81fe8d0a9b14c00d5b2781a Reviewed-on: https://chromium-review.googlesource.com/400106 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400106" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/06/400106/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I81ced8c6e02b00a3835e3b42c9cf2669b1b2bd3e" commit="0d3246f1986e1fbd0ca412a709c926a81f48fefb" commit_message="UPSTREAM: RISCV: change make-spike-elf to use the coreboot toolchain. BUG=None BRANCH=None TEST=None Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> [jn: Added XGCC_BIN variable to avoid requiring the tools in $PATH] Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16955 Tested-by: build bot (Jenkins) Change-Id: I81ced8c6e02b00a3835e3b42c9cf2669b1b2bd3e Reviewed-on: https://chromium-review.googlesource.com/400107 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400107" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/07/400107/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id5f3f7f25041189d137ef4daa9f63a3b478763bc" commit="6bfa8301410bbf609582404a5003d37b5cf4f9f7" commit_message="UPSTREAM: MAINTAINERS/RISCV: Cover mb/emulation/spike-riscv BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16988 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: Id5f3f7f25041189d137ef4daa9f63a3b478763bc Reviewed-on: https://chromium-review.googlesource.com/400108 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400108" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/08/400108/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I53ba5ba790ae683082e712dc0b92f1ac5bf27ddb" commit="ae67aca9133109759bc83828fe4e5bf216cb0ff5" commit_message="UPSTREAM: MAINTAINERS: Add Jonathan Neuschfer as RISC-V co-maintainer BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16990 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: I53ba5ba790ae683082e712dc0b92f1ac5bf27ddb Reviewed-on: https://chromium-review.googlesource.com/400109 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400109" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/09/400109/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a" commit="30163666f34b17192646cdf5fb2832e9ede5a34d" commit_message="UPSTREAM: nb/i945/gma.c: correct VSYNC end offset According to "G45: Volume 3: Display Register Intel 965G Express Chipset Family and Intel G35 Express Chipset Graphics Controller" the VSYNC end should start at bit 16. This is also how Linux (at least 4.4) sets this register, which can be seen with intel-gpu-tools. TESTED on Lenovo thinkpad X60 (it does not change anything). BUG=None BRANCH=None TEST=None Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17015 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a Reviewed-on: https://chromium-review.googlesource.com/400110 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400110" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/10/400110/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I60aa7102977c2b1775ab8c54d1c147737d2af5e2" commit="b455f9c1be4254dadc3cc7368fe27724cd46b948" commit_message="UPSTREAM: soc/intel/apollolake: clear PMC registers The clearing of the PMC registers was not being called resulting in state persisting across reboots. This state is queried and events are added to the eventlog like 'RTC reset' events. However, the RTC reset event is a one time thing so it should only be logged once. Without the clearing of the state the event was logged on every boot. BUG=chrome-os-partner:58496 BRANCH=None TEST=None Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17027 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I60aa7102977c2b1775ab8c54d1c147737d2af5e2 Reviewed-on: https://chromium-review.googlesource.com/400111 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400111" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/11/400111/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I77eed0e1bdc1ba49381b72e21b0e18f573cadff0" commit="45f0053901edb4bf38406529eb0414786e3b6c85" commit_message="UPSTREAM: soc/intel/skylake: Select VBOOT_EC_SLOW_UPDATE if EC_GOOGLE_CHROMEEC is selected VBOOT_EC_SLOW_UPDATE should be selected if EC_GOOGLE_CHROMEEC is used as building coreboot with Chrome OS support & without Chrome EC gives a build error in coreboot. BUG=None BRANCH=None TEST=None Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17020 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I77eed0e1bdc1ba49381b72e21b0e18f573cadff0 Reviewed-on: https://chromium-review.googlesource.com/400112 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400112" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/12/400112/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I99ce0ccd42610112a361a48ba31168c9feaa0332" commit="9cf9d52bece9215244597c6d9f501dbc1bfdaa92" commit_message="UPSTREAM: soc/intel/skylake: Enable HECI BAR for ME communication This patch programs and enables BAR for ME (bus:0/ device:0x16/function:0) device to have early ME communication. BUG=none BRANCH=none TEST=Verified Global Reset MEI message can able to perform platform global reset during romstage. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/17016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332 Reviewed-on: https://chromium-review.googlesource.com/400113 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400113" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/13/400113/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If326a137eeadaa695668b76b84c510e12c546024" commit="175c561c6929667a1971ce29c9304858f97eb336" commit_message="UPSTREAM: soc/intel/skylake: Implement Global Reset MEI message As per ME BWG, there are two mechanism to generate a Global Reset (resets both host and Intel ME), one is through CF9h IO write of 6h or Eh with "CF9h Global Reset" (CF9GR) bit set, PMC PCI offset ACh[20]. Another is to issue the Global Reset MEI message. Because any attempts to cause global reset without synchronizing the two sides might cause unwanted side effects, such as unwritten flash data that will get destroyed if the host were to cause a global reset without informing Intel ME firmware, the recommended method is to send a Global Reset MEI message when the following conditions are met: The PCH chipset firmware just needs to complete the Intel ME Interface #1 initialization and check the Intel ME HFSTS state if Intel ME is not in ERROR state and is accepting MEI commands then firmware should be able to use Global Reset MEI message to trigger global reset. Furthermore, if Intel ME is in ERROR state, BIOS can use I/O 0xCF9 write of 0x06 or 0x0E command with PCH ETR3 register bit [20] to perform the global reset. BUG=none BRANCH=none TEST=Verified Global Reset MEI message is able to perform platform global issue in ME good state. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16902 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: If326a137eeadaa695668b76b84c510e12c546024 Reviewed-on: https://chromium-review.googlesource.com/400114 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400114" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/14/400114/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I57e55caa6d20b15644bac686be8734d9652f21e5" commit="95df8f1a45bb501b562883c3503b32fd58fd3374" commit_message="UPSTREAM: soc/intel/skylake: Handle platform global reset In FSP1.1 all the platform resets including global was handled on its own without any intervention from coreboot. In FSP2.0, any reset required will be notified to coreboot and it is expected that coreboot will perform platform reset. Hence, implement platform global reset hooks in coreboot. If Intel ME is in non ERROR state then MEI message will able to perform global reset else force global reset by writing 0x6 or 0xE to 0xCF9 port with PCH ETR3 register bit [20] set. BUG=none BRANCH=none TEST=Verified platform global reset is working with MEI message or writing to PCH ETR3. Signed-off-by: Subrata Banik <subrata.banik@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16903 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I57e55caa6d20b15644bac686be8734d9652f21e5 Reviewed-on: https://chromium-review.googlesource.com/400115 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400115" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/15/400115/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I34208048a6d4a127e9b1267d2df043cb2c46cf77" commit="05aed59a10598395e5b447711d179eed33857a39" commit_message="UPSTREAM: soc/intel/apollolake: Set PL1 limits for RAPL MSR registers This patch sets the package power limit (PL1) value in RAPL MSR and disables MMIO register. Added configurable PL1 override parameter to leverage full TDP capacity. BUG=chrome-os-partner:56922 BRANCH=None TEST=webGL performance(fps) not impacted before and after S3. Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16884 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I34208048a6d4a127e9b1267d2df043cb2c46cf77 Reviewed-on: https://chromium-review.googlesource.com/400116 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> " fail_count="0" gerrit_number="400116" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/16/400116/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I21c278e82b82d805f6925f4d9c82187825fd0aa0" commit="ddc21c7221b2af05212f7efde98e9bfe8a077041" commit_message="UPSTREAM: mainboard/google/reef: Set PL1 override to 12000mW Reef is using APL SoC SKU's with 6W TDP max. We've done experiments and found the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:56922 BRANCH=None TEST=webGL performance(fps) not impacted before and after S3. Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I21c278e82b82d805f6925f4d9c82187825fd0aa0 Reviewed-on: https://chromium-review.googlesource.com/400117 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> " fail_count="0" gerrit_number="400117" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/17/400117/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I97c3d82f654be30a0d2d88cb68c8212af3d6f767" commit="a0fd80020204f63350919d699bf78080e6f77c27" commit_message="UPSTREAM: soc/apollolake: Add soc core init Skip FSP initiated core/MP init as it is implemented and initiated in coreboot. Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16587 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: I97c3d82f654be30a0d2d88cb68c8212af3d6f767 Reviewed-on: https://chromium-review.googlesource.com/400458 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400458" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/58/400458/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I02f72841a20db3d86d1b67ccf371bd40bb9a4d51" commit="c74ceb779b7cee4309d97c5cadde3c125e59beba" commit_message="UPSTREAM: util/cbfstool: Allow overwriting CBFS regions with raw data on request Add a --force/-F option and enable it for cbfstool write, where it has the effect of not testing if the fmap region contains a CBFS or if the data to write is a CBFS image. BUG=None BRANCH=None TEST=None Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/16998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I02f72841a20db3d86d1b67ccf371bd40bb9a4d51 Reviewed-on: https://chromium-review.googlesource.com/398759 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="398759" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/59/398759/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Ic5a3be1128f2f9a53d21e0a2c577192962260df6" commit="8d58e03c24f5e8b5543e34dbf643abf3cf5c7a66" commit_message="UPSTREAM: cbfstool: Fix typo in help text BUG=None BRANCH=None TEST=None Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/17018 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: Ic5a3be1128f2f9a53d21e0a2c577192962260df6 Reviewed-on: https://chromium-review.googlesource.com/398760 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="398760" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/60/398760/2" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="Ib60061fa60e81e36234355aeecd6fefad8f5fed1" commit="2bd46df11b7a61edbb5699dfea9e0ae7631441b4" commit_message="UPSTREAM: ec/lenovo/h8: fix whitespaces/tabs BUG=None BRANCH=None TEST=None Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/17037 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Change-Id: Ib60061fa60e81e36234355aeecd6fefad8f5fed1 Reviewed-on: https://chromium-review.googlesource.com/400459 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400459" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/59/400459/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Iab18b2de621a1a9226c78493f6defa15081db875" commit="d405aa7dabcaf1de5f5f5132ee97b8cd3701a5ca" commit_message="UPSTREAM: mainboard/google/reef: Configure PERST pin for reef DVT Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:55877 BRANCH=None TEST=S0ix functional on DVT Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/17030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875 Reviewed-on: https://chromium-review.googlesource.com/400460 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400460" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/60/400460/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I3f99190401d8df1415328da9c3b928194593901c" commit="45f7cd57e12b2f80e5aed870ba56818a3de6f25a" commit_message="UPSTREAM: northbridge/via/vx800: Convert 'for (;;)' to 'die' BUG=None BRANCH=None TEST=None Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16989 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Change-Id: I3f99190401d8df1415328da9c3b928194593901c Reviewed-on: https://chromium-review.googlesource.com/400461 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400461" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/61/400461/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I3c66c688dbfd903ecf5303abcdf6b5ded84585c7" commit="fa4a3cefb2d742be05488bca3420ef04e01c1e32" commit_message="UPSTREAM: Revert "[WIP] console/Kconfig: Calculate COM port base addresses only on x86" This reverts commit 2c8f3bd91b54e85b4d2e24894ee8bbbfb9ad8a31. I mistakenly commited a WIP, sorry. BUG=None BRANCH=None TEST=None Reviewed-on: https://review.coreboot.org/17028 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Change-Id: I3c66c688dbfd903ecf5303abcdf6b5ded84585c7 Reviewed-on: https://chromium-review.googlesource.com/400462 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400462" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/62/400462/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I156cf5734a16605decc2280e54e6db3089e094a2" commit="a8e8a43f568d8af1555b5427d3934dba4798a441" commit_message="UPSTREAM: arch/riscv: In trap handler, don't print SP twice The stack pointer (SP) is already printed in print_trap_information. Don't print it again in handle_misaligned_{load,store}. BUG=None BRANCH=None TEST=None Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2 Reviewed-on: https://chromium-review.googlesource.com/400463 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400463" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/63/400463/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5050c58d18db38fffabc7666e67a622d4a828590" commit="80456b1b1a2ee76ad364eaf13ec3d96cf01442a3" commit_message="UPSTREAM: rk3399: display: Use edid_set_framebuffer_bits_per_pixel() helper This refactoring was already carried into RK3288 with commit 6911219 (edid: Add helper function to calculate bits-per-pixel dependent values) but it seems that the code for RK3399 was copy&pasted from it too early to pick this up. Fix that so that future Rockchip SoCs can copy&paste the right thing. BUG=None BRANCH=None TEST=None Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17050 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590 Reviewed-on: https://chromium-review.googlesource.com/400464 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> " fail_count="0" gerrit_number="400464" owner_email="furquan@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/64/400464/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I567d5879555f4ae7382fc47ef79135e7a13b7600" commit="fbd6d2e519a4cfc6d3689a502f24513a4892a813" commit_message="bdb: Add --data_version to futility-bdb --resign This change makes futility-bdb command take --data_version parameter. BUG=chromium:649554 BRANCH=none TEST=make runtests $ futility bdb --resign test/futility/data/bin.bdb --data_version 2 then futility show --type bdb test/futility/data/bin.bdb Change-Id: I567d5879555f4ae7382fc47ef79135e7a13b7600 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/399593 Reviewed-by: Randall Spangler <rspangler@chromium.org> " fail_count="1" gerrit_number="399593" owner_email="dnojiri@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/vboot_reference" project_url="https://chromium-review.googlesource.com/chromiumos/platform/vboot_reference" ref="refs/changes/93/399593/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ib4dec86c2a043e0989c91bbc01f39776e3630e4c" commit="ba008a1bd9afcc9e210e74dfb8a9c3ef712a3d97" commit_message="bdb: Add --load_address to futility-bdb --create This change makes futility-bdb --create take --load_address parameter, which sets the load address field in the BDB header. BUG=chromium:649554 BRANCH=none TEST=make runtests $ futility bdb --resign test/futility/data/bin.bdb --data_version 2 then futility show --type bdb test/futility/data/bin.bdb Change-Id: Ib4dec86c2a043e0989c91bbc01f39776e3630e4c Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/399594 Reviewed-by: Randall Spangler <rspangler@chromium.org> " fail_count="2" gerrit_number="399594" owner_email="dnojiri@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/vboot_reference" project_url="https://chromium-review.googlesource.com/chromiumos/platform/vboot_reference" ref="refs/changes/94/399594/2" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I3c57f03d82fb0daefad6ec516fd9767c5ec82d5b" commit="2de13984bac1a6df41db03542197b6c728a1e798" commit_message="profiles: unset CC and CXX for serf. This unsets CC and CXX for serf. Otherwise, it will use target compiler as host compiler and causes configure error. BUG=chromium:656818 TEST=CC=x86_64-cros-linux-gnu-gcc CXX=x86_64-cros-linux-gnu-g++ emerge-guado_moblab serf Change-Id: I3c57f03d82fb0daefad6ec516fd9767c5ec82d5b Reviewed-on: https://chromium-review.googlesource.com/400027 Commit-Ready: Luis Lozano <llozano@chromium.org> Tested-by: Luis Lozano <llozano@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="400027" owner_email="yunlian@chromium.org" pass_count="0" patch_number="3" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/27/400027/3" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I1c8a3db77a95e908e74b641d9d9b9be18ad6b276" commit="0915bc2ada1cd867f8bca2441891b542316c7582" commit_message="moblab: use gcc as the default compiler. With CL:396170, we will set the default compiler to LLVM for amd64 boards. We have not tested the moblab, so we contiue to use gcc for moblab. BUG=chromium:537368 TEST=moblab still uses gcc to build it. CQ-DEPEND=CL:400027 Change-Id: I1c8a3db77a95e908e74b641d9d9b9be18ad6b276 Reviewed-on: https://chromium-review.googlesource.com/397863 Commit-Ready: Yunlian Jiang <yunlian@chromium.org> Tested-by: Yunlian Jiang <yunlian@chromium.org> Reviewed-by: Luis Lozano <llozano@chromium.org> " fail_count="0" gerrit_number="397863" owner_email="yunlian@chromium.org" pass_count="0" patch_number="5" project="chromiumos/overlays/board-overlays" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/board-overlays" ref="refs/changes/63/397863/5" remote="cros" total_fail_count="4"/><pending_commit branch="master" change_id="Ic5fe6370cd6bba8bdd17b7ec5b9543fb12451a42" commit="546dcc9c38e3aaedbc7426b984676b3095a0de8f" commit_message="login: Adding systemd recipes Extracted the Upstart script sections and created special files for them which are used by both Upstart and systemd. BUG=chromium:583671 TEST=test_that [ip] login_RemoteOwnership login_OwnershipRetaken login_OwnershipNotRetaken login_LoginSuccess login_Cryptohome login_SameSessionTwice login_OwnershipApi login_MultipleSessions login_MultiUserPolicy login_LogoutProcessCleanup login_CryptohomeOwnerQuery login_CryptohomeIncognito login_OobeLocalization login_OwnershipTaken login_ChromeProfileSanitary login_RetrieveActiveSessions login_UserPolicyKeys login_GaiaLogin login_GuestAndActualSession suite:bvt-inline CQ-DEPEND=CL:390811 Change-Id: Ic5fe6370cd6bba8bdd17b7ec5b9543fb12451a42 Reviewed-on: https://chromium-review.googlesource.com/390771 Commit-Ready: Dan Shi <dshi@google.com> Tested-by: Sabin Floares <sabin.floares@intel.com> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="2" gerrit_number="390771" owner_email="sabin.floares@intel.com" pass_count="0" patch_number="6" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/71/390771/6" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I71cbf0947742b61f831149015eb331a602d56dab" commit="25805f8ac87fcd5b0c7b63bd91d6c1f2e404fd20" commit_message="chromeos-base/chromeos-login: Adding systemd recipes BUG=chromium:583671 TEST=Built packages. CQ-DEPEND=CL:390771 Change-Id: I71cbf0947742b61f831149015eb331a602d56dab Reviewed-on: https://chromium-review.googlesource.com/390811 Commit-Ready: Dan Shi <dshi@google.com> Tested-by: Sabin Floares <sabin.floares@intel.com> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="2" gerrit_number="390811" owner_email="sabin.floares@intel.com" pass_count="0" patch_number="3" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/11/390811/3" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I1e832d712d51e1f5b87521800c74f75a7d6bfa8c" commit="a7dca4d5c7ed9ae73fd2a4befccf99d94621950c" commit_message="Adding eMMC write load test. BUG=None TEST=Ran load test on two separate boards to completion. Change-Id: I1e832d712d51e1f5b87521800c74f75a7d6bfa8c Adding eMMC write load test. BUG=None TEST=Ran load test on two separate boards to completion. Change-Id: I1e832d712d51e1f5b87521800c74f75a7d6bfa8c Reviewed-on: https://chromium-review.googlesource.com/397299 Commit-Ready: danny chan <dchan@chromium.org> Commit-Ready: Tyler Reid <twreid@chromium.org> Tested-by: Tyler Reid <twreid@chromium.org> Reviewed-by: danny chan <dchan@chromium.org> " fail_count="0" gerrit_number="397299" owner_email="twreid@chromium.org" pass_count="0" patch_number="5" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/99/397299/5" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I7a15a281306e29f589de2ef59da9c424f3f6710d" commit="14b67a7667f39798c058624272fc109b03378f24" commit_message="reef: usb_pd_policy: Fix multi-func mode for USB PD Without this change the Alternate mode adapter with multi-function capablity would only be configured as DP instead of (DP + USB). BUG=chrome-os-partner:58670 BRANCH=master TEST=On Reef, with Dell dongle verified on both ports that USB 3.0 device and ethernet is working. Change-Id: I7a15a281306e29f589de2ef59da9c424f3f6710d Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/400080 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="400080" owner_email="divya.s.sasidharan@intel.com" pass_count="0" patch_number="1" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/80/400080/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I5a6bfde742a5c698680f99f342b1696084fd002a" commit="f64466a3583489fe62b11641f4c993fe018842b0" commit_message="Re-enable Google USBC peripheral FW updates. Signed-off-by: Todd Broch <tbroch@chromium.org> BRANCH=glados,gru,oak BUG=chrome-os-partner:57458 TEST=usbpd_GFU Change-Id: I5a6bfde742a5c698680f99f342b1696084fd002a Reviewed-on: https://chromium-review.googlesource.com/397862 Commit-Ready: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Benson Leung <bleung@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> " fail_count="0" gerrit_number="397862" owner_email="tbroch@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/62/397862/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I557e807ab9ebf3c8d89db8c16ac11973961cdb17" commit="579e0544a029a4d31b8b09d3b7ab2ae5c767354a" commit_message="guado_labstation overlay: Readd bluetooth. The guado_labstation-release builder is failing to build due a missing bluetooth/bluetooth.h header. I'll add it back in for now to get the build green again and figure out what other deps I need to take out. BUG=None TEST=trybot succeeds Change-Id: I557e807ab9ebf3c8d89db8c16ac11973961cdb17 Reviewed-on: https://chromium-review.googlesource.com/399982 Commit-Ready: Kevin Cheng <kevcheng@chromium.org> Tested-by: Kevin Cheng <kevcheng@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="399982" owner_email="kevcheng@chromium.org" pass_count="0" patch_number="3" project="chromiumos/overlays/board-overlays" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/board-overlays" ref="refs/changes/82/399982/3" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I99ea58ab6a2e6b268097d909d3186c75ec55936f" commit="92c01f1eea22daaeb199201f96ab583ef640c3d9" commit_message="kevin: make sure foreground ARC++ threads run on big cores Apparently our little cores are too slow to execute ARC++ apps without dropping frames, as even with performance governor Fps2D application does not produce acceptable framerate when running on little cores. BUG=chrome-os-partner:58716 TEST=Build and boot kevin, check cpus assigned to Android 'foreground' cpuset, run Fps2D. Change-Id: I99ea58ab6a2e6b268097d909d3186c75ec55936f Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/400522 Reviewed-by: Dylan Reid <dgreid@chromium.org> " fail_count="0" gerrit_number="400522" owner_email="dtor@chromium.org" pass_count="0" patch_number="1" project="chromiumos/overlays/board-overlays" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/board-overlays" ref="refs/changes/22/400522/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I34ef301704b343e3b89c66fb383985741d58280f" commit="e5db5c87aefc3cc344a92058ce0f2d11c1d92649" commit_message="vboot: Add vb2ex_printf() callback for vboot2 The vboot2 library uses a different debug printf call than vboot1. Add it. Currently, this has no effect because no vboot2 apis which generate debug output are linked into depthcharge, but this is about to change. BUG=chromium:611535 BRANCH=none TEST=emerge-samus depthcharge; build samus firmware; still boots Change-Id: I34ef301704b343e3b89c66fb383985741d58280f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/399763 Reviewed-by: Julius Werner <jwerner@chromium.org> " fail_count="0" gerrit_number="399763" owner_email="rspangler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/depthcharge" project_url="https://chromium-review.googlesource.com/chromiumos/platform/depthcharge" ref="refs/changes/63/399763/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I33afbb9c034758ef5ab939836d0a0486eefd5a43" commit="196ffc4003daf83f4b7dd607f6ac67cc29057d61" commit_message="Pbody: add override for JTAG to UART for USBPD Enable access to USBPD on Pbody boards. BUG=chrome-os-partner:56978 TEST=1. Run 'cros_workon --host start hdctools' 'sudo emerge hdctools' 'sudo servod --board pbody' 2. Then see if PD MCU UART is served successfully. Change-Id: I33afbb9c034758ef5ab939836d0a0486eefd5a43 Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/400140 Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="0" gerrit_number="400140" owner_email="kaiyen.chang@intel.com" pass_count="0" patch_number="1" project="chromiumos/third_party/hdctools" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/hdctools" ref="refs/changes/40/400140/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I6f6a3bfc0d6b748d24c31de6940dc23c9ed200cb" commit="641b30663e53eabc96d6f6aa97dc4ad15d1b6dac" commit_message="security_SandboxedServices: ignore ping/check_ethernet from autotest Add 'ping' and 'check_ethernet' to exclude list since they will be run periodically as autotest utils. BUG=chromium:656903 TEST=run the test on veyron_minnie Change-Id: I6f6a3bfc0d6b748d24c31de6940dc23c9ed200cb Reviewed-on: https://chromium-review.googlesource.com/400438 Commit-Ready: Mike Frysinger <vapier@chromium.org> Tested-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Luigi Semenzato <semenzato@chromium.org> " fail_count="0" gerrit_number="400438" owner_email="vapier@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/38/400438/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I6c4cdbd082c49169e8ede1f0c919ebc73543fe67" commit="fabc13affcef61aacaa397ba001e12f896170ff8" commit_message="security_SandboxedServices: add brcm_patchram_plus for veyron Broadcom bluetooth firmware patch downloader brcm_patchram_plus is run on some veyron_* boards. BUG=chromium:656903 TEST=run the test on veyron_minnie Change-Id: I6c4cdbd082c49169e8ede1f0c919ebc73543fe67 Reviewed-on: https://chromium-review.googlesource.com/400318 Commit-Ready: Mike Frysinger <vapier@chromium.org> Tested-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org> " fail_count="0" gerrit_number="400318" owner_email="cychiang@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/autotest" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/autotest" ref="refs/changes/18/400318/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I5d04a89d1c2acfd47d3b02dd069219c379cfe670" commit="a4243a78903691e26fa0b8b5cb2e43d5d183be4c" commit_message="container_utils: add device_jail This allows us to proxy open calls to permission_broker from inside a container by running device_jail on an existing device and then bind-mounting the resulting fake device over the real one in the container. Post-open functionality should be left alone, but open calls are intercepted by permission_broker. BUG=chromium:644338 TEST=In a terminal: # chmod a+rw /dev/cuse # sudo -u chronos device_jail /dev/bus/usb/001/001 # cat /dev/jailed-189-0 | od -tx1 and check that permission_broker was invoked to open /dev/bus/usb/001/001 in syslog Plug in a device that won't be automatically claimed by Chrome e.g. an android device and jail it, then cat the jailed device and make sure permission is allowed and you get data Change-Id: I5d04a89d1c2acfd47d3b02dd069219c379cfe670 Reviewed-on: https://chromium-review.googlesource.com/395608 Commit-Ready: Eric Caruso <ejcaruso@chromium.org> Tested-by: Eric Caruso <ejcaruso@chromium.org> Reviewed-by: Chirantan Ekbote <chirantan@chromium.org> " fail_count="0" gerrit_number="395608" owner_email="ejcaruso@chromium.org" pass_count="0" patch_number="6" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/08/395608/6" remote="cros" total_fail_count="0"/><lkgm version="8911.0.0-rc1"/></manifest> |
