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| <pending_commit branch="chromeos-2016.05" change_id="I9983d6c92b2729c602f4de1a593bd250e1fc80e4" commit="ff518c9fb576e2b0afa4d9301648f15370973ee6" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Fix normalize_training Remove cross rank/cross channel dependency. I guess this is a mistake that could lead to instabilities. Tested on Lenovo T430 (Intel IvyBridge). BUG=none BRANCH=none TEST=none Change-Id: I9983d6c92b2729c602f4de1a593bd250e1fc80e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3c8cb97ea726cfc4643f75380240e253c095bc14 Original-Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/17610 Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com> Original-Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/472706 " fail_count="0" gerrit_number="472706" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/06/472706/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1f947fcece53776fa71c55a5557c57ef526c91a2" commit="8b4d08f28b0df1f0d35ec82f3dbffa526ca0e37c" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Reduce log level Silency noisy raminit logging by: * Removing verbose logging from loops. * Printing detailed summary at end of loop instead. * Using the same scheme already present in some functions. BUG=none BRANCH=none TEST=none Change-Id: I1f947fcece53776fa71c55a5557c57ef526c91a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 368b615243ddd9848768d088c9b42fe3db4d325a Original-Change-Id: I412d81592436ac0d2422caf396c64e0c34acc2d1 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/17611 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/472707 " fail_count="0" gerrit_number="472707" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/07/472707/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I903fd25adfa117b0b466a7c191ae2bf54d7af867" commit="444773097e61179813f67e581e69fb87cbdfb6df" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Always run quick_ram_check quick_ram_check doesn't change contents of memory. Run it in S3 resume, too. BUG=none BRANCH=none TEST=none Change-Id: I903fd25adfa117b0b466a7c191ae2bf54d7af867 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 77db3e153bca631c542e0f1ea54920bbb9f24ec1 Original-Change-Id: Icaf3650fadbb3bb87d8c780a9e79737c3cf7eb06 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/17615 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/472708 " fail_count="0" gerrit_number="472708" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/08/472708/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie348a49ed33b841503f0e54b24969f7faf02b546" commit="39858314f8d2bf4d4b2dadbe2d4cdde8ab1ce8ed" commit_message="UPSTREAM: nb/intel/sandybridge/raminit: Fix odt stretch Move odt stretch into own function. Apply workaround on SandyBridge C-stepping CPU only. Apply odt stretch on all other CPU types. Don't depend on empty DIMM detection, as in case one slot is empty ref_card_offset is zero. BUG=none BRANCH=none TEST=none Change-Id: Ie348a49ed33b841503f0e54b24969f7faf02b546 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 19c3dad0ad9fb5e8c20b6c98431601250c029540 Original-Change-Id: I4320f14e0522ec997b1f9f3b12ba2c2070ee8e9e Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/17616 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/472709 " fail_count="0" gerrit_number="472709" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/09/472709/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I4e7112bb82e790719bc608ce8fe2f852f56e3ce2" commit="57c6b36dbb99e1f2d87ff9334040611d833f48ca" commit_message="UPSTREAM: libpayload: Add gru config This adds a gru libpayload config, that should fit all gru-based devices such as kevin. As gru-based devices are CrOS devices, select the associated config to enable CrOS-specific features. BUG=none BRANCH=none TEST=none Change-Id: I4e7112bb82e790719bc608ce8fe2f852f56e3ce2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 038818f00ca62b37915347bd56a1c06c350d795c Original-Change-Id: I6e79b763fc497c126612b8786a669a33b57ea29f Original-Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Original-Reviewed-on: https://review.coreboot.org/19137 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/472710 " fail_count="0" gerrit_number="472710" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/10/472710/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie41e0d5dc6a50e9b2ba170cf1ad6c25b74a47f2e" commit="050b096a773e73e8bf58ad99e457f7f1175e7feb" commit_message="UPSTREAM: nb/intel/i945: Move INTEL_EDID All boards select INTEL_EDID, move it to nb folder. BUG=none BRANCH=none TEST=none Change-Id: Ie41e0d5dc6a50e9b2ba170cf1ad6c25b74a47f2e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 46cf5c29b3f08c0ddb1893b5c87907304994fcd5 Original-Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/19086 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/472711 " fail_count="0" gerrit_number="472711" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/11/472711/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If7a8efa7bd02cb70eba10686396274d44953d6e9" commit="00f48eec753288af76b263a4f69d053d42cc9282" commit_message="UPSTREAM: mainboard/intel: Fix checkpatch errors in minnowmax This fixes the following issues, with no functional changes: ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar" ERROR:SPACING: space required after that ',' (ctx:VxV) WARNING:LONG_LINE_COMMENT: line over 80 characters WARNING:SPACE_BEFORE_TAB: please, no space before tabs ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition ERROR:SPACING: space prohibited before that close parenthesis ')' WARNING:RETURN_VOID: void function return statements are not generally useful 2 unfixed issues: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses Verified that the binary was the same before and after the changes. BUG=none BRANCH=none TEST=none Change-Id: If7a8efa7bd02cb70eba10686396274d44953d6e9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9931f66581f18adcbb2f1efd5cec7119e50a0291 Original-Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6 Original-Signed-off-by: Martin Roth <gaumless@gmail.com> Original-Reviewed-on: https://review.coreboot.org/19078 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com> Original-Reviewed-by: York Yang <york.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/472712 " fail_count="0" gerrit_number="472712" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/12/472712/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I55cba41ba898e8e4f2b74805ae9cf5a391adc277" commit="febd6cf895815008ad5705385a034f6c063abc11" commit_message="UPSTREAM: intel/minnow3: Clean up Kconfig, devicetree and FMAP This patch cleans up the code by: o adding necessary default definitions to Kconfig o removing incorrect definitions from devicetree o removing irrelevant entries from FMD file devicetree.cb and minnow3.fmd carried over a lot of code from google/reef which is not correct for Minnow3 hardware. Minnow3 is not intended to boot Chrome OS and does not need Chrome related flash regions. The erroneous code is removed. These changes are the same as those done for leafhill in commit: 6a48923 mainboard/intel/leafhill: Clean up This was tested by building with the new configuration and booting to UEFI Payload BUG=none BRANCH=none TEST=none Change-Id: I55cba41ba898e8e4f2b74805ae9cf5a391adc277 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44ff10eaa6f480067b080138ced567122cb2a000 Original-Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b Original-Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Original-Reviewed-on: https://review.coreboot.org/18963 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/472713 " fail_count="0" gerrit_number="472713" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/13/472713/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1fee9776173a5e15436da3839868584187cddc51" commit="04fe0c825fe3bbbeb1ad8b20a6eba09bdb302b59" commit_message="UPSTREAM: soc/intel/skylake: Enable XHCI clock gate control in ACPI Enable SS link trunk clock gating & D3hot when device enters D3 state. Similarly disable SS link trunk clock gating & D3hot when device enters D0 state TEST=Build & boot Poppy board. Check working for XHCI wake when DUT is in S3. Change-Id: I1fee9776173a5e15436da3839868584187cddc51 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fb7937918ae4c52c2c6b9749e3cd3277615e2f6e Original-Change-Id: Ida2afa2e5f9404c0c15d7027480a28a003ad9a40 Original-Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Original-Reviewed-on: https://review.coreboot.org/18879 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/472714 " fail_count="0" gerrit_number="472714" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/14/472714/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I12453343389f6241e529b536d62c7682db28a477" commit="fb59d4e5931e370737f6d991685677990f5d16ef" commit_message="UPSTREAM: libgfxinit: Select CONFIG_VGA when needed This wasn't caught earlier because many boards select it manually. BUG=none BRANCH=none TEST=none Change-Id: I12453343389f6241e529b536d62c7682db28a477 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ee130a5a23626ecbc37aee7d321a7501ed3c2b3 Original-Change-Id: I245ef8f44923b5384123bd549570db7c348e03b8 Original-Signed-off-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-on: https://review.coreboot.org/18771 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/472715 " fail_count="0" gerrit_number="472715" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/15/472715/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I403eb53816ac533432241c8fbbc7d81387793cf5" commit="96eff8d4eb054ebafdca28e3e1e65648cccc67a9" commit_message="UPSTREAM: ec/acpi: Add function to read EC status register BUG=none BRANCH=none TEST=none Change-Id: I403eb53816ac533432241c8fbbc7d81387793cf5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 105d8e8b01bd024c3df100b4809684628d3e8f2c Original-Change-Id: I7b690d1f23ecf4083952c173be1d3a1246bc1593 Original-Signed-off-by: Nico Huber <nico.huber@secunet.com> Original-Reviewed-on: https://review.coreboot.org/18706 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/472716 " fail_count="0" gerrit_number="472716" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/16/472716/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9671c6a3ad5127e41808247be13c99dae315ab5a" commit="e44b33061ef34ecf6c9fc761b04bfd991c1b7f21" commit_message="UPSTREAM: ec/roda/it8518: Do EC write manually with long timeout The EC may take very long for the first command on a cold boot (~180ms witnessed). Since this needs an incredibly long timeout, we do this single command manually. BUG=none BRANCH=none TEST=none Change-Id: I9671c6a3ad5127e41808247be13c99dae315ab5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e223c3aee9ac7f3b91fbbb810e9f2b2acd3fc4f6 Original-Change-Id: I3302622a845ac6651bc7f563370d8f0511836f94 Original-Signed-off-by: Nico Huber <nico.huber@secunet.com> Original-Reviewed-on: https://review.coreboot.org/18707 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/472717 " fail_count="0" gerrit_number="472717" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/17/472717/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If241c224ecb5b5aed3e308d126cd1d7d0314417e" commit="1223f5698b1d2e673d0022482e3f36f42d1776f9" commit_message="UPSTREAM: AGESA f14: Fix memory clock register decoding Bottom five LSBs are used to store the running frequency of memory clock. BUG=none BRANCH=none TEST=none Change-Id: If241c224ecb5b5aed3e308d126cd1d7d0314417e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e522258907c0f16fb46c8abfed64532fd3d81202 Original-Change-Id: I2dfcf1950883836499ea2ca95f9eb72ccdfb979c Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Original-Reviewed-on: https://review.coreboot.org/19042 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/472718 " fail_count="0" gerrit_number="472718" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/18/472718/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ibbc2ad791c59adefd90c35374aab6cb35385d942" commit="7ece233d49c33b6fa9c63b974c36020a88492b69" commit_message="UPSTREAM: AGESA: Add helpers to track heap relocation BUG=none BRANCH=none TEST=none Change-Id: Ibbc2ad791c59adefd90c35374aab6cb35385d942 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: acc599b839dff95d062883ef3a5ff6f1f9fc256c Original-Change-Id: Ib43e59e4d4ee5e48abf7177b36cb06fdae40bde9 Original-Signed-off-by: Kysti Mlkki <kyosti.malkki@gmail.com> Original-Reviewed-on: https://review.coreboot.org/18627 Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/472719 " fail_count="0" gerrit_number="472719" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/19/472719/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I34c0ae5c9f5e862ad523c58ceeeb1ab3873bc4c3" commit="9d6805cd460ef22dd0a7bde361a68dbfa6cc73e0" commit_message="UPSTREAM: arch/x86: remove CAR global migration when postcar stage is used When a platform is using postcar stage it's by definition not tearing down cache-as-ram from within romstage prior to loading ramstage. Because of this property there's no need to migrate CAR_GLOBAL variables to cbmem. BUG=none BRANCH=none TEST=none Change-Id: I34c0ae5c9f5e862ad523c58ceeeb1ab3873bc4c3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bc17cdef0d3370f10f43ef45272399e3103eb01b Original-Change-Id: I7c683e1937c3397cbbba15f0f5d4be9e624ac27f Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://review.coreboot.org/19215 Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Tested-by: build bot (Jenkins) Original-Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Kysti Mlkki <kyosti.malkki@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/472720 " fail_count="0" gerrit_number="472720" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/20/472720/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id2a1447d3112dc0f33f35b1357a039f1852da44d" commit="de4aac1292d3e8dc0d27188dee5d3aab395d31e8" commit_message="UPSTREAM: drivers/spi: Get rid of spi_get_config There is only one user for spi_get_config i.e. SPI ACPI. Also, the values provided by spi_get_config are constant for now. Thus, get rid of the spi_get_config call and fill in these constant values in SPI ACPI code itself. If there is a need in the future to change these, appropriate device-tree configs can be added. BUG=b:36873582 Change-Id: Id2a1447d3112dc0f33f35b1357a039f1852da44d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5bda642bcb0fc6004f08d8acdfe0e71d5b3c5012 Original-Change-Id: Ied38e2670784ee3317bb12e542666c224bd9e819 Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://review.coreboot.org/19203 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) Reviewed-on: https://chromium-review.googlesource.com/472721 " fail_count="0" gerrit_number="472721" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/21/472721/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="If71b610475376f348d78d709982f7c19c5ad4df9" commit="569508b38fee104ea16947ffddd2dcef60d131e8" commit_message="usb: Add scale and jpeg converter in image_processor Also set exif tags from metadata. BUG=b:24674340 TEST=image has correct exif info. Change-Id: If71b610475376f348d78d709982f7c19c5ad4df9 Reviewed-on: https://chromium-review.googlesource.com/455605 Commit-Ready: Heng-ruey Hsu <henryhsu@chromium.org> Tested-by: Heng-ruey Hsu <henryhsu@chromium.org> Reviewed-by: Ricky Liang <jcliang@chromium.org> " fail_count="3" gerrit_number="455605" owner_email="henryhsu@chromium.org" pass_count="0" patch_number="17" project="chromiumos/platform/arc-camera" project_url="https://chromium-review.googlesource.com/chromiumos/platform/arc-camera" ref="refs/changes/05/455605/17" remote="cros" total_fail_count="3"/><pending_commit branch="master" change_id="I4c90e446a0cea10cde6527b5596e41bfef4cc2ff" commit="daee997e58dd29fcd675ea5619893c27269e586e" commit_message="Mickey: Add Micron MT52L256M64D2PP-107WT:B for Mickey Read tristate GPIOs:001Z(RAM Config) = 17 BUG=b:35583545 BRANCH=none TEST=emerge-veyron_mickey mosys; ./mosys memory spd print all Change-Id: I4c90e446a0cea10cde6527b5596e41bfef4cc2ff Signed-off-by: jiazi Yang <Tomato_Yang@asus.com> Reviewed-on: https://chromium-review.googlesource.com/469526 Commit-Ready: Jiazi Yang <Tomato_Yang@asus.com> Tested-by: Jiazi Yang <Tomato_Yang@asus.com> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> " fail_count="2" gerrit_number="469526" owner_email="Tomato_Yang@asus.com" pass_count="0" patch_number="1" project="chromiumos/platform/mosys" project_url="https://chromium-review.googlesource.com/chromiumos/platform/mosys" ref="refs/changes/26/469526/1" remote="cros" total_fail_count="2"/><lkgm version="9448.0.0-rc2"/></manifest> |
