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| <pending_commit branch="chromeos-2016.05" change_id="I34d374c7397772ae2497c00a7126a8209fee3bd2" commit="56444e6387c73a8d9b90aca1cf9b3832d780ff9c" commit_message="UPSTREAM: util/gitconfig: Refuse to commit on lint failure After running `lint-stable` in the pre-commit hook, its result is ignored. This behavior was introduced in commit b18f522b (lint/gitconfig: Enable checkpatch.pl checking of commits) and it doesn't seem intentional. This issue was also mentioned in the revert discussion (https://review.coreboot.org/c/coreboot/+/17440). Enable `errexit` mode of the shell so that the hook fails when an error occurs in any of the tests. Also, enable `nounset` mode to catch typos easier. BUG=none BRANCH=none TEST=none Change-Id: I34d374c7397772ae2497c00a7126a8209fee3bd2 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 6719862de80cec31a910ab1cc39fb7d3ba7b9a80 Original-Change-Id: I749963167660ea6a1a04d40a14ad1113e82f0f86 Original-Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Original-Reviewed-on: https://review.coreboot.org/23130 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/865526 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865526" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/26/865526/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I32539920ee04abc786836cb82851a01ae606a275" commit="e467d27244048065eba06dbde5f0674c10bdc977" commit_message="UPSTREAM: mainboard/google/kahlee: Enable PCIe Lane 2 The Port initializer had been changed from PortDisabled to PortEnabled, but engine inializer hadn't been updated from PcieUnusedEngine to PciePortEngine. Update this so the port works. Also change disabled port to PcieUnusedEngine. BUG=b:71818026 TEST=PCIe device now shows up on D2F4 Change-Id: I32539920ee04abc786836cb82851a01ae606a275 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 3441292ecda5e76a98ff63f55fc45d010fc76188 Original-Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7 Original-Signed-off-by: Martin Roth <martinroth@google.com> Original-Reviewed-on: https://review.coreboot.org/23210 Original-Reviewed-by: Daniel Kurtz <djkurtz@google.com> Original-Reviewed-by: Chris Ching <chingcodes@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/865527 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865527" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/27/865527/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7d6deeff44560e78ea54314beaa51a78a355d375" commit="c66238414622525dffeec6b76a841027d2a4d2d7" commit_message="UPSTREAM: soc/amd/common/pi: Fix issue in AGESA heap allocator The heap allocator would try to split a buffer node that was too small for another node. In the failing case, the buffer node was 0x140 bytes and the requested size was 0x133 bytes. The logic would check that there was room for the header and buffer and try to split the buffer node. The buffer node header is 0xC bytes, so 0x13F bytes are need. The problem is that it didn't leave room for another node header and a little space for a buffer. BUG=b:71764350 TEST= Boot grunt. BRANCH=none Change-Id: I7d6deeff44560e78ea54314beaa51a78a355d375 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: ca966f9a2df171848e57f4deac0dda6ce24cc938 Original-Change-Id: Iece5e12d5787415a335bb953985331a5dc312152 Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-on: https://review.coreboot.org/23211 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-on: https://chromium-review.googlesource.com/865528 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865528" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/28/865528/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ic59d57cd4a722daedec6cd64ba03253a6558db98" commit="dd7c5fecf68436e6fdf240dae9e41dcff2959872" commit_message="UPSTREAM: mb/google/poppy/variants/nautilus: enable digitizer pen device - Add pen device property into devicetree.cb. - Set GPP_C9 to 0 as default. BUG=none BRANCH=master TEST=emerge-nautilus coreboot and check pen device operation Change-Id: Ic59d57cd4a722daedec6cd64ba03253a6558db98 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 533ea7adb5d23d32c854f4a3bdbf9c31df7299b4 Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Original-Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f Original-Reviewed-on: https://review.coreboot.org/23010 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/865529 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865529" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/29/865529/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia9ec826672983a66a5aac9fc32a2bc1a1595c9db" commit="2b791ec160a683b56d6f41dee5abbc859d93fcbb" commit_message="UPSTREAM: amd/stoneyridge: Keep SPI flash cacheable during POST A side effect of using the common MTRR assignment code is the flash device loses its WP setting and is no longer cacheable. After MTRR setup, reenable the setting for the duration of POST. TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate() BUG=b:70536683 Change-Id: Ia9ec826672983a66a5aac9fc32a2bc1a1595c9db Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 0814b122281d2e4f10e40c2a8d5085f810e2730e Original-Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730 Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-on: https://review.coreboot.org/23205 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://chromium-review.googlesource.com/865530 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865530" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/30/865530/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I383f76dd41dab00a78b00d11c5109193a0e13888" commit="bb87b2ed2c9a95f4233eb98ba784dc405230795b" commit_message="UPSTREAM: soc/intel/common: Add Intel HDA common block driver There is common HDA code in soc/intel/common that provides generic HDA support functions, but it does not provide a driver. This change adds a common block driver for HDA that provides a ramstage driver for SOCs that need to initialize an HDA codec. This was tested on a board with an HDA codec to ensure that it properly detected it and ran the codec init steps. BUG=none BRANCH=none TEST=none Change-Id: I383f76dd41dab00a78b00d11c5109193a0e13888 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 93142a452e4c0cb35ea04394ded171b1cf58ff72 Original-Change-Id: I41b4c54d3c81e1f09810cfaf934ffacafca1cf38 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23187 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/865531 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865531" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/31/865531/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Icdecc14ce309f8911a0d5331a0a51ffee3ed1cdf" commit="ed458fba01a0af8bd4680f4b012e8ab14d14f5c0" commit_message="UPSTREAM: mb/intel/kblrvp: Use common HDA code Instead of duplicating code in each mainboard that supports HDA use the common driver and provide the HDA verb table. This was compile tested for both variants with "abuild -t intel/kblrvp" BUG=none BRANCH=none TEST=none Change-Id: Icdecc14ce309f8911a0d5331a0a51ffee3ed1cdf Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: a4b253a4b423c8eb85b47015a129d086415dece9 Original-Change-Id: Ie3bab7aabcfa040935062b7764853df8fb19b04d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23188 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/865532 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865532" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/32/865532/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I3b9e12f2c5d6997cf9902817fb9804a29abe352c" commit="a327e810e66379385ca247c91f7d703ca196966c" commit_message="UPSTREAM: mb/google/poppy: Remove digitizer reset control from ACPI Digitizer power is not controlled by SoC. Also, since the digitizer uses I2C-HID driver in Linux kernel, the device is put into sleep anytime system is suspended. Thus, there is no need to control the reset gpio using ACPI power resource. TEST=Verified that digitizer device is properly detected on boot-up and after suspend/resume. Change-Id: I3b9e12f2c5d6997cf9902817fb9804a29abe352c Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 3b543a2dfe1c3534da26f1c5855444eb86e0cfd0 Original-Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23212 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/865533 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="865533" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/33/865533/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I1c2704d92408797561b416dd3d996aae09aacd0b" commit="a365c2b8d38b36fb2f07897d669d01d7f46254cb" commit_message="UPSTREAM: mainboard/glkrvp: Add RECOVERY_CACHE This patch adds recovery cache. TEST:glkrvp boots with this change and also FAFT test firmware_CorruptRecoveryCache passes. BUG=none BRANCH=none TEST=none Change-Id: I1c2704d92408797561b416dd3d996aae09aacd0b Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: f9bd2c505268e514d951bb754df4663fc24c4296 Original-Change-Id: I9b32628d814693fb0591fc3750348d48cf9e26f1 Original-Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Original-Reviewed-on: https://review.coreboot.org/23067 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/866370 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866370" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/70/866370/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I3bf417e17e79d3f7e595c0cd2b2d42750cdf4457" commit="49de080f14ceb1951da8f6d72778b54719d612aa" commit_message="UPSTREAM: mainboard/glkrvp: Add EC_GOOGLE_CHROMEEC_SWITCHES This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we use the common switch.c file BUG=none BRANCH=none TEST=none Change-Id: I3bf417e17e79d3f7e595c0cd2b2d42750cdf4457 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: f40fd5b5087ee8ab43d94c8e51d042095d597276 Original-Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com> Original-Reviewed-on: https://review.coreboot.org/23131 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/866371 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866371" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/71/866371/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If162a9d5234636b93d6ebc3b04161c4ffa00ddc3" commit="d4aecd886e6724d53a38b90452ba79eaa8ac9c4c" commit_message="UPSTREAM: mb/google/fizz: Disable PCH Lan Fizz has external Lan on PCIE port. The Lan device on PCH is not used. BUG=b:70889517 Change-Id: If162a9d5234636b93d6ebc3b04161c4ffa00ddc3 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: e13a269f589b0ede64c24bb8cf7644a92d05792a Original-Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78 Original-Signed-off-by: Kane Chen <kane.chen@intel.com> Original-Reviewed-on: https://review.coreboot.org/23180 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/866372 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866372" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/72/866372/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I992881308192a4a0458f0c72bcad6b2ffa83da8d" commit="77b369f66c684d06fc8383fdae20da33b496ec9b" commit_message="UPSTREAM: mb/google/fizz: update DPTF settings TCPU: _CRT: 100 _PSV: 93 _TRT: 100/5(s) TSR0: _CRT: 83 _PSV: 70 _TRT: 100/10(s) TSR1: _CRT: 73 _PSV: 67 _TRT: 100/30(s) TCC: 6 for 94'C PL1: max: 15W min: 3W BUG=b:70294260 BRANCH=master TEST=build Change-Id: I992881308192a4a0458f0c72bcad6b2ffa83da8d Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 09f8a834b3a57bb35021c0f1705a2583135edb7e Original-Change-Id: Ie17f4395d2199009fd68a600d818f2be54bc8935 Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Original-Reviewed-on: https://review.coreboot.org/23155 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/866373 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866373" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/73/866373/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If80478c245413115ed7cfff97440b078696ded6b" commit="a3b2830d46a471c180e2c1ee4af097e04ee928c9" commit_message="UPSTREAM: ec/lenovo/h8: Add support for bluetooth on wifi The EC does enable bluetooth on wifi cards and BDC at the same time. Check the new Kconfig to support bluetooth on wifi in case no BDC is installed and the BDC detection fails. BUG=none BRANCH=none TEST=none Change-Id: If80478c245413115ed7cfff97440b078696ded6b Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 7c2a6f984a19cab6f2c51e5dce270562a8a27d47 Original-Change-Id: I23f14c937252a296dc543db49ec9e093e7e24604 Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-on: https://review.coreboot.org/21578 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/866374 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866374" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/74/866374/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If0865181e9e9f25bf7b1b2c456cebb75b896f92c" commit="44775bbc52d399f2b85f5073094b56fdfd6a1326" commit_message="UPSTREAM: soc/intel/skylake: Override KBL IccMax settings According to Intel document #559100 KBL EDS v2.8, section 7.2 DC specifications, the IccMax setting for KBL-U, KBL-U42 and Celeron/Pentium are different. This patch overrides the IccMax settings for KBL-U/R/Y since device tree could not handle all KBL-U/R combinations when multiple SKUs are adopted in a project. Besides, it is inefficient to maintain the same code for all variants. Hence, place it in the common code so that all variants could leverage the benefits. +----------------+-------------+---------------+------+-----+ | Domain/Setting | SA | IA | GTUS | GTS | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-U/R)| 6A(U42) | 64A(U42) | 31A | 31A | | | 4.5A(Others)| 29A(Celeron) | | | | | | 32A(i3/i5) | | | +----------------+-------------+---------------+------+-----+ | IccMax(KBL-Y) | 4.1A | 24A | 24A | 24A | +----------------+-------------+---------------+------+-----+ BUG=b:71369428 BRANCH=None TEST=Remove icc_max setting from devicetree & emerge-fizz coreboot chromeos-bootimage & Ensure the KBL-U42, KBL-U22 and Celeron SKUs are identified correctly and IccMax settings are passed to FSPS correctly. Change-Id: If0865181e9e9f25bf7b1b2c456cebb75b896f92c Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: e1a75d4a94e32f72a5e99410cdaafef0431cfc8f Original-Change-Id: I291462b73d3fbd17f17975de7fd77dc48ca99251 Original-Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Original-Reviewed-on: https://review.coreboot.org/23060 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/866375 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866375" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/75/866375/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I52ab0e4f2cde1cf3420ec78e0acf2f012e57b42b" commit="191772f669e1bf6a9ca07d88b85c7b3ab2ed7835" commit_message="UPSTREAM: soc/intel/common/block: Check for NULL before dereference We check for NULL from the return of function acpi_device_path before passing it to acpigen_write_scope to avoid NULL pointer dereference. BUG=none BRANCH=none TEST=none Change-Id: I52ab0e4f2cde1cf3420ec78e0acf2f012e57b42b Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5a44176047595120c42e9971b718d9f78110ef1b Original-Change-Id: I997461c9b639acc3c323263d304333d3a894267c Original-Found-by: Klockworks Original-Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Original-Reviewed-on: https://review.coreboot.org/23094 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/866376 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866376" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/76/866376/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I525a82286adf4c0daf18d34b8519f76716e427b8" commit="1457817068a0db00524bbd068dc4a65f4c360d69" commit_message="UPSTREAM: mb/google/poppy/variants/nami: Fix DA7219 IRQ issue Change PAD_CFG_GPI_GPIO_DRIVE to PAD_CFG_GPI_APIC for GPIO D9 to meet the requirement of DA7219 IRQ pin. BUG=b:70646770 BRANCH=none TEST=Use aplay and arecord to verify headphone function. Change-Id: I525a82286adf4c0daf18d34b8519f76716e427b8 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b15fe8e74edda7b21352d4df3c6186d7f59cc108 Original-Change-Id: Id6cff8325c4c7f02f6f4df547fde286e2ef83d5c Original-Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com> Original-Reviewed-on: https://review.coreboot.org/23160 Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/866377 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866377" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/77/866377/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I799b670f62cde64f83d0243f15c7b15c6476acbd" commit="9beea4ba004d60aa83cd9851baefac9ca9c4cebf" commit_message="UPSTREAM: mainboard/hp: Add Elitebook Revolve 810 G1 The code is based on autoport and that for 8470p. Tested: - CPU i5-3437U - Slotted DIMM 8GiB - Soldered RAM 4GiB from Hynix (There may be more models here) - Onboard USB2 interfaces (digitizer, wlan slot, wwan slot, camera) - Mini pci-e on wlan slot - On board SDHCI connected to pci-e - USB3 ports - USB3 hub on dock (connected to USB3 port 1) - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.13.13-1 within Debian GNU/Linux testing, loaded from SeaBIOS, or Linux payload (Heads) Not work: - An "NFC" device connected to LPC Not implemented yet: - Detecting the model of Soldered RAM at runtime, and loading the corresponding SPD datum (3 observed) from CBFS BUG=none BRANCH=none TEST=none Change-Id: I799b670f62cde64f83d0243f15c7b15c6476acbd Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: ee8da1c3ae873a21767d82c88539b34fd9eff10b Original-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Original-Signed-off-by: Bill XIE <persmule@gmail.com> Original-Reviewed-on: https://review.coreboot.org/22972 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/866378 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866378" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/78/866378/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Iff0d16a623d7ca2bf4569f06dd9ae106c60df27c" commit="9decf5b5db0fcad1b11d53be74b11f5a0840f907" commit_message="UPSTREAM: mb/compulab/intense_pc: enable SuperIO UART Enable the UART via SMSC SIO1007 SuperIO, this allows you to see boot boot messages from coreboot over the integrated RS-232 port (requires use of included dongle). BUG=none BRANCH=none TEST=none Change-Id: Iff0d16a623d7ca2bf4569f06dd9ae106c60df27c Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: aba468b329f68976c6ac5c4a04b3b78b224f07df Original-Change-Id: I11a4c532ed73a0cf27d6e7bef6e04035c3942567 Original-Signed-off-by: Hal Martin <hal.martin@gmail.com> Original-Reviewed-on: https://review.coreboot.org/22737 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/866379 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866379" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/79/866379/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7315e7b72755c0f33f14be9d019f1cb4992bff28" commit="ecdeeb480543dc4c4eaa9f8e897a1488f8796d86" commit_message="UPSTREAM: mb/compulab/intense_pc: Change devicetree to correct CPU socket Intense PC uses FCBGA1023 socket, not rPGA989. Correct the socket in the devicetree. BUG=none BRANCH=none TEST=none Change-Id: I7315e7b72755c0f33f14be9d019f1cb4992bff28 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 1291c44abd4d7dfa23789653895e0940f0af86ab Original-Change-Id: Ie657af2f51dfb7add90b19b26c0c37d312d59821 Original-Signed-off-by: Hal Martin <hal.martin@gmail.com> Original-Reviewed-on: https://review.coreboot.org/22762 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/866380 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866380" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/80/866380/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I03bf2b7dc1ff58e320bb00d6fc8b7b624455cbc5" commit="9d2be4c1009152501cf6ede839df36a2db30633c" commit_message="UPSTREAM: mainboard/google/zoombini/variants/meowth: set GPD_2 to NF1 Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must be set to use NF1 instead of gpio. BUG=b:64395641 BRANCH=none TEST=none Change-Id: I03bf2b7dc1ff58e320bb00d6fc8b7b624455cbc5 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: f46fca4befee792e1762709a0e94344602bb9277 Original-Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd Original-Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23222 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/866381 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866381" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/81/866381/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2ce165083aa823d199bd61f995dc8caab1d24b30" commit="85e168b62b622ff0e4bab140ad5df665052e4e24" commit_message="UPSTREAM: Revert "soc/amd/common/pi: Fix issue in AGESA heap allocator" This reverts commit 0f5651584ebb8e2ccfa151275bfd2f70e74bae9b. This is not the correct fix for the heap allocator. It looks like the root cause is in the buffer size of the deallocate function. BUG=none BRANCH=none TEST=none Change-Id: I2ce165083aa823d199bd61f995dc8caab1d24b30 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: a273753c729eeb2bde30ad8886649a5058430461 Original-Change-Id: I33c479a30d89a665677d3e4914194ae8136504af Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-on: https://review.coreboot.org/23245 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Chris Ching <chingcodes@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/866382 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866382" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/82/866382/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie42061ed67f5399ea2cadc161001024b9f4e31e5" commit="e865844de4d3e8c9f9b81e03551af1bbf2d101e6" commit_message="UPSTREAM: soc/amd/stonyridge: Give I2C devices unique _UIDs The ACPI unique identifier (_UID) should be unique. This doesn't actually matter much for Linux, though, since the kernel can handle it when the BIOS doesn't get this right. See: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID BUG=none BRANCH=none TEST=none Change-Id: Ie42061ed67f5399ea2cadc161001024b9f4e31e5 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: dc512f893f61e731504d6867f40de502acfd66ed Original-Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12 Original-Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23233 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-on: https://chromium-review.googlesource.com/866383 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866383" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/83/866383/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I27542229381015ba4fd6642f42bb58ba253c0ca5" commit="6c07ba98f3054ccdb11313bf51cc3f3382748edb" commit_message="UPSTREAM: google/kahlee/grunt: Move ASL to variants Move the apci/ to the baseboard and move mainboard.asl to each variant. BUG=b:71873651 TEST=build BRANCH=none Change-Id: I27542229381015ba4fd6642f42bb58ba253c0ca5 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 5fb261303886836f6a0fe06d54fe6a2b9af4f07b Original-Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028 Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Reviewed-on: https://review.coreboot.org/23229 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://chromium-review.googlesource.com/866384 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866384" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/84/866384/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia720b0d63d07af0b57944e7ecc607f8decc84fa0" commit="ec2954bd4a3995be6ce19abfd235169ba4fe5f76" commit_message="UPSTREAM: google/kahlee/grunt: Add Grunt audio codec ASL Grunt and Kahlee have different audio codecs. Create a new audio .asl for the baseboard for grunt's codec, link to it from the grunt mainboard, and move the kahlee codec table from the baseboard mainboard to its own .asl in variant/kahlee. Note, we can't use the generic drivers due to the PCI scope expectation. The AMD I2C are not PCI devices. BUG=b:69397774 TEST=Codec driver loads. Check dmesg. Change-Id: Ia720b0d63d07af0b57944e7ecc607f8decc84fa0 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b57799ed5efe9ca5c8c36c61576b9e54a0e1188a Original-Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb Original-Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Original-Signed-off-by: Marc Jones <marcj303@gmail.com> Original-Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23226 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/866385 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866385" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/85/866385/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia0f7951ec478f62e08bb3ae68ac409aad9b0b56e" commit="88c47dc24f1bb10519652be8b601ce206531484b" commit_message="UPSTREAM: google/kahlee/grunt: Add grunt touchpad ASL Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD, respectively. Since grunt is the 'baseboard', put its configuration under baseboard, and include it from the grunt variant. BUG=b:71820409 TEST=Boot grunt to kernel, use evtest to test trackpad. TEST=Boot kahlee to kernel, use evtest to test trackpad. Change-Id: Ia0f7951ec478f62e08bb3ae68ac409aad9b0b56e Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: c40d690b781fc1fb91f9c1029e6d9f6f039b6907 Original-Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57 Original-Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/866386 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866386" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/86/866386/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I6daef0b031f93dccef99f92ea7dd35d169cfd518" commit="dcb56a76b7513fa1157d0f8a2c6716011ef3558b" commit_message="UPSTREAM: mainboard/google/kahlee: Fix GPIO table The GPIOs that are being set low had the wrong value getting set. FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE. BUG=b:70234300 TEST=Build and boot Grunt Change-Id: I6daef0b031f93dccef99f92ea7dd35d169cfd518 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 883de54fed25aebe3e68418adc63e7d54b400f91 Original-Change-Id: I16792b76252506a43aac92738b04096ae3fde01c Original-Signed-off-by: Martin Roth <martinroth@google.com> Original-Reviewed-on: https://review.coreboot.org/23224 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://chromium-review.googlesource.com/866387 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866387" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/87/866387/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ief38ea2a8f572cc08af97c0a07ce21eee153b631" commit="b181c10d1b521d983358a4bc472defbe164ab9b7" commit_message="UPSTREAM: soc/amd/stoneyridge: Add definition for GENINT_DISABLE BUG=b:71867096 TEST=None Change-Id: Ief38ea2a8f572cc08af97c0a07ce21eee153b631 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 2572153aefbb8def000cddea973c34be5829c63d Original-Change-Id: Ic8111d34355e6667c37a51d285ebb50c1659f4e5 Original-Signed-off-by: Martin Roth <martinroth@google.com> Original-Reviewed-on: https://review.coreboot.org/23227 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/866388 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866388" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/88/866388/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ia934a6341481dfc7664393f3f475853b78a99901" commit="1219a0ee959def0ee3b955deca13cf7b5bbdab13" commit_message="UPSTREAM: mainboard/google/kahlee: Finish GPIO90 setup for Grunt GPIO 90 is being used as a GPIO. The IOMUX register is set correctly, but these additional registers need to be set to use it as a GPIO. - Split structures into variant specific versions. These will be moved into the variant tree in a follow-on patch - Set GENINT_DISABLE bit - Disable interrupts for this GPIO. BUG=b:71867096 TEST=Build and boot grunt. Verify registers are set correctly. Change-Id: Ia934a6341481dfc7664393f3f475853b78a99901 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: 6c14cd32ae71c89b286c6ea0aa07671eb94d03ee Original-Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0 Original-Signed-off-by: Martin Roth <martinroth@google.com> Original-Reviewed-on: https://review.coreboot.org/23228 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/866389 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Martin Roth <martinroth@chromium.org> " fail_count="0" gerrit_number="866389" owner_email="martinroth@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/89/866389/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I6c09888f1810a442d0d08ebfd371e2fb869e31ab" commit="159488fe371f4e2e073ef8eeecfd77c87961a496" commit_message="rmi4utils: update rmi4utils to set the correct mode on close BUG=b:68361897 TEST=verified successful firmware update on Lulu and partners verified on Hana CQ-DEPEND=CL:858302 Change-Id: I6c09888f1810a442d0d08ebfd371e2fb869e31ab Reviewed-on: https://chromium-review.googlesource.com/865436 Commit-Ready: Wuxy - <wuxy@bitland.corp-partner.google.com> Tested-by: Vineeth Starly <vineeths@google.com> Reviewed-by: Chirantan Ekbote <chirantan@chromium.org> " fail_count="1" gerrit_number="865436" owner_email="aduggan@synaptics.corp-partner.google.com" pass_count="0" patch_number="2" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/36/865436/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I80d08146367af0b91d8d9ac1495c85fe8edd0203" commit="e2cdba0448d6ff4a9d04cb31b6ae46aa7fa0360f" commit_message="grunt: Enable BMI160 gyro interrupts Setup bmi160_interrupt and enable in board_init. BUG=b:69379621 BRANCH=none TEST=none Change-Id: I80d08146367af0b91d8d9ac1495c85fe8edd0203 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/864827 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> " fail_count="1" gerrit_number="864827" owner_email="ecgh@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/27/864827/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ib9271d6cbe9befdf4ed492a9c2b676452e5f4d9b" commit="4c04b8451572e7a5c9360a2e4965b3b2f15044d3" commit_message="grunt: Fix ENABLE_BACKLIGHT to be active low BUG=b:71806495 BRANCH=none TEST=backlight turns on in S0 Change-Id: Ib9271d6cbe9befdf4ed492a9c2b676452e5f4d9b Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/865155 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> " fail_count="1" gerrit_number="865155" owner_email="ecgh@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/55/865155/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I5f1052257db4c581bcb700c7f0306f14f792ea03" commit="a7e35c98c1befe13dc54f24c546cb4dd7b604d1c" commit_message="wand: Enable CONFIG_CHARGE_RAMP_HW Enable ramping by default. Follow-up CL will have EC-EC master tell the slave if it's necessary to ramp. BRANCH=none BUG=b:71840796 TEST=lux fully charged, in S0ix, wand connected. Connect old BC1.2 charger, see that the charger is not browning out anymore. Change-Id: I5f1052257db4c581bcb700c7f0306f14f792ea03 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/863349 Reviewed-by: Shawn N <shawnn@chromium.org> " fail_count="1" gerrit_number="863349" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/49/863349/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ib819e4917b3acc337348764f6cc2aa7380bed700" commit="f9e54f96f2d1de213fb248df873afdb8aab340f5" commit_message="battery: Add support for reading base battery through host command This adds support for EC_CMD_BATTERY_GET_STATIC and EC_CMD_BATTERY_GET_DYNAMIC host commands, that can currently only fetch the base battery information using index = 1. In the future, all battery information can be passed to AP using these host commands (i.e. lid could provide its own battery information on index = 0). BRANCH=none BUG=b:65697620 TEST=ectool battery shows lid battery information (no change) TEST=ectool battery 1 shows base battery information Change-Id: Ib819e4917b3acc337348764f6cc2aa7380bed700 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/863863 Reviewed-by: Randall Spangler <rspangler@chromium.org> " fail_count="1" gerrit_number="863863" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/63/863863/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ic0e2a8245c0193e9ea249c7764b31ea9948b9457" commit="ad2b552ee6b84fbd3e46f848892168051af5c762" commit_message="libpasswordprovider: Change shared lib export macros to from brillo to libpasswordprovider. BUG=chromium:386606 TEST=Built chromeos-login, ran unit tests Change-Id: Ic0e2a8245c0193e9ea249c7764b31ea9948b9457 Reviewed-on: https://chromium-review.googlesource.com/860731 Commit-Ready: May Lippert <maybelle@chromium.org> Tested-by: May Lippert <maybelle@chromium.org> Reviewed-by: Dan Erat <derat@chromium.org> " fail_count="0" gerrit_number="860731" owner_email="maybelle@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/31/860731/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I9b03ba8a8ceb6fd3f498b61f016f88a3c918bfce" commit="933e240722b37c30d037466c0ccba0dd0635d0f8" commit_message="parseelf: Do not ignore empty symbol_name This reverts commit d1884d81c8ab196493cadf6f36f5d09d481a9452. We added this workaround as some incorrectly formed binary blobs appeared to import empty string symbols, but this should not happen. Since then, the binary blobs have been fixed, so we should probably throw errors on empty strings again. BUG=chromium:668568 BUG=chromium:788925 TEST=sudo /mnt/host/source/chromite/bin/test_image --board edgar \ chromiumos_base_image_R65-10302.0.0.bin Change-Id: I9b03ba8a8ceb6fd3f498b61f016f88a3c918bfce Reviewed-on: https://chromium-review.googlesource.com/866130 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="866130" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="1" project="chromiumos/chromite" project_url="https://chromium-review.googlesource.com/chromiumos/chromite" ref="refs/changes/30/866130/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I976f78756e7fdbe8dd0b836e91ad4e90aa394aee" commit="b00c3fd4b2970eec45b998b235bc1bc867b453ec" commit_message="Remove out-of-date comment for old verity input The verity command evidently does not take a reserved "0" argument since switching to the key/value command-line style. BUG=None TEST=None, just a comment change Change-Id: I976f78756e7fdbe8dd0b836e91ad4e90aa394aee Reviewed-on: https://chromium-review.googlesource.com/866253 Commit-Ready: Nicholas Bishop <nbishop@neverware.com> Tested-by: Nicholas Bishop <nbishop@neverware.com> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="866253" owner_email="nbishop@neverware.com" pass_count="0" patch_number="1" project="chromiumos/platform/crosutils" project_url="https://chromium-review.googlesource.com/chromiumos/platform/crosutils" ref="refs/changes/53/866253/1" remote="cros" total_fail_count="0"/><lkgm version="10308.0.0-rc5"/></manifest> |
