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| <pending_commit branch="chromeos-2016.05" change_id="I596fd6f4a58b43ff3fd80e669f34f65e1ccad28e" commit="a57ae4b7582943bfdb6addb0871e422494752075" commit_message="UPSTREAM: soc/amd/stoneyridge: Add API to initialize non-early_init i2c buses Provide a method for initializing i2c buses that are not marked as early_init in the device tree. These i2c buses can be enabled in a mainboard's ramstage, for example. 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Change-Id: I4ef631ef4cd3d5b0fb892a34deb772e6b647593f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 25874b86c311a836e93ab505ee552d154a441f23 Original-Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23512 Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/906445 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906445" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/45/906445/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I6ab445c5c5c9e83bc12045ea5686a233c8084720" commit="94430c0c8be96cddb4414c05c161fa7f4bde8191" commit_message="UPSTREAM: mb/asus/m2v-mx_se: Add `cmos.default` Add `cmos.default` to get rid of four seconds in romstage. Choose 8 MB for size for video RAM. Order the entries like in `cmos.layout`. BUG=none BRANCH=none TEST=none Change-Id: I6ab445c5c5c9e83bc12045ea5686a233c8084720 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 75f5d9991deba9c73e021a93800915ee8c042ab9 Original-Change-Id: If2dcc266f6f061807401b62647124ce96e9a3802 Original-Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Original-Reviewed-on: https://review.coreboot.org/23468 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://chromium-review.googlesource.com/906446 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906446" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/46/906446/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ic175913a9e65a901591e03b8d1e30f605fd37b85" commit="63204819f0fd28c9c0eec311d0e3ae7cb2f5ae6f" commit_message="UPSTREAM: mainboard/broadcom/blast: Remove unnecessary braces {} Fix coding style BUG=none BRANCH=none TEST=none Change-Id: Ic175913a9e65a901591e03b8d1e30f605fd37b85 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9cf7a469b6a7ce878fb3c0f78b79c7dcea071308 Original-Change-Id: I1b6913f9fe97e42836a6698645d0d380ceecec0d Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/23523 Original-Reviewed-by: Martin Roth <martinroth@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/906447 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906447" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/47/906447/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I5063681d4efd222c84694df67429accfce89efab" commit="65ff1dff68d5a3a9b7bd9166b82c3d14bf08fbc1" commit_message="UPSTREAM: soc/intel/cannonlake: Increase heap size After adding NHLT and max98373 amp support, cnlrvp fails to boot with error: out of memory (free_mem_ptr >= free_mem_end_ptr). Increase HEAP_SIZE from 0x4000 to 0x8000. BUG=None TEST= emerge-cnlrvp coreboot nhlt-blobs chromeos-bootimage coreboot-private-files-cnlrvp and verify cnlrvp boots to kernel. Change-Id: I5063681d4efd222c84694df67429accfce89efab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 7492bcbb5a33fdcd7b1ed733acc6968a218bbf28 Original-Change-Id: Icb0f3c626b784d73e417e5722b3b4da29ab5acce Original-Signed-off-by: John Zhao <john.zhao@intel.com> Original-Reviewed-on: https://review.coreboot.org/23560 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/906448 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906448" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/48/906448/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7d7f02fd2ca0bfde6f3479b93370cafb9d1ac3fc" commit="7b7697f7c9221c894f9d448b5400a1e38c6766fd" commit_message="UPSTREAM: mb/google/kahlee: Remove cmos.layout CMOS layout is not used and can be removed. A change to Kconfig is needed in order not to break the build. BUG=b:64207749 TEST=Build kahlee. Change-Id: I7d7f02fd2ca0bfde6f3479b93370cafb9d1ac3fc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 7b6a32f5c4e71e712e03a0de1bcb3ec11d62ad72 Original-Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3 Original-Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Original-Reviewed-on: https://review.coreboot.org/23596 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/906449 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906449" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/49/906449/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I0c0cf322f6baebb3025f1cbec7e3aba50aa68a4f" commit="6f4da96a42df4ef1dc9900b1fbe8b4ef11b80fee" commit_message="UPSTREAM: soc/amd/stoneyridge/acpi/sleepstates.asl: Fix guarded code Remove #if statement and replace it with if(IS_ENABLED(...)) per coreboot recommendations. BUG=b:62200858 TEST=Build kahlee. Change-Id: I0c0cf322f6baebb3025f1cbec7e3aba50aa68a4f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ddb4dcab8a6e08364d30b671dbd60c5c9ce71db7 Original-Change-Id: I268b228706a625e1415c4f24e808261c279ba41e Original-Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Original-Reviewed-on: https://review.coreboot.org/23575 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/906450 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906450" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/50/906450/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id343ad57946acf35c525ba302a2068abf1827edc" commit="13778852b6a6f5d9db91130750d80994b349ca89" commit_message="UPSTREAM: nvramtool: Fix message when option table is not found Having an option table pertains to CONFIG_USE_OPTION_TABLE. BUG=none BRANCH=none TEST=none Change-Id: Id343ad57946acf35c525ba302a2068abf1827edc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 179a9048ddd1f45aa80865eb07a793394c6152e5 Original-Change-Id: Ia8a84e3e59ee50444c7f7d17b34bea86ee475909 Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/23410 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/906451 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906451" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/51/906451/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ib8b3ec239318099c0e4b2662a80527ae2c1ee344" commit="366ce9652167afd4d34ca180ecfee872edc99826" commit_message="UPSTREAM: cpu/intel/haswell: Don't select PARALLEL_CPU_INIT PARALLEL_CPU_INIT pertains to initialize_cpus() in src/cpu/x86/lapic/lapic_cpu_init.c which haswell does not use as it uses PARALLEL_MP init. BUG=none BRANCH=none TEST=none Change-Id: Ib8b3ec239318099c0e4b2662a80527ae2c1ee344 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4004081e08af79238ef69fe8b6a9930419c26b39 Original-Change-Id: I46b6f72e8e372b8c8564243ece7aed3a9371c621 Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/23409 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/906452 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906452" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/52/906452/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I82caf5af22c8ba5599d645485bf7f19de0b19a25" commit="7c38ebde2355cb3521dc83eee9dea56f7376994e" commit_message="UPSTREAM: soc/intel/appololake: Remove dead MPINIT code selection This not hooked up anywhere. BUG=none BRANCH=none TEST=none Change-Id: I82caf5af22c8ba5599d645485bf7f19de0b19a25 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f9d9781292aab5ea6c4a5058aca895b575e279a7 Original-Change-Id: I95a2d14aea6f1a6013edf1bcb88bb35de88cba4f Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/23458 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/906453 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906453" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/53/906453/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ied98f1ee8c95ea8dc6210dc8f02ea7c5a1f36d45" commit="9e6a9aa314a78781737a9f7e1c996d5ecebfaec2" commit_message="UPSTREAM: mb/google/kahlee: Fix grunt I2C rise/fall times I2C bus rise/fall times were measured as follows. Signals were generated with: - bus 0: manual i2c driver in depthcharge - bus 2,3: i2cdetect -r <bus_number> and then measured manually with an oscilloscope. BUG=b:72442912 Change-Id: Ied98f1ee8c95ea8dc6210dc8f02ea7c5a1f36d45 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ad282592b450c6309abe829f3c4e0d2b0111fb31 Original-Change-Id: I291e144249271ec34a93417398e54e68b8e21e23 Original-Signed-off-by: Justin TerAvest <teravest@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23520 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/906454 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906454" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/54/906454/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I69c7b60655b9369c70a8c0f1bd9a5a81d8d105d5" commit="4678398470c20ca315d3088e857ecfe3418c7410" commit_message="UPSTREAM: inteltool: Fix displaying 64bit spi registers The registers were taken from the wrong addess since the spibar offset was not added to it. This also fixes the endianness. BUG=none BRANCH=none TEST=none Change-Id: I69c7b60655b9369c70a8c0f1bd9a5a81d8d105d5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 921fa84f9e6802b28dd42cb905c396d033e64836 Original-Change-Id: I8bb91517770359599fe5f579c4686434da8d1c27 Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/23478 Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/906455 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906455" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/55/906455/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2810e6bddb6a8ffd7316b6d3e165e1ad0d33f7ed" commit="ca2d6d9c1ce9b2b0690cdb680f38e53ccb19b93d" commit_message="UPSTREAM: inteltool: Add Cougar- and Pantherpoint PCH PCI IDs for SPI Tested to display the register content correctly on a Lenovo Thinkpad X220. BUG=none BRANCH=none TEST=none Change-Id: I2810e6bddb6a8ffd7316b6d3e165e1ad0d33f7ed Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 485c0ad0783aa168feab8944e498a393774512fd Original-Change-Id: I8b65302ed52d4ef1a31bf0cdd9208b368eb7ad67 Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/23479 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/906456 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906456" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/56/906456/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I548850c6f2f008dd42c3e1110f0e961d4a7cbf83" commit="88ad4233cd76d914d9542dfe8a2e5e6575a95b48" commit_message="UPSTREAM: nb/intel/haswell: Use the common MRC cache driver This driver uses an fmap region for the MRC cache instead of a CBFS file which makes it easier to manage if one wants to write protect it. BUG=none BRANCH=none TEST=none Change-Id: I548850c6f2f008dd42c3e1110f0e961d4a7cbf83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f300f362103306775dab4fd994ca5e9fd59b96e4 Original-Change-Id: Iaa6b9f87c752088d70882fd05cb792e61a091391 Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/23464 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/906457 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906457" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/57/906457/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I62dde53a0960b551288f56eff5a95c3636a4c8b4" commit="664ab979ecbf7dfb229004fad7497a96591d428d" commit_message="UPSTREAM: util/broadcom/secimage: Add HMAC test One of responsibilities of the `secimage` tool is signing the image using the HMAC-SHA256 algorithm. The test being added verifies that secimage's internal call yields same result as the according openssl tool does. BUG=none BRANCH=none TEST=none Change-Id: I62dde53a0960b551288f56eff5a95c3636a4c8b4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 457d1c8fa2c47a17c76e7d32b418ac49661bdbe8 Original-Change-Id: I8de4328f435af56901a861e3d5e733657c3c7f78 Original-Signed-off-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com> Original-Reviewed-on: https://review.coreboot.org/23474 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/906458 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906458" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/58/906458/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id228bb562bb998e6a113c2db8f5cddc3343b675d" commit="2a4fb7428e8aebe3fb81ec8eeb96b90cffd73a85" commit_message="UPSTREAM: soc/intel/skylake: sort CPU_SPECIFIC_OPTIONS and drop duplicate ACPI_NHLT happens to be selected twice. BRANCH=none BUG=none TEST=generated fizz .config does not change Change-Id: Id228bb562bb998e6a113c2db8f5cddc3343b675d Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5542bb653115ecd0cad9928c7e2b9065bb7a35c2 Original-Change-Id: Ic525ee07015deb88fff4c15cad9dbbeada8a4479 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23601 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/906459 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906459" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/59/906459/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Iee55fe722a06ec78ff8b6020174ace4d4e9cdacd" commit="3b42ec282115cad96116a64977e3fa3aba72c960" commit_message="UPSTREAM: google/gru: Add another 512KB to the COREBOOT FMAP region With the new extra detachable UI elements, we're running out of space in Scarlet's RO CBFS. Thankfully, the GBB is still massively overdimensioned, so we can steal another half MB from there. This patch changes the FMAP for some boards that have already had production firmware releases. However, all the new changes are to the RO parts of the FMAP, so there shouldn't be a way this could cause a problem for updates. BUG=none BRANCH=none TEST=none Change-Id: Iee55fe722a06ec78ff8b6020174ace4d4e9cdacd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 3f7411e198a35f63cac575223c80668b37c4ac25 Original-Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23595 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/906460 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906460" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/60/906460/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9caa7270caff2a5c1df666560bdfd24fcdade7be" commit="0ca04f528eb541a5c85cd7e775ccc3ef195e4d3e" commit_message="UPSTREAM: nb/intel/sandybridge: Always use the same MMCONF_BASE_ADDRESS 'Optimizing' MMCONF_BASE_ADDRESS for the native codepath prevents the use of fallback/normal with both the native raminit and the mrc.bin. Using the same MMCONF_BASE_ADDRESS as the mrc.bin codepath means that 128MB less is available to devices using the native raminit. Most devices reserve 2048M for non memory resources below 4G, which in most cases is more than adequate. Devices with only 1024M (and that don't already use the mrc.bin) are: * lenovo/x220 * lenovo/x230 * lenovo/x131e * lenovo/x1_carbon_gen1 Those could fail to allocate PCI resources, but on at least x220 with a somewhat default configuration (USB3 expresscard, Wireless PCIe card) it still boots fine, so one should not expect many problems from this change. BUG=none BRANCH=none TEST=none Change-Id: I9caa7270caff2a5c1df666560bdfd24fcdade7be Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 742a0e911ca1682a06856731c69479aaf9c77ab4 Original-Change-Id: I1d0648fe36c88bd9279ac19e5c710055327599fd Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Reviewed-on: https://review.coreboot.org/23490 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/906461 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906461" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/61/906461/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ie52f10e21688362497c761afd184050333a84dea" commit="e4efe3eefb2a5a6e1a061b9cfcefe6be740a98c3" commit_message="UPSTREAM: soc/intel/skylake: Add Kabylake PCH H device ID's Add PCH,MCH,IGD,I2C,PMC,SMBUS,XCHI and UART IDs for PCH H. BUG=none BRANCH=none TEST=none Change-Id: Ie52f10e21688362497c761afd184050333a84dea Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: acc2a4819c44b2f111eed64f329ae54db7ff9489 Original-Change-Id: I52b38457bc727735ceb5003cbccda6d7ba3340a2 Original-Signed-off-by: V Sowmya <v.sowmya@intel.com> Original-Reviewed-on: https://review.coreboot.org/23382 Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/906462 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906462" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/62/906462/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="If01d5777ae5624075f24e7c38a2d43fde448101e" commit="b1733be1676ecda1e77b728701cd3d0690c7ef5e" commit_message="UPSTREAM: intel/common/block/cpu: Change post_cpus_init after BS_DEV RESOURCES This patch changes the sequence of post_cpus_init() function of mp_init to very last of the stages, i.e., ON_EXIT of BS_WRITE_TABLES for normal boot path, and to ON_ENTRY of BS_OS_RESUME for S3 Resume path. Also, the fast_spi_cache_bios_region() call inside post_cpus_init() function is left out, since caching the SPI Bios region is not required now at this stage. BUG=none BRANCH=none TEST=Build and boot in Soraka (KBL), executed stability tests on multiple systems. Change-Id: If01d5777ae5624075f24e7c38a2d43fde448101e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f43adf0b894e916f0403761ecb9147d7061b0619 Original-Change-Id: I97c4a4096a3529a21bae6f2cf5aac654523a5b22 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Reviewed-on: https://review.coreboot.org/23540 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/906463 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906463" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/63/906463/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I06e2acb34cfb0e68291abef535365109dad436e5" commit="5f52128d901a78ff9d6a4edcc348a2e735a7b3a1" commit_message="UPSTREAM: storage: Fix CMD13 failure issue This patch stores the correct capabilities for EMMC media which in turn sets the correct timing data for HS400 mode. Without this code change, EMMC CMD13 is failing at the end of HS400 mode switching. BUG=none BRANCH=none TEST=Build and boot Soraka Change-Id: I06e2acb34cfb0e68291abef535365109dad436e5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e9628402820b88543443529fae87106f74689aa7 Original-Change-Id: I3f00c9eace7cc136d86a1e07f040fbfc09e0e02e Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/23541 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/906464 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906464" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/64/906464/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I526caa79b8c712710e6e02533b6e5e27c5f911e8" commit="9457dbce7cfbada1819071c12dd32e2b98a33c48" commit_message="UPSTREAM: mb/google/poppy/variants/nami: Change WiFi wake pin to GPP_E22 This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to match the latest schematic changes). Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is removed from deep_sx_config as well. BUG=b:72697650 TEST=Verified: 1. Wake-on-wifi works. 2. Device is able to enter G3 without WAKE# pin causing unwanted wakes from deep S5. Change-Id: I526caa79b8c712710e6e02533b6e5e27c5f911e8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9076b7bd077810cb219ef2a58e999fad2b3e0b93 Original-Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org> Original-Reviewed-on: https://review.coreboot.org/23594 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/906465 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906465" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/65/906465/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ifbc7170583bbe7a51b94df3983e09f71b11c2320" commit="801982625a741536beb8b05a83009867b0764896" commit_message="UPSTREAM: soc/intel/common/block: Fix SATA chipset register definitions anomalies SATA PCH configuration space registers bit mapping is different for various SOCs hence common API between SPT-PCH and CNL-PCH causing issue. Add new Kconfig option to address this delta between different PCH. BUG=none BRANCH=none TEST=none Change-Id: Ifbc7170583bbe7a51b94df3983e09f71b11c2320 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 828c39eb6ba4aa72ffb027a0fc70d8ec78a83d24 Original-Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/23589 Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/906466 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906466" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/66/906466/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ib39a77baf4a00162719a4ec7204099184becfa86" commit="15c30221c4b0aa4e9f302208d416260a583a6d15" commit_message="UPSTREAM: soc/intel/cannonlake: Select SOC_AHCI_PORT_IMPLEMENTED_INVERT Kconfig for CNP-PCH This patch ensures soc/sata.c correctly translates pci config offset 0x92 Bit 0-2 [SATA Port x Present (SPDx)] 0 = Port x is enabled. 1 = Port x is disabled. BUG=none BRANCH=none TEST=none Change-Id: Ib39a77baf4a00162719a4ec7204099184becfa86 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ac1cd44525d7230a0138fdd3e442ad8b1363c4dc Original-Change-Id: Ide093dafe33b947ba7845cc0b74a975471353e39 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/23591 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/906467 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="906467" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/67/906467/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="If376ee35088c19dd86fbc6b8673d1cbce1fbf940" commit="d96b0bd7e4f337bded0b775be28d42aae93bf107" commit_message="vboot/screens: Remove logo liftup spacing The Chrome logo looks a little too high above the divider line for my tastes right now, especially compared to the language descriptor to the right of it. The logo image already has some white padding on the bottom in the image itself, which looks like more than enough on its own. Remove the extra padding. BRANCH=None BUG=b:65479973 TEST=Booted Scarlet, was more aesthetically pleased. Change-Id: If376ee35088c19dd86fbc6b8673d1cbce1fbf940 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/903241 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> " fail_count="0" gerrit_number="903241" owner_email="jwerner@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/depthcharge" project_url="https://chromium-review.googlesource.com/chromiumos/platform/depthcharge" ref="refs/changes/41/903241/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I187bcf3c5cf30cfae030f0709e95c6cc17e31a6e" commit="904f22b4293a6fa24f43ae0b6373e966710430ce" commit_message="vboot/screens: Remove REMOVE and BASE screens The REMOVE screen hasn't been used in years. The BASE screen has apparently never been used to start with. Remove both. BRANCH=None BUG=None TEST=None Change-Id: I187bcf3c5cf30cfae030f0709e95c6cc17e31a6e Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/903362 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> " fail_count="0" gerrit_number="903362" owner_email="jwerner@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/depthcharge" project_url="https://chromium-review.googlesource.com/chromiumos/platform/depthcharge" ref="refs/changes/62/903362/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I82308fc76dc10b2c8b408af7a15a819120043632" commit="b3abbc6ae9d7f0655361bb516c32992def7380db" commit_message="vboot_api: Remove unused VB_SCREEN constants Some of the defined screens have never been used or we've stopped using them a while ago. Remove the respective constants to make it clearer that callers of the library are not expected to handle them. CQ-DEPEND=CL:903362 BRANCH=None BUG=None TEST=make runtests Change-Id: I82308fc76dc10b2c8b408af7a15a819120043632 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/902899 Reviewed-by: Randall Spangler <rspangler@chromium.org> " fail_count="0" gerrit_number="902899" owner_email="jwerner@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/vboot_reference" project_url="https://chromium-review.googlesource.com/chromiumos/platform/vboot_reference" ref="refs/changes/99/902899/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I3c087e8f378c5cef0006f6bfe58335228a880e5b" commit="28ed4e10b120037dbddf33bea8485507b0ccefc4" commit_message="charge_state_v2: Store battery information in new structures On dual battery systems, this allows to keep both batteries information in similar structures. This also means that battery information can only be fetched via host commands EC_CMD_BATTERY_GET_STATIC/DYNAMIC (next CL will make it possible to fetch the information via shared memory/ACPI). BRANCH=none BUG=b:65697620 TEST=Boot lux/wand, dual-battery algorithm works, AP can fetch both battery information via host commands. Change-Id: I3c087e8f378c5cef0006f6bfe58335228a880e5b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/888381 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="888381" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="6" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/81/888381/6" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ife008370218f0d9eb0f96088ec144b0aba40716f" commit="1d274f49c57d93bac7a3bee1f9fe9453264ac02f" commit_message="charge_state_v2: Separate update_base_battery_info Indentation in charger_task is getting out of control, let's move the logic to a new function. BRANCH=none BUG=b:71881017 TEST=Flash lux and wand, battery algorithm works as expected. Change-Id: Ife008370218f0d9eb0f96088ec144b0aba40716f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/901442 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> " fail_count="0" gerrit_number="901442" owner_email="drinkcat@chromium.org" pass_count="0" patch_number="3" project="chromiumos/platform/ec" project_url="https://chromium-review.googlesource.com/chromiumos/platform/ec" ref="refs/changes/42/901442/3" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Idee3b45d985b88ddca44d5e23c4de0b38efca74a" commit="564168a9d81fa95b14b710839db9f350e6f5c5ae" commit_message="cryptohome: Use delegate to get endorsement key for locked TPM After the TPM gets locked, and the password is deleted, the endorsement key is removed from attestation data. This change gives the right to delegate to get the endorsement key. BUG=chromium:793326 TEST=cryptohome --action=get_enrollment_id Change-Id: Idee3b45d985b88ddca44d5e23c4de0b38efca74a Reviewed-on: https://chromium-review.googlesource.com/887024 Commit-Ready: Igor <igorcov@chromium.org> Tested-by: Igor <igorcov@chromium.org> Reviewed-by: Igor <igorcov@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> " fail_count="0" gerrit_number="887024" owner_email="igorcov@chromium.org" pass_count="0" patch_number="10" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/24/887024/10" remote="cros" total_fail_count="0"/><pending_commit branch="master-0.3.13" change_id="I48b1818fa911413e28f4c4f14cc0308fe2a8067b" commit="c005c1290732ae5d16a190b1bd3410a20bdc55f8" commit_message="Expose the FieldUpgrade command. Fill in gaps in FieldUpgrade handling to allow client code to issue FieldUpgrade commands via the tcsd socket. Note that this only supports unauthenticated FieldUpgrade commands, which is sufficient for the IFX FieldUpgradInfoRequest2 use case that motivates this change. BUG=chromium:780817 TEST=Manual: tpm-manager get_ifx_field_upgrade_info Change-Id: I48b1818fa911413e28f4c4f14cc0308fe2a8067b Reviewed-on: https://chromium-review.googlesource.com/822338 Commit-Ready: Mattias Nissler <mnissler@chromium.org> Tested-by: Mattias Nissler <mnissler@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> " fail_count="1" gerrit_number="822338" owner_email="mnissler@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/trousers" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/trousers" ref="refs/changes/38/822338/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I902024525fc7dd97986509a005e2aafd7859387b" commit="535beab0734a8cbebb5f0a7a5313e8abb755d173" commit_message="cros-workon: Introduce CROS_WORKON_SUBTREE. CROS_WORKON_SUBTREE allows to declare subtrees in source checkouts needed to build the package. It will also be used in cros_mark_as_stable to avoid unnecessary uprevs. CQ-DEPEND=CL:807598 BUG=chromium:791888 TEST=precq Change-Id: I902024525fc7dd97986509a005e2aafd7859387b Reviewed-on: https://chromium-review.googlesource.com/807599 Commit-Ready: Shuhei Takahashi <nya@chromium.org> Tested-by: Shuhei Takahashi <nya@chromium.org> Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="1" gerrit_number="807599" owner_email="nya@chromium.org" pass_count="0" patch_number="15" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/99/807599/15" remote="cros" total_fail_count="2"/><pending_commit branch="master" change_id="I188a3322644c27413ffc517ba44d5b78fdfc4c20" commit="b3ab295d6f246aa211ca690b6df27cb97cfed28d" commit_message="intel: ipu3: use V4L2_META_FMT_IPU3_STAT_3A in statistics frame worker Configure the node with V4L2_META_FMT_IPU3_STAT_3A format in the statistics frame worker. BUG=b/62358788 TEST=Make sure camera works on Poppy Change-Id: I188a3322644c27413ffc517ba44d5b78fdfc4c20 Reviewed-on: https://chromium-review.googlesource.com/897023 Commit-Ready: WeiX Meng <weix.meng@intel.com> Tested-by: WeiX Meng <weix.meng@intel.com> Reviewed-by: Ricky Liang <jcliang@chromium.org> Reviewed-by: Liang L Yang <liang.l.yang@intel.com> " fail_count="1" gerrit_number="897023" owner_email="hywu@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform/arc-camera" project_url="https://chromium-review.googlesource.com/chromiumos/platform/arc-camera" ref="refs/changes/23/897023/1" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I0de23e4421b6fd5983392667db0df9cb9b9ccbc4" commit="c2403c85d5cf7d611f3024a47b75358e79342a6c" commit_message="hammerd: fix hammerd_api GetSectionVersion. Originally when we passed the section version to hammerd_api, we returned a copied string, which is freed after exiting the function. This CL fixed this bug by storing the value in a static variable. BUG=b:72668384 TEST=FEATURES=test emerge-poppy hammerd hammerd-test-utils TEST=Run hammer_info.py at device and check ro_version is correct Change-Id: I0de23e4421b6fd5983392667db0df9cb9b9ccbc4 Reviewed-on: https://chromium-review.googlesource.com/903304 Commit-Ready: Chih-Yu Huang <akahuang@chromium.org> Tested-by: Chih-Yu Huang <akahuang@chromium.org> Reviewed-by: Joel Kitching <kitching@chromium.org> " fail_count="0" gerrit_number="903304" owner_email="akahuang@chromium.org" pass_count="0" patch_number="4" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/04/903304/4" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I9e8211e63952f02e746f812b84a27a0cccb9693b" commit="d843763bcbe9143468553d0b1f1b04e288fab20c" commit_message="hwid/database: Make `Database` object friendly to `pickle`. This CL removes nested classes defined in `database.py` so that python `pickle` module can load and dump a `Database` object. BUG=None TEST=make test; manually test Change-Id: I9e8211e63952f02e746f812b84a27a0cccb9693b Reviewed-on: https://chromium-review.googlesource.com/903343 Commit-Ready: Yong Hong <yhong@google.com> Tested-by: Yong Hong <yhong@google.com> Reviewed-by: Yilun Lin <yllin@chromium.org> " fail_count="1" gerrit_number="903343" owner_email="yhong@google.com" pass_count="0" patch_number="5" project="chromiumos/platform/factory" project_url="https://chromium-review.googlesource.com/chromiumos/platform/factory" ref="refs/changes/43/903343/5" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I14d2b2c32e14ff0c2c714a55ce62ab9ab9721ca3" commit="278c5c03b047b93133fffb1075fb37088f582202" commit_message="test_lists: Add SyncFactoryServer into default station tests Add SyncFactoryServer test into the default station-based test lists. This makes it possible to have a management over all the toolkit version running on the test stations. And allowing the tests to communicate with factory server. It's also an easy task if one need to use another Umpire instance: just overriding the factory_server setting in the constant section. Reviewed current test lists inherit from station-based test list, they should all working well with this change. BUG=b:72620477 TEST=make BOARD=meowth toolkit Change-Id: I14d2b2c32e14ff0c2c714a55ce62ab9ab9721ca3 Reviewed-on: https://chromium-review.googlesource.com/903602 Commit-Ready: Shen-En Shih <petershih@chromium.org> Tested-by: Shen-En Shih <petershih@chromium.org> Reviewed-by: Wei-Han Chen <stimim@chromium.org> " fail_count="0" gerrit_number="903602" owner_email="petershih@chromium.org" pass_count="0" patch_number="3" project="chromiumos/platform/factory" project_url="https://chromium-review.googlesource.com/chromiumos/platform/factory" ref="refs/changes/02/903602/3" remote="cros" total_fail_count="1"/><pending_commit branch="chromeos-2016.05" change_id="I48d8bb4f9fc0e5276e6ec81247b3b6768ec9fa3b" commit="d331191599fd1fb4a2fdfb36f5bdeaa25af19205" commit_message="UPSTREAM: security/vboot: overwrite existing spaces during factory init for tpm2 In TPM 2.0 case, if the factory initialization is interrupted after defining, say, the kernel tpm nvram space but before writing to this space, the following will happen upon reboot when the factory initialization will be re-attempted. Writing to this space will be skipped, and coreboot will finish the factory initialization with this space remained unwritten. At a later stage, when the rollback logic will attempt to check the version in the kernel space, it will fail (TPM2.0 returns an error when reading from unwritten spaces), and the system will go into recovery with no way out (since the kernel space will never be written). This change fixes that by always writing to the kernel, MRC hash and firmware spaces during factory initialization, even if the space already existed by that time. BRANCH=none BUG=b:71884828 TEST=delete, define, but not write to the kernel space; trigger factory initialization; coreboot should fill the kernel space and continue booting. Change-Id: I48d8bb4f9fc0e5276e6ec81247b3b6768ec9fa3b Signed-off-by: Andrey Pronin <apronin@google.com> Reviewed-on: https://review.coreboot.org/23456 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit 278a5064b4a8e7c0a5742872a9d5b4464e22da00) Reviewed-on: https://chromium-review.googlesource.com/905817 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="0" gerrit_number="905817" owner_email="apronin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/17/905817/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I7c30876b63576fdcf9180f8dbb4d4d8730ddf477" commit="918fa8c263954e41e8c3cbc1ed7af65cf2e94489" commit_message="arc-camera3-hal-intel-ipu3: Add libcamera_common dependency BUG=b:68923633 TEST=emerge-${BOARD} arc-camera3-hal-intel-ipu3 Change-Id: I7c30876b63576fdcf9180f8dbb4d4d8730ddf477 Reviewed-on: https://chromium-review.googlesource.com/802608 Commit-Ready: Heng-ruey Hsu <henryhsu@chromium.org> Tested-by: Heng-ruey Hsu <henryhsu@chromium.org> Reviewed-by: Heng-ruey Hsu <henryhsu@chromium.org> " fail_count="0" gerrit_number="802608" owner_email="henryhsu@chromium.org" pass_count="0" patch_number="2" project="chromiumos/overlays/board-overlays" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/board-overlays" ref="refs/changes/08/802608/2" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I4438379252114540797d86a844b44bc1e6a27a38" commit="3e8fa2d84e1c533dc8629d70afca28566be73542" commit_message="utils: Fix bug in DHCPManager When there are multiple ethernet ports waiting to be bound to DHCP server, the DHCP manager simply failed to start. This is because the exclude ip list should contains the number of netmask bits (e.g., 24), rather than a string like 255.255.255.0. BUG=b:72979581 TEST=Connect multiple ethernets to station, and start goofy with a station-based test list Change-Id: I4438379252114540797d86a844b44bc1e6a27a38 Reviewed-on: https://chromium-review.googlesource.com/903606 Commit-Ready: Shen-En Shih <petershih@chromium.org> Tested-by: Shen-En Shih <petershih@chromium.org> Reviewed-by: Pi-Hsun Shih <pihsun@chromium.org> " fail_count="0" gerrit_number="903606" owner_email="petershih@chromium.org" pass_count="0" patch_number="2" project="chromiumos/platform/factory" project_url="https://chromium-review.googlesource.com/chromiumos/platform/factory" ref="refs/changes/06/903606/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I9bb71c8d09f8cbb9919ddefcd7e7891cc71f3a13" commit="c83f79eb62e64be3671abec4196bc92a86d0cf40" commit_message="chromeos-config: Fix broken unittest for whitelabel. The whitelabel tag format has been changed and the models populated in chromeos-config should prefix reference model name. BUG=chromium:808583 TEST=FEATURES=test sudo -E emerge chromeos-config-host Change-Id: I9bb71c8d09f8cbb9919ddefcd7e7891cc71f3a13 Reviewed-on: https://chromium-review.googlesource.com/905242 Commit-Ready: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: C Shapiro <shapiroc@google.com> " fail_count="0" gerrit_number="905242" owner_email="hungte@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/42/905242/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="If8e39dde42e632afdf9f171c1cbca9707c15417c" commit="dc0bc3521b0fe45ccb0306531736bdcd9900049d" commit_message="layout.conf: Make sure all overlays have eclass-overlay Some overlays seem to be missing eclass-overlay. BUG=chromium:796216 TEST=git grep 'masters .*portage-stable' | grep -v eclass-overlay Change-Id: If8e39dde42e632afdf9f171c1cbca9707c15417c Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/906168 Reviewed-by: Mike Frysinger <vapier@chromium.org> " fail_count="0" gerrit_number="906168" owner_email="jeffy.chen@rock-chips.com" pass_count="0" patch_number="1" project="chromiumos/overlays/board-overlays" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/board-overlays" ref="refs/changes/68/906168/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I8381c43d8ede2e797504f752ac46d464599be608" commit="cdfc8dc545581767fb7433c7ca0aa945b4cdbe02" commit_message="intel: ipu3: Remove code unreachable Remove unnecessary checks that some codes are unreachable BUG=b:62358788 TEST=Build and deploy package to poppy and camera works Change-Id: I8381c43d8ede2e797504f752ac46d464599be608 Signed-off-by: fangya2x <fangx.yang@intel.com> Reviewed-on: https://chromium-review.googlesource.com/905800 Commit-Ready: WeiX Meng <weix.meng@intel.com> Tested-by: WeiX Meng <weix.meng@intel.com> Reviewed-by: Ricky Liang <jcliang@chromium.org> " fail_count="0" gerrit_number="905800" owner_email="weix.meng@intel.com" pass_count="0" patch_number="1" project="chromiumos/platform/arc-camera" project_url="https://chromium-review.googlesource.com/chromiumos/platform/arc-camera" ref="refs/changes/00/905800/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="If241b6fe8fa60ca5c6ba4a066c15b513243c436e" commit="3898fa73f2983bdd49da32bea6e12a1eac415c32" commit_message="infineon-firmware-updater: Add test cases. This adds test cases covering various scenarios to make sure tpm-firmware-updater works as expected. This will be helpful to speed up validation of future changes. The tests are run in the test step of the ebuild. BUG=None TEST=New tests pass :) Change-Id: If241b6fe8fa60ca5c6ba4a066c15b513243c436e Reviewed-on: https://chromium-review.googlesource.com/854839 Commit-Ready: Mattias Nissler <mnissler@chromium.org> Tested-by: Mattias Nissler <mnissler@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> " fail_count="1" gerrit_number="854839" owner_email="mnissler@chromium.org" pass_count="0" patch_number="6" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/39/854839/6" remote="cros" total_fail_count="1"/><lkgm version="10383.0.0-rc1"/></manifest> |
