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<pending_commit branch="chromeos-2016.05" change_id="I7c681f44305a2aeeafc58922729513e970af0abb" commit="ea84ea850b34949f56e523ccc2d37df513242e5e" commit_message="UPSTREAM: mb/ocp/wedge100s: Remove MAINBOARD_USES_IFD_GBE_REGION It has 2x 10GbE XGMII and 1x i210IT on PCIe, but no GBE. BUG=none BRANCH=none TEST=none Change-Id: I7c681f44305a2aeeafc58922729513e970af0abb Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: c47d43a8af5dfdbdb7afebb39f999f18f36c9d23 Original-Change-Id: I641c336350a0b05f3db7603cc7f6281ff3b0c388 Original-Signed-off-by: Patrick Rudolph &lt;patrick.rudolph@9elements.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31198 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Philipp Deppenwiese &lt;zaolin.daisuki@gmail.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1454377 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454377" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/77/1454377/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I230f1aaa6cd532ca0c2bb6579c67d30e7398af3e" commit="bd0254e4ff74a536bfda823eb02d2e3f5ec2e556" commit_message="UPSTREAM: riscv: Simplify payload handling 1. Simplify payload code and convert it to C 2. Save the FDT pointer to HLS (hart-local storage). 3. Don't use mscratch to pass FDT pointer as it is used for exception handling. BUG=none BRANCH=none TEST=none Change-Id: I230f1aaa6cd532ca0c2bb6579c67d30e7398af3e Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 820dcfceb3901dbb00bb90c876e374126ca14e20 Original-Change-Id: I32bf2a99e07a65358a7f19b899259f0816eb45e8 Original-Signed-off-by: Xiang Wang &lt;wxjstz@126.com&gt; Original-Signed-off-by: Philipp Hug &lt;philipp@hug.cx&gt; Original-Reviewed-on: https://review.coreboot.org/c/31179 Original-Reviewed-by: ron minnich &lt;rminnich@gmail.com&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1454378 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454378" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/78/1454378/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I21caaa404385c43e1df5db2c5e6632e3f88372e0" commit="5140f1b85e433b8ae438aced5cf68d746288d3bb" commit_message="UPSTREAM: riscv: Show hart id in trap handler Also show hart id in trap information for easier debugging. BUG=none BRANCH=none TEST=none Change-Id: I21caaa404385c43e1df5db2c5e6632e3f88372e0 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 909be6a7d8ea87e23e4098a97c23e3263a80057d Original-Change-Id: I20acf86e1af111600c158295ae03b2167838d127 Original-Signed-off-by: Philipp Hug &lt;philipp@hug.cx&gt; Original-Reviewed-on: https://review.coreboot.org/c/31201 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: ron minnich &lt;rminnich@gmail.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1454379 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454379" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/79/1454379/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I3d4195773f549f4a7d5a8e7b93e0d4698d9bfa0d" commit="29fa3a4ee961a03246c68dc11c82261a10452c95" commit_message="UPSTREAM: usbdebug: Fix reserve in CAR We need sizeof(struct ehci_dbg_info) of 88 but only reserved 64 bytes. If usbdebug_hw_init() was called late in romstage, for some builds it would corrupt CAR_GLOBALs like console_inited variable and stop logging anything. Also change pointer initialisation such that glob_dbg_info will hit garbage collection for PRE_RAM stages. BUG=none BRANCH=none TEST=none Change-Id: I3d4195773f549f4a7d5a8e7b93e0d4698d9bfa0d Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: f88208e0acbcb771fdbf5ef851eb6aec12ccc188 Original-Change-Id: Ib49fca781e55619179aa8888e2d859560e050876 Original-Signed-off-by: Kysti Mlkki &lt;kyosti.malkki@gmail.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31174 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt; Original-Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt; Reviewed-on: https://chromium-review.googlesource.com/1454380 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454380" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/80/1454380/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2e6edb816568c34164396728e866ee3322963925" commit="248cdfd24418fffc51a69e8fdecb62bd70647523" commit_message="UPSTREAM: usbdebug: Use fixed size field The structure is placed inside CBMEM, one should use types with fixed size. Seems we prefer to prepare for 64-bit builds even for MMIO pointers. BUG=none BRANCH=none TEST=none Change-Id: I2e6edb816568c34164396728e866ee3322963925 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 45ad4f041bcf69f7988d87ae390977c10203b1a8 Original-Change-Id: I60382664a53650b225abc1f77c87ed4e121d429e Original-Signed-off-by: Kysti Mlkki &lt;kyosti.malkki@gmail.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31182 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt; Reviewed-on: https://chromium-review.googlesource.com/1454381 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454381" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/81/1454381/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I3cb4f2ea2a4b223e2b5c29af71be0a7d90ec4c72" commit="9336af82df1e5dfbe5dd41474edf26451b653d28" commit_message="UPSTREAM: soc/intel/cannonlake: Remove SOC_INTEL_CANNONLAKE_MEMCFG_INIT Kconfig This patch removes duplicate selects of same SOC_INTEL_CANNONLAKE_MEMCFG_INIT from various CFL/WHL SoC based boards to include cnl_memcfg_init.c file and include the cnl_memcfg_init.c file by default in CNL SoC Makefile.inc. BUG=none BRANCH=none TEST=none Change-Id: I3cb4f2ea2a4b223e2b5c29af71be0a7d90ec4c72 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: cff6a1df3bacb9cd336c01c4ca5fe33ecd61dc80 Original-Change-Id: Ib21ea305871dc859e7db0720c18a9479100346c3 Original-Signed-off-by: Subrata Banik &lt;subrata.banik@intel.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31134 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1454382 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454382" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/82/1454382/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9dff6431a603ec4c3db8481242d5be839446e8dc" commit="7ae1db8cc10eae357b3fac68823c94fd8a447c84" commit_message="UPSTREAM: superio/winbond/w83627ehg: Correct CR 0x2a comment Register 0x2a [Bit 1] is a PIN89, PIN90 function select for i2c BUG=none BRANCH=none TEST=none Change-Id: I9dff6431a603ec4c3db8481242d5be839446e8dc Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 2b2325ef87ce57a1e53ad4bfc757854a36cf638e Original-Change-Id: I9231a68ec7e9a3130a6b6975544bf89ab09cb3e6 Original-Signed-off-by: Elyes HAOUAS &lt;ehaouas@noos.fr&gt; Original-Reviewed-on: https://review.coreboot.org/c/31185 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Felix Held &lt;felix-coreboot@felixheld.de&gt; Reviewed-on: https://chromium-review.googlesource.com/1454383 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454383" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/83/1454383/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id053546d75c1878c62ed77d3731127fca73db26b" commit="b0d0138894605b7f80848582253d0b5df5965d4c" commit_message="UPSTREAM: sb/amd/agesa/hudson/Kconfig: Disable xHCI by default if no USE_BLOBS Disable xHCI by default if USE_BLOBS option has not been selected. BUG=none BRANCH=none TEST=none Change-Id: Id053546d75c1878c62ed77d3731127fca73db26b Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 5b230027991cab928dfaee39c2b47daf4d89f5a6 Original-Signed-off-by: Mike Banon &lt;mikebdp2@gmail.com&gt; Original-Change-Id: I1c3f0ff49fbe3db3ef095d99055f75d65cd6f661 Original-Reviewed-on: https://review.coreboot.org/c/31216 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt; Reviewed-on: https://chromium-review.googlesource.com/1454384 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454384" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/84/1454384/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I8aebd7da7ade4f75f08382f04d1f8de16b7308ee" commit="384fe46dc40f1d5d687df636dc34bae29e0a8415" commit_message="UPSTREAM: ec/google/wilco: Add S0ix support handlers 1) In the EC _REG method set the flag indicating S0ix support in the OS. 2) Add a function that can be called by the LPI _DSM method to indicate to the EC that the OS is entering or exiting S0ix. BUG=b:73137291 Change-Id: I8aebd7da7ade4f75f08382f04d1f8de16b7308ee Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 286a0ab143722a53f359e78e6df195b65105f87b Original-Change-Id: Iddc33a08542a6657694c47a9fda1b02dd39d89f7 Original-Signed-off-by: Duncan Laurie &lt;dlaurie@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31094 Original-Reviewed-by: Lijian Zhao &lt;lijian.zhao@intel.com&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-by: Shaunak Saha &lt;shaunak.saha@intel.corp-partner.google.com&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1454385 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454385" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/85/1454385/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I37c0bcd8cabc82c1f5b2032a8e5c752ff4e7b025" commit="5e268973534cdf30dddd244d36c993471767da00" commit_message="UPSTREAM: ec/google/wilco: Add ACPI device for event interface Add a separate ACPI device for the Wilco EC event interface so that the OS drivers can bind to it separately. Since the event handling is all done with ACPI and not mailbox calls this will be implemented as a standard acpi_driver in the kernel. BUG=b:119046283 TEST=veriy device exists in DSDT Change-Id: I37c0bcd8cabc82c1f5b2032a8e5c752ff4e7b025 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: aaac678e800dd9a6c0b2ca63d3cebfb3005628f8 Original-Change-Id: I5259a926fb6d5faea835bcdefa12f0184c5adf4a Original-Signed-off-by: Duncan Laurie &lt;dlaurie@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31204 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1454386 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454386" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/86/1454386/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9256e23668df64b9e772de77d9e25e1bed209554" commit="a92bfd22150a75e09b41b6f2c9b9ded1076e48c2" commit_message="UPSTREAM: soc/amd/stoneyridge: Reboot if missing MRC cache info AGESA doesn't detect invalid NV data during AmdInitResume(). In cases where the data has been erased, or cannot be found, reboot the system. Otherwise the user will experience a hang when cbmem isn't recovered and the postcar frame cannot be initialized. BUG=b:122725586 TEST=Write S3 NV save data with 0xff and force reboot Change-Id: I9256e23668df64b9e772de77d9e25e1bed209554 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: f56249ba0b1cf4bf83d93f3d717d3eb8a0624ff2 Original-Change-Id: Ib3cf2515f300decd3de198f7741660d95ee4c744 Original-Signed-off-by: Marshall Dawson &lt;marshalldawson3rd@gmail.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31160 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Martin Roth &lt;martinroth@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1454387 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454387" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/87/1454387/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2bc00616eafe6b1d9519c94cad69e3fe02365719" commit="10209e8cb3086d94b1666201cf871a36d49c6f3e" commit_message="UPSTREAM: mb/google/hatch: Add USB port capability ACPI support for USB2 port10 This implementation adds support to create ACPI package for USB port capability (_UPC) and physical location of device (_PLD) for USB2 port 10. BUG:b:123375275 TEST:Verify _UPC and _PLD ACPI packages gets published for USB2 Port 10 in SSDT and BT is functional in discrete and integrated mode. BUG=none BRANCH=none TEST=none Change-Id: I2bc00616eafe6b1d9519c94cad69e3fe02365719 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: fc63b8bbc0d2f16bc2693c23c50db531382b6ade Original-Change-Id: Ifeab24505a700e8e4677be20074c7d0400769cec Original-Signed-off-by: Aamir Bohra &lt;aamir.bohra@intel.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31197 Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-by: Paul Menzel &lt;paulepanter@users.sourceforge.net&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1454388 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454388" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/88/1454388/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Id87ff45fed61fadbe745cd6bd179015bd305372b" commit="8d23d4b5fc51895c4cc0c36cab2c1af84bba4e77" commit_message="UPSTREAM: soc/intel/apollolake: Update XHCI ports for GLK in ACPI tables GLK has a dedicated USB2 port that is used specifically for CNVi BT. This requires that the ACPI tables define an additional USB 2 port which results in _ADR for USB 3 ports being different for GLK than APL. This change splits the ports in xhci.asl into APL and GLK specific ports.asl and selects the appropriate file based on CONFIG_SOC_INTEL_GLK. It also adds support for returning HS09 for GLK if ACPI name is requested for that port. BUG=b:123670712 BRANCH=octopus TEST=Verified that generated DSDT for octopus (GLK) includes HS09 and for reef (APL) does not include HS09 definition. Change-Id: Id87ff45fed61fadbe745cd6bd179015bd305372b Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: ad62b9af651eddf78fd6db37a32f99f429019324 Original-Change-Id: I2d3d3690ec9ea1f6e35c38c3b3cbb82e961b7950 Original-Signed-off-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31172 Original-Reviewed-by: Karthik Ramasubramanian &lt;kramasub@google.com&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1454389 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454389" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/89/1454389/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7eed8275467a997a39fa728b5663abec8bd32922" commit="e7667c2fdb0966692fba6efc469f542c51d61069" commit_message="UPSTREAM: mb/google/octopus: Add USB ACPI configuration for CNVi BT module This change enables exporting the reset GPIO for CNVi Bluetooth module to the kernel for use in an rf-kill operation. BUG=b:123296264 BRANCH=octopus TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured that the kernel btusb driver is able to find the exported GPIO in the devices with CNVi BT module. Change-Id: I7eed8275467a997a39fa728b5663abec8bd32922 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 8a64b6fbdbbf32dafe84ff8d8c74a3a79f1ae169 Original-Change-Id: I10f28bfe705da5104d709ae2ed91a8ae003fa639 Original-Signed-off-by: Karthikeyan Ramasubramanian &lt;kramasub@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31183 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1454390 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454390" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/90/1454390/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I960023af493813c110ecc0e6365d4df860d0284d" commit="d2d0c4cfb0da77518c344396ff65088ffc910cc7" commit_message="UPSTREAM: intel/apollolake: Add parameter to enable VTD in devicetree The FSP has a parameter to enable or disable the VTD feature (Intel's Virtualization Technology for Directed I/O). In current header files for FSP-S (Apollo Lake and Gemini Lake) this parameter is set to disabled per default. Therefore, if the FSP was not modified via BCT, this feature is most likely disabled on all mainboards. Add a chip parameter so that VTD can be enabled on mainboard level in devicetree and therefore this feature can be activated if needed. BUG=none BRANCH=none TEST=none Change-Id: I960023af493813c110ecc0e6365d4df860d0284d Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 279afdc24b3c65275cad222be53b908bb0f752ef Original-Change-Id: Ic0bfcf1719e1ccc678a932bf3d38c6dbce3556bc Original-Signed-off-by: Werner Zeh &lt;werner.zeh@siemens.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31194 Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-by: Nico Huber &lt;nico.h@gmx.de&gt; Original-Reviewed-by: Paul Menzel &lt;paulepanter@users.sourceforge.net&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1454391 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454391" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/91/1454391/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I8b0694a66526314d8de1b8969f8cb51fd5e18b55" commit="ed8e8716551171fb2fc1128daddece562da54bf9" commit_message="UPSTREAM: mb/siemens/mc_apl1: Enable VTD for mc_apl2 and mc_apl5 These boards need a working VTD therefore enable this feature. BUG=none BRANCH=none TEST=none Change-Id: I8b0694a66526314d8de1b8969f8cb51fd5e18b55 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: d7e5f4b7c50eacf033154e2514a6bef3db80d4b5 Original-Change-Id: I74c64bf1bd66188c4c32b85c66683dafd0e1fd38 Original-Signed-off-by: Werner Zeh &lt;werner.zeh@siemens.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31195 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Mario Scheithauer &lt;mario.scheithauer@siemens.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1454392 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1454392" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/92/1454392/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I459336e07d880ca5edda190f3a28d21dbd2320f6" commit="6bd49e902c98934b4ed4f4554601f6bf162de7b7" commit_message="cryptohome: Create GCache and GCache/v2 for ephemeral cryptohomes. Cros-disks data dir preparation for DriveFS mounting relies on &lt;cryptohome&gt;/GCache/v2 being accessible and writeable. This is the case for regular cryptohomes, but not for ephemeral cryptohomes. This causes cros-disks to fail to mount DriveFS when ephemeral mode is enabled. Create GCache and GCache/v2 for ephemeral cryptohomes as well so DriveFS can be mounted in ephemeral mode. BUG=chromium:928233 TEST=unit tests, manual Change-Id: I459336e07d880ca5edda190f3a28d21dbd2320f6 Reviewed-on: https://chromium-review.googlesource.com/1452216 Commit-Ready: Sam McNally &lt;sammc@chromium.org&gt; Tested-by: Sam McNally &lt;sammc@chromium.org&gt; Reviewed-by: Sergei Datsenko &lt;dats@chromium.org&gt; " fail_count="1" gerrit_number="1452216" owner_email="sammc@chromium.org" pass_count="0" patch_number="4" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/16/1452216/4" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="I306beec1ec45fa2551f2bfb36a15c0ea53d81db8" commit="c8da726a48e2bd471fd8b83221603cfb3e2b4131" commit_message="lxd: patches for export and import progress Patches originall submited to head, but modified here to work against 3.0.2. BUG=chromium:927550 TEST=local device Change-Id: I306beec1ec45fa2551f2bfb36a15c0ea53d81db8 Reviewed-on: https://chromium-review.googlesource.com/1452399 Commit-Ready: Joel Hockey &lt;joelhockey@chromium.org&gt; Tested-by: Joel Hockey &lt;joelhockey@chromium.org&gt; Reviewed-by: Joel Hockey &lt;joelhockey@chromium.org&gt; " fail_count="1" gerrit_number="1452399" owner_email="joelhockey@chromium.org" pass_count="0" patch_number="2" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/99/1452399/2" remote="cros" total_fail_count="1"/><pending_commit branch="master" change_id="Ie2c485d1b4879c1755ff194ec67e4d81c9258e06" commit="3f7b5c957c7e927bd5e3af855fd7b1071a9d3728" commit_message="cryptohome: Remove obsolete variable No functional change. BUG=None TEST=ran unittests Change-Id: Ie2c485d1b4879c1755ff194ec67e4d81c9258e06 Reviewed-on: https://chromium-review.googlesource.com/1451931 Commit-Ready: Thiemo Nagel &lt;tnagel@chromium.org&gt; Tested-by: Thiemo Nagel &lt;tnagel@chromium.org&gt; Reviewed-by: Andrey Pronin &lt;apronin@chromium.org&gt; " fail_count="0" gerrit_number="1451931" owner_email="tnagel@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/31/1451931/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I048507aa5213f80bc8dd1a6fc4dd93734be65524" commit="2c5d3bf13cee3e15ca2ce29da3d447098bb7e22d" commit_message="Add user and group for Kerberos daemon Adds a user and group for a new system daemon for managing Kerberos tickets. It will eventually allow all Chrome OS users to use Kerberos SSO, e.g. for SMB file shares. See bug and dependend bug for more information. See also CL:1446412 and CL:1446095. BUG=chromium:926945 TEST=Emerges Change-Id: I048507aa5213f80bc8dd1a6fc4dd93734be65524 Reviewed-on: https://chromium-review.googlesource.com/1446511 Commit-Ready: Lutz Justen &lt;ljusten@chromium.org&gt; Tested-by: Lutz Justen &lt;ljusten@chromium.org&gt; Reviewed-by: Chirantan Ekbote &lt;chirantan@chromium.org&gt; " fail_count="0" gerrit_number="1446511" owner_email="ljusten@chromium.org" pass_count="0" patch_number="3" project="chromiumos/overlays/eclass-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/eclass-overlay" ref="refs/changes/11/1446511/3" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I0253aec8fe17496df724e238581974ae8d12da2e" commit="16f8f0d92c6958f5619ae113df7fd42d8b77b2ae" commit_message="authpolicy: Set forwardable and proxiable flags It makes clients request corresponding tickets. (see https://tools.ietf.org/html/rfc4120#section-2.5) BUG=chromium:928267 TEST=manual Change-Id: I0253aec8fe17496df724e238581974ae8d12da2e Reviewed-on: https://chromium-review.googlesource.com/1451928 Commit-Ready: Roman Sorokin [CET] &lt;rsorokin@chromium.org&gt; Tested-by: Roman Sorokin [CET] &lt;rsorokin@chromium.org&gt; Reviewed-by: Lutz Justen &lt;ljusten@chromium.org&gt; " fail_count="0" gerrit_number="1451928" owner_email="rsorokin@chromium.org" pass_count="0" patch_number="1" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/28/1451928/1" remote="cros" total_fail_count="0"/><lkgm version="11705.0.0-rc7"/></manifest>