blob: bfb170ca1437e08135334e63c3beec3ca8e3c5d8 [file] [log] [blame]
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<pending_commit branch="chromeos-2016.05" change_id="Icb5b922583a005652a666ed4c2087fcd9af9601a" commit="35c9977c3c296d6269338d729d7136453551cbf7" commit_message="UPSTREAM: mb/google/reef: Expand the coreboot RO section Current coreboot size is not adequate for adding new features. Note for cros: This change is for merge to ToT only and should not be cherry-picked into reef's firmware branch. BUG=chromium:903833 TEST=emerge-reef coreboot Change-Id: Icb5b922583a005652a666ed4c2087fcd9af9601a Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 946fa5f9418f0bff49c1dc90492c08e79f47a81f Original-Change-Id: Ie7a25c4638c474e81fb34b57de0dfc1bf393ea67 Original-Signed-off-by: Mathew King &lt;mathewk@chromium.org&gt; Original-Reviewed-on: https://review.coreboot.org/c/31230 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460836 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460836" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/36/1460836/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I27f50336b6bea537040763ea3c5de8886043faba" commit="614f49b19bd723242ebbf879f3bfbc6d0b8bca52" commit_message="UPSTREAM: mb/google/hatch: Configure I2C buses This change enables I2C bus 2, 3 and 4 in devicetree and configures GPIO pads for the same. It also configures pads for I2C5 as no-connect. BUG=b:123711244 TEST=Verified that i2c shows up in &quot;i2cdetect -l&quot; after booting to OS. Change-Id: I27f50336b6bea537040763ea3c5de8886043faba Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: eaf83489f619ec974943c53b006f17042e3b7b9e Original-Change-Id: Ib4714a670d73228332115415e4393f82802c6475 Original-Signed-off-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31237 Original-Reviewed-by: Aaron Durbin &lt;adurbin@chromium.org&gt; Original-Reviewed-by: Sumeet R Pawnikar &lt;sumeet.r.pawnikar@intel.com&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460837 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460837" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/37/1460837/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I462dd0760a9a07665123c24cbf50d4d0b7560d0b" commit="fc589a96080e6cc1ddb498c057e4b79e96aaa1eb" commit_message="UPSTREAM: Makefile.inc: Optimize generating the default x86 fmap Put the FMAP FMAP region right above the coreboot CBFS region. The other regions like RW_MRC_CACHE and CONSOLE often have alignment requirements so it makes sense to put those on top. This also simplifies the code the generate the default fmap a little. BUG=none BRANCH=none TEST=none Change-Id: I462dd0760a9a07665123c24cbf50d4d0b7560d0b Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 0b75679cbb9302e16ff4cb2266879cfb5476a4a2 Original-Change-Id: I24fa6c89ecf85fb9002c0357f14aa970ee51b1df Original-Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt; Original-Reviewed-on: https://review.coreboot.org/c/30419 Original-Reviewed-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460838 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460838" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/38/1460838/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I64dd074e6691f0c0a74d22d676ea6d3affda0a27" commit="833980c3a2d2361a918db52722849d40b262113a" commit_message="UPSTREAM: Makefile.inc: Make sure the BIOS region is 64K aligned If a non aligned CONFIG_CBFS_SIZE is used the region RW_MRC_CACHE and CONSOLE could end up non aligned. Currently this is only possible if the user messes with CONFIG_CBFS_SIZE in menuconfig, but better be safe than sorry. BUG=none BRANCH=none TEST=none Change-Id: I64dd074e6691f0c0a74d22d676ea6d3affda0a27 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: d37c2c231831d84f738fed22ca973a85622ae4d8 Original-Change-Id: Ieb7e3c7112bd4b3f9733c36af21b1d59b3836811 Original-Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt; Original-Reviewed-on: https://review.coreboot.org/c/30420 Original-Reviewed-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460839 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460839" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/39/1460839/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I2f2867e447cdeb92fe77e1aaa6e960ae911fea63" commit="8a7f5a4900fc586537e528fdcc0071d18e3c0119" commit_message="UPSTREAM: Makefile.inc: Create a default SMMSTORE region BUG=none BRANCH=none TEST=none Change-Id: I2f2867e447cdeb92fe77e1aaa6e960ae911fea63 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 12431d6eef53454907711dcd1545a0540ba57bbe Original-Change-Id: I7b7b75050e0139ea9a0a4f2ad3c0d69a482fb38b Original-Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt; Original-Reviewed-on: https://review.coreboot.org/c/30421 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460840 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460840" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/40/1460840/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I54312a7a8c9154e0260ba66d770f54077136093e" commit="8e666e2094b4b14898f308dd63ec138927d98475" commit_message="UPSTREAM: soc/intel/cannonlake: Add Whiskeylake SoC kconfig This patch performs below tasks 1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig. 2. Allow required SoC to select this kconfig to extend CANNONLAKE SoC support and add incremental changes. 3. Select correct SoC support for hatch, sarien, cflrvps and whlrvp. * Hatch is WHL SoC based board * Sarien is WHL SoC based board * CFLRVP U/8/11 are CFL SoC based board * WHLRVP is based on WHL SoC 4. Add correct FSP blobs path for WHL SoC based designs. BUG=none BRANCH=none TEST=none Change-Id: I54312a7a8c9154e0260ba66d770f54077136093e Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 6527b1acc7a020e1f0594a7ea30daed0978dd5fd Original-Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3 Original-Signed-off-by: Subrata Banik &lt;subrata.banik@intel.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31133 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Aamir Bohra &lt;aamir.bohra@intel.com&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460841 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460841" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/41/1460841/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ief6817572db74e0811ee0b1f233f35e4036ff157" commit="3b959e913073b6223b5b98a7aa6e8290b22abb7e" commit_message="UPSTREAM: soc/intel/cannonlake: Configure GPIOs again after FSP-S is done FSP-S is currently configuring GPIOs that it should not. This results in issues where mainboard devices don't behave as expected e.g. host unable to receive TPM interrupts as the pad for the interrupt is re-configured as something else. Until FSP-S is fixed, this change adds a workaround by reconfiguring GPIOs after FSP-S is run. All mainboards need to call cnl_configure_pads instead of gpio_configure_pads so that SoC code can maintain a reference to the GPIO table and use that to re-configure GPIOs after FSP-S is run. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: Ief6817572db74e0811ee0b1f233f35e4036ff157 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 86d2afb86b5c76fe8da719ce7746609eb1109ff0 Original-Change-Id: I7787aa8f185f633627bcedc7f23504bf4a5250b4 Original-Signed-off-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31250 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Duncan Laurie &lt;dlaurie@chromium.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460842 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460842" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/42/1460842/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I325d39b5cfdcf0c868e2f5476cc56c243d2424fd" commit="0347e48002db4cb1d18e3e8facfaa01b621f7d1d" commit_message="UPSTREAM: mb/google/{hatch,sarien}: Configure GPIOs using cnl_configure_pads This change uses cnl_configure_pads to configure GPIOs in ramstage so that cannonlake SoC code can re-configure the GPIOs after FSP-S is run. This is just adding a workaround until FSP-S is fixed. BUG=b:123721147 BRANCH=None TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch. Change-Id: I325d39b5cfdcf0c868e2f5476cc56c243d2424fd Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: a08765d2871b891c8da2e8686a0db35b320c96b0 Original-Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18 Original-Signed-off-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31251 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Duncan Laurie &lt;dlaurie@chromium.org&gt; Original-Reviewed-by: Aaron Durbin &lt;adurbin@chromium.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460843 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460843" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/43/1460843/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I4198a9d2f5dc4da5e60711db29e47546ec55c4dc" commit="d5d1c789e9092fcfa32fa4e258448db11559c101" commit_message="UPSTREAM: src: Remove unused include device/pnp_def.h BUG=none BRANCH=none TEST=none Change-Id: I4198a9d2f5dc4da5e60711db29e47546ec55c4dc Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 0c152cf1bbc3673d80f255fcc102d5784e0974c1 Original-Change-Id: Ibb7ce42588510dc5ffb04c950c4c8c64e9a2fa37 Original-Signed-off-by: Elyes HAOUAS &lt;ehaouas@noos.fr&gt; Original-Reviewed-on: https://review.coreboot.org/c/31238 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Micha ygowski &lt;michal.zygowski@3mdeb.com&gt; Original-Reviewed-by: Paul Menzel &lt;paulepanter@users.sourceforge.net&gt; Original-Reviewed-by: Felix Held &lt;felix-coreboot@felixheld.de&gt; Reviewed-on: https://chromium-review.googlesource.com/1460844 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460844" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/44/1460844/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I9841f79213c04789f7072490be65d3161f9800e7" commit="ca776d8de877f5f4c1e4a9ffaa877bd91a647e2a" commit_message="UPSTREAM: Documentation: Mention PC Engines as ships-with-coreboot hardware BUG=none BRANCH=none TEST=none Change-Id: I9841f79213c04789f7072490be65d3161f9800e7 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 2aaf169cbe91eb429a5944216474d26e844edf4f Original-Change-Id: I9d57abcff9c2472cc58b7fbca00441cd38a7f1a1 Original-Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31259 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Paul Menzel &lt;paulepanter@users.sourceforge.net&gt; Original-Reviewed-by: Piotr Krl &lt;piotr.krol@3mdeb.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460845 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460845" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/45/1460845/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Ib0cf169669aedf57779a252d88012b08938d1b03" commit="1b41cd1f1d4cf156809b6b4acab4b6151d526864" commit_message="UPSTREAM: drivers/keyboard: Fix spelling of *interface* `git grep iterface` shows that these are the only two occurrences. BUG=none BRANCH=none TEST=none Change-Id: Ib0cf169669aedf57779a252d88012b08938d1b03 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 9e366b4e0b4135eb8f4d4a5aed021d3858243a88 Original-Change-Id: I838a60c95c5d0fc3dee902f0b72761dd60c36221 Original-Signed-off-by: Paul Menzel &lt;pmenzel@molgen.mpg.de&gt; Original-Reviewed-on: https://review.coreboot.org/c/31286 Original-Reviewed-by: Kysti Mlkki &lt;kyosti.malkki@gmail.com&gt; Original-Reviewed-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460846 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460846" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/46/1460846/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I0850df1a3cd2af64021c7fbae9def683e996c279" commit="38ae5ae6fdc8a9eb5913a0e9927d805c5528eae0" commit_message="UPSTREAM: mb/*/*/romstage: curly braces after the function definition See Documentation/coding_style.md, specifically &quot;Placing Braces and Spaces&quot; section. BUG=none BRANCH=none TEST=none Change-Id: I0850df1a3cd2af64021c7fbae9def683e996c279 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 498f1cc1f3c3c501101c0b052502ec9a04bbd874 Original-Change-Id: Ia6a2f3d3547c16500996260b0ece9ec693f00113 Original-Signed-off-by: Peter Lemenkov &lt;lemenkov@gmail.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31268 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Kysti Mlkki &lt;kyosti.malkki@gmail.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460847 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460847" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/47/1460847/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I31ab8ccaed68fc8251e8b0d370a867d2118f13f8" commit="6a5665fe117668d2330fef4d6a078b7e29f6a640" commit_message="UPSTREAM: drivers/gpio_keys: Remove redundant is_wakeup_source flag &quot;is_wakeup_source&quot; flag is used to indicate if the concerned device can trigger a wakeup. This flag is redundant with the &quot;wake&quot; GPE event definition. So remove the redundant flag and use the &quot;wake&quot; GPE event to mark the wakeup source. BUG=None BRANCH=None TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source in SSDT if wake GPE is configured. Ensure that the system can suspend and the device acts as a wakeup source Change-Id: I31ab8ccaed68fc8251e8b0d370a867d2118f13f8 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: d5c458f98ad71f66815f637c5cb6305adc133b27 Original-Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa Original-Signed-off-by: Karthikeyan Ramasubramanian &lt;kramasub@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31258 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460848 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460848" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/48/1460848/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I31a0bdfb5de798b3819bdf24b2a63ffaef330344" commit="40c8f21ea4df6004a1dfdf720a8f9122891115b3" commit_message="UPSTREAM: mb/{asrock,intel,kontron}: Include missing &lt;arch/io.h&gt; Also includes lines sorted BUG=none BRANCH=none TEST=none Change-Id: I31a0bdfb5de798b3819bdf24b2a63ffaef330344 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 8c905a82f5d07ae7936114d392ec897756c0df9d Original-Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729 Original-Signed-off-by: Elyes HAOUAS &lt;ehaouas@noos.fr&gt; Original-Reviewed-on: https://review.coreboot.org/c/31267 Original-Reviewed-by: Felix Held &lt;felix-coreboot@felixheld.de&gt; Original-Reviewed-by: Paul Menzel &lt;paulepanter@users.sourceforge.net&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460849 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460849" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/49/1460849/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="Idff746e9c3fa2ab0e4966f85bd2d81e89b0a444b" commit="78ac161bb4884e55922f18cca3a80fe555020aa1" commit_message="UPSTREAM: mb/ocp/wedge100s: Fix devicetree Match devicetree what's present and in use. Tested on wedge100s: All PCI devices show up. BUG=none BRANCH=none TEST=none Change-Id: Idff746e9c3fa2ab0e4966f85bd2d81e89b0a444b Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: a1024ac933e74fa2c607e991be4ee705215f563d Original-Change-Id: I669d059da1876ed669793db8c7eb1b96b481cb4c Original-Signed-off-by: Patrick Rudolph &lt;patrick.rudolph@9elements.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31228 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt; Original-Reviewed-by: Paul Menzel &lt;paulepanter@users.sourceforge.net&gt; Original-Reviewed-by: Felix Held &lt;felix-coreboot@felixheld.de&gt; Original-Reviewed-by: Angel Pons &lt;th3fanbus@gmail.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460850 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460850" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/50/1460850/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I321fa9bd6415b5377f5da4035ea6f836f4f56374" commit="4b12b77c9ea9f6f88c6cebc730201d08f344b2d3" commit_message="UPSTREAM: cpu/intel/model_1067x: Check for lock bit on IA32_FEATURE_CONTROL df7aecd &quot;cpu/intel: Configure IA32_FEATURE_CONTROL for alternative SMRR&quot; introduced a regression because it unconditionally writes to IA32_FEATURE_CONTROL, which if it is already locked results in an unhandled exception. The lock bit is already set on a system reboot. BUG=none BRANCH=none TEST=none Change-Id: I321fa9bd6415b5377f5da4035ea6f836f4f56374 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: 667108199a04972ebd83c8a0430f2dddd6009879 Original-Change-Id: I7d2df9e1b9d767809da7a61ccd877c6c40f132eb Original-Signed-off-by: Arthur Heymans &lt;arthur@aheymans.xyz&gt; Original-Reviewed-on: https://review.coreboot.org/c/31255 Original-Reviewed-by: Patrick Rudolph &lt;siro@das-labor.org&gt; Original-Reviewed-by: Bill XIE &lt;persmule@gmail.com&gt; Original-Reviewed-by: Paul Menzel &lt;paulepanter@users.sourceforge.net&gt; Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Reviewed-on: https://chromium-review.googlesource.com/1460851 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460851" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/51/1460851/1" remote="cros" total_fail_count="0"/><pending_commit branch="chromeos-2016.05" change_id="I7b7fe10f037d6dc3391a0b40fe9c5ee7c77f56c9" commit="12f727c86c88c0f061b0d5b51dda927a9d666c3b" commit_message="UPSTREAM: x86/acpi: Use PM_TABLET where appropriate Instead of having SYSTEM_TYPE_DETACHABLE and SYSTEM_TYPE_TABLET use PM_MOBILE have them use PM_TABLET instead. BUG=none BRANCH=none TEST=none Change-Id: I7b7fe10f037d6dc3391a0b40fe9c5ee7c77f56c9 Signed-off-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Original-Commit-Id: fa9c6f13d2734ddaad6197564e3a072a4cecd515 Original-Change-Id: If0ce51e522d36420ecd5b51bdfec6cca11c00333 Original-Signed-off-by: Duncan Laurie &lt;dlaurie@google.com&gt; Original-Reviewed-on: https://review.coreboot.org/c/31277 Original-Tested-by: build bot (Jenkins) &lt;no-reply@coreboot.org&gt; Original-Reviewed-by: HAOUAS Elyes &lt;ehaouas@noos.fr&gt; Original-Reviewed-by: Furquan Shaikh &lt;furquan@google.com&gt; Original-Reviewed-by: Patrick Georgi &lt;pgeorgi@google.com&gt; Reviewed-on: https://chromium-review.googlesource.com/1460852 Commit-Ready: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Tested-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; Reviewed-by: Patrick Georgi &lt;pgeorgi@chromium.org&gt; " fail_count="0" gerrit_number="1460852" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="1" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/52/1460852/1" remote="cros" total_fail_count="0"/><pending_commit branch="master" change_id="I354999fedc9e25587506ea0e0cbd56a80b203321" commit="0b668e00a3d6977c0a09b1cf0d7e244c10526b31" commit_message="mosys: Add &quot;firmware_name_match&quot; to config_map struct. - If set on the struct, &quot;firmware_name_match&quot; will be used to match against smbios_name or the device tree for x86 and ARM respectively. BUG=chromium:894995 TEST=Manually ran CrosConfig tast test for coral, caroline, elm, and scarlet. CQ-DEPEND=CL:1435795 Change-Id: I354999fedc9e25587506ea0e0cbd56a80b203321 Reviewed-on: https://chromium-review.googlesource.com/1430433 Commit-Ready: Andrew Lamb &lt;andrewlamb@chromium.org&gt; Tested-by: Andrew Lamb &lt;andrewlamb@chromium.org&gt; Reviewed-by: C Shapiro &lt;shapiroc@chromium.org&gt; " fail_count="15" gerrit_number="1430433" owner_email="andrewlamb@chromium.org" pass_count="0" patch_number="14" project="chromiumos/platform/mosys" project_url="https://chromium-review.googlesource.com/chromiumos/platform/mosys" ref="refs/changes/33/1430433/14" remote="cros" total_fail_count="15"/><pending_commit branch="master" change_id="I0d2daca8fc99d7b1675530f5c12fc06c4a289b72" commit="66b41107e9a788a63b09435ea0d70d6131149694" commit_message="chromeos-config: Pass &quot;firmware_match_name&quot; to mosys. - Instead of passing device_tree_compatible_match for ARM and smbios-name-match for x86, merge them into &quot;firmware_match_name&quot;. - Future CLs can change schema and model.yaml files to use firmware_match_name instead of architecture-specific concepts. BUG=chromium:894995 TEST=Manually ran CrosConfig tast test for coral, caroline, elm, and scarlet. TEST=chromeos-config $ ./run_tests.sh CQ-DEPEND=CL:1430433, CL:1446035 Change-Id: I0d2daca8fc99d7b1675530f5c12fc06c4a289b72 Reviewed-on: https://chromium-review.googlesource.com/1435795 Commit-Ready: Andrew Lamb &lt;andrewlamb@chromium.org&gt; Tested-by: Andrew Lamb &lt;andrewlamb@chromium.org&gt; Reviewed-by: Andrew Lamb &lt;andrewlamb@chromium.org&gt; " fail_count="3" gerrit_number="1435795" owner_email="andrewlamb@chromium.org" pass_count="0" patch_number="6" project="chromiumos/platform2" project_url="https://chromium-review.googlesource.com/chromiumos/platform2" ref="refs/changes/95/1435795/6" remote="cros" total_fail_count="6"/><pending_commit branch="master" change_id="I124deb203c64c597beaac59ca698a90177a3b35c" commit="98e7b81ad283f4b781fd8309070d15660f8da910" commit_message="g2touch: add ebuild for g2touch touchscreen update tool BUG=b:112702160 TEST=Auto Firmware update tested with SeaStar(Syndra) chromebook equipped g2touch touchscreen device. Change-Id: I124deb203c64c597beaac59ca698a90177a3b35c Reviewed-on: https://chromium-review.googlesource.com/1402954 Commit-Ready: Jerry - &lt;jerry@g2touch.corp-partner.google.com&gt; Tested-by: Jerry - &lt;jerry@g2touch.corp-partner.google.com&gt; Tested-by: Harry Cutts &lt;hcutts@chromium.org&gt; Reviewed-by: Jerry - &lt;jerry@g2touch.corp-partner.google.com&gt; Reviewed-by: Harry Cutts &lt;hcutts@chromium.org&gt; Reviewed-by: Andrew de los Reyes &lt;adlr@chromium.org&gt; " fail_count="2" gerrit_number="1402954" owner_email="jerry@g2touch.corp-partner.google.com" pass_count="0" patch_number="20" project="chromiumos/overlays/chromiumos-overlay" project_url="https://chromium-review.googlesource.com/chromiumos/overlays/chromiumos-overlay" ref="refs/changes/54/1402954/20" remote="cros" total_fail_count="2"/><lkgm version="11725.0.0-rc4"/></manifest>