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| <pending_commit branch="chromeos-2016.05" change_id="I226fd6e809cf412a4e50c7c05d43633d7e3d8ade" commit="78f44bb72eef22d457ca2655b7cbbfea1e05d00d" commit_message="UPSTREAM: mb/google/nami: Add VBT blobs and include them in cbfs Add vbt files for nami variants and select Kconfig option to utilize them. The default vbt is automatically added by the Kconfig selection and so does not need to be specified in the makefile with the others. Test: boot vayne and akali nami variants, verify display functional and correct vbt loaded. Cq-Depend: chrome-internal:1297897 BUG=none BRANCH=none TEST=none Change-Id: I226fd6e809cf412a4e50c7c05d43633d7e3d8ade Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9d9ce62ae9bd122e43ab87468de541a822a0ff1f Original-Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1 Original-Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/30427 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609394 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="5" gerrit_number="1609394" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="4" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/94/1609394/4" remote="cros" total_fail_count="6"/><pending_commit branch="chromeos-2016.05" change_id="I8c0e001214606ee9f7c9585984c9306ee90fda05" commit="33427a32028232a1783499a8857f1d37a850c779" commit_message="UPSTREAM: sb/i82801gx: Don't rewrite over BCTRL PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). BCTRL registry for D30:F0 is defined at offset 0x3e for i82801gx (see ICH7 Family Datasheet page 355). The write on that register is already done some lines above. So remove wrong register name and the wrong code line. BUG=none BRANCH=none TEST=none Change-Id: I8c0e001214606ee9f7c9585984c9306ee90fda05 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: c9f6bd90857d3a7efe08c60f7f5fc19995fb1756 Original-Change-Id: Ib8a0514200f424049503bb8e4bc076ee6ae86ce3 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32699 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609395 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609395" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/95/1609395/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I346220a6cb067ce03cd0201599cba5eda34b1939" commit="17deb51ce3fcfd1de50211eece5bbf2091569374" commit_message="UPSTREAM: sb/bd82x6x: Don't rewrite over BCTRL PCI_MIN_GNT is defined at offset 0x3e in <pci_def.h> which does not apply to this PCI bridge because it is only defined for "Header type 0 (normal devices)" (line 82). Some lines obove that code line, the "write" on BCTRL is already done. BUG=none BRANCH=none TEST=none Change-Id: I346220a6cb067ce03cd0201599cba5eda34b1939 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9646cfe989a096372a717d8ef16ce5096d1b2708 Original-Change-Id: I8f1b98ba627947ab6652a4ba31d2acb159dd3e32 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32700 Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1609396 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609396" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/96/1609396/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I94aa023ed519de92b6ba3136d1abaeef20c095cc" commit="ed4c93e9988bdf6a108a99fd4102af02c1ea7cab" commit_message="UPSTREAM: mb/google/sarien: Fix s5 touchscreen power leakage Leakage power is observed from TOUCH_SCREEN_PD# (GPP_E7 which is connected to RESET pin of Wacom controller) during S5. To avoid leakage power, GPP_E7 needs to be turned off before S5 entry. BUG=b:129899315 TEST=Measure leakage power in S5 from both Arcada and Sarien Change-Id: I94aa023ed519de92b6ba3136d1abaeef20c095cc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f36fcdf2ab6a9956ac60012404e0edf1d6653fac Original-Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Original-Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32367 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1609397 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609397" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/97/1609397/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="If6f9eda11d0b47825929c3c94db34681fbd9ce44" commit="42e01e02bcfeab1656d1049149d5f94051bc170f" commit_message="UPSTREAM: soc/amd/stoneyridge: Add IO access functions for PMx Replace locations in the source that explicitely use the CD6/CD7 index/data pair with utility function calls. BUG=none BRANCH=none TEST=none Change-Id: If6f9eda11d0b47825929c3c94db34681fbd9ce44 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 939bfccb3dbf04a0a2f7e15b82db1fdb469b7a73 Original-Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4 Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/1609398 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609398" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/98/1609398/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I5ad1df26c807163bba8013199643ec984dc944c4" commit="42e73dd7f2d7cac3d25bd8fa586b24389e9536b8" commit_message="UPSTREAM: vboot: Make vboot_logic_executed() a bit more precise This patch adds another check to vboot_logic_executed() to make sure we only do a runtime check for verstage_should_load() if CONFIG_VBOOT_RETURN_FROM_VERSTAGE is enabled. That's the only case where the stage that's loading the verstage can execute after verification has run (because the verstage will return to it when it's done). In the other case, the stage that loads verstage really just loads it and will never do anything again after hand-off, so it's guaranteed to always execute before verification. This change may allow extra dead-code elimination in some cases. BUG=none BRANCH=none TEST=none Change-Id: I5ad1df26c807163bba8013199643ec984dc944c4 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ef7d89cabe658e7f2951112c50853328988cea98 Original-Change-Id: I7019b6f7b0acfbf0a8173914b53364751b08f2cf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32714 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1609399 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609399" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/99/1609399/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I81ad283c17118b0f679962241a09fda82f027c22" commit="467682aeb0969237622bfc260c89e701ccc6c5fd" commit_message="UPSTREAM: assert.h: Undefine ASSERT macro in case vendorcode headers set it Some edk2 vendorcode headers define an ASSERT macro. They're guarded with an #ifndef ASSERT, but if coreboot's assert.h gets included after that header, we still have a problem. Add code to assert.h to undefine any rogue definitions that may have already been set by vendorcode headers. This is ugly and should only be a stopgap... it would be nice if someone maintaining those vendorcode parts could eventually replace it with a better solution. One option would be to use a "guard header" for every vendorcode header we want to pull into normal coreboot code which would chain-include the vendorcode header and then undefine anything that clashes with coreboot again. BUG=none BRANCH=none TEST=none Change-Id: I81ad283c17118b0f679962241a09fda82f027c22 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: a73e5a75b1b1ba03e7712d981456974e89a21264 Original-Change-Id: Ibf8dc8b2365821e401ce69705df20aa7540aefb2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32715 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1609420 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609420" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/20/1609420/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Ibc732b31c8eb4aa69952bb602db70417b66168b5" commit="5bdf394cb5f54d713a9af2a56d4d3a1d691ccc6d" commit_message="UPSTREAM: vboot: Turn vboot_logic_executed() into a static inline This patch moves vboot_logic_executed() (and its dependencies) into a header and turns it into a static inline function. The function is used to guard larger amounts of code in several places, so this should allow us to save some more space through compile-time elimination (and also makes it easier to avoid undefined reference issues in some cases). BUG=none BRANCH=none TEST=none Change-Id: Ibc732b31c8eb4aa69952bb602db70417b66168b5 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 998dc17f522af6ef8fc7c85fa1e90fa7873fe7d1 Original-Change-Id: I193f608882cbfe07dc91ee90d02fafbd67a3c324 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32716 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://chromium-review.googlesource.com/1609421 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609421" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/21/1609421/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I816cf0d4172bc7203f1c33aef56073cc2a87f673" commit="56f81d02103814a9c16b3e0e7dabb68818155d81" commit_message="UPSTREAM: Define ENV_PAYLOAD_LOADER We've been assuming that ENV_RAMSTAGE is always the payload loader. In order to test out different models, we need a way to mark the "stage we are in" as the payload loader. Define a new rule, ENV_PAYLOAD_LOADER. For now, it is set to ENV_RAMSTAGE. It is not used yet pending approval of this approach. BUG=none BRANCH=none TEST=none Change-Id: I816cf0d4172bc7203f1c33aef56073cc2a87f673 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4249348735d18cb2d44506090a675a29b0567e7f Original-Change-Id: I7d4aa71bad92987374d57ff350b9b0178ee7c12b Original-Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32709 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1609422 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609422" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/22/1609422/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I4ec74fa2e22af1d02b2de15d41bce1dc0e71fd9e" commit="b09f16827615530f5b7e39eb5337554b04755e4a" commit_message="UPSTREAM: soc/intel/cnl: Enable VT-d Enable VT-d through fsp upd VtdDisable. Update remapping structure types in numerical order as all remapping structures of type 0 (DRHD) enumerated before remapping structures of type 1 (RMRR), and so forth. BUG=b:130351429 TEST=Booted to kernel and verified the DMAR table contents. Change-Id: I4ec74fa2e22af1d02b2de15d41bce1dc0e71fd9e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 1159a163cd36318d27f8f3b71617ad4a5b781efb Original-Change-Id: I1d20932e417b9d324edd98c8f2195dc228d2e092 Original-Signed-off-by: John Zhao <john.zhao@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32432 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1609423 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609423" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/23/1609423/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I95d472981a1e37cd3e14c9ea20f11b215a92df52" commit="251cd05d57d29e835f2168d15c8689ce1671a2ac" commit_message="UPSTREAM: arch/cpu: Rename mp_get_apic_id() and add_cpu_map_entry() function This patch renames mp_get_apic_id() to cpu_get_apic_id() and add_cpu_map_entry() to cpu_add_map_entry() in order access it outside CONFIG_PARALLEL_MP kconfig scope. Also make below changes - Make cpu_add_map_entry() function available externally to call it from mp_init.c and lapic_cpu_init.c. BRANCH=none BUG=b:79562868 Change-Id: I95d472981a1e37cd3e14c9ea20f11b215a92df52 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 7bc9036d160c6235d96e1bed49331696d7fa9a09 Original-Change-Id: I6a6c85df055bc0b5fc8c850cfa04d50859067088 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32701 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609424 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609424" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/24/1609424/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I94ecdf8235b7f0c11e0cade3046609afb70904a9" commit="a7b8435f8bc48c78a6345d77b082b715ede751e8" commit_message="UPSTREAM: Kconfig: Create RAMPAYLOAD kconfig This patch enables coreboot flow to skip ramstage as individual stage to load payload. Instead it is expected to load payload from postcar stage. BUG=none BRANCH=none TEST=none Change-Id: I94ecdf8235b7f0c11e0cade3046609afb70904a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 7e893a02c0cc04b8fdcfee0b4dc0ff790bfe40c5 Original-Change-Id: I839f2d34a93b69ca6bf3de6594e2ad9f66ee7135 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32618 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/1609425 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609425" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/25/1609425/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Ic2b442349267049500d611efd81e0bebac35363e" commit="1a2f7547d59ec33c0d022e22c79033a49dd3095a" commit_message="UPSTREAM: lib/timestamp: Make timestamp_sync_cache_to_cbmem() in postcar This patch ensures to have correct timestamp value in postcar. BUG=none BRANCH=none TEST=none Change-Id: Ic2b442349267049500d611efd81e0bebac35363e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2d7a52c784efb6be86bac5cb7aa1f8e1bd7088a6 Original-Change-Id: I3ba3a54c20dfcdaf5b87818cc5da9a812f5f2edf Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32726 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609426 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609426" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/26/1609426/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I53b3428f3ff157ec0d046dd158e0d57bf201ba26" commit="1164936534e229300ed5730994a273ae1a199ae2" commit_message="UPSTREAM: boot_device: Constify argument Add const qualifier to first argument. BUG=none BRANCH=none TEST=none Change-Id: I53b3428f3ff157ec0d046dd158e0d57bf201ba26 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2be0b50be5783f173989a7882f3650d2a106f974 Original-Change-Id: I6655e04401b6a7aa5cafb717ff6f46b80b96646e Original-Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32703 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://chromium-review.googlesource.com/1609427 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609427" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/27/1609427/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I70d8b232dda9a870f1b916034dccc7c585c2839f" commit="24190645419e855c58619fc558f137ec98a57d19" commit_message="UPSTREAM: mb/lenovo/*: Add MAINBOARD_FAMILY The Kconfig MAINBOARD_FAMILY sets the family field of SMBIOS entry 1. Match what vendor firmware does and use the same value as in the version field. Required for fwupd which uses the family field to generate a GUID. BUG=none BRANCH=none TEST=none Change-Id: I70d8b232dda9a870f1b916034dccc7c585c2839f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f77eb44433c99a4b3fff5ec67300457a6a52498b Original-Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534 Original-Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32727 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/1609428 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609428" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/28/1609428/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I40cc662e17c1ec8e1a10044b1c2e4bea06306c4a" commit="94ab9ed3ccebd31c5bd36bcd6a86ced682e643e9" commit_message="UPSTREAM: mb/asrock/h81m-hds: Drop now obsolete libgfxinit override CPU type is detected at runtime now. BUG=none BRANCH=none TEST=none Change-Id: I40cc662e17c1ec8e1a10044b1c2e4bea06306c4a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: a6d401c193c9bb53162df9523f9ba4ebb2a6f1a7 Original-Change-Id: I5e54176e235e43ca28e4baf43dbb9860e7fc3dbd Original-Signed-off-by: Nico Huber <nico.huber@secunet.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/31465 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Original-Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://chromium-review.googlesource.com/1609429 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609429" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/29/1609429/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I74f0ff20942510dffe0e23a28ef8317ca046affc" commit="d2d274d95bc1c47035f27e3d88f6150d1cdebf9e" commit_message="UPSTREAM: src/arch/x86: Use core apic id to get cpu_index() This cpu_index() implementation assumes that cpu_index() function might always getting called from coreboot context (ESP stack pointer will always refer to coreboot). This might not be true in case of proposed PI spec MP_SERVICES_PPI implementation, where FSP context (stack pointer refers to fsp) will request to get cpu_index(), natural alignment logic will use ESP and retrieve struct cpu_info *ci from (stack_top - 8 byte). This is not the place where cpu_index is actually stored by ramstage c_start.S Hence this patch tries to remove those dependencies while retrieving cpu_index(), rather it uses cpuid to fetch lapic id and matches with cpus_default_apic_id[] variable to return correct cpu_index(). BRANCH=none BUG=b:79562868 TEST=Ensures functions can be run on APs without any failure and cpu_index() also provides correct index number. Change-Id: I74f0ff20942510dffe0e23a28ef8317ca046affc Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 095c931cf12924da9011b47aa64f4a6f11d89f13 Original-Change-Id: I55023a3e0cf42f0496d45bc6af8ead447f402350 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/26346 Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1609430 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609430" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/30/1609430/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I068d78bf8d0a9674c74c3ed2bfb033056c2403f8" commit="9132b6e46e5135797be6a24470c1fb3f26537970" commit_message="UPSTREAM: lapic/lapic_cpu_init: Add cpu_add_map_entry() to store default_apic_id This patch ensures start_cpu() function to store default_apic_id using common cpu_add_map_entry() function to make cpu_index() implementation generic. BRANCH=none BUG=b:79562868 Change-Id: I068d78bf8d0a9674c74c3ed2bfb033056c2403f8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: e091d0efc40581ce789fdef5f44a327b75adc999 Original-Change-Id: Iac4d6e9e6e6f9ba644335b4b70da8689c405f638 Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32722 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609431 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609431" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/31/1609431/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Iaea44864268cf89eeb8ce0d1fd16dbf1b791d68a" commit="de4dad32dd2e945ada19bfdeb41c8c61da118194" commit_message="UPSTREAM: util/ifdtool: Add find_fd null check As the previous comment indicated, this null check is currently superfluous, but adding it in makes Coverity happy, and future-proofs the code in case someone changes the internals of 'find_fcba' later and forgets/doesn't know to update this error check. BUG=none BRANCH=none TEST=none Change-Id: Iaea44864268cf89eeb8ce0d1fd16dbf1b791d68a Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9bb0461fbd8cdcceabde0ec266a5207bc40ea9a7 Original-Found-by: Coverity Scan #1395066 Original-Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Original-Change-Id: I594cd0098f5b36cef5b3efc4c904710d3ba9b815 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32691 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609432 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609432" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/32/1609432/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Ie2e4d0cb33b82cd2a000dd7b36ef49abc85a5b63" commit="43863b80191f0c6dcde6ff69b28101d485044443" commit_message="UPSTREAM: util/intelvbttool: Free file object on error path Prevents a memory leak. BUG=none BRANCH=none TEST=none Change-Id: Ie2e4d0cb33b82cd2a000dd7b36ef49abc85a5b63 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2be617b58b500214d45c338eda88237730524cac Original-Found-by: Coverity Scan #1396047 Original-Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Original-Change-Id: I4c72a17351d8afbe23302edfeeba74b17608aef2 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32685 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609433 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609433" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/33/1609433/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Ide5cb5f0dae6c6379cc4f94dfaeb264707036ea7" commit="6a4a46f0c6001c0cb184e695b931346e3f8a3bf4" commit_message="UPSTREAM: util/intelvbttool: Add error checking for memory allocation It is possible that 'malloc_fo_sub' and 'remalloc_fo' can fail, so add appropriate error checks for those cases. This incidentally fixes a possible memory leak when 'malloc_fo_sub' succeeds but 'remalloc_fo' does not. BUG=none BRANCH=none TEST=none Change-Id: Ide5cb5f0dae6c6379cc4f94dfaeb264707036ea7 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 4fbd22e38d42faf7654cf9ded1f4001652e7fd37 Original-Found-by: Coverity Scan #1396050 Original-Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Original-Change-Id: I944b67f5cdcfd7a687e81d8bb01a209c9dc9b0b8 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32696 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609434 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609434" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/34/1609434/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Ie6f2b7bf6dac85d2f0bda485645ec24c65bd75f9" commit="abbba9a1ce237acfe2cc2f09a8bf0d3c60a50966" commit_message="UPSTREAM: soc/intel/braswell: Add tsc_freq.c and pmutil.c in verstage Systems with C_EVIRONMENT_BOOTBLOCK and VBOOT enabled requires functions tsc_freq_mhz(), vbnv_cmos_failed() and vboot_platform_is_resuming() in verstage. Add tsc_freq.c and pmutil.c to verstage. BUG=NA TEST=Booting Embedded Linux on Facebook FBG-1701 + Building Google Banon Change-Id: Ie6f2b7bf6dac85d2f0bda485645ec24c65bd75f9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9c90609331b33292c7aeacc944cd97fe5a2da056 Original-Change-Id: Ia509eda6bf415aaa63be71013249493aa472289d Original-Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32733 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609435 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609435" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/35/1609435/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I9cb5a4426ac20acb2ac8e8ec0f41d06dc9f4b8b3" commit="2be2210d7e4ed9aece68790fd63e25e4713a5181" commit_message="UPSTREAM: mainboard: Remove unused include <timestamp.h> BUG=none BRANCH=none TEST=none Change-Id: I9cb5a4426ac20acb2ac8e8ec0f41d06dc9f4b8b3 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9d6f6459080e6ca1f82fabd7e05ada506c58204d Original-Change-Id: Id05fc39c0c0d0560e34e55f793060d29df82d026 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32676 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1609436 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609436" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/36/1609436/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Id5773f58da12fc9862d3551991eb34142aa5ead2" commit="7295af49f9d2624d5ae8bd84a334d5171addeb09" commit_message="UPSTREAM: soc/intel/braswell: Remove unused include <timestamp.h> BUG=none BRANCH=none TEST=none Change-Id: Id5773f58da12fc9862d3551991eb34142aa5ead2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: cb6f6a10b3223dce446a1ce8e01cba0357b55b91 Original-Change-Id: Ied645a583f78bc47c8358240acd639132fd499db Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32711 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: David Hendricks <david.hendricks@gmail.com> Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1609437 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609437" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/37/1609437/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I4a0431a6a9f492796303100e66787fd84051631f" commit="a6b73b2654b4ff9fd2a89dc7dd9bd15edd6c51d8" commit_message="UPSTREAM: util/kconfig: Use snprintf to avoid buffer overflow 'name' and 'env' are supposed to be file system paths, but could overflow the buffer if configured incorrectly. Let's avoid that entirely. BUG=none BRANCH=none TEST=none Change-Id: I4a0431a6a9f492796303100e66787fd84051631f Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 554e55b0f07e7913afad6b374e30661df9db617a Original-Found-by: Coverity Scan #1362515 Original-Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Original-Change-Id: I1aef36819d49ebcbde1c51995dc0961c85e74150 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32686 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609438 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609438" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/38/1609438/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I6fd94025b8a7d45269d5f8453be8fd7ee67a8ee6" commit="06aebdc297caab63287638d039a54795f146edf8" commit_message="UPSTREAM: lib/hexdump: Drop redundant isprint() implementation BUG=none BRANCH=none TEST=none Change-Id: I6fd94025b8a7d45269d5f8453be8fd7ee67a8ee6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ac6bf7dc1259ae09dfbd123dc6dee1400b26c801 Original-Change-Id: I23e2d89274553cbc75e42f0420a1a84d4cec4340 Original-Signed-off-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32739 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1609439 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609439" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/39/1609439/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Iaf9663e8e258f1d9612ba129c0f9bc652f887239" commit="29a3382466f52699541fbde9cf5dc75cf263acd2" commit_message="UPSTREAM: mb/google/sarien: config ISH_GP6 with NF2 A12 is not current set for ISH_GP6 so the ISH_LID_CL#_TAB signal is not making it to the ISH properly. Enable the second native function instead of the first. BRANCH=none BUG=b:131785573 TEST=gpioget on ISH now shows the correct gpio level Change-Id: Iaf9663e8e258f1d9612ba129c0f9bc652f887239 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: f2d173a554b82b731fceeecd00095f6c6433c7ba Original-Change-Id: Ib3a654ae659037263aa9aa29d45b42ca67b7955b Original-Signed-off-by: Jett Rink <jettrink@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32738 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1609440 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609440" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/40/1609440/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I7243fbbd331bca5e80f67c9c86725d3f9aefdd83" commit="820ab114d2e7bc2ac4f8edfb3c7ca90746dce38d" commit_message="UPSTREAM: libpayload: classify all keyboards Depthcharge uses the keyboard type to help determine whether it can trust the keyboard for security-sensitive confirmations. Currently it trusts anything except usb, but now there's a need to distrust ec-based ps/2 keyboards that are associated with untrusted ECs. To help facilitate this, coreboot needs to report more details about non-usb keyboards, so this change replaces the current instances of unknown with enum values that distinguish uart and gpio from ec-based keyboards. BUG=b:129471321 BRANCH=None TEST=Local compile and flash to systems with trusted and non-trusted ECs. Confirmed that security confirmation can't be performed via keyboard on a system with an untrusted EC but can still be performed on a system with a trusted EC. Change-Id: I7243fbbd331bca5e80f67c9c86725d3f9aefdd83 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: a20e59da157231f0a0e41774af80f6bccde1b280 Original-Change-Id: Iee6295dafadf7cb3da98b62f43b0e184b2b69b1e Original-Signed-off-by: Matt Delco <delco@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32717 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1609441 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609441" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/41/1609441/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Id547c658fc251454d7daac1ab2d0a8b0dbf0e2d2" commit="85d11949bafb92f1fa2be4621afe4b6c57baa12e" commit_message="UPSTREAM: soc/intel: Geminilake Refresh feature request support Add 0x706a8 for GLK Refresh CPU stepping ID. BUG=b:132414963 BRANCH=None TEST=Image built successfully. Change-Id: Id547c658fc251454d7daac1ab2d0a8b0dbf0e2d2 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 7528f834447de52d1d62e979cd93af0ac30d5f6f Original-Signed-off-by: John Zhao <john.zhao@intel.com> Original-Change-Id: I4641d9bd4c82211e7200f617cae9043b0f2f38d1 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32744 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1609442 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609442" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/42/1609442/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I08a1317c01dab15ff6f9b442bbee66b669411d1e" commit="7948d3481ddbd626bdb1cd3bda7752bb1e727492" commit_message="UPSTREAM: util/inteltool: Use appropriate channel for printing timings At least one channel must be present, so print an error if there is not. However, we cannot always assume it will be the first channel, so make the appropriate selection when printing the timings. BUG=none BRANCH=none TEST=none Change-Id: I08a1317c01dab15ff6f9b442bbee66b669411d1e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: a75440739d172bea6eeefc08af2bbdefc528e912 Original-Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Original-Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Original-Change-Id: I6b59989242e498474782876302e0850e3e4cf2d3 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32713 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609443 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609443" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/43/1609443/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I40979aaa60b856b4b7f06e3f8c70b0a8d4e8ca9e" commit="271a2eb8c44c12c7b4938541e97575b2eeae49be" commit_message="UPSTREAM: libpayload/drivers/i8042: Add fallthrough comment Ctrl-delete does nothing, so it falls through to the default case. Add a comment to make this explicit. BUG=none BRANCH=none TEST=none Change-Id: I40979aaa60b856b4b7f06e3f8c70b0a8d4e8ca9e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: dbc787d13d461bf0d96002bfc36936de4c64cea7 Original-Found-by: Coverity Scan #1260878 Original-Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Original-Change-Id: I4a6f51cb04696b6ebcb554c5667a5bbea58622c1 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32750 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609444 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609444" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/44/1609444/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I4d8836339a095cd529bd039ecf8f204b622159cd" commit="9467a0e15fc723528d4735007da814f5e5b378c7" commit_message="UPSTREAM: mb/t400/acpi: Update ATPR buffer to fit all entries Error spotted using acpica version 20190509 (Change-Id: I6779a20). BUG=none BRANCH=none TEST=none Change-Id: I4d8836339a095cd529bd039ecf8f204b622159cd Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: ef9e85bbfdb24d228f1e6c37d916025c5d06ea53 Original-Change-Id: Ic9cf16a7494667f6dab156c697fb8f8e9966051e Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32743 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/1609445 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609445" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/45/1609445/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="If7eff37d46f756b90a634247610e29bc2ba8b224" commit="8843ef6ec702b671e4ba7533172985bb501003ba" commit_message="UPSTREAM: mb/lenovo/s230u: Rewrite trigger inversion ACPI code The GPIO invert registers are already defined in the PCH code, so just use the 8-bit versions of the registers instead of creating a new GPIO field for the single bits. This allows us to get rid of the Field(GPIO...) code that's causing problems with IASL version 20190509. BUG=none BRANCH=none TEST=none Change-Id: If7eff37d46f756b90a634247610e29bc2ba8b224 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 2f0bbbfe9f3b3d68d75eabd35280fe8aaa9d8619 Original-Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-on: https://chromium-review.googlesource.com/1609446 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609446" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/46/1609446/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I7451cf700e7a1a6d17af5f4c57d984fa81f6a8ef" commit="f85ee2fd4cf65558068ca465d5d8f623f9c276fd" commit_message="UPSTREAM: src/ec/lenovo/h8/acpi: Serialize Control Method IASL reports warning 'Control Method should be made Serialized'. BUG=none BRANCH=none TEST=none Change-Id: I7451cf700e7a1a6d17af5f4c57d984fa81f6a8ef Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 60ab1d8c52799d70d1956ce7261d94be439aa63a Original-Change-Id: I034f2c00e912e8f9ef87b9918de1db06fade38b9 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32745 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609447 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609447" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/47/1609447/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I5313dcb26442cc957c1dc0c7f00d229590ee2661" commit="98abd1d9c1621ec79255130360c443518a4edd29" commit_message="UPSTREAM: nb/intel/sandybridge: Update pei_data comments Update outdated comments. BUG=none BRANCH=none TEST=none Change-Id: I5313dcb26442cc957c1dc0c7f00d229590ee2661 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 44105942df5a396c5ff999d7dd8384bfd44784c0 Original-Change-Id: I100f71345281a1dc52e99d2395f528d60a9a1f58 Original-Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32706 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609448 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609448" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/48/1609448/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="Ia0a73aad8644336d147c31d921a91d40c6beb622" commit="8d023c17e46feed9f1edf3df19eacae22f96dcef" commit_message="UPSTREAM: mb/samsung/lumpy: Move onboard SPD to second channel Move the onboard SPD to second channel as native raminit does and workaround mrc expecations in northbridge code. Required to move pei data to devicetree and to use the same code for mrc and native raminit. Tested on Lenovo T520: Other fields then spd_data[0] are ignored. BUG=none BRANCH=none TEST=none Change-Id: Ia0a73aad8644336d147c31d921a91d40c6beb622 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 59b4255c63b54739b9a095021508a13eab86c2a1 Original-Change-Id: If1910e82a4bd178c2a6c2991c91e09782122888e Original-Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32682 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609449 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609449" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/49/1609449/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I548d1b3a078a98f61d05e954c0b955bd888b2023" commit="fa821fdf3b0a1d3c3f226995421e1833d588b7c7" commit_message="UPSTREAM: nb/intel/sandybridge: Migrate MRC settings to devicetree * Add more chip register to move PEI data to devicetree.cb. * Set northbridge/southbridge and runtime detectable settings. * Fill in values from devicetree. This change is still a noop as the pei structure is completely overwritten with the exsting mainboard pei structure. The followup commit will migrate to devicetree.cb. Tested on Lenovo T520, boots MRC path with the new devicetree settings. BUG=none BRANCH=none TEST=none Change-Id: I548d1b3a078a98f61d05e954c0b955bd888b2023 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 5709e03613b342f9dc00a659b6474c6ee510fcc3 Original-Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Original-Change-Id: Ic6d9f0fd6a2b792ac693d6016ed9ce44945c900c Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32069 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://chromium-review.googlesource.com/1609450 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="7" gerrit_number="1609450" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/50/1609450/2" remote="cros" total_fail_count="7"/><pending_commit branch="chromeos-2016.05" change_id="I7c8211cd18e35f5a7d2cc27d34fc9fcee5e3e86e" commit="5582ce2307b94aa67b278ae55d5e638145972cf7" commit_message="UPSTREAM: nb/intel/sandybridge: Move boot_count_increment() Move boot_count_increment() to romstage.c, drop preprocessor code and only increase counter once on regular boot. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. BUG=none BRANCH=none TEST=none Change-Id: I7c8211cd18e35f5a7d2cc27d34fc9fcee5e3e86e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 9005071c5fb1d75b2a54aa0b3e7af47e25d2de54 Original-Change-Id: I6aa52b75edf19953405b70284c7e7db30f607cd6 Original-Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32067 Original-Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1609451 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="5" gerrit_number="1609451" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/51/1609451/2" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-2016.05" change_id="I866bc46ad47634c702516d05ff964ef0f2a8d264" commit="b3c97eed3728a2170a21b115f53a8cc81a3fc922" commit_message="UPSTREAM: {bd82x6x,i82801gx,ibexpeak,lynxpoint}: Remove dead code and use macro Use BIOS_CNTL defined macro instead of magic number. BUG=none BRANCH=none TEST=none Change-Id: I866bc46ad47634c702516d05ff964ef0f2a8d264 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 0c22d2fe46fbc59fa12fec46c21874f422b10e44 Original-Change-Id: I0d2b555ada9c2893af4f85422128f5a8b04e2fc6 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/29990 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609452 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="5" gerrit_number="1609452" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/52/1609452/2" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-2016.05" change_id="Ic7272f90f4de965ff9704c90bcace9b047dcf089" commit="b3d2e3442f93bbb486f255b9f7e3afc0d1e9dafc" commit_message="UPSTREAM: soc/intel/{cannonlake,icelake}: Drop unused cbmem.c file BUG=none BRANCH=none TEST=none Change-Id: Ic7272f90f4de965ff9704c90bcace9b047dcf089 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 8dd518969cf02e37412019e4a6a4a5ce496da8c0 Original-Change-Id: Ib9444f7797289c9b8250cfb16eb1c12dff867ec3 Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32756 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Nico Huber <nico.h@gmx.de> Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1609453 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="5" gerrit_number="1609453" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/53/1609453/2" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-2016.05" change_id="I293f510102a20ea3ca64238eef52c3ee03a7eaf1" commit="ab94b921bb915052926efab4feec115b0982da75" commit_message="UPSTREAM: i82801gx/bootblock: Use macro instead of magic number BUG=none BRANCH=none TEST=none Change-Id: I293f510102a20ea3ca64238eef52c3ee03a7eaf1 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 11a5b6b577d5e4c2611ac80dd0b7f761b80f942f Original-Change-Id: I2556c150f53d9580bc3b70ab49b3a2c8477c18ea Original-Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32755 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://chromium-review.googlesource.com/1609454 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="5" gerrit_number="1609454" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/54/1609454/2" remote="cros" total_fail_count="5"/><pending_commit branch="chromeos-2016.05" change_id="Iac0e2ab5cebc1d28a943ab0cdbb86f56870dfb10" commit="47ba3426797a10e08d99c119dc837127ecc34ea6" commit_message="UPSTREAM: Makefile.inc: Enable -Wtype-limits This patch enables -Wtype-limits for the whole repository, which disallows checking for a condition that must be always true or always false based on type width (e.g. checking whether an unsigned variable is negative or whether a 32-bit integer is larger than 4G). This helps avoid easy to make and hard to find (because they often only affect error paths) mistakes like size_t size = fmap_read_area(...); if (size < 0) die("If only the compiler could've told me to use ssize_t instead"); [pgeorgi: fold in revert + reland] BUG=none BRANCH=none TEST=none Change-Id: Iac0e2ab5cebc1d28a943ab0cdbb86f56870dfb10 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Commit-Id: 795fda033656982a8aeef0e105bcfbc9a73c8c13 Original-Change-Id: I19edabfd092d09dad720e3fc47b44838163bfe25 Original-Change-Id: I9cce10462b9e57189513fa49e11fd27ebe35ba51 Original-Change-Id: I32e8cc88e69072e7ee66cf443b578a9a8ea0ebe2 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32749 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32670 Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/32536 Original-Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Original-Reviewed-by: Furquan Shaikh <furquan@google.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-on: https://chromium-review.googlesource.com/1609455 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> " fail_count="5" gerrit_number="1609455" owner_email="pgeorgi@chromium.org" pass_count="0" patch_number="2" project="chromiumos/third_party/coreboot" project_url="https://chromium-review.googlesource.com/chromiumos/third_party/coreboot" ref="refs/changes/55/1609455/2" remote="cros" total_fail_count="5"/><lkgm version="12205.0.0-rc6"/></manifest> |
