v3/ec: Updates for Proto 1

* Update SYSMON signal mappings to include the new current monitors
and VREF for those monitors, remove unused signal.
* Update devicetree for new GPIO pins for controlling power on the
IT68051, and for muxing the HPD signals to choose between the STM32,
the FPGA, and the IT68051.
* Add documentation of where the HPD signal can be generated, and
how it is routed to the HDMI and DisplayPort connectors.

BUG=None
TEST=Build and load. Run the ad-hoc tests in README.md

Change-Id: I8cd3465cdaf4d8d71026c88c8cd39b8d62f4115d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/chameleon/+/2826034
Reviewed-by: Alexandru M Stan <amstan@chromium.org>
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: Paul Fagerburg <pfagerburg@chromium.org>
diff --git a/v3/ec/boards/arm/chameleon/chameleon.dts b/v3/ec/boards/arm/chameleon/chameleon.dts
index b79a585..eb2bfed 100644
--- a/v3/ec/boards/arm/chameleon/chameleon.dts
+++ b/v3/ec/boards/arm/chameleon/chameleon.dts
@@ -233,11 +233,36 @@
 			gpios = <&gpiog 11 GPIO_OUTPUT_HIGH>;
 			label = "DP2_HDMI_RST_L";
 		};
+
+		/*
+		 * Mux signals for selecting which IC drives the HPD signal to
+		 * the HDMI or DisplayPort connectors. See `proto1_hpd` docs for
+		 * more information.
+		 */
+		hdmirx_hpd_sel {
+			gpios = <&gpioa 1 GPIO_OUTPUT_LOW>;
+			label = "HDMIRX_HPD_SEL";
+		};
+
+		hdmi_hpd_sel {
+			gpios = <&gpioa 8 GPIO_OUTPUT_LOW>;
+			label = "HDMI_HPD_SEL";
+		};
+
+		dp_hpd_sel {
+			gpios = <&gpiob 9 GPIO_OUTPUT_HIGH>;
+			label = "DP_HPD_SEL";
+		};
 	};
 
 	it68051 {
 		compatible = "gpio-keys";
 
+		it68051_en {
+			gpios = <&gpiof 3 GPIO_OUTPUT_HIGH>;
+			label = "IT68051_EN";
+		};
+
 		it68051p0_pwr_det {
 			gpios = <&gpiof 0 GPIO_OUTPUT_HIGH>;
 			label = "IT68051P0_PWR_DET";
@@ -390,6 +415,7 @@
 			label = "DP_IN_PWR_EN";
 		};
 	};
+
 	dp_cfg {
 		compatible = "gpio-keys";
 
diff --git a/v3/ec/doc/README.md b/v3/ec/doc/README.md
index 3fae21e..2616f9f 100644
--- a/v3/ec/doc/README.md
+++ b/v3/ec/doc/README.md
@@ -179,75 +179,92 @@
 The command `sysmon` prints a list of the various voltages being monitored:
 
 ```
-uart:~$ sysmon
-12V: 12.242871
-CMON_SOM: 0.294067
-CMON_BOARD: 0.235254
-PP1200: 1.217358
-PP1360: 1.372046
-PP1260: 1.280200
-PP1000: 1.005469
-VMON_9V: 9.174902
-VMON_5V: 4.908105
-VMON_3V3: 3.232727
-PP1800: 1.813550
-SOM_VMON: 1.527539
-SOM_VMON_1V2: 1.959375
-SOM_VMON_MGT: 1.735400
-SOM_VMON_1V8A: 1.886865
-SOM_VMON_C8: 1.913452
-SOM_VREF_CS: 0.001611
+$ sysmon
+12V: 12.304102
+CMON_SOM: 0.278760
+CMON_BOARD: 0.479370
+PP1200: 1.205273
+CMON_PP1200: 1.068310
+CMON_PP3300: 0.555103
+VMON_9V: 9.223242
+VMON_5V: 5.169141
+VMON_3V3: 3.325781
+PP1800: 2.239746
+SOM_VMON: 1.458252
+SOM_VMON_1V2: 2.482251
+SOM_VMON_MGT: 1.549292
+SOM_VMON_1V8A: 2.015771
+SOM_VMON_C8: 2.193017
+VREF_CS1: 0.001611
+VREF_CS2: 0.000806
+VREF_CS3: 0.000806
 ```
 
 The SOM_VMON voltages will not be accurate unless the FPGA SOM is installed
 and its power supplies are enabled. In this example, the FPGA SOM is not
 installed.
 
-Note that on proto0, the current monitors (CMON_SOM and CMON_BOARD) are not
-accurate due to a parts issue.
-
 Because of the use of a timer to drive the sampling sequence, you can get
-zero values if you run the `sysmon` command soon after start-up:
+zero values if you run the `sysmon` command soon after start-up. Within a
+few seconds, all of the values are populated.
 ```
-sysmon
-12V: 12.091406
-CMON_SOM: 0.275537
-CMON_BOARD: 0.229614
-PP1200: 1.207690
-PP1360: 1.374463
-PP1260: 1.304370
-PP1000: 1.030444
-VMON_9V: 9.139453
-VMON_5V: 5.017676
-VMON_3V3: 3.295569
-PP1800: 1.774878
+$ sysmon
+12V: 12.294434
+CMON_SOM: 0.274731
+CMON_BOARD: 0.411694
+PP1200: 1.227832
+CMON_PP1200: 0.000000
+CMON_PP3300: 0.000000
+VMON_9V: 0.000000
+VMON_5V: 0.000000
+VMON_3V3: 0.000000
+PP1800: 0.000000
 SOM_VMON: 0.000000
 SOM_VMON_1V2: 0.000000
 SOM_VMON_MGT: 0.000000
 SOM_VMON_1V8A: 0.000000
 SOM_VMON_C8: 0.000000
-SOM_VREF_CS: 0.000000
-```
-Even a second later, all of the values are non-zero:
-```
+VREF_CS1: 0.000000
+VREF_CS2: 0.000000
+VREF_CS3: 0.000000
 $ sysmon
-12V: 12.117188
-CMON_SOM: 0.281177
-CMON_BOARD: 0.248145
-PP1200: 1.200439
-PP1360: 1.374463
-PP1260: 1.304370
-PP1000: 1.030444
-VMON_9V: 9.139453
-VMON_5V: 5.017676
-VMON_3V3: 3.295569
-PP1800: 1.774878
-SOM_VMON: 1.290674
-SOM_VMON_1V2: 1.688672
-SOM_VMON_MGT: 1.513843
-SOM_VMON_1V8A: 1.596020
-SOM_VMON_C8: 1.546875
-SOM_VREF_CS: 0.001611
+12V: 12.294434
+CMON_SOM: 0.274731
+CMON_BOARD: 0.411694
+PP1200: 1.227832
+CMON_PP1200: 0.617139
+CMON_PP3300: 0.509985
+VMON_9V: 9.245801
+VMON_5V: 5.136914
+VMON_3V3: 3.318530
+PP1800: 2.280835
+SOM_VMON: 1.400244
+SOM_VMON_1V2: 2.552344
+SOM_VMON_MGT: 1.494507
+SOM_VMON_1V8A: 1.969849
+SOM_VMON_C8: 0.000000
+VREF_CS1: 0.000000
+VREF_CS2: 0.000000
+VREF_CS3: 0.000000
+$ sysmon
+12V: 12.294434
+CMON_SOM: 0.277148
+CMON_BOARD: 0.512402
+PP1200: 1.198828
+CMON_PP1200: 1.206885
+CMON_PP3300: 0.550269
+VMON_9V: 9.236133
+VMON_5V: 5.136914
+VMON_3V3: 3.318530
+PP1800: 2.280835
+SOM_VMON: 1.400244
+SOM_VMON_1V2: 2.552344
+SOM_VMON_MGT: 1.494507
+SOM_VMON_1V8A: 1.969849
+SOM_VMON_C8: 2.158374
+VREF_CS1: 0.001611
+VREF_CS2: 0.000806
+VREF_CS3: 0.000806
 ```
 
 ## Clock Generator
@@ -272,7 +289,7 @@
 
 The STM32 controls the power enable and power-on-reset for the FPGA, and
 monitors the signals for power good and configuration done. With an FPGA
-module installed, the FPGA module power good LED (on proto0 this is D21,
+module installed, the FPGA module power good LED (D21,
 just to the right and above the PCIe connector) will briefly turn on and
 then off again as the STM32 asserts control over the signal.
 [Chameleon FPGA Power/Boot Sequence State Machine](./fpgaboot_sm.md)
@@ -353,7 +370,7 @@
 
 ```
 $ board
-ver = 0
+BOARD_VERSION[2:0] = 4
 $ io get TP125
 TP125 = 0
 $ io get TP126
diff --git a/v3/ec/doc/images/proto1_hpd.png b/v3/ec/doc/images/proto1_hpd.png
new file mode 100644
index 0000000..95943a8
--- /dev/null
+++ b/v3/ec/doc/images/proto1_hpd.png
Binary files differ
diff --git a/v3/ec/doc/proto1_hpd.dot b/v3/ec/doc/proto1_hpd.dot
new file mode 100644
index 0000000..ca3a9cc
--- /dev/null
+++ b/v3/ec/doc/proto1_hpd.dot
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Graphviz "dot" source for the HPD connections.
+ */
+
+digraph {
+	node [shape=rect];
+	graph [pad="1", ranksep="1", nodesep="1"];
+	edge [color="#aaaaaa" labelangle="0" labeldistance="3"]
+
+	dp1 [label="DisplayPort 1"];
+	hdmi1 [label="HDMI 1"];
+
+	dp2 [label="DisplayPort 2"];
+	hdmi2 [label="HDMI 2"];
+
+	u128 [label="DP1 HPD mux (U128)\nDP_HPD_SEL"];
+	u130 [label="HDMI2 HPD mux (U130)\nHDMI_HPD_SEL"];
+	u129 [label="DP2 HPD mux (U129)\nDP_HPD_SEL"];
+	u131 [label="HDMI2 HPD mux (U131)\nHDMI_HPD_SEL"];
+
+	u9 [label="HDMI redriver (U110)"];
+	u10 [label="HDMI 1 demux (U10)\nHDMI1_GP213_CH_SEL"];
+	u3 [label="DP 1 demux (U3)\nDP1_PS8468_SW"];
+	u17 [label="MCDP2900 DP to HDMI (U17)"];
+	u11 [label="Port 1 FPGA mux (U11)\nSOMP1_MODE_SEL"];
+	u18 [label="Port 1 RX mux (U18)\nGP213_IT68051P1_CH_SEL"];
+
+	u28 [label="HDMI redriver (U112)"];
+	u29 [label="HDMI 2 demux (U29)\nHDMI2_GP213_CH_SEL"];
+	u22 [label="DP 2 demux (U22)\nDP2_PS8468_SW"];
+	u30 [label="MCDP2900 DP to HDMI (U30)"];
+	u14 [label="Port 2 FPGA mux (U14)\nSOMP2_MODE_SEL"];
+	u31 [label="Port 2 RX mux (U31)\nGP213_IT68051P0_CH_SEL"];
+
+	u125 [label="HPD mux (U125)\nHDMIRX_HPD_SEL"];
+	u127 [label="HPD mux (U127)\nHDMIRX_HPD_SEL"];
+
+	fpga [label="FPGA"];
+	u33 [label="IT68051 HDMI receiver (U33)"];
+
+	stm32_1 [label="STM32\nHDMI1_MCU_HPD"];
+	stm32_2 [label="STM32\nGP213_IT68051P1_HPD"];
+	stm32_3 [label="STM32\nDP1_MCU_HPD"];
+	stm32_4 [label="STM32\nHDMI2_MCU_HPD"];
+	stm32_5 [label="STM32\nDP2_MCU_HPD"];
+
+	fpga -> u11 [edgetooltip="DP213_SOMP1_HPD"];
+	u11 -> u3 [edgetooltip="DP1_PS8468_OUT2_HPD" taillabel="IN1\nSEL=0" headlabel="OUT2\nSW=1"];
+	u11 -> u10 [edgetooltip="HDMI_GP213_CH2_HPD" taillabel="IN2\nSEL=1" headlabel="IN2\nSEL=1"];
+	u10 -> u9;
+	u9 -> u130 [edgetooltip="HDMI1_RT_HPD" headlabel="S1\nSEL=0"];
+	stm32_1 -> u130 [headlabel="S2\nSEL=1"];
+	u130 -> hdmi1;
+
+	fpga -> u125 [edgetooltip="FPGA_HPD1" headlabel="S2\nSEL=1"];
+	stm32_2 -> u125 [headlabel="S1\nSEL=0"]; /* TODO change headlabel to "S1\nHPD_SEL=0"? */
+	u125 -> u18;
+	u18 -> u10 [edgetooltip="HDMI1_GP213_CH1_HPD" taillabel="IN2\nSEL=1" headlabel="IN1\nSEL=0"];
+	u18 -> u17 [taillabel="IN1\nSEL=0"];
+
+	u17 -> u3 [edgetooltip="DP1_PS8468_OUT1_HPD" headlabel="OUT1\nSW=0"];
+
+	u3 -> u128 [edgetooltip="PS8468 HPD_SRC" headlabel="S2\nSEL=1"];
+	stm32_3 -> u128 [headlabel="S1\nSEL=0"];
+	u128 -> dp1;
+
+
+	fpga -> u14 [edgetooltip="DP213_SOMP2"];
+	u14 -> u22 [edgetooltip="DP2_PS8468_OUT2_HPD" headlabel="OUT2\nSW=1" taillabel="IN1\nSEL=0"];
+	u14 -> u29 [edgetooltip="HDMI2_GP213_CH2_HPD" headlabel="IN2\nSEL=1" taillabel="IN2\nSEL=1"];
+	u29 -> u28;
+	u28 -> u131 [edgetooltop="HDMI2_RT_HPD" headlabel="S1\nSEL=0"];
+	stm32_4 -> u131 [headlabel="S2\nSEL=1"];
+	u131 -> hdmi2;
+
+	fpga -> u127 [edgetooltip="FPGA_HPD2" headlabel="S2\nSEL=1"];
+	u33 -> u127 [edgetooltip="GP213_IT68051P0_HPD" headlabel="S1\nSEL=0"];
+	u127 -> u31;
+	u31 -> u29 [edgetooltip="HDMI1_GP213_CH2_HPD" taillabel="IN2\nSEL=1" headlabel="IN1\nSEL=0"];
+	u31 -> u30 [taillabel="IN1\nSEL=0"];
+
+	u30 -> u22 [edgetooltip="DP2_PS8468_OUT1_HPD" headlabel="OUT1\nSW=0"];
+
+	u22 -> u129 [edgetooltip="PS8468 HPD_SRC" headlabel="S2\nSEL=1"];
+	stm32_5 -> u129 [headlabel="S1\nSEL=0"];
+	u129 -> dp2;
+
+	{rank=min; fpga}
+	{rank=same; u33}
+	{rank=same; u18; u11; u14; u31}
+	{rank=same; u3; u22; u10; u29}
+	{rank=same; u128; u130; u129; u131}
+	{rank=max; hdmi1; dp1; dp2; hdmi2}
+}
diff --git a/v3/ec/doc/videomux.dot b/v3/ec/doc/videomux.dot
index 53e1e4d..91e1012 100644
--- a/v3/ec/doc/videomux.dot
+++ b/v3/ec/doc/videomux.dot
@@ -63,4 +63,4 @@
 	{rank=same; u18; u11; u14; u31}
 	{rank=same; u33}
 	{rank=max; fpga}
-}
\ No newline at end of file
+}
diff --git a/v3/ec/include/io.h b/v3/ec/include/io.h
index 681e1e1..51ec6db 100644
--- a/v3/ec/include/io.h
+++ b/v3/ec/include/io.h
@@ -44,6 +44,10 @@
 	dp2_ps8468_rst_l,
 	dp1_hdmi_rst_l,
 	dp2_hdmi_rst_l,
+	hdmirx_hpd_sel,
+	hdmi_hpd_sel,
+	dp_hpd_sel,
+	it68051_en,
 	it68051p0_pwr_det,
 	it68051p1_pwr_det,
 	it68051_rst_l,
diff --git a/v3/ec/include/sysmon.h b/v3/ec/include/sysmon.h
index dce4d94..cc10a03 100644
--- a/v3/ec/include/sysmon.h
+++ b/v3/ec/include/sysmon.h
@@ -18,28 +18,29 @@
 	SYSMON_CMON_SOM,	/**< CMON_PP12000_SOM, scaled to 1V/A. */
 	SYSMON_CMON_BOARD,	/**< CMON_PP12000_CHAMELEON, scaled to 1V/A. */
 
-	/* These are connected to SYSMON1..8 through the "NO" terminals of the
-	 * analog switches (SYSMON_SEL_REGULATORS).
+	/* These are connected to SYSMON1..3 and 5..8 through the "NO"
+	 * terminals of the analog switches (SYSMON_SEL_REGULATORS).
 	 */
 	SYSMON_VMON_PP1200,	/**< PP1200, the 1.2V supply. */
-	SYSMON_VMON_PP1360,	/**< PP1360, the 1.36V supply. */
-	SYSMON_VMON_PP1260,	/**< PP1260, the 1.26V supply. */
-	SYSMON_VMON_PP1000,	/**< PP1000, the 1.00V supply. */
+	SYSMON_CMON_PP1200,	/**< Current monitor for PP1200 */
+	SYSMON_CMON_PP3300,	/**< Current monitor for PP3300 */
+	/* There is no connection through the "NO" terminal to SYSMON4 */
 	SYSMON_VMON_9V,		/**< VMON_9V, scaled to 2.25V. */
 	SYSMON_VMON_5V,		/**< VMON_5V, scaled to 1.25V. */
 	SYSMON_VMON_3V3,	/**< VMON_3V3, scaled to 2.2V. */
 	SYSMON_VMON_PP1800,	/**< PP1800, the 1.8V supply. */
 
-	/* These are connected to SYSMON1..6 through the "NC" terminals of the
-	 * analog switches (SYSMON_SEL_SOM). The "NC" terminals on the analog
-	 * switches for SYSMON7 and SYSMON8 are no-connect.
+	/* These are connected to SYSMON1..8 through the "NC" terminals of the
+	 * analog switches (SYSMON_SEL_SOM).
 	 */
 	SYSMON_SOM_VMON,	/**< VMON on the SOM. */
 	SYSMON_SOM_VMON_1V2,	/**< VMON_1V2 on the SOM. */
 	SYSMON_SOM_VMON_MGT,	/**< VMON_MGT on the SOM. */
 	SYSMON_SOM_VMON_1V8A,	/**< VMON_1V8A on the SOM. */
 	SYSMON_SOM_VMON_C8,	/**< "VMON_C8" on the SOM. */
-	SYSMON_SOM_VREF_CS,	/**< VREF_CS (CS=current sense), 0V. */
+	SYSMON_SOM_VREF_CS1,	/**< VREF_CS1 (CS=current sense), 0V. */
+	SYSMON_SOM_VREF_CS2,	/**< VREF_CS2 (CS=current sense), 0V. */
+	SYSMON_SOM_VREF_CS3,	/**< VREF_CS3 (CS=current sense), 0V. */
 
 	SYSMON_VMON_NUM_INPUTS	/**< Number of monitored inputs. */
 };
diff --git a/v3/ec/src/io.c b/v3/ec/src/io.c
index 3f3c7ad..abb6807 100644
--- a/v3/ec/src/io.c
+++ b/v3/ec/src/io.c
@@ -62,6 +62,10 @@
 	GPIO(videomux, dp2_ps8468_rst_l),
 	GPIO(videomux, dp1_hdmi_rst_l),
 	GPIO(videomux, dp2_hdmi_rst_l),
+	GPIO(videomux, hdmirx_hpd_sel),
+	GPIO(videomux, hdmi_hpd_sel),
+	GPIO(videomux, dp_hpd_sel),
+	GPIO(it68051, it68051_en),
 	GPIO(it68051, it68051p0_pwr_det),
 	GPIO(it68051, it68051p1_pwr_det),
 	GPIO(it68051, it68051_rst_l),
diff --git a/v3/ec/src/sysmon.c b/v3/ec/src/sysmon.c
index 0569254..3a62fbe 100644
--- a/v3/ec/src/sysmon.c
+++ b/v3/ec/src/sysmon.c
@@ -130,21 +130,16 @@
 				 .channel = 13,
 				 .scale_factor = 1.0,
 				 .name = "PP1200" },
-	[SYSMON_VMON_PP1360] = { .sel = SYSMON_SEL_REGULATORS,
+	[SYSMON_CMON_PP1200] = { .sel = SYSMON_SEL_REGULATORS,
 				 .adc_num = 0,
 				 .channel = 14,
 				 .scale_factor = 1.0,
-				 .name = "PP1360" },
-	[SYSMON_VMON_PP1260] = { .sel = SYSMON_SEL_REGULATORS,
+				 .name = "CMON_PP1200" },
+	[SYSMON_CMON_PP3300] = { .sel = SYSMON_SEL_REGULATORS,
 				 .adc_num = 0,
 				 .channel = 15,
 				 .scale_factor = 1.0,
-				 .name = "PP1260" },
-	[SYSMON_VMON_PP1000] = { .sel = SYSMON_SEL_REGULATORS,
-				 .adc_num = 1,
-				 .channel = 4,
-				 .scale_factor = 1.0,
-				 .name = "PP1000" },
+				 .name = "CMON_PP3300" },
 	[SYSMON_VMON_9V] = { .sel = SYSMON_SEL_REGULATORS,
 			     .adc_num = 1,
 			     .channel = 5,
@@ -191,11 +186,21 @@
 				 .channel = 5,
 				 .scale_factor = 1.0,
 				 .name = "SOM_VMON_C8" },
-	[SYSMON_SOM_VREF_CS] = { .sel = SYSMON_SEL_SOM,
+	[SYSMON_SOM_VREF_CS1] = { .sel = SYSMON_SEL_SOM,
 				 .adc_num = 1,
 				 .channel = 6,
 				 .scale_factor = 1.0,
-				 .name = "SOM_VREF_CS" },
+				 .name = "VREF_CS1" },
+	[SYSMON_SOM_VREF_CS2] = { .sel = SYSMON_SEL_SOM,
+				 .adc_num = 1,
+				 .channel = 7,
+				 .scale_factor = 1.0,
+				 .name = "VREF_CS2" },
+	[SYSMON_SOM_VREF_CS3] = { .sel = SYSMON_SEL_SOM,
+				 .adc_num = 1,
+				 .channel = 8,
+				 .scale_factor = 1.0,
+				 .name = "VREF_CS3" },
 
 };