drivers/storage: Rename confusing mmc constants
MMC_MODE_ should really be MMC_CAPS_ since it's only used by the caps
field. I also cleaned up other ones I found strange.
Generated with:
s/MMC_AUTO_CMD12/MMC_CAPS_AUTO_CMD12/g
s/MMC_MODE_HS_200MHz/MMC_CAPS_HS200/g
s/MMC_MODE_/MMC_CAPS_/g
s/MMC_HS_200MHZ/EXT_CSD_CARD_TYPE_HS200_1_8V/g
s/MMC_HS400/EXT_CSD_CARD_TYPE_HS400_1_8V/g
I'm honestly not quite sure what MMC_CAPS_HS is supposed to mean, or
what it encodes that the other CAPS don't.
BRANCH=grunt
BUG=b:122244718
TEST=Built grunt
Change-Id: Id5c83f4f2f197cd22549f521a2422919e51b8f9b
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1662621
Reviewed-by: Julius Werner <jwerner@chromium.org>
diff --git a/src/drivers/storage/dw_mmc.c b/src/drivers/storage/dw_mmc.c
index eab828a..c1c8451 100644
--- a/src/drivers/storage/dw_mmc.c
+++ b/src/drivers/storage/dw_mmc.c
@@ -422,13 +422,13 @@
ctrlr->mmc.bus_hz = ctrlr->mmc.f_min;
ctrlr->mmc.b_max = 65535; // Some controllers use 16-bit regs.
if (bus_width == 8) {
- ctrlr->mmc.caps |= MMC_MODE_8BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_4BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_8BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_4BIT;
} else {
- ctrlr->mmc.caps |= MMC_MODE_4BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_8BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_4BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_8BIT;
}
- ctrlr->mmc.caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+ ctrlr->mmc.caps |= MMC_CAPS_HS | MMC_CAPS_HS_52MHz | MMC_CAPS_HC;
ctrlr->mmc.send_cmd = &dwmci_send_cmd;
ctrlr->mmc.set_ios = &dwmci_set_ios;
diff --git a/src/drivers/storage/ipq40xx_mmc.c b/src/drivers/storage/ipq40xx_mmc.c
index 34fc893..de766c6 100644
--- a/src/drivers/storage/ipq40xx_mmc.c
+++ b/src/drivers/storage/ipq40xx_mmc.c
@@ -786,8 +786,8 @@
new_host->mmc.b_max = 512;
new_host->mmc.bus_width = bus_width;
new_host->mmc.bus_hz = new_host->mmc.f_min;
- new_host->mmc.caps = MMC_MODE_8BIT ;
- new_host->mmc.caps |= MMC_MODE_HC;
+ new_host->mmc.caps = MMC_CAPS_8BIT ;
+ new_host->mmc.caps |= MMC_CAPS_HC;
clock_config_mmc(&(new_host->mmc), 1);
clock_disable_mmc();
diff --git a/src/drivers/storage/ipq806x_mmc.c b/src/drivers/storage/ipq806x_mmc.c
index ec8f5e3..7dea56c 100644
--- a/src/drivers/storage/ipq806x_mmc.c
+++ b/src/drivers/storage/ipq806x_mmc.c
@@ -754,9 +754,9 @@
new_host->mmc.bus_width = bus_width;
new_host->mmc.bus_hz = new_host->mmc.f_min;
new_host->mmc.caps = (bus_width == 8) ?
- MMC_MODE_8BIT : MMC_MODE_4BIT;
- new_host->mmc.caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz |
- MMC_MODE_HC;
+ MMC_CAPS_8BIT : MMC_CAPS_4BIT;
+ new_host->mmc.caps |= MMC_CAPS_HS | MMC_CAPS_HS_52MHz |
+ MMC_CAPS_HC;
}
return new_host;
diff --git a/src/drivers/storage/mmc.c b/src/drivers/storage/mmc.c
index 35fe332..9a75aff 100644
--- a/src/drivers/storage/mmc.c
+++ b/src/drivers/storage/mmc.c
@@ -214,7 +214,7 @@
/* SPI multiblock writes terminate using a special
* token, not a STOP_TRANSMISSION request.
*/
- if ((block_count > 1) && !(media->ctrlr->caps & MMC_AUTO_CMD12)) {
+ if ((block_count > 1) && !(media->ctrlr->caps & MMC_CAPS_AUTO_CMD12)) {
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1b;
@@ -258,7 +258,7 @@
if (mmc_send_cmd(media->ctrlr, &cmd, &data))
return 0;
- if ((block_count > 1) && !(media->ctrlr->caps & MMC_AUTO_CMD12)) {
+ if ((block_count > 1) && !(media->ctrlr->caps & MMC_CAPS_AUTO_CMD12)) {
cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
cmd.cmdarg = 0;
cmd.resp_type = MMC_RSP_R1b;
@@ -363,7 +363,7 @@
(OCR_VOLTAGE_MASK | OCR_ACCESS_MODE);
cmd->cmdarg = media->ctrlr->voltages & mask;
- if (media->ctrlr->caps & MMC_MODE_HC)
+ if (media->ctrlr->caps & MMC_CAPS_HC)
cmd->cmdarg |= OCR_HCS;
}
cmd->flags = 0;
@@ -511,16 +511,16 @@
uint32_t clock = 1;
if (IS_SD(media)) {
- if (media->caps & MMC_MODE_HS)
+ if (media->caps & MMC_CAPS_HS)
clock = MMC_CLOCK_50MHZ;
else
clock = MMC_CLOCK_25MHZ;
} else {
- if (media->caps & MMC_MODE_HS) {
- if ((media->caps & MMC_MODE_HS_200MHz) ||
- (media->caps & MMC_MODE_HS400ES))
+ if (media->caps & MMC_CAPS_HS) {
+ if ((media->caps & MMC_CAPS_HS200) ||
+ (media->caps & MMC_CAPS_HS400ES))
clock = MMC_CLOCK_200MHZ;
- else if (media->caps & MMC_MODE_HS_52MHz)
+ else if (media->caps & MMC_CAPS_HS_52MHz)
clock = MMC_CLOCK_52MHZ;
else
clock = MMC_CLOCK_26MHZ;
@@ -540,7 +540,7 @@
return ret;
mmc_set_timing(media->ctrlr, MMC_TIMING_MMC_HS);
- media->caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ media->caps |= MMC_CAPS_HS_52MHz | MMC_CAPS_HS;
mmc_recalculate_clock(media);
ret = mmc_send_status(media, MMC_IO_RETRIES);
@@ -581,7 +581,7 @@
}
/* Set host controller to HS400 timing and frequency */
mmc_set_timing(media->ctrlr, MMC_TIMING_MMC_HS400ES);
- media->caps |= MMC_MODE_HS400ES | MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ media->caps |= MMC_CAPS_HS400ES | MMC_CAPS_HS_52MHz | MMC_CAPS_HS;
mmc_recalculate_clock(media);
@@ -610,7 +610,7 @@
return ret;
mmc_set_timing(media->ctrlr, MMC_TIMING_MMC_HS200);
- media->caps |= MMC_MODE_HS_200MHz | MMC_MODE_HS_52MHz | MMC_MODE_HS;
+ media->caps |= MMC_CAPS_HS200 | MMC_CAPS_HS_52MHz | MMC_CAPS_HS;
mmc_recalculate_clock(media);
@@ -635,12 +635,12 @@
if (err)
return err;
- if ((media->ctrlr->caps & MMC_MODE_HS400ES) &&
- (ext_csd[EXT_CSD_CARD_TYPE] & MMC_HS400) &&
+ if ((media->ctrlr->caps & MMC_CAPS_HS400ES) &&
+ (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_HS400_1_8V) &&
ext_csd[EXT_CSD_STROBE_SUPPORT])
err = mmc_select_hs400es(media);
- else if ((media->ctrlr->caps & MMC_MODE_HS_200MHz) &&
- (ext_csd[EXT_CSD_CARD_TYPE] & MMC_HS_200MHZ))
+ else if ((media->ctrlr->caps & MMC_CAPS_HS200) &&
+ (ext_csd[EXT_CSD_CARD_TYPE] & EXT_CSD_CARD_TYPE_HS200_1_8V))
err = mmc_select_hs200(media);
else
err = mmc_select_hs(media);
@@ -729,7 +729,7 @@
}
if (media->scr[0] & SD_DATA_4BIT)
- media->caps |= MMC_MODE_4BIT;
+ media->caps |= MMC_CAPS_4BIT;
/* Version 1.0 doesn't support switching */
if (media->version == SD_VERSION_1_0)
@@ -757,8 +757,8 @@
* This can avoid furthur problem when the card runs in different
* mode between the host.
*/
- if (!((media->ctrlr->caps & MMC_MODE_HS_52MHz) &&
- (media->ctrlr->caps & MMC_MODE_HS)))
+ if (!((media->ctrlr->caps & MMC_CAPS_HS_52MHz) &&
+ (media->ctrlr->caps & MMC_CAPS_HS)))
goto out;
err = sd_switch(media->ctrlr, SD_SWITCH_SWITCH, 0, 1,
@@ -767,7 +767,7 @@
return err;
if ((ntohl(switch_status[4]) & 0x0f000000) == 0x01000000) {
- media->caps |= MMC_MODE_HS;
+ media->caps |= MMC_CAPS_HS;
mmc_set_timing(media->ctrlr, MMC_TIMING_SD_HS);
}
@@ -955,7 +955,7 @@
media->caps &= media->ctrlr->caps;
if (IS_SD(media)) {
- if (media->caps & MMC_MODE_4BIT) {
+ if (media->caps & MMC_CAPS_4BIT) {
cmd.cmdidx = MMC_CMD_APP_CMD;
cmd.resp_type = MMC_RSP_R1;
cmd.cmdarg = media->rca << 16;
@@ -978,8 +978,8 @@
} else {
for (width = EXT_CSD_BUS_WIDTH_8; width >= 0; width--) {
/* If HS200 is switched, Bus Width has been 8-bit */
- if ((media->caps & MMC_MODE_HS_200MHz) ||
- (media->caps & MMC_MODE_HS400ES))
+ if ((media->caps & MMC_CAPS_HS200) ||
+ (media->caps & MMC_CAPS_HS400ES))
break;
/* Set the card to use 4 bit*/
diff --git a/src/drivers/storage/mmc.h b/src/drivers/storage/mmc.h
index f24b816..a093a13 100644
--- a/src/drivers/storage/mmc.h
+++ b/src/drivers/storage/mmc.h
@@ -38,17 +38,17 @@
#define MMC_VERSION_3 (MMC_VERSION_MMC | 0x30)
#define MMC_VERSION_4 (MMC_VERSION_MMC | 0x40)
-#define MMC_MODE_HS 0x001
-#define MMC_MODE_HS_52MHz 0x010
-#define MMC_MODE_HS_200MHz 0x020
-#define MMC_MODE_HS400 0x040
-#define MMC_MODE_HS400ES 0x080
-#define MMC_MODE_1V8_VDD 0x100
-#define MMC_MODE_4BIT 0x200
-#define MMC_MODE_8BIT 0x400
-#define MMC_MODE_SPI 0x800
-#define MMC_MODE_HC 0x1000
-#define MMC_AUTO_CMD12 0x2000
+#define MMC_CAPS_HS 0x001
+#define MMC_CAPS_HS_52MHz 0x010
+#define MMC_CAPS_HS200 0x020
+#define MMC_CAPS_HS400 0x040
+#define MMC_CAPS_HS400ES 0x080
+#define MMC_CAPS_1V8_VDD 0x100
+#define MMC_CAPS_4BIT 0x200
+#define MMC_CAPS_8BIT 0x400
+#define MMC_CAPS_SPI 0x800
+#define MMC_CAPS_HC 0x1000
+#define MMC_CAPS_AUTO_CMD12 0x2000
#define SD_DATA_4BIT 0x00040000
@@ -107,11 +107,6 @@
#define SD_HIGHSPEED_BUSY 0x00020000
#define SD_HIGHSPEED_SUPPORTED 0x00020000
-#define MMC_HS_TIMING 0x00000100
-#define MMC_HS_52MHZ 0x2
-#define MMC_HS_200MHZ 0x10
-#define MMC_HS400 0x40
-
#define OCR_BUSY 0x80000000
#define OCR_HCS 0x40000000
#define OCR_VOLTAGE_MASK 0x007FFF80
@@ -179,8 +174,10 @@
#define EXT_CSD_CMD_SET_SECURE (1 << 1)
#define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
-#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
-#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_HS200_1_8V (1 << 4)
+#define EXT_CSD_CARD_TYPE_HS400_1_8V (1 << 6)
#define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
#define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
diff --git a/src/drivers/storage/mtk_mmc.c b/src/drivers/storage/mtk_mmc.c
index 83b44df..9218ebf 100644
--- a/src/drivers/storage/mtk_mmc.c
+++ b/src/drivers/storage/mtk_mmc.c
@@ -490,13 +490,13 @@
ctrlr->mmc.b_max = 65535; /* Some controllers use 16-bit regs. */
if (bus_width == 8) {
- ctrlr->mmc.caps |= MMC_MODE_8BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_4BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_8BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_4BIT;
} else {
- ctrlr->mmc.caps |= MMC_MODE_4BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_8BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_4BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_8BIT;
}
- ctrlr->mmc.caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+ ctrlr->mmc.caps |= MMC_CAPS_HS | MMC_CAPS_HS_52MHz | MMC_CAPS_HC;
ctrlr->mmc.send_cmd = &mtk_mmc_send_cmd;
ctrlr->mmc.set_ios = &mtk_mmc_set_ios;
diff --git a/src/drivers/storage/s5p_mshc.c b/src/drivers/storage/s5p_mshc.c
index 2834fb0..9ede4e2 100644
--- a/src/drivers/storage/s5p_mshc.c
+++ b/src/drivers/storage/s5p_mshc.c
@@ -530,13 +530,13 @@
ctrlr->mmc.bus_hz = ctrlr->mmc.f_min;
ctrlr->mmc.b_max = 65535; // Some controllers use 16-bit regs.
if (bus_width == 8) {
- ctrlr->mmc.caps |= MMC_MODE_8BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_4BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_8BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_4BIT;
} else {
- ctrlr->mmc.caps |= MMC_MODE_4BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_8BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_4BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_8BIT;
}
- ctrlr->mmc.caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_HC;
+ ctrlr->mmc.caps |= MMC_CAPS_HS_52MHz | MMC_CAPS_HS | MMC_CAPS_HC;
ctrlr->mmc.send_cmd = &s5p_mshci_send_command;
ctrlr->mmc.set_ios = &s5p_mshci_set_ios;
diff --git a/src/drivers/storage/sdhci.c b/src/drivers/storage/sdhci.c
index f65e05e..fa8a783 100644
--- a/src/drivers/storage/sdhci.c
+++ b/src/drivers/storage/sdhci.c
@@ -397,7 +397,7 @@
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
- if (host->host_caps & MMC_AUTO_CMD12) {
+ if (host->host_caps & MMC_CAPS_AUTO_CMD12) {
if (sdhci_setup_adma(host, data, bbstate))
return -1;
@@ -415,7 +415,7 @@
sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
- if (data && (host->host_caps & MMC_AUTO_CMD12))
+ if (data && (host->host_caps & MMC_CAPS_AUTO_CMD12))
return sdhci_complete_adma(host, cmd);
start = timer_us(0);
@@ -682,7 +682,7 @@
sdhci_set_clock(host, mmc_ctrlr->bus_hz);
/* Switch to 1.8 volt for HS200 */
- if (mmc_ctrlr->caps & MMC_MODE_1V8_VDD)
+ if (mmc_ctrlr->caps & MMC_CAPS_1V8_VDD)
if (mmc_ctrlr->bus_hz == MMC_CLOCK_200MHZ)
sdhci_set_power(host, MMC_VDD_165_195_SHIFT);
@@ -709,7 +709,7 @@
sdhci_set_uhs_signaling(host, mmc_ctrlr->timing);
- if (host->host_caps & MMC_AUTO_CMD12) {
+ if (host->host_caps & MMC_CAPS_AUTO_CMD12) {
ctrl &= ~SDHCI_CTRL_DMA_MASK;
if (host->dma64)
ctrl |= SDHCI_CTRL_ADMA64;
@@ -738,10 +738,10 @@
if ((caps_1 & SDHCI_SUPPORT_HS400) &&
(host->quirks & SDHCI_QUIRK_SUPPORTS_HS400ES))
- host->host_caps |= MMC_MODE_HS400ES;
+ host->host_caps |= MMC_CAPS_HS400ES;
if (caps & SDHCI_CAN_DO_ADMA2)
- host->host_caps |= MMC_AUTO_CMD12;
+ host->host_caps |= MMC_CAPS_AUTO_CMD12;
/* get base clock frequency from CAP register */
if (!(host->quirks & SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN)) {
@@ -787,17 +787,17 @@
host->mmc_ctrlr.voltages |= host->voltages;
if (host->quirks & SDHCI_QUIRK_NO_EMMC_HS200)
- host->mmc_ctrlr.caps = MMC_MODE_HS | MMC_MODE_HS_52MHz |
- MMC_MODE_4BIT | MMC_MODE_HC;
+ host->mmc_ctrlr.caps = MMC_CAPS_HS | MMC_CAPS_HS_52MHz |
+ MMC_CAPS_4BIT | MMC_CAPS_HC;
else
- host->mmc_ctrlr.caps = MMC_MODE_HS | MMC_MODE_HS_52MHz |
- MMC_MODE_4BIT | MMC_MODE_HC | MMC_MODE_HS_200MHz;
+ host->mmc_ctrlr.caps = MMC_CAPS_HS | MMC_CAPS_HS_52MHz |
+ MMC_CAPS_4BIT | MMC_CAPS_HC | MMC_CAPS_HS200;
if (host->quirks & SDHCI_QUIRK_EMMC_1V8_POWER)
- host->mmc_ctrlr.caps |= MMC_MODE_1V8_VDD;
+ host->mmc_ctrlr.caps |= MMC_CAPS_1V8_VDD;
if (caps & SDHCI_CAN_DO_8BIT)
- host->mmc_ctrlr.caps |= MMC_MODE_8BIT;
+ host->mmc_ctrlr.caps |= MMC_CAPS_8BIT;
if (host->host_caps)
host->mmc_ctrlr.caps |= host->host_caps;
if (caps & SDHCI_CAN_64BIT)
diff --git a/src/drivers/storage/tegra_mmc.c b/src/drivers/storage/tegra_mmc.c
index 7016969..3fe951d 100644
--- a/src/drivers/storage/tegra_mmc.c
+++ b/src/drivers/storage/tegra_mmc.c
@@ -591,13 +591,13 @@
ctrlr->mmc.bus_hz = ctrlr->mmc.f_min;
ctrlr->mmc.b_max = 65535; // Some controllers use 16-bit regs.
if (bus_width == 8) {
- ctrlr->mmc.caps |= MMC_MODE_8BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_4BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_8BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_4BIT;
} else {
- ctrlr->mmc.caps |= MMC_MODE_4BIT;
- ctrlr->mmc.caps &= ~MMC_MODE_8BIT;
+ ctrlr->mmc.caps |= MMC_CAPS_4BIT;
+ ctrlr->mmc.caps &= ~MMC_CAPS_8BIT;
}
- ctrlr->mmc.caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
+ ctrlr->mmc.caps |= MMC_CAPS_HS | MMC_CAPS_HS_52MHz | MMC_CAPS_HC;
ctrlr->mmc.send_cmd = &tegra_mmc_send_cmd;
ctrlr->mmc.set_ios = &tegra_mmc_set_ios;
