depthcharge: spi-nand: Remove "wait until ready" in the write path
The "wait until ready" call reads the STATUS (0xC0) register, and waits
until the OIP (Operation-In-Progress) flag is cleared.
Currently, it is used after page program and block erase commands are sent,
to check they are completed and the device is idle.
The call is also used between the cache programand the page program
commands. However, the GD5F specification does not mention it as part
of the write sequence. Instead, the write sequence is specified as:
1) Program Load (cache program)
2) Write Enable
3) Program Execute (page program)
4) Read Status register and wait until ready
Intensive testing shows it's actually problematic, causing pages to not get
properly written. Remove it.
TEST=tested on Pistachio bring up board; works as expected;
Author: Ezequiel Garcia <email@example.com>
Signed-off-by: Ionela Voinescu <firstname.lastname@example.org>
Reviewed-by: Daniel Ehrenberg <email@example.com>
1 file changed