blob: dabf9dfc40658e5209a4812c6aba3e072ed5d496 [file] [log] [blame]
/*
* Copyright 2015 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
/* This file is autogenerated by the g_regs utility. Do not edit. */
#ifndef __EC_CHIP_G_CR50_FPGA_REGDEFS_H
#define __EC_CHIP_G_CR50_FPGA_REGDEFS_H
#define GC___REVA__ 1
#define GC___REVB__ 2
#define GC___REVC__ 3
#define GC___REVD__ 4
#define GC___REVE__ 5
#define GC___HAVEN__ 1
#define GC___MAJOR_REV__ __REVB__
#define GC___MINOR_REV__ 1
#define GC_PINMUX_DIOA0_SEL 0x19
#define GC_PINMUX_DIOA1_SEL 0x18
#define GC_PINMUX_DIOA2_SEL 0x17
#define GC_PINMUX_DIOA3_SEL 0x16
#define GC_PINMUX_DIOA4_SEL 0x15
#define GC_PINMUX_DIOA5_SEL 0x14
#define GC_PINMUX_DIOA6_SEL 0x13
#define GC_PINMUX_DIOA7_SEL 0x12
#define GC_PINMUX_DIOA8_SEL 0x11
#define GC_PINMUX_DIOA9_SEL 0x10
#define GC_PINMUX_DIOA10_SEL 0xf
#define GC_PINMUX_DIOA11_SEL 0xe
#define GC_PINMUX_DIOA12_SEL 0xd
#define GC_PINMUX_DIOA13_SEL 0xc
#define GC_PINMUX_DIOA14_SEL 0xb
#define GC_PINMUX_DIOB0_SEL 0xa
#define GC_PINMUX_DIOB1_SEL 0x9
#define GC_PINMUX_DIOB2_SEL 0x8
#define GC_PINMUX_DIOB3_SEL 0x7
#define GC_PINMUX_DIOB4_SEL 0x6
#define GC_PINMUX_DIOB5_SEL 0x5
#define GC_PINMUX_DIOB6_SEL 0x4
#define GC_PINMUX_DIOB7_SEL 0x3
#define GC_PINMUX_DIOM0_SEL 0x1e
#define GC_PINMUX_DIOM1_SEL 0x1d
#define GC_PINMUX_DIOM2_SEL 0x1c
#define GC_PINMUX_DIOM3_SEL 0x1b
#define GC_PINMUX_DIOM4_SEL 0x1a
#define GC_PINMUX_GPIO0_GPIO0_SEL 0x1
#define GC_PINMUX_GPIO0_GPIO1_SEL 0x2
#define GC_PINMUX_GPIO0_GPIO2_SEL 0x3
#define GC_PINMUX_GPIO0_GPIO3_SEL 0x4
#define GC_PINMUX_GPIO0_GPIO4_SEL 0x5
#define GC_PINMUX_GPIO0_GPIO5_SEL 0x6
#define GC_PINMUX_GPIO0_GPIO6_SEL 0x7
#define GC_PINMUX_GPIO0_GPIO7_SEL 0x8
#define GC_PINMUX_GPIO0_GPIO8_SEL 0x9
#define GC_PINMUX_GPIO0_GPIO9_SEL 0xa
#define GC_PINMUX_GPIO0_GPIO10_SEL 0xb
#define GC_PINMUX_GPIO0_GPIO11_SEL 0xc
#define GC_PINMUX_GPIO0_GPIO12_SEL 0xd
#define GC_PINMUX_GPIO0_GPIO13_SEL 0xe
#define GC_PINMUX_GPIO0_GPIO14_SEL 0xf
#define GC_PINMUX_GPIO0_GPIO15_SEL 0x10
#define GC_PINMUX_GPIO1_GPIO0_SEL 0x11
#define GC_PINMUX_GPIO1_GPIO1_SEL 0x12
#define GC_PINMUX_GPIO1_GPIO2_SEL 0x13
#define GC_PINMUX_GPIO1_GPIO3_SEL 0x14
#define GC_PINMUX_GPIO1_GPIO4_SEL 0x15
#define GC_PINMUX_GPIO1_GPIO5_SEL 0x16
#define GC_PINMUX_GPIO1_GPIO6_SEL 0x17
#define GC_PINMUX_GPIO1_GPIO7_SEL 0x18
#define GC_PINMUX_GPIO1_GPIO8_SEL 0x19
#define GC_PINMUX_GPIO1_GPIO9_SEL 0x1a
#define GC_PINMUX_GPIO1_GPIO10_SEL 0x1b
#define GC_PINMUX_GPIO1_GPIO11_SEL 0x1c
#define GC_PINMUX_GPIO1_GPIO12_SEL 0x1d
#define GC_PINMUX_GPIO1_GPIO13_SEL 0x1e
#define GC_PINMUX_GPIO1_GPIO14_SEL 0x1f
#define GC_PINMUX_GPIO1_GPIO15_SEL 0x20
#define GC_PINMUX_I2C0_SCL_SEL 0x21
#define GC_PINMUX_I2C0_SDA_SEL 0x22
#define GC_PINMUX_I2C1_SCL_SEL 0x23
#define GC_PINMUX_I2C1_SDA_SEL 0x24
#define GC_PINMUX_I2CS0_SCL_SEL 0x25
#define GC_PINMUX_I2CS0_SDA_SEL 0x26
#define GC_PINMUX_PMU_BROWNOUT_DET_SEL 0x27
#define GC_PINMUX_PMU_TESTBUS0_SEL 0x28
#define GC_PINMUX_PMU_TESTBUS1_SEL 0x29
#define GC_PINMUX_PMU_TESTBUS2_SEL 0x2a
#define GC_PINMUX_PMU_TESTBUS3_SEL 0x2b
#define GC_PINMUX_PMU_TESTBUS4_SEL 0x2c
#define GC_PINMUX_PMU_TESTBUS5_SEL 0x2d
#define GC_PINMUX_PMU_TESTBUS6_SEL 0x2e
#define GC_PINMUX_PMU_TESTBUS7_SEL 0x2f
#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL 0x30
#define GC_PINMUX_SPI1_SPICLK_SEL 0x31
#define GC_PINMUX_SPI1_SPICSB_SEL 0x32
#define GC_PINMUX_SPI1_SPIMISO_SEL 0x33
#define GC_PINMUX_SPI1_SPIMOSI_SEL 0x34
#define GC_PINMUX_SPS0_TESTBUS0_SEL 0x35
#define GC_PINMUX_SPS0_TESTBUS1_SEL 0x36
#define GC_PINMUX_SPS0_TESTBUS2_SEL 0x37
#define GC_PINMUX_SPS0_TESTBUS3_SEL 0x38
#define GC_PINMUX_SPS0_TESTBUS4_SEL 0x39
#define GC_PINMUX_SPS0_TESTBUS5_SEL 0x3a
#define GC_PINMUX_SPS0_TESTBUS6_SEL 0x3b
#define GC_PINMUX_SPS0_TESTBUS7_SEL 0x3c
#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL 0x3d
#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL 0x3e
#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL 0x3f
#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL 0x40
#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL 0x41
#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL 0x42
#define GC_PINMUX_UART0_CTS_SEL 0x43
#define GC_PINMUX_UART0_RTS_SEL 0x44
#define GC_PINMUX_UART0_RX_SEL 0x45
#define GC_PINMUX_UART0_TX_SEL 0x46
#define GC_PINMUX_UART1_CTS_SEL 0x47
#define GC_PINMUX_UART1_RTS_SEL 0x48
#define GC_PINMUX_UART1_RX_SEL 0x49
#define GC_PINMUX_UART1_TX_SEL 0x4a
#define GC_PINMUX_UART2_CTS_SEL 0x4b
#define GC_PINMUX_UART2_RTS_SEL 0x4c
#define GC_PINMUX_UART2_RX_SEL 0x4d
#define GC_PINMUX_UART2_TX_SEL 0x4e
#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x4f
#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x50
#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x51
#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x52
#define GC_PINMUX_USB0_EXT_RX_DMI_SEL 0x53
#define GC_PINMUX_USB0_EXT_RX_DPI_SEL 0x54
#define GC_PINMUX_USB0_EXT_RX_RCV_SEL 0x55
#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL 0x56
#define GC_PINMUX_USB0_EXT_TX_DMO_SEL 0x57
#define GC_PINMUX_USB0_EXT_TX_DPO_SEL 0x58
#define GC_PINMUX_USB0_EXT_TX_OEB_SEL 0x59
#define GC_PINMUX_VIO0_SEL 0x2
#define GC_PINMUX_VIO1_SEL 0x1
#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL 0x5a
#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL 0x5b
#define GC_PINMUX_XO0_TESTBUS0_SEL 0x5c
#define GC_PINMUX_XO0_TESTBUS1_SEL 0x5d
#define GC_PINMUX_XO0_TESTBUS2_SEL 0x5e
#define GC_PINMUX_XO0_TESTBUS3_SEL 0x5f
#define GC_PINMUX_XO0_TESTBUS4_SEL 0x60
#define GC_PINMUX_XO0_TESTBUS5_SEL 0x61
#define GC_PINMUX_XO0_TESTBUS6_SEL 0x62
#define GC_PINMUX_XO0_TESTBUS7_SEL 0x63
#define GC_PINMUX_SEL_COUNT 129
#define GC_EXCEPTNUM_RESET 0x1
#define GC_EXCEPTNUM_NMI 0x2
#define GC_EXCEPTNUM_HARDFAULT 0x3
#define GC_EXCEPTNUM_MEMORYMANAGEMENT 0x4
#define GC_EXCEPTNUM_BUSFAULT 0x5
#define GC_EXCEPTNUM_USAGEFAULT 0x6
#define GC_EXCEPTNUM_RESERVED7 0x7
#define GC_EXCEPTNUM_RESERVED8 0x8
#define GC_EXCEPTNUM_RESERVED9 0x9
#define GC_EXCEPTNUM_RESERVED10 0xa
#define GC_EXCEPTNUM_SVCALL 0xb
#define GC_EXCEPTNUM_DEBUGMONITOR 0xc
#define GC_EXCEPTNUM_RESERVED13 0xd
#define GC_EXCEPTNUM_PENDSV 0xe
#define GC_EXCEPTNUM_SYSTICK 0xf
#define GC_EXCEPTNUM_CRYPTO0_BREAK_INT 0x10
#define GC_EXCEPTNUM_CRYPTO0_DMEM_PTRS_OVERFLOW_INT 0x11
#define GC_EXCEPTNUM_CRYPTO0_DONE_WIPE_SECRETS_INT 0x12
#define GC_EXCEPTNUM_CRYPTO0_DRF_PTRS_OVERFLOW_INT 0x13
#define GC_EXCEPTNUM_CRYPTO0_HOST_CMD_DONE_INT 0x14
#define GC_EXCEPTNUM_CRYPTO0_HOST_CMD_RECV_INT 0x15
#define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 0x16
#define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 0x17
#define GC_EXCEPTNUM_CRYPTO0_MOD_OPERAND_OUT_OF_RANGE_INT 0x18
#define GC_EXCEPTNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 0x19
#define GC_EXCEPTNUM_CRYPTO0_PGM_FAULT_INT 0x1a
#define GC_EXCEPTNUM_CRYPTO0_TRAP_INT 0x1b
#define GC_EXCEPTNUM_DMA0_INTR_COMPLETE_CHAN_INT 0x1c
#define GC_EXCEPTNUM_DMA0_INTR_ERROR_CHAN_INT 0x1d
#define GC_EXCEPTNUM_DMA0_INTR_PROG_CHAN_INT 0x1e
#define GC_EXCEPTNUM_DMA0_INTR_TIMEOUT_CHAN_INT 0x1f
#define GC_EXCEPTNUM_FLASH0_EDONEINT 0x20
#define GC_EXCEPTNUM_FLASH0_PDONEINT 0x21
#define GC_EXCEPTNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 0x22
#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 0x23
#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 0x24
#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 0x25
#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 0x26
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 0x27
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 0x28
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 0x29
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 0x2a
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 0x2b
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 0x2c
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 0x2d
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 0x2e
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 0x2f
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 0x30
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 0x31
#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 0x32
#define GC_EXCEPTNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 0x33
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 0x34
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 0x35
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 0x36
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 0x37
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 0x38
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 0x39
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 0x3a
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 0x3b
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 0x3c
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 0x3d
#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 0x3e
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 0x3f
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 0x40
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 0x41
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 0x42
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 0x43
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 0x44
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 0x45
#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 0x46
#define GC_EXCEPTNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 0x47
#define GC_EXCEPTNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 0x48
#define GC_EXCEPTNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 0x49
#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 0x4a
#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 0x4b
#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 0x4c
#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 0x4d
#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 0x4e
#define GC_EXCEPTNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 0x4f
#define GC_EXCEPTNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 0x50
#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x51
#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x52
#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x53
#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x54
#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x55
#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x56
#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x57
#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x58
#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x59
#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x5a
#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x5b
#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x5c
#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x5d
#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x5e
#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x5f
#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x60
#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x61
#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x62
#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x63
#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x64
#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x65
#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x66
#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x67
#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x68
#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x69
#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x6a
#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x6b
#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x6c
#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x6d
#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x6e
#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x6f
#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x70
#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x71
#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x72
#define GC_EXCEPTNUM_I2C0_I2CINT 0x73
#define GC_EXCEPTNUM_I2C1_I2CINT 0x74
#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x75
#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x76
#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x77
#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_CIPHER_INT 0x78
#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 0x79
#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 0x7a
#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 0x7b
#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 0x7c
#define GC_EXCEPTNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 0x7d
#define GC_EXCEPTNUM_KEYMGR0_DSHA_INT 0x7e
#define GC_EXCEPTNUM_KEYMGR0_SHA_WFIFO_FULL_INT 0x7f
#define GC_EXCEPTNUM_PMU_INTR_WAKEUP_INT 0x80
#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_FED_INT 0x81
#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_RED_INT 0x82
#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 0x83
#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 0x84
#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 0x85
#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_FED_INT 0x86
#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_RED_INT 0x87
#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_FED_INT 0x88
#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_RED_INT 0x89
#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_FED_INT 0x8a
#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_RED_INT 0x8b
#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_FED_INT 0x8c
#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_RED_INT 0x8d
#define GC_EXCEPTNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 0x8e
#define GC_EXCEPTNUM_SPI0_SPITXINT 0x8f
#define GC_EXCEPTNUM_SPI1_SPITXINT 0x90
#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x91
#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x92
#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 0x93
#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 0x94
#define GC_EXCEPTNUM_SPS0_INTR_CMD_MEM_OVFL_INT 0x95
#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 0x96
#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 0x97
#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 0x98
#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 0x99
#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x9a
#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x9b
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x9c
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x9d
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x9e
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x9f
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0xa0
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0xa1
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0xa2
#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0xa3
#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0xa4
#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0xa5
#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0xa6
#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0xa7
#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0xa8
#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0xa9
#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0xaa
#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0xab
#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0xac
#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0xad
#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0xae
#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0xaf
#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0xb0
#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 0xb1
#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 0xb2
#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 0xb3
#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 0xb4
#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 0xb5
#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 0xb6
#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 0xb7
#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 0xb8
#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0xb9
#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0xba
#define GC_EXCEPTNUM_TRNG0_INTR_READ_EMPTY_INT 0xbb
#define GC_EXCEPTNUM_UART0_RXBINT 0xbc
#define GC_EXCEPTNUM_UART0_RXFINT 0xbd
#define GC_EXCEPTNUM_UART0_RXINT 0xbe
#define GC_EXCEPTNUM_UART0_RXOVINT 0xbf
#define GC_EXCEPTNUM_UART0_RXTOINT 0xc0
#define GC_EXCEPTNUM_UART0_TXINT 0xc1
#define GC_EXCEPTNUM_UART0_TXOVINT 0xc2
#define GC_EXCEPTNUM_UART1_RXBINT 0xc3
#define GC_EXCEPTNUM_UART1_RXFINT 0xc4
#define GC_EXCEPTNUM_UART1_RXINT 0xc5
#define GC_EXCEPTNUM_UART1_RXOVINT 0xc6
#define GC_EXCEPTNUM_UART1_RXTOINT 0xc7
#define GC_EXCEPTNUM_UART1_TXINT 0xc8
#define GC_EXCEPTNUM_UART1_TXOVINT 0xc9
#define GC_EXCEPTNUM_UART2_RXBINT 0xca
#define GC_EXCEPTNUM_UART2_RXFINT 0xcb
#define GC_EXCEPTNUM_UART2_RXINT 0xcc
#define GC_EXCEPTNUM_UART2_RXOVINT 0xcd
#define GC_EXCEPTNUM_UART2_RXTOINT 0xce
#define GC_EXCEPTNUM_UART2_TXINT 0xcf
#define GC_EXCEPTNUM_UART2_TXOVINT 0xd0
#define GC_EXCEPTNUM_USB0_USBINTR 0xd1
#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0xd2
#define GC_EXCEPTNUM_XO0_CLK_JTR_NOP_SEEN_INT 0xd3
#define GC_EXCEPTNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 0xd4
#define GC_EXCEPTNUM_XO0_CLK_TIMER_NOP_SEEN_INT 0xd5
#define GC_EXCEPTNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 0xd6
#define GC_EXCEPTNUM_XO0_FAST_CALIB_OVERFLOW_INT 0xd7
#define GC_EXCEPTNUM_XO0_FAST_CALIB_UNDERRUN_INT 0xd8
#define GC_EXCEPTNUM_XO0_SLOW_CALIB_OVERFLOW_INT 0xd9
#define GC_EXCEPTNUM_XO0_SLOW_CALIB_UNDERRUN_INT 0xda
#define GC_EXCEPTIONS_COUNT 218
#define GC_IRQNUM_RESET 0
#define GC_IRQNUM_NMI 0
#define GC_IRQNUM_HARDFAULT 0
#define GC_IRQNUM_MEMORYMANAGEMENT 0
#define GC_IRQNUM_BUSFAULT 0
#define GC_IRQNUM_USAGEFAULT 0
#define GC_IRQNUM_RESERVED7 0
#define GC_IRQNUM_RESERVED8 0
#define GC_IRQNUM_RESERVED9 0
#define GC_IRQNUM_RESERVED10 0
#define GC_IRQNUM_SVCALL 0
#define GC_IRQNUM_DEBUGMONITOR 0
#define GC_IRQNUM_RESERVED13 0
#define GC_IRQNUM_PENDSV 0
#define GC_IRQNUM_SYSTICK 0
#define GC_IRQNUM_CRYPTO0_BREAK_INT 0
#define GC_IRQNUM_CRYPTO0_DMEM_PTRS_OVERFLOW_INT 1
#define GC_IRQNUM_CRYPTO0_DONE_WIPE_SECRETS_INT 2
#define GC_IRQNUM_CRYPTO0_DRF_PTRS_OVERFLOW_INT 3
#define GC_IRQNUM_CRYPTO0_HOST_CMD_DONE_INT 4
#define GC_IRQNUM_CRYPTO0_HOST_CMD_RECV_INT 5
#define GC_IRQNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 6
#define GC_IRQNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 7
#define GC_IRQNUM_CRYPTO0_MOD_OPERAND_OUT_OF_RANGE_INT 8
#define GC_IRQNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 9
#define GC_IRQNUM_CRYPTO0_PGM_FAULT_INT 10
#define GC_IRQNUM_CRYPTO0_TRAP_INT 11
#define GC_IRQNUM_DMA0_INTR_COMPLETE_CHAN_INT 12
#define GC_IRQNUM_DMA0_INTR_ERROR_CHAN_INT 13
#define GC_IRQNUM_DMA0_INTR_PROG_CHAN_INT 14
#define GC_IRQNUM_DMA0_INTR_TIMEOUT_CHAN_INT 15
#define GC_IRQNUM_FLASH0_EDONEINT 16
#define GC_IRQNUM_FLASH0_PDONEINT 17
#define GC_IRQNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 18
#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 19
#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 20
#define GC_IRQNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 21
#define GC_IRQNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 22
#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 23
#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 24
#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 25
#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 26
#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 27
#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 28
#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 29
#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 30
#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 31
#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 32
#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 33
#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 34
#define GC_IRQNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 35
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 36
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 37
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 38
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 39
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 40
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 41
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 42
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 43
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 44
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 45
#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 46
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 47
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 48
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 49
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 50
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 51
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 52
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 53
#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 54
#define GC_IRQNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 55
#define GC_IRQNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 56
#define GC_IRQNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 57
#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 58
#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 59
#define GC_IRQNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 60
#define GC_IRQNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 61
#define GC_IRQNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 62
#define GC_IRQNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 63
#define GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 64
#define GC_IRQNUM_GPIO0_GPIO0INT 65
#define GC_IRQNUM_GPIO0_GPIO1INT 66
#define GC_IRQNUM_GPIO0_GPIO2INT 67
#define GC_IRQNUM_GPIO0_GPIO3INT 68
#define GC_IRQNUM_GPIO0_GPIO4INT 69
#define GC_IRQNUM_GPIO0_GPIO5INT 70
#define GC_IRQNUM_GPIO0_GPIO6INT 71
#define GC_IRQNUM_GPIO0_GPIO7INT 72
#define GC_IRQNUM_GPIO0_GPIO8INT 73
#define GC_IRQNUM_GPIO0_GPIO9INT 74
#define GC_IRQNUM_GPIO0_GPIO10INT 75
#define GC_IRQNUM_GPIO0_GPIO11INT 76
#define GC_IRQNUM_GPIO0_GPIO12INT 77
#define GC_IRQNUM_GPIO0_GPIO13INT 78
#define GC_IRQNUM_GPIO0_GPIO14INT 79
#define GC_IRQNUM_GPIO0_GPIO15INT 80
#define GC_IRQNUM_GPIO0_GPIOCOMBINT 81
#define GC_IRQNUM_GPIO1_GPIO0INT 82
#define GC_IRQNUM_GPIO1_GPIO1INT 83
#define GC_IRQNUM_GPIO1_GPIO2INT 84
#define GC_IRQNUM_GPIO1_GPIO3INT 85
#define GC_IRQNUM_GPIO1_GPIO4INT 86
#define GC_IRQNUM_GPIO1_GPIO5INT 87
#define GC_IRQNUM_GPIO1_GPIO6INT 88
#define GC_IRQNUM_GPIO1_GPIO7INT 89
#define GC_IRQNUM_GPIO1_GPIO8INT 90
#define GC_IRQNUM_GPIO1_GPIO9INT 91
#define GC_IRQNUM_GPIO1_GPIO10INT 92
#define GC_IRQNUM_GPIO1_GPIO11INT 93
#define GC_IRQNUM_GPIO1_GPIO12INT 94
#define GC_IRQNUM_GPIO1_GPIO13INT 95
#define GC_IRQNUM_GPIO1_GPIO14INT 96
#define GC_IRQNUM_GPIO1_GPIO15INT 97
#define GC_IRQNUM_GPIO1_GPIOCOMBINT 98
#define GC_IRQNUM_I2C0_I2CINT 99
#define GC_IRQNUM_I2C1_I2CINT 100
#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 101
#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 102
#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 103
#define GC_IRQNUM_KEYMGR0_AES_DONE_CIPHER_INT 104
#define GC_IRQNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 105
#define GC_IRQNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 106
#define GC_IRQNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 107
#define GC_IRQNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 108
#define GC_IRQNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 109
#define GC_IRQNUM_KEYMGR0_DSHA_INT 110
#define GC_IRQNUM_KEYMGR0_SHA_WFIFO_FULL_INT 111
#define GC_IRQNUM_PMU_INTR_WAKEUP_INT 112
#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT 113
#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT 114
#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 115
#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 116
#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 117
#define GC_IRQNUM_RBOX0_INTR_EC_RST_FED_INT 118
#define GC_IRQNUM_RBOX0_INTR_EC_RST_RED_INT 119
#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_FED_INT 120
#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_RED_INT 121
#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_FED_INT 122
#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_RED_INT 123
#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT 124
#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT 125
#define GC_IRQNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 126
#define GC_IRQNUM_SPI0_SPITXINT 127
#define GC_IRQNUM_SPI1_SPITXINT 128
#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 129
#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 130
#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 131
#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 132
#define GC_IRQNUM_SPS0_INTR_CMD_MEM_OVFL_INT 133
#define GC_IRQNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 134
#define GC_IRQNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 135
#define GC_IRQNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 136
#define GC_IRQNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 137
#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 138
#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 139
#define GC_IRQNUM_SPS0_SPSCTRLINT0 140
#define GC_IRQNUM_SPS0_SPSCTRLINT1 141
#define GC_IRQNUM_SPS0_SPSCTRLINT2 142
#define GC_IRQNUM_SPS0_SPSCTRLINT3 143
#define GC_IRQNUM_SPS0_SPSCTRLINT4 144
#define GC_IRQNUM_SPS0_SPSCTRLINT5 145
#define GC_IRQNUM_SPS0_SPSCTRLINT6 146
#define GC_IRQNUM_SPS0_SPSCTRLINT7 147
#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 148
#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 149
#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 150
#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 151
#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 152
#define GC_IRQNUM_TIMEHS0_TIMINT1 153
#define GC_IRQNUM_TIMEHS0_TIMINT2 154
#define GC_IRQNUM_TIMEHS0_TIMINTC 155
#define GC_IRQNUM_TIMEHS1_TIMINT1 156
#define GC_IRQNUM_TIMEHS1_TIMINT2 157
#define GC_IRQNUM_TIMEHS1_TIMINTC 158
#define GC_IRQNUM_TIMELS0_TIMINT0 159
#define GC_IRQNUM_TIMELS0_TIMINT1 160
#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 161
#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 162
#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 163
#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 164
#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 165
#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 166
#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 167
#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 168
#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 169
#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 170
#define GC_IRQNUM_TRNG0_INTR_READ_EMPTY_INT 171
#define GC_IRQNUM_UART0_RXBINT 172
#define GC_IRQNUM_UART0_RXFINT 173
#define GC_IRQNUM_UART0_RXINT 174
#define GC_IRQNUM_UART0_RXOVINT 175
#define GC_IRQNUM_UART0_RXTOINT 176
#define GC_IRQNUM_UART0_TXINT 177
#define GC_IRQNUM_UART0_TXOVINT 178
#define GC_IRQNUM_UART1_RXBINT 179
#define GC_IRQNUM_UART1_RXFINT 180
#define GC_IRQNUM_UART1_RXINT 181
#define GC_IRQNUM_UART1_RXOVINT 182
#define GC_IRQNUM_UART1_RXTOINT 183
#define GC_IRQNUM_UART1_TXINT 184
#define GC_IRQNUM_UART1_TXOVINT 185
#define GC_IRQNUM_UART2_RXBINT 186
#define GC_IRQNUM_UART2_RXFINT 187
#define GC_IRQNUM_UART2_RXINT 188
#define GC_IRQNUM_UART2_RXOVINT 189
#define GC_IRQNUM_UART2_RXTOINT 190
#define GC_IRQNUM_UART2_TXINT 191
#define GC_IRQNUM_UART2_TXOVINT 192
#define GC_IRQNUM_USB0_USBINTR 193
#define GC_IRQNUM_WATCHDOG0_WDOGINT 194
#define GC_IRQNUM_XO0_CLK_JTR_NOP_SEEN_INT 195
#define GC_IRQNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 196
#define GC_IRQNUM_XO0_CLK_TIMER_NOP_SEEN_INT 197
#define GC_IRQNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 198
#define GC_IRQNUM_XO0_FAST_CALIB_OVERFLOW_INT 199
#define GC_IRQNUM_XO0_FAST_CALIB_UNDERRUN_INT 200
#define GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT 201
#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT 202
#define GC_INTERRUPTS_COUNT 218
#define GC_CAMO0_BASE_ADDR 0x40560000
#define GC_CAMO_BASE_ADDR 0x40560000
#define GC_CRYPTO0_BASE_ADDR 0x40420000
#define GC_CRYPTO_BASE_ADDR 0x40420000
#define GC_DMA0_BASE_ADDR 0x40430000
#define GC_DMA_BASE_ADDR 0x40430000
#define GC_FLASH0_BASE_ADDR 0x40720000
#define GC_FLASH_BASE_ADDR 0x40720000
#define GC_FUSE0_BASE_ADDR 0x40450000
#define GC_FUSE_BASE_ADDR 0x40450000
#define GC_GLOBALSEC_BASE_ADDR 0x40090000
#define GC_GPIO0_BASE_ADDR 0x40200000
#define GC_GPIO_BASE_ADDR 0x40200000
#define GC_GPIO1_BASE_ADDR 0x40210000
#define GC_I2C0_BASE_ADDR 0x40630000
#define GC_I2C_BASE_ADDR 0x40630000
#define GC_I2C1_BASE_ADDR 0x40640000
#define GC_I2CS0_BASE_ADDR 0x40530000
#define GC_I2CS_BASE_ADDR 0x40530000
#define GC_KEYMGR0_BASE_ADDR 0x40570000
#define GC_KEYMGR_BASE_ADDR 0x40570000
#define GC_PINMUX_BASE_ADDR 0x40060000
#define GC_PMU_BASE_ADDR 0x40000000
#define GC_M3_BASE_ADDR 0xe0000000
#define GC_RBOX0_BASE_ADDR 0x40550000
#define GC_RBOX_BASE_ADDR 0x40550000
#define GC_RDD0_BASE_ADDR 0x40440000
#define GC_RDD_BASE_ADDR 0x40440000
#define GC_RTC0_BASE_ADDR 0x400a0000
#define GC_RTC_BASE_ADDR 0x400a0000
#define GC_SPI0_BASE_ADDR 0x40700000
#define GC_SPI_BASE_ADDR 0x40700000
#define GC_SPI1_BASE_ADDR 0x40710000
#define GC_SPS0_BASE_ADDR 0x40510000
#define GC_SPS_BASE_ADDR 0x40510000
#define GC_SWDP0_BASE_ADDR 0x40520000
#define GC_SWDP_BASE_ADDR 0x40520000
#define GC_TEMP0_BASE_ADDR 0x40400000
#define GC_TEMP_BASE_ADDR 0x40400000
#define GC_TIMEHS0_BASE_ADDR 0x40650000
#define GC_TIMEHS_BASE_ADDR 0x40650000
#define GC_TIMEHS1_BASE_ADDR 0x40660000
#define GC_TIMELS0_BASE_ADDR 0x40540000
#define GC_TIMELS_BASE_ADDR 0x40540000
#define GC_TIMEUS0_BASE_ADDR 0x40670000
#define GC_TIMEUS_BASE_ADDR 0x40670000
#define GC_TRNG0_BASE_ADDR 0x40410000
#define GC_TRNG_BASE_ADDR 0x40410000
#define GC_UART0_BASE_ADDR 0x40600000
#define GC_UART_BASE_ADDR 0x40600000
#define GC_UART1_BASE_ADDR 0x40610000
#define GC_UART2_BASE_ADDR 0x40620000
#define GC_USB0_BASE_ADDR 0x40300000
#define GC_USB_BASE_ADDR 0x40300000
#define GC_VOLT0_BASE_ADDR 0x40460000
#define GC_VOLT_BASE_ADDR 0x40460000
#define GC_WATCHDOG0_BASE_ADDR 0x40500000
#define GC_WATCHDOG_BASE_ADDR 0x40500000
#define GC_XO0_BASE_ADDR 0x400b0000
#define GC_XO_BASE_ADDR 0x400b0000
#define GC_CAMO_BREACH_COUNT_OFFSET 0x0
#define GC_CAMO_BREACH_COUNT_DEFAULT 0x0
#define GC_CAMO_CLEAR_COUNTER_OFFSET 0x4
#define GC_CAMO_CLEAR_COUNTER_DEFAULT 0x0
#define GC_CAMO_VERSION_OFFSET 0x8
#define GC_CAMO_VERSION_DEFAULT 0x1014125
#define GC_CRYPTO_VERSION_OFFSET 0x0
#define GC_CRYPTO_VERSION_DEFAULT 0x101424a
#define GC_CRYPTO_CONTROL_OFFSET 0x4
#define GC_CRYPTO_CONTROL_DEFAULT 0x0
#define GC_CRYPTO_PARITY_CFG_OFFSET 0x8
#define GC_CRYPTO_PARITY_CFG_DEFAULT 0x10
#define GC_CRYPTO_IMEM_SCRUB_RANGE_OFFSET 0xc
#define GC_CRYPTO_IMEM_SCRUB_RANGE_DEFAULT 0x3ff
#define GC_CRYPTO_DMEM_SCRUB_RANGE_OFFSET 0x10
#define GC_CRYPTO_DMEM_SCRUB_RANGE_DEFAULT 0x7f
#define GC_CRYPTO_INT_ENABLE_OFFSET 0x14
#define GC_CRYPTO_INT_ENABLE_DEFAULT 0x0
#define GC_CRYPTO_INT_STATE_OFFSET 0x18
#define GC_CRYPTO_INT_STATE_DEFAULT 0x0
#define GC_CRYPTO_INT_TEST_OFFSET 0x1c
#define GC_CRYPTO_INT_TEST_DEFAULT 0x0
#define GC_CRYPTO_HOST_CMD_OFFSET 0x20
#define GC_CRYPTO_HOST_CMD_DEFAULT 0xffffffff
#define GC_CRYPTO_INSTR_OFFSET 0x24
#define GC_CRYPTO_INSTR_DEFAULT 0x0
#define GC_CRYPTO_STATUS_OFFSET 0x28
#define GC_CRYPTO_STATUS_DEFAULT 0x0
#define GC_CRYPTO_AUX_CC_OFFSET 0x2c
#define GC_CRYPTO_AUX_CC_DEFAULT 0x0
#define GC_CRYPTO_RAND_STALL_CTL_OFFSET 0x30
#define GC_CRYPTO_RAND_STALL_CTL_DEFAULT 0x5
#define GC_CRYPTO_RAND256_OFFSET 0x34
#define GC_CRYPTO_RAND256_DEFAULT 0x1
#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x38
#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0
#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x3c
#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0
#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_OFFSET 0x40
#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_DEFAULT 0x0
#define GC_CRYPTO_PGM_LFSR_OFFSET 0x44
#define GC_CRYPTO_PGM_LFSR_DEFAULT 0x0
#define GC_CRYPTO_DEBUG_BRKPT0_OFFSET 0x48
#define GC_CRYPTO_DEBUG_BRKPT0_DEFAULT 0x0
#define GC_CRYPTO_DEBUG_BRKPT1_OFFSET 0x4c
#define GC_CRYPTO_DEBUG_BRKPT1_DEFAULT 0x0
#define GC_CRYPTO_WIPE_SECRETS_OFFSET 0x50
#define GC_CRYPTO_WIPE_SECRETS_DEFAULT 0x0
#define GC_CRYPTO_DMEM_DUMMY_OFFSET 0x4000
#define GC_CRYPTO_IMEM_DUMMY_OFFSET 0x8000
#define GC_DMA_VERSION_OFFSET 0x0
#define GC_DMA_VERSION_DEFAULT 0x101424a
#define GC_DMA_INT_ENABLE_OFFSET 0x4
#define GC_DMA_INT_ENABLE_DEFAULT 0x0
#define GC_DMA_INT_STATE_OFFSET 0x8
#define GC_DMA_INT_STATE_DEFAULT 0x0
#define GC_DMA_INT_TEST_OFFSET 0xc
#define GC_DMA_INT_TEST_DEFAULT 0x0
#define GC_DMA_START_CHAN0_OFFSET 0x100
#define GC_DMA_START_CHAN0_DEFAULT 0x0
#define GC_DMA_STOP_CHAN0_OFFSET 0x104
#define GC_DMA_STOP_CHAN0_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN0_OFFSET 0x108
#define GC_DMA_CTRL_CHAN0_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN0_OFFSET 0x10c
#define GC_DMA_SRC_ADDR_CHAN0_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN0_OFFSET 0x110
#define GC_DMA_DST_ADDR_CHAN0_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x114
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN0_OFFSET 0x118
#define GC_DMA_PROG_COUNT_CHAN0_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x11c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_OFFSET 0x120
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN0_OFFSET 0x124
#define GC_DMA_PAUSE_COUNTER_CHAN0_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN0_OFFSET 0x128
#define GC_DMA_FSM_STATE_CHAN0_DEFAULT 0x1
#define GC_DMA_START_CHAN1_OFFSET 0x200
#define GC_DMA_START_CHAN1_DEFAULT 0x0
#define GC_DMA_STOP_CHAN1_OFFSET 0x204
#define GC_DMA_STOP_CHAN1_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN1_OFFSET 0x208
#define GC_DMA_CTRL_CHAN1_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN1_OFFSET 0x20c
#define GC_DMA_SRC_ADDR_CHAN1_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN1_OFFSET 0x210
#define GC_DMA_DST_ADDR_CHAN1_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x214
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN1_OFFSET 0x218
#define GC_DMA_PROG_COUNT_CHAN1_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x21c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_OFFSET 0x220
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN1_OFFSET 0x224
#define GC_DMA_PAUSE_COUNTER_CHAN1_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN1_OFFSET 0x228
#define GC_DMA_FSM_STATE_CHAN1_DEFAULT 0x1
#define GC_DMA_START_CHAN2_OFFSET 0x300
#define GC_DMA_START_CHAN2_DEFAULT 0x0
#define GC_DMA_STOP_CHAN2_OFFSET 0x304
#define GC_DMA_STOP_CHAN2_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN2_OFFSET 0x308
#define GC_DMA_CTRL_CHAN2_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN2_OFFSET 0x30c
#define GC_DMA_SRC_ADDR_CHAN2_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN2_OFFSET 0x310
#define GC_DMA_DST_ADDR_CHAN2_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x314
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN2_OFFSET 0x318
#define GC_DMA_PROG_COUNT_CHAN2_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x31c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_OFFSET 0x320
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN2_OFFSET 0x324
#define GC_DMA_PAUSE_COUNTER_CHAN2_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN2_OFFSET 0x328
#define GC_DMA_FSM_STATE_CHAN2_DEFAULT 0x1
#define GC_DMA_START_CHAN3_OFFSET 0x400
#define GC_DMA_START_CHAN3_DEFAULT 0x0
#define GC_DMA_STOP_CHAN3_OFFSET 0x404
#define GC_DMA_STOP_CHAN3_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN3_OFFSET 0x408
#define GC_DMA_CTRL_CHAN3_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN3_OFFSET 0x40c
#define GC_DMA_SRC_ADDR_CHAN3_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN3_OFFSET 0x410
#define GC_DMA_DST_ADDR_CHAN3_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x414
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN3_OFFSET 0x418
#define GC_DMA_PROG_COUNT_CHAN3_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x41c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_OFFSET 0x420
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN3_OFFSET 0x424
#define GC_DMA_PAUSE_COUNTER_CHAN3_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN3_OFFSET 0x428
#define GC_DMA_FSM_STATE_CHAN3_DEFAULT 0x1
#define GC_DMA_START_CHAN4_OFFSET 0x500
#define GC_DMA_START_CHAN4_DEFAULT 0x0
#define GC_DMA_STOP_CHAN4_OFFSET 0x504
#define GC_DMA_STOP_CHAN4_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN4_OFFSET 0x508
#define GC_DMA_CTRL_CHAN4_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN4_OFFSET 0x50c
#define GC_DMA_SRC_ADDR_CHAN4_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN4_OFFSET 0x510
#define GC_DMA_DST_ADDR_CHAN4_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x514
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN4_OFFSET 0x518
#define GC_DMA_PROG_COUNT_CHAN4_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x51c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_OFFSET 0x520
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN4_OFFSET 0x524
#define GC_DMA_PAUSE_COUNTER_CHAN4_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN4_OFFSET 0x528
#define GC_DMA_FSM_STATE_CHAN4_DEFAULT 0x1
#define GC_DMA_START_CHAN5_OFFSET 0x600
#define GC_DMA_START_CHAN5_DEFAULT 0x0
#define GC_DMA_STOP_CHAN5_OFFSET 0x604
#define GC_DMA_STOP_CHAN5_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN5_OFFSET 0x608
#define GC_DMA_CTRL_CHAN5_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN5_OFFSET 0x60c
#define GC_DMA_SRC_ADDR_CHAN5_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN5_OFFSET 0x610
#define GC_DMA_DST_ADDR_CHAN5_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x614
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN5_OFFSET 0x618
#define GC_DMA_PROG_COUNT_CHAN5_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x61c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_OFFSET 0x620
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN5_OFFSET 0x624
#define GC_DMA_PAUSE_COUNTER_CHAN5_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN5_OFFSET 0x628
#define GC_DMA_FSM_STATE_CHAN5_DEFAULT 0x1
#define GC_DMA_START_CHAN6_OFFSET 0x700
#define GC_DMA_START_CHAN6_DEFAULT 0x0
#define GC_DMA_STOP_CHAN6_OFFSET 0x704
#define GC_DMA_STOP_CHAN6_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN6_OFFSET 0x708
#define GC_DMA_CTRL_CHAN6_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN6_OFFSET 0x70c
#define GC_DMA_SRC_ADDR_CHAN6_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN6_OFFSET 0x710
#define GC_DMA_DST_ADDR_CHAN6_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x714
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN6_OFFSET 0x718
#define GC_DMA_PROG_COUNT_CHAN6_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x71c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_OFFSET 0x720
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN6_OFFSET 0x724
#define GC_DMA_PAUSE_COUNTER_CHAN6_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN6_OFFSET 0x728
#define GC_DMA_FSM_STATE_CHAN6_DEFAULT 0x1
#define GC_DMA_START_CHAN7_OFFSET 0x800
#define GC_DMA_START_CHAN7_DEFAULT 0x0
#define GC_DMA_STOP_CHAN7_OFFSET 0x804
#define GC_DMA_STOP_CHAN7_DEFAULT 0x0
#define GC_DMA_CTRL_CHAN7_OFFSET 0x808
#define GC_DMA_CTRL_CHAN7_DEFAULT 0xa
#define GC_DMA_SRC_ADDR_CHAN7_OFFSET 0x80c
#define GC_DMA_SRC_ADDR_CHAN7_DEFAULT 0x0
#define GC_DMA_DST_ADDR_CHAN7_OFFSET 0x810
#define GC_DMA_DST_ADDR_CHAN7_DEFAULT 0x0
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x814
#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x3ff
#define GC_DMA_PROG_COUNT_CHAN7_OFFSET 0x818
#define GC_DMA_PROG_COUNT_CHAN7_DEFAULT 0x0
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x81c
#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x0
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_OFFSET 0x820
#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_DEFAULT 0xf9f
#define GC_DMA_PAUSE_COUNTER_CHAN7_OFFSET 0x824
#define GC_DMA_PAUSE_COUNTER_CHAN7_DEFAULT 0x0
#define GC_DMA_FSM_STATE_CHAN7_OFFSET 0x828
#define GC_DMA_FSM_STATE_CHAN7_DEFAULT 0x1
#define GC_FLASH_FSH_PE_CONTROL0_OFFSET 0x0
#define GC_FLASH_FSH_PE_CONTROL0_DEFAULT 0x0
#define GC_FLASH_FSH_PE_CONTROL0_PROG 0x27182818
#define GC_FLASH_FSH_PE_CONTROL0_READ 0x16021765
#define GC_FLASH_FSH_PE_CONTROL0_BULKERASE 0x1d1e2bad
#define GC_FLASH_FSH_PE_CONTROL0_ERASE 0x31415927
#define GC_FLASH_FSH_PE_CONTROL1_OFFSET 0x4
#define GC_FLASH_FSH_PE_CONTROL1_DEFAULT 0x0
#define GC_FLASH_FSH_PE_CONTROL1_PROG 0x27182818
#define GC_FLASH_FSH_PE_CONTROL1_READ 0x16021765
#define GC_FLASH_FSH_PE_CONTROL1_BULKERASE 0x1d1e2bad
#define GC_FLASH_FSH_PE_CONTROL1_ERASE 0x31415927
#define GC_FLASH_FSH_TRANS_OFFSET 0x8
#define GC_FLASH_FSH_TRANS_DEFAULT 0x0
#define GC_FLASH_FSH_PROTECT_INFO1_OFFSET 0xc
#define GC_FLASH_FSH_PROTECT_INFO1_DEFAULT 0x0
#define GC_FLASH_FSH_ENABLE_INFO0_SHADOW_READ_OFFSET 0x10
#define GC_FLASH_FSH_ENABLE_INFO0_SHADOW_READ_DEFAULT 0x0
#define GC_FLASH_FSH_ICTRL_OFFSET 0x14
#define GC_FLASH_FSH_ICTRL_DEFAULT 0x0
#define GC_FLASH_FSH_ISTATE_OFFSET 0x18
#define GC_FLASH_FSH_ISTATE_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD0_UNLOCK_OFFSET 0x1c
#define GC_FLASH_FSH_OVRD0_UNLOCK_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD0_UNLOCK_KEY 0x13806488
#define GC_FLASH_FSH_OVRD1_UNLOCK_OFFSET 0x20
#define GC_FLASH_FSH_OVRD1_UNLOCK_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD1_UNLOCK_KEY 0x13806488
#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_OFFSET 0x24
#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_OFFSET 0x28
#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET 0x2c
#define GC_FLASH_FSH_OVRD_SIGVAL_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET 0x30
#define GC_FLASH_FSH_OVRD_SIGEN_DEFAULT 0x0
#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_OFFSET 0x34
#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_DEFAULT 0x0
#define GC_FLASH_FSH_DOUT_VAL0_OFFSET 0x38
#define GC_FLASH_FSH_DOUT_VAL0_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD_SIGVAL_TC0_OFFSET 0x3c
#define GC_FLASH_FSH_OVRD_SIGVAL_TC0_DEFAULT 0x0
#define GC_FLASH_FSH_DOUT_VAL1_OFFSET 0x40
#define GC_FLASH_FSH_DOUT_VAL1_DEFAULT 0x0
#define GC_FLASH_FSH_OVRD_SIGVAL_TC1_OFFSET 0x44
#define GC_FLASH_FSH_OVRD_SIGVAL_TC1_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA0_OFFSET 0x48
#define GC_FLASH_FSH_WR_DATA0_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA1_OFFSET 0x4c
#define GC_FLASH_FSH_WR_DATA1_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA2_OFFSET 0x50
#define GC_FLASH_FSH_WR_DATA2_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA3_OFFSET 0x54
#define GC_FLASH_FSH_WR_DATA3_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA4_OFFSET 0x58
#define GC_FLASH_FSH_WR_DATA4_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA5_OFFSET 0x5c
#define GC_FLASH_FSH_WR_DATA5_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA6_OFFSET 0x60
#define GC_FLASH_FSH_WR_DATA6_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA7_OFFSET 0x64
#define GC_FLASH_FSH_WR_DATA7_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA8_OFFSET 0x68
#define GC_FLASH_FSH_WR_DATA8_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA9_OFFSET 0x6c
#define GC_FLASH_FSH_WR_DATA9_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA10_OFFSET 0x70
#define GC_FLASH_FSH_WR_DATA10_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA11_OFFSET 0x74
#define GC_FLASH_FSH_WR_DATA11_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA12_OFFSET 0x78
#define GC_FLASH_FSH_WR_DATA12_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA13_OFFSET 0x7c
#define GC_FLASH_FSH_WR_DATA13_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA14_OFFSET 0x80
#define GC_FLASH_FSH_WR_DATA14_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA15_OFFSET 0x84
#define GC_FLASH_FSH_WR_DATA15_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA16_OFFSET 0x88
#define GC_FLASH_FSH_WR_DATA16_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA17_OFFSET 0x8c
#define GC_FLASH_FSH_WR_DATA17_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA18_OFFSET 0x90
#define GC_FLASH_FSH_WR_DATA18_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA19_OFFSET 0x94
#define GC_FLASH_FSH_WR_DATA19_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA20_OFFSET 0x98
#define GC_FLASH_FSH_WR_DATA20_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA21_OFFSET 0x9c
#define GC_FLASH_FSH_WR_DATA21_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA22_OFFSET 0xa0
#define GC_FLASH_FSH_WR_DATA22_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA23_OFFSET 0xa4
#define GC_FLASH_FSH_WR_DATA23_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA24_OFFSET 0xa8
#define GC_FLASH_FSH_WR_DATA24_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA25_OFFSET 0xac
#define GC_FLASH_FSH_WR_DATA25_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA26_OFFSET 0xb0
#define GC_FLASH_FSH_WR_DATA26_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA27_OFFSET 0xb4
#define GC_FLASH_FSH_WR_DATA27_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA28_OFFSET 0xb8
#define GC_FLASH_FSH_WR_DATA28_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA29_OFFSET 0xbc
#define GC_FLASH_FSH_WR_DATA29_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA30_OFFSET 0xc0
#define GC_FLASH_FSH_WR_DATA30_DEFAULT 0x0
#define GC_FLASH_FSH_WR_DATA31_OFFSET 0xc4
#define GC_FLASH_FSH_WR_DATA31_DEFAULT 0x0
#define GC_FLASH_FSH_PE_EN_OFFSET 0xc8
#define GC_FLASH_FSH_PE_EN_DEFAULT 0x0
#define GC_FLASH_FSH_PE_EN_KEY 0xb11924e1
#define GC_FLASH_FSH_REDUN0_OFFSET 0xcc
#define GC_FLASH_FSH_REDUN0_DEFAULT 0x0
#define GC_FLASH_FSH_REDUN1_OFFSET 0xd0
#define GC_FLASH_FSH_REDUN1_DEFAULT 0x0
#define GC_FLASH_FSH_ERROR_OFFSET 0xd4
#define GC_FLASH_FSH_ERROR_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_OFFSET 0xd8
#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_DEFAULT 0x1
#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_OFFSET 0xdc
#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_OFFSET 0xe0
#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_OFFSET 0xe4
#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_OFFSET 0xe8
#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_OFFSET 0xec
#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_OFFSET 0xf0
#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_OFFSET 0xf4
#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_OFFSET 0xf8
#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_OFFSET 0xfc
#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_OFFSET 0x100
#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_OFFSET 0x104
#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_DEFAULT 0x1
#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_OFFSET 0x108
#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_DEFAULT 0x37e
#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_OFFSET 0x10c
#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_OFFSET 0x110
#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_DEFAULT 0x265
#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_OFFSET 0x114
#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_DEFAULT 0x1a7
#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_OFFSET 0x118
#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_DEFAULT 0x1d6
#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_OFFSET 0x11c
#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_DEFAULT 0x1a6
#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_OFFSET 0x120
#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_DEFAULT 0x1d7
#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_OFFSET 0x124
#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_DEFAULT 0x1
#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_OFFSET 0x128
#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_DEFAULT 0x1d7
#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_OFFSET 0x12c
#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_DEFAULT 0x8d
#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_OFFSET 0x130
#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_DEFAULT 0x264
#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_OFFSET 0x134
#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_DEFAULT 0x1
#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_OFFSET 0x138
#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_DEFAULT 0xbb12
#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_OFFSET 0x13c
#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_OFFSET 0x140
#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_DEFAULT 0xb9f9
#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_OFFSET 0x144
#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_DEFAULT 0x1
#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_OFFSET 0x148
#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_DEFAULT 0xb96b
#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_OFFSET 0x14c
#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_DEFAULT 0x8d
#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_OFFSET 0x150
#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_DEFAULT 0xb9f8
#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_OFFSET 0x154
#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_DEFAULT 0x1
#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_OFFSET 0x158
#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_DEFAULT 0xc585
#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_OFFSET 0x15c
#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_OFFSET 0x160
#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_DEFAULT 0xc46c
#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_OFFSET 0x164
#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_DEFAULT 0x1
#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_OFFSET 0x168
#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_DEFAULT 0xb96b
#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_OFFSET 0x16c
#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_DEFAULT 0x0
#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_OFFSET 0x170
#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_DEFAULT 0xc46c
#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_OFFSET 0x174
#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_DEFAULT 0x8d
#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_OFFSET 0x178
#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_DEFAULT 0xc46b
#define GC_FLASH_FSH_DBG_OFFSET 0x17c
#define GC_FLASH_FSH_DBG_DEFAULT 0x0
#define GC_FLASH_FSH_ITCR_OFFSET 0xf00
#define GC_FLASH_FSH_ITCR_DEFAULT 0x0
#define GC_FLASH_FSH_ITOP_OFFSET 0xf04
#define GC_FLASH_FSH_ITOP_DEFAULT 0x0
#define GC_FUSE_STATUS_OFFSET 0x0
#define GC_FUSE_STATUS_DEFAULT 0x0
#define GC_FUSE_READ_START_OFFSET 0x4
#define GC_FUSE_READ_START_DEFAULT 0x0
#define GC_FUSE_READ_START_DISABLE 0x0
#define GC_FUSE_READ_START_ENABLE 0xc8eca61e
#define GC_FUSE_PROG_START_OFFSET 0x8
#define GC_FUSE_PROG_START_DEFAULT 0x0
#define GC_FUSE_PROG_START_DISABLE 0x0
#define GC_FUSE_PROG_START_ENABLE 0xdc98157b
#define GC_FUSE_OVERRIDE_START_OFFSET 0xc
#define GC_FUSE_OVERRIDE_START_DEFAULT 0x0
#define GC_FUSE_OVERRIDE_START_DISABLE 0x0
#define GC_FUSE_OVERRIDE_START_ENABLE 0x894e4cf3
#define GC_FUSE_FPGA_MODEL_CTRL_OFFSET 0x10
#define GC_FUSE_FPGA_MODEL_CTRL_DEFAULT 0x0
#define GC_FUSE_SCRUB_PRBS_CLK_DIV_OFFSET 0x14
#define GC_FUSE_SCRUB_PRBS_CLK_DIV_DEFAULT 0xffffff
#define GC_FUSE_SCRUB_PRBS_THRESHOLD_VAL_OFFSET 0x18
#define GC_FUSE_SCRUB_PRBS_THRESHOLD_VAL_DEFAULT 0x7fff
#define GC_FUSE_SCRUB_ENABLE_OFFSET 0x1c
#define GC_FUSE_SCRUB_ENABLE_DEFAULT 0x0
#define GC_FUSE_SCRUB_ENABLE_DISABLE 0x0
#define GC_FUSE_SCRUB_ENABLE_ENABLE 0x5
#define GC_FUSE_ERROR_INJECT_OFFSET 0x20
#define GC_FUSE_ERROR_INJECT_DEFAULT 0x0
#define GC_FUSE_ERROR_INJECT_DISABLE 0x0
#define GC_FUSE_ERROR_INJECT_ENABLE 0x690c7334
#define GC_FUSE_VDDQ_RAMP_TIMING_OFFSET 0x24
#define GC_FUSE_VDDQ_RAMP_TIMING_DEFAULT 0x1d4c0
#define GC_FUSE_ANTEST_EN_OFFSET 0x28
#define GC_FUSE_ANTEST_EN_DEFAULT 0x0
#define GC_FUSE_VERSION_OFFSET 0x2c
#define GC_FUSE_VERSION_DEFAULT 0x1014125
#define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET 0x30
#define GC_FUSE_BNK0_INTG_CHKSUM_DEFAULT 0x55000000
#define GC_FUSE_BNK0_INTG_LOCK_OFFSET 0x34
#define GC_FUSE_BNK0_INTG_LOCK_DEFAULT 0x55555550
#define GC_FUSE_DS_GRP0_OFFSET 0x38
#define GC_FUSE_DS_GRP0_DEFAULT 0x55555400
#define GC_FUSE_DS_GRP1_OFFSET 0x3c
#define GC_FUSE_DS_GRP1_DEFAULT 0x55555400
#define GC_FUSE_DS_GRP2_OFFSET 0x40
#define GC_FUSE_DS_GRP2_DEFAULT 0x55555400
#define GC_FUSE_DEV_ID0_OFFSET 0x44
#define GC_FUSE_DEV_ID0_DEFAULT 0x0
#define GC_FUSE_DEV_ID1_OFFSET 0x48
#define GC_FUSE_DEV_ID1_DEFAULT 0x0
#define GC_FUSE_BNK1_INTG_CHKSUM_OFFSET 0x4c
#define GC_FUSE_BNK1_INTG_CHKSUM_DEFAULT 0x55000000
#define GC_FUSE_BNK1_INTG_LOCK_OFFSET 0x50
#define GC_FUSE_BNK1_INTG_LOCK_DEFAULT 0x55555550
#define GC_FUSE_LB0_POST_OVRD_OFFSET 0x54
#define GC_FUSE_LB0_POST_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB0_POST_PATCNT_OFFSET 0x58
#define GC_FUSE_LB0_POST_PATCNT_DEFAULT 0x55555554
#define GC_FUSE_LB0_POST_WARMUP_OVRD_OFFSET 0x5c
#define GC_FUSE_LB0_POST_WARMUP_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB0_POST_WARMUP_CNT_OFFSET 0x60
#define GC_FUSE_LB0_POST_WARMUP_CNT_DEFAULT 0x55555554
#define GC_FUSE_LB1_POST_OVRD_OFFSET 0x64
#define GC_FUSE_LB1_POST_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB1_POST_PATCNT_OFFSET 0x68
#define GC_FUSE_LB1_POST_PATCNT_DEFAULT 0x55555554
#define GC_FUSE_LB1_POST_WARMUP_OVRD_OFFSET 0x6c
#define GC_FUSE_LB1_POST_WARMUP_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB1_POST_WARMUP_CNT_OFFSET 0x70
#define GC_FUSE_LB1_POST_WARMUP_CNT_DEFAULT 0x55555554
#define GC_FUSE_LB2_POST_OVRD_OFFSET 0x74
#define GC_FUSE_LB2_POST_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB2_POST_PATCNT_OFFSET 0x78
#define GC_FUSE_LB2_POST_PATCNT_DEFAULT 0x55555554
#define GC_FUSE_LB2_POST_WARMUP_OVRD_OFFSET 0x7c
#define GC_FUSE_LB2_POST_WARMUP_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB2_POST_WARMUP_CNT_OFFSET 0x80
#define GC_FUSE_LB2_POST_WARMUP_CNT_DEFAULT 0x55555554
#define GC_FUSE_LB3_POST_OVRD_OFFSET 0x84
#define GC_FUSE_LB3_POST_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB3_POST_PATCNT_OFFSET 0x88
#define GC_FUSE_LB3_POST_PATCNT_DEFAULT 0x55555554
#define GC_FUSE_LB3_POST_WARMUP_OVRD_OFFSET 0x8c
#define GC_FUSE_LB3_POST_WARMUP_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB3_POST_WARMUP_CNT_OFFSET 0x90
#define GC_FUSE_LB3_POST_WARMUP_CNT_DEFAULT 0x55555554
#define GC_FUSE_LB4_POST_OVRD_OFFSET 0x94
#define GC_FUSE_LB4_POST_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB4_POST_PATCNT_OFFSET 0x98
#define GC_FUSE_LB4_POST_PATCNT_DEFAULT 0x55555554
#define GC_FUSE_LB4_POST_WARMUP_OVRD_OFFSET 0x9c
#define GC_FUSE_LB4_POST_WARMUP_OVRD_DEFAULT 0x55555550
#define GC_FUSE_LB4_POST_WARMUP_CNT_OFFSET 0xa0
#define GC_FUSE_LB4_POST_WARMUP_CNT_DEFAULT 0x55555554
#define GC_FUSE_MBIST_POST_SEQ_OFFSET 0xa4
#define GC_FUSE_MBIST_POST_SEQ_DEFAULT 0x54000000
#define GC_FUSE_LBIST_POST_SEQ_OFFSET 0xa8
#define GC_FUSE_LBIST_POST_SEQ_DEFAULT 0x54000000
#define GC_FUSE_LBIST_VIA_TAP_DIS_OFFSET 0xac
#define GC_FUSE_LBIST_VIA_TAP_DIS_DEFAULT 0x55555550
#define GC_FUSE_MBIST_VIA_TAP_DIS_OFFSET 0xb0
#define GC_FUSE_MBIST_VIA_TAP_DIS_DEFAULT 0x55555550
#define GC_FUSE_TAP_DISABLE_OFFSET 0xb4
#define GC_FUSE_TAP_DISABLE_DEFAULT 0x55555550
#define GC_FUSE_RNGBIST_AR_EN_OFFSET 0xb8
#define GC_FUSE_RNGBIST_AR_EN_DEFAULT 0x55555550
#define GC_FUSE_TESTMODE_KEYS_EN_OFFSET 0xbc
#define GC_FUSE_TESTMODE_KEYS_EN_DEFAULT 0x55555550
#define GC_FUSE_PKG_ID_OFFSET 0xc0
#define GC_FUSE_PKG_ID_DEFAULT 0x55555550
#define GC_FUSE_BIN_ID_OFFSET 0xc4
#define GC_FUSE_BIN_ID_DEFAULT 0x55555550
#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_OFFSET 0xc8
#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x55555500
#define GC_FUSE_RC_JTR_OSC48_CC_EN_OFFSET 0xcc
#define GC_FUSE_RC_JTR_OSC48_CC_EN_DEFAULT 0x55555550
#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_OFFSET 0xd0
#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x55555500
#define GC_FUSE_RC_JTR_OSC60_CC_EN_OFFSET 0xd4
#define GC_FUSE_RC_JTR_OSC60_CC_EN_DEFAULT 0x55555550
#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_OFFSET 0xd8
#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x55555500
#define GC_FUSE_RC_TIMER_OSC48_CC_EN_OFFSET 0xdc
#define GC_FUSE_RC_TIMER_OSC48_CC_EN_DEFAULT 0x55555550
#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_OFFSET 0xe0
#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x55555540
#define GC_FUSE_RC_TIMER_OSC48_FC_EN_OFFSET 0xe4
#define GC_FUSE_RC_TIMER_OSC48_FC_EN_DEFAULT 0x55555550
#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_OFFSET 0xe8
#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_DEFAULT 0x55555500
#define GC_FUSE_RC_RTC_OSC256K_CC_EN_OFFSET 0xec
#define GC_FUSE_RC_RTC_OSC256K_CC_EN_DEFAULT 0x55555550
#define GC_FUSE_SEL_VREG_REG_EN_OFFSET 0xf0
#define GC_FUSE_SEL_VREG_REG_EN_DEFAULT 0x55555550
#define GC_FUSE_SEL_VREF_REG_OFFSET 0xf4
#define GC_FUSE_SEL_VREF_REG_DEFAULT 0x55555550
#define GC_FUSE_SEL_VREF_BATMON_EN_OFFSET 0xf8
#define GC_FUSE_SEL_VREF_BATMON_EN_DEFAULT 0x55555550
#define GC_FUSE_SEL_VREF_BATMON_OFFSET 0xfc
#define GC_FUSE_SEL_VREF_BATMON_DEFAULT 0x55555550
#define GC_FUSE_X_OSC_LDO_CTRL_EN_OFFSET 0x100
#define GC_FUSE_X_OSC_LDO_CTRL_EN_DEFAULT 0x55555550
#define GC_FUSE_X_OSC_LDO_CTRL_OFFSET 0x104
#define GC_FUSE_X_OSC_LDO_CTRL_DEFAULT 0x55555550
#define GC_FUSE_TEMP_OFFSET_CAL_OFFSET 0x108
#define GC_FUSE_TEMP_OFFSET_CAL_DEFAULT 0x55555000
#define GC_FUSE_TRNG_LDO_CTRL_EN_OFFSET 0x10c
#define GC_FUSE_TRNG_LDO_CTRL_EN_DEFAULT 0x55555550
#define GC_FUSE_TRNG_LDO_CTRL_OFFSET 0x110
#define GC_FUSE_TRNG_LDO_CTRL_DEFAULT 0x55555540
#define GC_FUSE_TRNG_ANALOG_CTRL_EN_OFFSET 0x114
#define GC_FUSE_TRNG_ANALOG_CTRL_EN_DEFAULT 0x55555550
#define GC_FUSE_TRNG_ANALOG_CTRL_OFFSET 0x118
#define GC_FUSE_TRNG_ANALOG_CTRL_DEFAULT 0x55555550
#define GC_FUSE_EXT_XTAL_PDB_OFFSET 0x11c
#define GC_FUSE_EXT_XTAL_PDB_DEFAULT 0x55555554
#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x120
#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x55555550
#define GC_FUSE_OBFUSCATION_EN_OFFSET 0x124
#define GC_FUSE_OBFUSCATION_EN_DEFAULT 0x55555550
#define GC_FUSE_HIK_CREATE_LOCK_OFFSET 0x128
#define GC_FUSE_HIK_CREATE_LOCK_DEFAULT 0x55555550
#define GC_FUSE_BNK2_INTG_CHKSUM_OFFSET 0x12c
#define GC_FUSE_BNK2_INTG_CHKSUM_DEFAULT 0x55000000
#define GC_FUSE_BNK2_INTG_LOCK_OFFSET 0x130
#define GC_FUSE_BNK2_INTG_LOCK_DEFAULT 0x55555550
#define GC_FUSE_TESTMODE_OTPW_DIS_OFFSET 0x134
#define GC_FUSE_TESTMODE_OTPW_DIS_DEFAULT 0x55555550
#define GC_FUSE_HKEY_WDOG_TIMER_EN_OFFSET 0x138
#define GC_FUSE_HKEY_WDOG_TIMER_EN_DEFAULT 0x55555550
#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_OFFSET 0x13c
#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x55555550
#define GC_FUSE_ALERT_RSP_CFG_OFFSET 0x140
#define GC_FUSE_ALERT_RSP_CFG_DEFAULT 0x55555500
#define GC_FUSE_BNK3_INTG_CHKSUM_OFFSET 0x144
#define GC_FUSE_BNK3_INTG_CHKSUM_DEFAULT 0x55000000
#define GC_FUSE_BNK3_INTG_LOCK_OFFSET 0x148
#define GC_FUSE_BNK3_INTG_LOCK_DEFAULT 0x55555550
#define GC_FUSE_FW_DEFINED_DATA_BLK0_OFFSET 0x14c
#define GC_FUSE_FW_DEFINED_DATA_BLK0_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_OFFSET 0x150
#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_DEFAULT 0x55550000
#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_OFFSET 0x154
#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_DEFAULT 0x55555000
#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_OFFSET 0x158
#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_OFFSET 0x15c
#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_DEFAULT 0x55555500
#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x160
#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x55555554
#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x164
#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x55555500
#define GC_FUSE_RBOX_CLK10HZ_COUNT_OFFSET 0x168
#define GC_FUSE_RBOX_CLK10HZ_COUNT_DEFAULT 0x55550000
#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_OFFSET 0x16c
#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x55550000
#define GC_FUSE_RBOX_LONG_DELAY_COUNT_OFFSET 0x170
#define GC_FUSE_RBOX_LONG_DELAY_COUNT_DEFAULT 0x55555500
#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_OFFSET 0x174
#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_DEFAULT 0x55550000
#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x178
#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x55555554
#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x17c
#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x55555554
#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x180
#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x55555554
#define GC_FUSE_RBOX_KEY_COMBO0_VAL_OFFSET 0x184
#define GC_FUSE_RBOX_KEY_COMBO0_VAL_DEFAULT 0x55555500
#define GC_FUSE_RBOX_KEY_COMBO1_VAL_OFFSET 0x188
#define GC_FUSE_RBOX_KEY_COMBO1_VAL_DEFAULT 0x55555500
#define GC_FUSE_RBOX_KEY_COMBO2_VAL_OFFSET 0x18c
#define GC_FUSE_RBOX_KEY_COMBO2_VAL_DEFAULT 0x55555500
#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_OFFSET 0x190
#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x55555500
#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_OFFSET 0x194
#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x55555500
#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_OFFSET 0x198
#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x55555500
#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_OFFSET 0x19c
#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_DEFAULT 0x55555554
#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_OFFSET 0x1a0
#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_DEFAULT 0x55555554
#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_OFFSET 0x1a4
#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_DEFAULT 0x55555554
#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_OFFSET 0x1a8
#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_AC_PRESENT_OFFSET 0x1ac
#define GC_FUSE_RBOX_POL_AC_PRESENT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_PWRB_IN_OFFSET 0x1b0
#define GC_FUSE_RBOX_POL_PWRB_IN_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_PWRB_OUT_OFFSET 0x1b4
#define GC_FUSE_RBOX_POL_PWRB_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_KEY0_IN_OFFSET 0x1b8
#define GC_FUSE_RBOX_POL_KEY0_IN_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_KEY0_OUT_OFFSET 0x1bc
#define GC_FUSE_RBOX_POL_KEY0_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_KEY1_IN_OFFSET 0x1c0
#define GC_FUSE_RBOX_POL_KEY1_IN_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_KEY1_OUT_OFFSET 0x1c4
#define GC_FUSE_RBOX_POL_KEY1_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_EC_RST_OFFSET 0x1c8
#define GC_FUSE_RBOX_POL_EC_RST_DEFAULT 0x55555554
#define GC_FUSE_RBOX_POL_BATT_DISABLE_OFFSET 0x1cc
#define GC_FUSE_RBOX_POL_BATT_DISABLE_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_AC_PRESENT_OFFSET 0x1d0
#define GC_FUSE_RBOX_TERM_AC_PRESENT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_ENTERING_RW_OFFSET 0x1d4
#define GC_FUSE_RBOX_TERM_ENTERING_RW_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_PWRB_IN_OFFSET 0x1d8
#define GC_FUSE_RBOX_TERM_PWRB_IN_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_PWRB_OUT_OFFSET 0x1dc
#define GC_FUSE_RBOX_TERM_PWRB_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_KEY0_IN_OFFSET 0x1e0
#define GC_FUSE_RBOX_TERM_KEY0_IN_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_KEY0_OUT_OFFSET 0x1e4
#define GC_FUSE_RBOX_TERM_KEY0_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_KEY1_IN_OFFSET 0x1e8
#define GC_FUSE_RBOX_TERM_KEY1_IN_DEFAULT 0x55555554
#define GC_FUSE_RBOX_TERM_KEY1_OUT_OFFSET 0x1ec
#define GC_FUSE_RBOX_TERM_KEY1_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_OFFSET 0x1f0
#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_OFFSET 0x1f4
#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_OFFSET 0x1f8
#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x55555554
#define GC_FUSE_RBOX_DRIVE_EC_RST_OFFSET 0x1fc
#define GC_FUSE_RBOX_DRIVE_EC_RST_DEFAULT 0x55555554
#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x200
#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_DEFAULT 0x55555554
#define GC_FUSE_BNK4_INTG_CHKSUM_OFFSET 0x204
#define GC_FUSE_BNK4_INTG_CHKSUM_DEFAULT 0x55000000
#define GC_FUSE_BNK4_INTG_LOCK_OFFSET 0x208
#define GC_FUSE_BNK4_INTG_LOCK_DEFAULT 0x55555550
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x20c
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x210
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x214
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x218
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x21c
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x220
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x55555500
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x224
#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x55555540
#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_OFFSET 0x228
#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_DEFAULT 0x0
#define GC_FUSE_PROG_BNK0_INTG_LOCK_OFFSET 0x22c
#define GC_FUSE_PROG_BNK0_INTG_LOCK_DEFAULT 0x0
#define GC_FUSE_PROG_DS_GRP0_OFFSET 0x230
#define GC_FUSE_PROG_DS_GRP0_DEFAULT 0x0
#define GC_FUSE_PROG_DS_GRP1_OFFSET 0x234
#define GC_FUSE_PROG_DS_GRP1_DEFAULT 0x0
#define GC_FUSE_PROG_DS_GRP2_OFFSET 0x238
#define GC_FUSE_PROG_DS_GRP2_DEFAULT 0x0
#define GC_FUSE_PROG_DEV_ID0_OFFSET 0x23c
#define GC_FUSE_PROG_DEV_ID0_DEFAULT 0x0
#define GC_FUSE_PROG_DEV_ID1_OFFSET 0x240
#define GC_FUSE_PROG_DEV_ID1_DEFAULT 0x0
#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_OFFSET 0x244
#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_DEFAULT 0x0
#define GC_FUSE_PROG_BNK1_INTG_LOCK_OFFSET 0x248
#define GC_FUSE_PROG_BNK1_INTG_LOCK_DEFAULT 0x0
#define GC_FUSE_PROG_LB0_POST_OVRD_OFFSET 0x24c
#define GC_FUSE_PROG_LB0_POST_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB0_POST_PATCNT_OFFSET 0x250
#define GC_FUSE_PROG_LB0_POST_PATCNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_OFFSET 0x254
#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_OFFSET 0x258
#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB1_POST_OVRD_OFFSET 0x25c
#define GC_FUSE_PROG_LB1_POST_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB1_POST_PATCNT_OFFSET 0x260
#define GC_FUSE_PROG_LB1_POST_PATCNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_OFFSET 0x264
#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_OFFSET 0x268
#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB2_POST_OVRD_OFFSET 0x26c
#define GC_FUSE_PROG_LB2_POST_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB2_POST_PATCNT_OFFSET 0x270
#define GC_FUSE_PROG_LB2_POST_PATCNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_OFFSET 0x274
#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_OFFSET 0x278
#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB3_POST_OVRD_OFFSET 0x27c
#define GC_FUSE_PROG_LB3_POST_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB3_POST_PATCNT_OFFSET 0x280
#define GC_FUSE_PROG_LB3_POST_PATCNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_OFFSET 0x284
#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_OFFSET 0x288
#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB4_POST_OVRD_OFFSET 0x28c
#define GC_FUSE_PROG_LB4_POST_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB4_POST_PATCNT_OFFSET 0x290
#define GC_FUSE_PROG_LB4_POST_PATCNT_DEFAULT 0x0
#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_OFFSET 0x294
#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_DEFAULT 0x0
#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_OFFSET 0x298
#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_DEFAULT 0x0
#define GC_FUSE_PROG_MBIST_POST_SEQ_OFFSET 0x29c
#define GC_FUSE_PROG_MBIST_POST_SEQ_DEFAULT 0x0
#define GC_FUSE_PROG_LBIST_POST_SEQ_OFFSET 0x2a0
#define GC_FUSE_PROG_LBIST_POST_SEQ_DEFAULT 0x0
#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_OFFSET 0x2a4
#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_DEFAULT 0x0
#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_OFFSET 0x2a8
#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_DEFAULT 0x0
#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_OFFSET 0x2ac
#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_DEFAULT 0x0
#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_OFFSET 0x2b0
#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_DEFAULT 0x0
#define GC_FUSE_PROG_TAP_DISABLE_OFFSET 0x2b4
#define GC_FUSE_PROG_TAP_DISABLE_DEFAULT 0x0
#define GC_FUSE_PROG_RNGBIST_AR_EN_OFFSET 0x2b8
#define GC_FUSE_PROG_RNGBIST_AR_EN_DEFAULT 0x0
#define GC_FUSE_PROG_TESTMODE_KEYS_EN_OFFSET 0x2bc
#define GC_FUSE_PROG_TESTMODE_KEYS_EN_DEFAULT 0x0
#define GC_FUSE_PROG_PKG_ID_OFFSET 0x2c0
#define GC_FUSE_PROG_PKG_ID_DEFAULT 0x0
#define GC_FUSE_PROG_BIN_ID_OFFSET 0x2c4
#define GC_FUSE_PROG_BIN_ID_DEFAULT 0x0
#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_OFFSET 0x2c8
#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0
#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_OFFSET 0x2cc
#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_DEFAULT 0x0
#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_OFFSET 0x2d0
#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0
#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_OFFSET 0x2d4
#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_DEFAULT 0x0
#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_OFFSET 0x2d8
#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0
#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_OFFSET 0x2dc
#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0
#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_OFFSET 0x2e0
#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0
#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_OFFSET 0x2e4
#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0
#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_OFFSET 0x2e8
#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_DEFAULT 0x0
#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_OFFSET 0x2ec
#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_DEFAULT 0x0
#define GC_FUSE_PROG_SEL_VREG_REG_EN_OFFSET 0x2f0
#define GC_FUSE_PROG_SEL_VREG_REG_EN_DEFAULT 0x0
#define GC_FUSE_PROG_SEL_VREF_REG_OFFSET 0x2f4
#define GC_FUSE_PROG_SEL_VREF_REG_DEFAULT 0x0
#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_OFFSET 0x2f8
#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_DEFAULT 0x0
#define GC_FUSE_PROG_SEL_VREF_BATMON_OFFSET 0x2fc
#define GC_FUSE_PROG_SEL_VREF_BATMON_DEFAULT 0x0
#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_OFFSET 0x300
#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_DEFAULT 0x0
#define GC_FUSE_PROG_X_OSC_LDO_CTRL_OFFSET 0x304
#define GC_FUSE_PROG_X_OSC_LDO_CTRL_DEFAULT 0x0
#define GC_FUSE_PROG_TEMP_OFFSET_CAL_OFFSET 0x308
#define GC_FUSE_PROG_TEMP_OFFSET_CAL_DEFAULT 0x0
#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_OFFSET 0x30c
#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_DEFAULT 0x0
#define GC_FUSE_PROG_TRNG_LDO_CTRL_OFFSET 0x310
#define GC_FUSE_PROG_TRNG_LDO_CTRL_DEFAULT 0x0
#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_OFFSET 0x314
#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_DEFAULT 0x0
#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_OFFSET 0x318
#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_DEFAULT 0x0
#define GC_FUSE_PROG_EXT_XTAL_PDB_OFFSET 0x31c
#define GC_FUSE_PROG_EXT_XTAL_PDB_DEFAULT 0x0
#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x320
#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0
#define GC_FUSE_PROG_OBFUSCATION_EN_OFFSET 0x324
#define GC_FUSE_PROG_OBFUSCATION_EN_DEFAULT 0x0
#define GC_FUSE_PROG_OBS0_OFFSET 0x328
#define GC_FUSE_PROG_OBS0_DEFAULT 0x0
#define GC_FUSE_PROG_OBS1_OFFSET 0x32c
#define GC_FUSE_PROG_OBS1_DEFAULT 0x0
#define GC_FUSE_PROG_OBS2_OFFSET 0x330
#define GC_FUSE_PROG_OBS2_DEFAULT 0x0
#define GC_FUSE_PROG_OBS3_OFFSET 0x334
#define GC_FUSE_PROG_OBS3_DEFAULT 0x0
#define GC_FUSE_PROG_OBS4_OFFSET 0x338
#define GC_FUSE_PROG_OBS4_DEFAULT 0x0
#define GC_FUSE_PROG_OBS5_OFFSET 0x33c
#define GC_FUSE_PROG_OBS5_DEFAULT 0x0
#define GC_FUSE_PROG_OBS6_OFFSET 0x340
#define GC_FUSE_PROG_OBS6_DEFAULT 0x0
#define GC_FUSE_PROG_OBS7_OFFSET 0x344
#define GC_FUSE_PROG_OBS7_DEFAULT 0x0
#define GC_FUSE_PROG_HIK_CREATE_LOCK_OFFSET 0x348
#define GC_FUSE_PROG_HIK_CREATE_LOCK_DEFAULT 0x0
#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_OFFSET 0x34c
#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_DEFAULT 0x0
#define GC_FUSE_PROG_BNK2_INTG_LOCK_OFFSET 0x350
#define GC_FUSE_PROG_BNK2_INTG_LOCK_DEFAULT 0x0
#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_OFFSET 0x354
#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_DEFAULT 0x0
#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_OFFSET 0x358
#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_DEFAULT 0x0
#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_OFFSET 0x35c
#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x0
#define GC_FUSE_PROG_ALERT_RSP_CFG_OFFSET 0x360
#define GC_FUSE_PROG_ALERT_RSP_CFG_DEFAULT 0x0
#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_OFFSET 0x364
#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_DEFAULT 0x0
#define GC_FUSE_PROG_BNK3_INTG_LOCK_OFFSET 0x368
#define GC_FUSE_PROG_BNK3_INTG_LOCK_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_OFFSET 0x36c
#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_OFFSET 0x370
#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_OFFSET 0x374
#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_OFFSET 0x378
#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_OFFSET 0x37c
#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x380
#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x384
#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_OFFSET 0x388
#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_OFFSET 0x38c
#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_OFFSET 0x390
#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_OFFSET 0x394
#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x398
#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x39c
#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x3a0
#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_OFFSET 0x3a4
#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_OFFSET 0x3a8
#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_OFFSET 0x3ac
#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_OFFSET 0x3b0
#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_OFFSET 0x3b4
#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_OFFSET 0x3b8
#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_OFFSET 0x3bc
#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_OFFSET 0x3c0
#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_OFFSET 0x3c4
#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_OFFSET 0x3c8
#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_OFFSET 0x3cc
#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_OFFSET 0x3d0
#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_OFFSET 0x3d4
#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_OFFSET 0x3d8
#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_OFFSET 0x3dc
#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_OFFSET 0x3e0
#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_OFFSET 0x3e4
#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_EC_RST_OFFSET 0x3e8
#define GC_FUSE_PROG_RBOX_POL_EC_RST_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_OFFSET 0x3ec
#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_OFFSET 0x3f0
#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_OFFSET 0x3f4
#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_OFFSET 0x3f8
#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_OFFSET 0x3fc
#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_OFFSET 0x400
#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_OFFSET 0x404
#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_OFFSET 0x408
#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_OFFSET 0x40c
#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_OFFSET 0x410
#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_OFFSET 0x414
#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_OFFSET 0x418
#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_OFFSET 0x41c
#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_DEFAULT 0x0
#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x420
#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_DEFAULT 0x0
#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_OFFSET 0x424
#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_DEFAULT 0x0
#define GC_FUSE_PROG_BNK4_INTG_LOCK_OFFSET 0x428
#define GC_FUSE_PROG_BNK4_INTG_LOCK_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x42c
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x430
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x434
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x438
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x43c
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x440
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x0
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x444
#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_OFFSET 0x0
#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_OFFSET 0x4
#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_OFFSET 0x8
#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_OFFSET 0xc
#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_OFFSET 0x10
#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_OFFSET 0x14
#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_OFFSET 0x18
#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_OFFSET 0x1c
#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_CFG_EN_OFFSET 0x20
#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_CFG_EN_OFFSET 0x24
#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_CFG_EN_OFFSET 0x28
#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_CFG_EN_OFFSET 0x2c
#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_CFG_EN_OFFSET 0x30
#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_CFG_EN_OFFSET 0x34
#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_CFG_EN_OFFSET 0x38
#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_CFG_EN_OFFSET 0x3c
#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_OFFSET 0x40
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_OFFSET 0x44
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_OFFSET 0x48
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_OFFSET 0x4c
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_DEFAULT 0x7
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_CFG_EN_OFFSET 0x50
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_CFG_EN_OFFSET 0x54
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_CFG_EN_OFFSET 0x58
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_CFG_EN_OFFSET 0x5c
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_OFFSET 0x60
#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_OFFSET 0x64
#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_OFFSET 0x68
#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_OFFSET 0x6c
#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_OFFSET 0x70
#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_OFFSET 0x74
#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_OFFSET 0x78
#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_OFFSET 0x7c
#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_OFFSET 0x80
#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_OFFSET 0x84
#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_OFFSET 0x88
#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_OFFSET 0x8c
#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_CFG_EN_OFFSET 0x90
#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_CFG_EN_OFFSET 0x94
#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_CFG_EN_OFFSET 0x98
#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_CFG_EN_OFFSET 0x9c
#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_OFFSET 0xa0
#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_OFFSET 0xa4
#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_OFFSET 0xa8
#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_OFFSET 0xac
#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_CFG_EN_OFFSET 0xb0
#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_CFG_EN_OFFSET 0xb4
#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_CFG_EN_OFFSET 0xb8
#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_CFG_EN_OFFSET 0xbc
#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_OFFSET 0xc0
#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_OFFSET 0xc4
#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_OFFSET 0xc8
#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_OFFSET 0xcc
#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_CFG_EN_OFFSET 0xd0
#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_CFG_EN_OFFSET 0xd4
#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_CFG_EN_OFFSET 0xd8
#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_CFG_EN_OFFSET 0xdc
#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION0_CTRL_OFFSET 0xe0
#define GC_GLOBALSEC_FLASH_REGION0_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION1_CTRL_OFFSET 0xe4
#define GC_GLOBALSEC_FLASH_REGION1_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION2_CTRL_OFFSET 0xe8
#define GC_GLOBALSEC_FLASH_REGION2_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION3_CTRL_OFFSET 0xec
#define GC_GLOBALSEC_FLASH_REGION3_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION4_CTRL_OFFSET 0xf0
#define GC_GLOBALSEC_FLASH_REGION4_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION5_CTRL_OFFSET 0xf4
#define GC_GLOBALSEC_FLASH_REGION5_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION6_CTRL_OFFSET 0xf8
#define GC_GLOBALSEC_FLASH_REGION6_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION7_CTRL_OFFSET 0xfc
#define GC_GLOBALSEC_FLASH_REGION7_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION0_CTRL_CFG_EN_OFFSET 0x100
#define GC_GLOBALSEC_FLASH_REGION0_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION1_CTRL_CFG_EN_OFFSET 0x104
#define GC_GLOBALSEC_FLASH_REGION1_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION2_CTRL_CFG_EN_OFFSET 0x108
#define GC_GLOBALSEC_FLASH_REGION2_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION3_CTRL_CFG_EN_OFFSET 0x10c
#define GC_GLOBALSEC_FLASH_REGION3_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION4_CTRL_CFG_EN_OFFSET 0x110
#define GC_GLOBALSEC_FLASH_REGION4_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION5_CTRL_CFG_EN_OFFSET 0x114
#define GC_GLOBALSEC_FLASH_REGION5_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION6_CTRL_CFG_EN_OFFSET 0x118
#define GC_GLOBALSEC_FLASH_REGION6_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH_REGION7_CTRL_CFG_EN_OFFSET 0x11c
#define GC_GLOBALSEC_FLASH_REGION7_CTRL_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH0_BULKERASE_CFG_EN_OFFSET 0x120
#define GC_GLOBALSEC_FLASH0_BULKERASE_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH0_BULKERASE_CTRL_OFFSET 0x124
#define GC_GLOBALSEC_FLASH0_BULKERASE_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH1_BULKERASE_CFG_EN_OFFSET 0x128
#define GC_GLOBALSEC_FLASH1_BULKERASE_CFG_EN_DEFAULT 0x1
#define GC_GLOBALSEC_FLASH1_BULKERASE_CTRL_OFFSET 0x12c
#define GC_GLOBALSEC_FLASH1_BULKERASE_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_OFFSET 0x130
#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_OFFSET 0x134
#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_OFFSET 0x138
#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_OFFSET 0x13c
#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_OFFSET 0x140
#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_OFFSET 0x144
#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_OFFSET 0x148
#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_OFFSET 0x14c
#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_REGION4_BASE_ADDR_OFFSET 0x150
#define GC_GLOBALSEC_CPU0_D_REGION4_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION4_SIZE_OFFSET 0x154
#define GC_GLOBALSEC_CPU0_D_REGION4_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_REGION5_BASE_ADDR_OFFSET 0x158
#define GC_GLOBALSEC_CPU0_D_REGION5_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION5_SIZE_OFFSET 0x15c
#define GC_GLOBALSEC_CPU0_D_REGION5_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_REGION6_BASE_ADDR_OFFSET 0x160
#define GC_GLOBALSEC_CPU0_D_REGION6_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION6_SIZE_OFFSET 0x164
#define GC_GLOBALSEC_CPU0_D_REGION6_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_REGION7_BASE_ADDR_OFFSET 0x168
#define GC_GLOBALSEC_CPU0_D_REGION7_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_REGION7_SIZE_OFFSET 0x16c
#define GC_GLOBALSEC_CPU0_D_REGION7_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_OFFSET 0x170
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_OFFSET 0x174
#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_OFFSET 0x178
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_OFFSET 0x17c
#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_OFFSET 0x180
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_OFFSET 0x184
#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_OFFSET 0x188
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_OFFSET 0x18c
#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_OFFSET 0x190
#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_OFFSET 0x194
#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_OFFSET 0x198
#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_OFFSET 0x19c
#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_OFFSET 0x1a0
#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_OFFSET 0x1a4
#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_OFFSET 0x1a8
#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_OFFSET 0x1ac
#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_OFFSET 0x1b0
#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_OFFSET 0x1b4
#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_OFFSET 0x1b8
#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_OFFSET 0x1bc
#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_OFFSET 0x1c0
#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_OFFSET 0x1c4
#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_OFFSET 0x1c8
#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_OFFSET 0x1cc
#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_OFFSET 0x1d0
#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_OFFSET 0x1d4
#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_OFFSET 0x1d8
#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_OFFSET 0x1dc
#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_OFFSET 0x1e0
#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_OFFSET 0x1e4
#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_OFFSET 0x1e8
#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_OFFSET 0x1ec
#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_OFFSET 0x1f0
#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_OFFSET 0x1f4
#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_OFFSET 0x1f8
#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_OFFSET 0x1fc
#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_OFFSET 0x200
#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_OFFSET 0x204
#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_OFFSET 0x208
#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_OFFSET 0x20c
#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_OFFSET 0x210
#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_OFFSET 0x214
#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_OFFSET 0x218
#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_OFFSET 0x21c
#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_OFFSET 0x220
#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_OFFSET 0x224
#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_OFFSET 0x228
#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_OFFSET 0x22c
#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_DEFAULT 0xffffffff
#define GC_GLOBALSEC_FLASH_REGION0_BASE_ADDR_OFFSET 0x230
#define GC_GLOBALSEC_FLASH_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION0_SIZE_OFFSET 0x234
#define GC_GLOBALSEC_FLASH_REGION0_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION1_BASE_ADDR_OFFSET 0x238
#define GC_GLOBALSEC_FLASH_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION1_SIZE_OFFSET 0x23c
#define GC_GLOBALSEC_FLASH_REGION1_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION2_BASE_ADDR_OFFSET 0x240
#define GC_GLOBALSEC_FLASH_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION2_SIZE_OFFSET 0x244
#define GC_GLOBALSEC_FLASH_REGION2_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION3_BASE_ADDR_OFFSET 0x248
#define GC_GLOBALSEC_FLASH_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION3_SIZE_OFFSET 0x24c
#define GC_GLOBALSEC_FLASH_REGION3_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION4_BASE_ADDR_OFFSET 0x250
#define GC_GLOBALSEC_FLASH_REGION4_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION4_SIZE_OFFSET 0x254
#define GC_GLOBALSEC_FLASH_REGION4_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION5_BASE_ADDR_OFFSET 0x258
#define GC_GLOBALSEC_FLASH_REGION5_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION5_SIZE_OFFSET 0x25c
#define GC_GLOBALSEC_FLASH_REGION5_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION6_BASE_ADDR_OFFSET 0x260
#define GC_GLOBALSEC_FLASH_REGION6_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION6_SIZE_OFFSET 0x264
#define GC_GLOBALSEC_FLASH_REGION6_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION7_BASE_ADDR_OFFSET 0x268
#define GC_GLOBALSEC_FLASH_REGION7_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_FLASH_REGION7_SIZE_OFFSET 0x26c
#define GC_GLOBALSEC_FLASH_REGION7_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_OFFSET 0x270
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_OFFSET 0x274
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_OFFSET 0x278
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_OFFSET 0x27c
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_OFFSET 0x280
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_OFFSET 0x284
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_OFFSET 0x288
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_OFFSET 0x28c
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_OFFSET 0x290
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_OFFSET 0x294
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_OFFSET 0x298
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_OFFSET 0x29c
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_OFFSET 0x2a0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_OFFSET 0x2a4
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_OFFSET 0x2a8
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_OFFSET 0x2ac
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_OFFSET 0x2b0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_OFFSET 0x2b4
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_OFFSET 0x2b8
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_OFFSET 0x2bc
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_OFFSET 0x2c0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_OFFSET 0x2c4
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_OFFSET 0x2c8
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_OFFSET 0x2cc
#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_S_PERMISSION_OFFSET 0x2d0
#define GC_GLOBALSEC_CPU0_S_PERMISSION_DEFAULT 0x55
#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_OFFSET 0x2d4
#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DEFAULT 0x55
#define GC_GLOBALSEC_DDMA0_PERMISSION_OFFSET 0x2d8
#define GC_GLOBALSEC_DDMA0_PERMISSION_DEFAULT 0x55
#define GC_GLOBALSEC_SOFTWARE_LVL_OFFSET 0x2dc
#define GC_GLOBALSEC_SOFTWARE_LVL_DEFAULT 0x55
#define GC_GLOBALSEC_SB_COMP_STATUS_OFFSET 0x1000
#define GC_GLOBALSEC_SB_COMP_STATUS_DEFAULT 0x0
#define GC_GLOBALSEC_SB_BL_SIG0_OFFSET 0x1004
#define GC_GLOBALSEC_SB_BL_SIG0_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SB_BL_SIG1_OFFSET 0x1008
#define GC_GLOBALSEC_SB_BL_SIG1_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SB_BL_SIG2_OFFSET 0x100c
#define GC_GLOBALSEC_SB_BL_SIG2_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SB_BL_SIG3_OFFSET 0x1010
#define GC_GLOBALSEC_SB_BL_SIG3_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SB_BL_SIG4_OFFSET 0x1014
#define GC_GLOBALSEC_SB_BL_SIG4_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SB_BL_SIG5_OFFSET 0x1018
#define GC_GLOBALSEC_SB_BL_SIG5_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SB_BL_SIG6_OFFSET 0x101c
#define GC_GLOBALSEC_SB_BL_SIG6_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SB_BL_SIG7_OFFSET 0x1020
#define GC_GLOBALSEC_SB_BL_SIG7_DEFAULT 0xfacecafe
#define GC_GLOBALSEC_SIG_UNLOCK_OFFSET 0x1024
#define GC_GLOBALSEC_SIG_UNLOCK_DEFAULT 0x0
#define GC_GLOBALSEC_INT_ERR_FLAGS_OFFSET 0x1028
#define GC_GLOBALSEC_INT_ERR_FLAGS_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_CFG_LOCK_OFFSET 0x102c
#define GC_GLOBALSEC_ALERT_CFG_LOCK_DEFAULT 0x1
#define GC_GLOBALSEC_ALERT_FW_TRIGGER_OFFSET 0x4000
#define GC_GLOBALSEC_ALERT_FW_TRIGGER_DEFAULT 0xaa
#define GC_GLOBALSEC_ALERT_INTR_STS0_OFFSET 0x4004
#define GC_GLOBALSEC_ALERT_INTR_STS0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_INTR_STS1_OFFSET 0x4008
#define GC_GLOBALSEC_ALERT_INTR_STS1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_NMI_EN0_OFFSET 0x400c
#define GC_GLOBALSEC_ALERT_NMI_EN0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_NMI_EN1_OFFSET 0x4010
#define GC_GLOBALSEC_ALERT_NMI_EN1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPA_EN0_OFFSET 0x4014
#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPA_EN1_OFFSET 0x4018
#define GC_GLOBALSEC_ALERT_GROUPA_EN1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPB_EN0_OFFSET 0x401c
#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPB_EN1_OFFSET 0x4020
#define GC_GLOBALSEC_ALERT_GROUPB_EN1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPC_EN0_OFFSET 0x4024
#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPC_EN1_OFFSET 0x4028
#define GC_GLOBALSEC_ALERT_GROUPC_EN1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_OFFSET 0x402c
#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_OFFSET 0x4030
#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_OFFSET 0x4034
#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_OFFSET 0x4038
#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_OFFSET 0x403c
#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_OFFSET 0x4040
#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPA_CTR_OFFSET 0x4044
#define GC_GLOBALSEC_ALERT_GROUPA_CTR_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPB_CTR_OFFSET 0x4048
#define GC_GLOBALSEC_ALERT_GROUPB_CTR_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPC_CTR_OFFSET 0x404c
#define GC_GLOBALSEC_ALERT_GROUPC_CTR_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_GROUPA_THRESHOLD_OFFSET 0x4050
#define GC_GLOBALSEC_ALERT_GROUPA_THRESHOLD_DEFAULT 0x64
#define GC_GLOBALSEC_ALERT_GROUPB_THRESHOLD_OFFSET 0x4054
#define GC_GLOBALSEC_ALERT_GROUPB_THRESHOLD_DEFAULT 0x64
#define GC_GLOBALSEC_ALERT_GROUPC_THRESHOLD_OFFSET 0x4058
#define GC_GLOBALSEC_ALERT_GROUPC_THRESHOLD_DEFAULT 0x64
#define GC_GLOBALSEC_ALERT_CONTROL_OFFSET 0x405c
#define GC_GLOBALSEC_ALERT_CONTROL_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR0_OFFSET 0x4060
#define GC_GLOBALSEC_ALERT_DLYCTR0_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR1_OFFSET 0x4064
#define GC_GLOBALSEC_ALERT_DLYCTR1_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR2_OFFSET 0x4068
#define GC_GLOBALSEC_ALERT_DLYCTR2_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR0_LEN_OFFSET 0x406c
#define GC_GLOBALSEC_ALERT_DLYCTR0_LEN_DEFAULT 0xffff
#define GC_GLOBALSEC_ALERT_DLYCTR1_LEN_OFFSET 0x4070
#define GC_GLOBALSEC_ALERT_DLYCTR1_LEN_DEFAULT 0xffff
#define GC_GLOBALSEC_ALERT_DLYCTR2_LEN_OFFSET 0x4074
#define GC_GLOBALSEC_ALERT_DLYCTR2_LEN_DEFAULT 0xffff
#define GC_GLOBALSEC_ALERT_DLYCTR0_SHUTDOWN_EN_OFFSET 0x4078
#define GC_GLOBALSEC_ALERT_DLYCTR0_SHUTDOWN_EN_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR1_SHUTDOWN_EN_OFFSET 0x407c
#define GC_GLOBALSEC_ALERT_DLYCTR1_SHUTDOWN_EN_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR2_SHUTDOWN_EN_OFFSET 0x4080
#define GC_GLOBALSEC_ALERT_DLYCTR2_SHUTDOWN_EN_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR0_CLEAR_OFFSET 0x4084
#define GC_GLOBALSEC_ALERT_DLYCTR0_CLEAR_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR1_CLEAR_OFFSET 0x4088
#define GC_GLOBALSEC_ALERT_DLYCTR1_CLEAR_DEFAULT 0x0
#define GC_GLOBALSEC_ALERT_DLYCTR2_CLEAR_OFFSET 0x408c
#define GC_GLOBALSEC_ALERT_DLYCTR2_CLEAR_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_OFFSET 0x4090
#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_EMPTY_OFFSET 0x4094
#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_EMPTY_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_OFFSET 0x4098
#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_EMPTY_OFFSET 0x409c
#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_EMPTY_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_OFFSET 0x40a0
#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_DEFAULT 0x0
#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_EMPTY_OFFSET 0x40a4
#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_EMPTY_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_OFFSET 0x40a8
#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_DEFAULT 0x0
#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_EMPTY_OFFSET 0x40ac
#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_EMPTY_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_OFFSET 0x40b0
#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_DEFAULT 0x0
#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_EMPTY_OFFSET 0x40b4
#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_EMPTY_DEFAULT 0x0
#define GC_GLOBALSEC_OBFS_SW_EN_OFFSET 0x40b8
#define GC_GLOBALSEC_OBFS_SW_EN_DEFAULT 0x0
#define GC_GLOBALSEC_TRANSMISSION_PARITY_EN_OFFSET 0x40bc
#define GC_GLOBALSEC_TRANSMISSION_PARITY_EN_DEFAULT 0x0
#define GC_GLOBALSEC_SRAM_PARITY_CHECK_ENABLE_OFFSET 0x40c0
#define GC_GLOBALSEC_SRAM_PARITY_CHECK_ENABLE_DEFAULT 0x0
#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_FREQ_OFFSET 0x40c4
#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_FREQ_DEFAULT 0x0
#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_COUNT_OFFSET 0x40c8
#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_COUNT_DEFAULT 0x0
#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_ADDR_OFFSET 0x40cc
#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_ADDR_DEFAULT 0x0
#define GC_GLOBALSEC_HIDE_ROM_OFFSET 0x40d0
#define GC_GLOBALSEC_HIDE_ROM_DEFAULT 0x0
#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_OFFSET 0x40d4
#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DEFAULT 0x2f
#define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_OFFSET 0x40d8
#define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_DEFAULT 0x0
#define GC_GLOBALSEC_VERSION_OFFSET 0x40dc
#define GC_GLOBALSEC_VERSION_DEFAULT 0x59010913
#define GC_GPIO_DATAIN_OFFSET 0x0
#define GC_GPIO_DATAIN_DEFAULT 0x0
#define GC_GPIO_DOUT_OFFSET 0x4
#define GC_GPIO_DOUT_DEFAULT 0x0
#define GC_GPIO_SETDOUTEN_OFFSET 0x10
#define GC_GPIO_SETDOUTEN_DEFAULT 0x0
#define GC_GPIO_CLRDOUTEN_OFFSET 0x14
#define GC_GPIO_CLRDOUTEN_DEFAULT 0x0
#define GC_GPIO_RESERVED0_OFFSET 0x18
#define GC_GPIO_RESERVED0_DEFAULT 0x0
#define GC_GPIO_RESERVED1_OFFSET 0x1c
#define GC_GPIO_RESERVED1_DEFAULT 0x0
#define GC_GPIO_SETINTEN_OFFSET 0x20
#define GC_GPIO_SETINTEN_DEFAULT 0x0
#define GC_GPIO_CLRINTEN_OFFSET 0x24
#define GC_GPIO_CLRINTEN_DEFAULT 0x0
#define GC_GPIO_SETINTTYPE_OFFSET 0x28
#define GC_GPIO_SETINTTYPE_DEFAULT 0x0
#define GC_GPIO_CLRINTTYPE_OFFSET 0x2c
#define GC_GPIO_CLRINTTYPE_DEFAULT 0x0
#define GC_GPIO_SETINTPOL_OFFSET 0x30
#define GC_GPIO_SETINTPOL_DEFAULT 0x0
#define GC_GPIO_CLRINTPOL_OFFSET 0x34
#define GC_GPIO_CLRINTPOL_DEFAULT 0x0
#define GC_GPIO_CLRINTSTAT_OFFSET 0x38
#define GC_GPIO_CLRINTSTAT_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_400_OFFSET 0x400
#define GC_GPIO_MASKLOWBYTE_400_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_404_OFFSET 0x404
#define GC_GPIO_MASKLOWBYTE_404_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_408_OFFSET 0x408
#define GC_GPIO_MASKLOWBYTE_408_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_40C_OFFSET 0x40c
#define GC_GPIO_MASKLOWBYTE_40C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_410_OFFSET 0x410
#define GC_GPIO_MASKLOWBYTE_410_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_414_OFFSET 0x414
#define GC_GPIO_MASKLOWBYTE_414_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_418_OFFSET 0x418
#define GC_GPIO_MASKLOWBYTE_418_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_41C_OFFSET 0x41c
#define GC_GPIO_MASKLOWBYTE_41C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_420_OFFSET 0x420
#define GC_GPIO_MASKLOWBYTE_420_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_424_OFFSET 0x424
#define GC_GPIO_MASKLOWBYTE_424_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_428_OFFSET 0x428
#define GC_GPIO_MASKLOWBYTE_428_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_42C_OFFSET 0x42c
#define GC_GPIO_MASKLOWBYTE_42C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_430_OFFSET 0x430
#define GC_GPIO_MASKLOWBYTE_430_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_434_OFFSET 0x434
#define GC_GPIO_MASKLOWBYTE_434_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_438_OFFSET 0x438
#define GC_GPIO_MASKLOWBYTE_438_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_43C_OFFSET 0x43c
#define GC_GPIO_MASKLOWBYTE_43C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_440_OFFSET 0x440
#define GC_GPIO_MASKLOWBYTE_440_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_444_OFFSET 0x444
#define GC_GPIO_MASKLOWBYTE_444_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_448_OFFSET 0x448
#define GC_GPIO_MASKLOWBYTE_448_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_44C_OFFSET 0x44c
#define GC_GPIO_MASKLOWBYTE_44C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_450_OFFSET 0x450
#define GC_GPIO_MASKLOWBYTE_450_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_454_OFFSET 0x454
#define GC_GPIO_MASKLOWBYTE_454_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_458_OFFSET 0x458
#define GC_GPIO_MASKLOWBYTE_458_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_45C_OFFSET 0x45c
#define GC_GPIO_MASKLOWBYTE_45C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_460_OFFSET 0x460
#define GC_GPIO_MASKLOWBYTE_460_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_464_OFFSET 0x464
#define GC_GPIO_MASKLOWBYTE_464_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_468_OFFSET 0x468
#define GC_GPIO_MASKLOWBYTE_468_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_46C_OFFSET 0x46c
#define GC_GPIO_MASKLOWBYTE_46C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_470_OFFSET 0x470
#define GC_GPIO_MASKLOWBYTE_470_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_474_OFFSET 0x474
#define GC_GPIO_MASKLOWBYTE_474_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_478_OFFSET 0x478
#define GC_GPIO_MASKLOWBYTE_478_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_47C_OFFSET 0x47c
#define GC_GPIO_MASKLOWBYTE_47C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_480_OFFSET 0x480
#define GC_GPIO_MASKLOWBYTE_480_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_484_OFFSET 0x484
#define GC_GPIO_MASKLOWBYTE_484_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_488_OFFSET 0x488
#define GC_GPIO_MASKLOWBYTE_488_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_48C_OFFSET 0x48c
#define GC_GPIO_MASKLOWBYTE_48C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_490_OFFSET 0x490
#define GC_GPIO_MASKLOWBYTE_490_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_494_OFFSET 0x494
#define GC_GPIO_MASKLOWBYTE_494_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_498_OFFSET 0x498
#define GC_GPIO_MASKLOWBYTE_498_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_49C_OFFSET 0x49c
#define GC_GPIO_MASKLOWBYTE_49C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4A0_OFFSET 0x4a0
#define GC_GPIO_MASKLOWBYTE_4A0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4A4_OFFSET 0x4a4
#define GC_GPIO_MASKLOWBYTE_4A4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4A8_OFFSET 0x4a8
#define GC_GPIO_MASKLOWBYTE_4A8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4AC_OFFSET 0x4ac
#define GC_GPIO_MASKLOWBYTE_4AC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4B0_OFFSET 0x4b0
#define GC_GPIO_MASKLOWBYTE_4B0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4B4_OFFSET 0x4b4
#define GC_GPIO_MASKLOWBYTE_4B4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4B8_OFFSET 0x4b8
#define GC_GPIO_MASKLOWBYTE_4B8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4BC_OFFSET 0x4bc
#define GC_GPIO_MASKLOWBYTE_4BC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4C0_OFFSET 0x4c0
#define GC_GPIO_MASKLOWBYTE_4C0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4C4_OFFSET 0x4c4
#define GC_GPIO_MASKLOWBYTE_4C4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4C8_OFFSET 0x4c8
#define GC_GPIO_MASKLOWBYTE_4C8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4CC_OFFSET 0x4cc
#define GC_GPIO_MASKLOWBYTE_4CC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4D0_OFFSET 0x4d0
#define GC_GPIO_MASKLOWBYTE_4D0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4D4_OFFSET 0x4d4
#define GC_GPIO_MASKLOWBYTE_4D4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4D8_OFFSET 0x4d8
#define GC_GPIO_MASKLOWBYTE_4D8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4DC_OFFSET 0x4dc
#define GC_GPIO_MASKLOWBYTE_4DC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4E0_OFFSET 0x4e0
#define GC_GPIO_MASKLOWBYTE_4E0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4E4_OFFSET 0x4e4
#define GC_GPIO_MASKLOWBYTE_4E4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4E8_OFFSET 0x4e8
#define GC_GPIO_MASKLOWBYTE_4E8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4EC_OFFSET 0x4ec
#define GC_GPIO_MASKLOWBYTE_4EC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4F0_OFFSET 0x4f0
#define GC_GPIO_MASKLOWBYTE_4F0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4F4_OFFSET 0x4f4
#define GC_GPIO_MASKLOWBYTE_4F4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4F8_OFFSET 0x4f8
#define GC_GPIO_MASKLOWBYTE_4F8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_4FC_OFFSET 0x4fc
#define GC_GPIO_MASKLOWBYTE_4FC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_500_OFFSET 0x500
#define GC_GPIO_MASKLOWBYTE_500_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_504_OFFSET 0x504
#define GC_GPIO_MASKLOWBYTE_504_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_508_OFFSET 0x508
#define GC_GPIO_MASKLOWBYTE_508_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_50C_OFFSET 0x50c
#define GC_GPIO_MASKLOWBYTE_50C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_510_OFFSET 0x510
#define GC_GPIO_MASKLOWBYTE_510_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_514_OFFSET 0x514
#define GC_GPIO_MASKLOWBYTE_514_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_518_OFFSET 0x518
#define GC_GPIO_MASKLOWBYTE_518_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_51C_OFFSET 0x51c
#define GC_GPIO_MASKLOWBYTE_51C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_520_OFFSET 0x520
#define GC_GPIO_MASKLOWBYTE_520_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_524_OFFSET 0x524
#define GC_GPIO_MASKLOWBYTE_524_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_528_OFFSET 0x528
#define GC_GPIO_MASKLOWBYTE_528_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_52C_OFFSET 0x52c
#define GC_GPIO_MASKLOWBYTE_52C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_530_OFFSET 0x530
#define GC_GPIO_MASKLOWBYTE_530_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_534_OFFSET 0x534
#define GC_GPIO_MASKLOWBYTE_534_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_538_OFFSET 0x538
#define GC_GPIO_MASKLOWBYTE_538_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_53C_OFFSET 0x53c
#define GC_GPIO_MASKLOWBYTE_53C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_540_OFFSET 0x540
#define GC_GPIO_MASKLOWBYTE_540_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_544_OFFSET 0x544
#define GC_GPIO_MASKLOWBYTE_544_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_548_OFFSET 0x548
#define GC_GPIO_MASKLOWBYTE_548_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_54C_OFFSET 0x54c
#define GC_GPIO_MASKLOWBYTE_54C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_550_OFFSET 0x550
#define GC_GPIO_MASKLOWBYTE_550_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_554_OFFSET 0x554
#define GC_GPIO_MASKLOWBYTE_554_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_558_OFFSET 0x558
#define GC_GPIO_MASKLOWBYTE_558_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_55C_OFFSET 0x55c
#define GC_GPIO_MASKLOWBYTE_55C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_560_OFFSET 0x560
#define GC_GPIO_MASKLOWBYTE_560_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_564_OFFSET 0x564
#define GC_GPIO_MASKLOWBYTE_564_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_568_OFFSET 0x568
#define GC_GPIO_MASKLOWBYTE_568_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_56C_OFFSET 0x56c
#define GC_GPIO_MASKLOWBYTE_56C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_570_OFFSET 0x570
#define GC_GPIO_MASKLOWBYTE_570_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_574_OFFSET 0x574
#define GC_GPIO_MASKLOWBYTE_574_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_578_OFFSET 0x578
#define GC_GPIO_MASKLOWBYTE_578_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_57C_OFFSET 0x57c
#define GC_GPIO_MASKLOWBYTE_57C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_580_OFFSET 0x580
#define GC_GPIO_MASKLOWBYTE_580_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_584_OFFSET 0x584
#define GC_GPIO_MASKLOWBYTE_584_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_588_OFFSET 0x588
#define GC_GPIO_MASKLOWBYTE_588_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_58C_OFFSET 0x58c
#define GC_GPIO_MASKLOWBYTE_58C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_590_OFFSET 0x590
#define GC_GPIO_MASKLOWBYTE_590_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_594_OFFSET 0x594
#define GC_GPIO_MASKLOWBYTE_594_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_598_OFFSET 0x598
#define GC_GPIO_MASKLOWBYTE_598_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_59C_OFFSET 0x59c
#define GC_GPIO_MASKLOWBYTE_59C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5A0_OFFSET 0x5a0
#define GC_GPIO_MASKLOWBYTE_5A0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5A4_OFFSET 0x5a4
#define GC_GPIO_MASKLOWBYTE_5A4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5A8_OFFSET 0x5a8
#define GC_GPIO_MASKLOWBYTE_5A8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5AC_OFFSET 0x5ac
#define GC_GPIO_MASKLOWBYTE_5AC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5B0_OFFSET 0x5b0
#define GC_GPIO_MASKLOWBYTE_5B0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5B4_OFFSET 0x5b4
#define GC_GPIO_MASKLOWBYTE_5B4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5B8_OFFSET 0x5b8
#define GC_GPIO_MASKLOWBYTE_5B8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5BC_OFFSET 0x5bc
#define GC_GPIO_MASKLOWBYTE_5BC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5C0_OFFSET 0x5c0
#define GC_GPIO_MASKLOWBYTE_5C0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5C4_OFFSET 0x5c4
#define GC_GPIO_MASKLOWBYTE_5C4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5C8_OFFSET 0x5c8
#define GC_GPIO_MASKLOWBYTE_5C8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5CC_OFFSET 0x5cc
#define GC_GPIO_MASKLOWBYTE_5CC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5D0_OFFSET 0x5d0
#define GC_GPIO_MASKLOWBYTE_5D0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5D4_OFFSET 0x5d4
#define GC_GPIO_MASKLOWBYTE_5D4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5D8_OFFSET 0x5d8
#define GC_GPIO_MASKLOWBYTE_5D8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5DC_OFFSET 0x5dc
#define GC_GPIO_MASKLOWBYTE_5DC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5E0_OFFSET 0x5e0
#define GC_GPIO_MASKLOWBYTE_5E0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5E4_OFFSET 0x5e4
#define GC_GPIO_MASKLOWBYTE_5E4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5E8_OFFSET 0x5e8
#define GC_GPIO_MASKLOWBYTE_5E8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5EC_OFFSET 0x5ec
#define GC_GPIO_MASKLOWBYTE_5EC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5F0_OFFSET 0x5f0
#define GC_GPIO_MASKLOWBYTE_5F0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5F4_OFFSET 0x5f4
#define GC_GPIO_MASKLOWBYTE_5F4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5F8_OFFSET 0x5f8
#define GC_GPIO_MASKLOWBYTE_5F8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_5FC_OFFSET 0x5fc
#define GC_GPIO_MASKLOWBYTE_5FC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_600_OFFSET 0x600
#define GC_GPIO_MASKLOWBYTE_600_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_604_OFFSET 0x604
#define GC_GPIO_MASKLOWBYTE_604_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_608_OFFSET 0x608
#define GC_GPIO_MASKLOWBYTE_608_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_60C_OFFSET 0x60c
#define GC_GPIO_MASKLOWBYTE_60C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_610_OFFSET 0x610
#define GC_GPIO_MASKLOWBYTE_610_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_614_OFFSET 0x614
#define GC_GPIO_MASKLOWBYTE_614_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_618_OFFSET 0x618
#define GC_GPIO_MASKLOWBYTE_618_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_61C_OFFSET 0x61c
#define GC_GPIO_MASKLOWBYTE_61C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_620_OFFSET 0x620
#define GC_GPIO_MASKLOWBYTE_620_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_624_OFFSET 0x624
#define GC_GPIO_MASKLOWBYTE_624_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_628_OFFSET 0x628
#define GC_GPIO_MASKLOWBYTE_628_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_62C_OFFSET 0x62c
#define GC_GPIO_MASKLOWBYTE_62C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_630_OFFSET 0x630
#define GC_GPIO_MASKLOWBYTE_630_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_634_OFFSET 0x634
#define GC_GPIO_MASKLOWBYTE_634_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_638_OFFSET 0x638
#define GC_GPIO_MASKLOWBYTE_638_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_63C_OFFSET 0x63c
#define GC_GPIO_MASKLOWBYTE_63C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_640_OFFSET 0x640
#define GC_GPIO_MASKLOWBYTE_640_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_644_OFFSET 0x644
#define GC_GPIO_MASKLOWBYTE_644_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_648_OFFSET 0x648
#define GC_GPIO_MASKLOWBYTE_648_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_64C_OFFSET 0x64c
#define GC_GPIO_MASKLOWBYTE_64C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_650_OFFSET 0x650
#define GC_GPIO_MASKLOWBYTE_650_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_654_OFFSET 0x654
#define GC_GPIO_MASKLOWBYTE_654_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_658_OFFSET 0x658
#define GC_GPIO_MASKLOWBYTE_658_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_65C_OFFSET 0x65c
#define GC_GPIO_MASKLOWBYTE_65C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_660_OFFSET 0x660
#define GC_GPIO_MASKLOWBYTE_660_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_664_OFFSET 0x664
#define GC_GPIO_MASKLOWBYTE_664_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_668_OFFSET 0x668
#define GC_GPIO_MASKLOWBYTE_668_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_66C_OFFSET 0x66c
#define GC_GPIO_MASKLOWBYTE_66C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_670_OFFSET 0x670
#define GC_GPIO_MASKLOWBYTE_670_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_674_OFFSET 0x674
#define GC_GPIO_MASKLOWBYTE_674_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_678_OFFSET 0x678
#define GC_GPIO_MASKLOWBYTE_678_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_67C_OFFSET 0x67c
#define GC_GPIO_MASKLOWBYTE_67C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_680_OFFSET 0x680
#define GC_GPIO_MASKLOWBYTE_680_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_684_OFFSET 0x684
#define GC_GPIO_MASKLOWBYTE_684_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_688_OFFSET 0x688
#define GC_GPIO_MASKLOWBYTE_688_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_68C_OFFSET 0x68c
#define GC_GPIO_MASKLOWBYTE_68C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_690_OFFSET 0x690
#define GC_GPIO_MASKLOWBYTE_690_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_694_OFFSET 0x694
#define GC_GPIO_MASKLOWBYTE_694_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_698_OFFSET 0x698
#define GC_GPIO_MASKLOWBYTE_698_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_69C_OFFSET 0x69c
#define GC_GPIO_MASKLOWBYTE_69C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6A0_OFFSET 0x6a0
#define GC_GPIO_MASKLOWBYTE_6A0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6A4_OFFSET 0x6a4
#define GC_GPIO_MASKLOWBYTE_6A4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6A8_OFFSET 0x6a8
#define GC_GPIO_MASKLOWBYTE_6A8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6AC_OFFSET 0x6ac
#define GC_GPIO_MASKLOWBYTE_6AC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6B0_OFFSET 0x6b0
#define GC_GPIO_MASKLOWBYTE_6B0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6B4_OFFSET 0x6b4
#define GC_GPIO_MASKLOWBYTE_6B4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6B8_OFFSET 0x6b8
#define GC_GPIO_MASKLOWBYTE_6B8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6BC_OFFSET 0x6bc
#define GC_GPIO_MASKLOWBYTE_6BC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6C0_OFFSET 0x6c0
#define GC_GPIO_MASKLOWBYTE_6C0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6C4_OFFSET 0x6c4
#define GC_GPIO_MASKLOWBYTE_6C4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6C8_OFFSET 0x6c8
#define GC_GPIO_MASKLOWBYTE_6C8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6CC_OFFSET 0x6cc
#define GC_GPIO_MASKLOWBYTE_6CC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6D0_OFFSET 0x6d0
#define GC_GPIO_MASKLOWBYTE_6D0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6D4_OFFSET 0x6d4
#define GC_GPIO_MASKLOWBYTE_6D4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6D8_OFFSET 0x6d8
#define GC_GPIO_MASKLOWBYTE_6D8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6DC_OFFSET 0x6dc
#define GC_GPIO_MASKLOWBYTE_6DC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6E0_OFFSET 0x6e0
#define GC_GPIO_MASKLOWBYTE_6E0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6E4_OFFSET 0x6e4
#define GC_GPIO_MASKLOWBYTE_6E4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6E8_OFFSET 0x6e8
#define GC_GPIO_MASKLOWBYTE_6E8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6EC_OFFSET 0x6ec
#define GC_GPIO_MASKLOWBYTE_6EC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6F0_OFFSET 0x6f0
#define GC_GPIO_MASKLOWBYTE_6F0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6F4_OFFSET 0x6f4
#define GC_GPIO_MASKLOWBYTE_6F4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6F8_OFFSET 0x6f8
#define GC_GPIO_MASKLOWBYTE_6F8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_6FC_OFFSET 0x6fc
#define GC_GPIO_MASKLOWBYTE_6FC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_700_OFFSET 0x700
#define GC_GPIO_MASKLOWBYTE_700_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_704_OFFSET 0x704
#define GC_GPIO_MASKLOWBYTE_704_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_708_OFFSET 0x708
#define GC_GPIO_MASKLOWBYTE_708_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_70C_OFFSET 0x70c
#define GC_GPIO_MASKLOWBYTE_70C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_710_OFFSET 0x710
#define GC_GPIO_MASKLOWBYTE_710_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_714_OFFSET 0x714
#define GC_GPIO_MASKLOWBYTE_714_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_718_OFFSET 0x718
#define GC_GPIO_MASKLOWBYTE_718_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_71C_OFFSET 0x71c
#define GC_GPIO_MASKLOWBYTE_71C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_720_OFFSET 0x720
#define GC_GPIO_MASKLOWBYTE_720_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_724_OFFSET 0x724
#define GC_GPIO_MASKLOWBYTE_724_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_728_OFFSET 0x728
#define GC_GPIO_MASKLOWBYTE_728_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_72C_OFFSET 0x72c
#define GC_GPIO_MASKLOWBYTE_72C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_730_OFFSET 0x730
#define GC_GPIO_MASKLOWBYTE_730_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_734_OFFSET 0x734
#define GC_GPIO_MASKLOWBYTE_734_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_738_OFFSET 0x738
#define GC_GPIO_MASKLOWBYTE_738_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_73C_OFFSET 0x73c
#define GC_GPIO_MASKLOWBYTE_73C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_740_OFFSET 0x740
#define GC_GPIO_MASKLOWBYTE_740_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_744_OFFSET 0x744
#define GC_GPIO_MASKLOWBYTE_744_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_748_OFFSET 0x748
#define GC_GPIO_MASKLOWBYTE_748_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_74C_OFFSET 0x74c
#define GC_GPIO_MASKLOWBYTE_74C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_750_OFFSET 0x750
#define GC_GPIO_MASKLOWBYTE_750_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_754_OFFSET 0x754
#define GC_GPIO_MASKLOWBYTE_754_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_758_OFFSET 0x758
#define GC_GPIO_MASKLOWBYTE_758_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_75C_OFFSET 0x75c
#define GC_GPIO_MASKLOWBYTE_75C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_760_OFFSET 0x760
#define GC_GPIO_MASKLOWBYTE_760_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_764_OFFSET 0x764
#define GC_GPIO_MASKLOWBYTE_764_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_768_OFFSET 0x768
#define GC_GPIO_MASKLOWBYTE_768_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_76C_OFFSET 0x76c
#define GC_GPIO_MASKLOWBYTE_76C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_770_OFFSET 0x770
#define GC_GPIO_MASKLOWBYTE_770_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_774_OFFSET 0x774
#define GC_GPIO_MASKLOWBYTE_774_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_778_OFFSET 0x778
#define GC_GPIO_MASKLOWBYTE_778_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_77C_OFFSET 0x77c
#define GC_GPIO_MASKLOWBYTE_77C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_780_OFFSET 0x780
#define GC_GPIO_MASKLOWBYTE_780_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_784_OFFSET 0x784
#define GC_GPIO_MASKLOWBYTE_784_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_788_OFFSET 0x788
#define GC_GPIO_MASKLOWBYTE_788_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_78C_OFFSET 0x78c
#define GC_GPIO_MASKLOWBYTE_78C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_790_OFFSET 0x790
#define GC_GPIO_MASKLOWBYTE_790_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_794_OFFSET 0x794
#define GC_GPIO_MASKLOWBYTE_794_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_798_OFFSET 0x798
#define GC_GPIO_MASKLOWBYTE_798_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_79C_OFFSET 0x79c
#define GC_GPIO_MASKLOWBYTE_79C_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7A0_OFFSET 0x7a0
#define GC_GPIO_MASKLOWBYTE_7A0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7A4_OFFSET 0x7a4
#define GC_GPIO_MASKLOWBYTE_7A4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7A8_OFFSET 0x7a8
#define GC_GPIO_MASKLOWBYTE_7A8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7AC_OFFSET 0x7ac
#define GC_GPIO_MASKLOWBYTE_7AC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7B0_OFFSET 0x7b0
#define GC_GPIO_MASKLOWBYTE_7B0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7B4_OFFSET 0x7b4
#define GC_GPIO_MASKLOWBYTE_7B4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7B8_OFFSET 0x7b8
#define GC_GPIO_MASKLOWBYTE_7B8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7BC_OFFSET 0x7bc
#define GC_GPIO_MASKLOWBYTE_7BC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7C0_OFFSET 0x7c0
#define GC_GPIO_MASKLOWBYTE_7C0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7C4_OFFSET 0x7c4
#define GC_GPIO_MASKLOWBYTE_7C4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7C8_OFFSET 0x7c8
#define GC_GPIO_MASKLOWBYTE_7C8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7CC_OFFSET 0x7cc
#define GC_GPIO_MASKLOWBYTE_7CC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7D0_OFFSET 0x7d0
#define GC_GPIO_MASKLOWBYTE_7D0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7D4_OFFSET 0x7d4
#define GC_GPIO_MASKLOWBYTE_7D4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7D8_OFFSET 0x7d8
#define GC_GPIO_MASKLOWBYTE_7D8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7DC_OFFSET 0x7dc
#define GC_GPIO_MASKLOWBYTE_7DC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7E0_OFFSET 0x7e0
#define GC_GPIO_MASKLOWBYTE_7E0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7E4_OFFSET 0x7e4
#define GC_GPIO_MASKLOWBYTE_7E4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7E8_OFFSET 0x7e8
#define GC_GPIO_MASKLOWBYTE_7E8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7EC_OFFSET 0x7ec
#define GC_GPIO_MASKLOWBYTE_7EC_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7F0_OFFSET 0x7f0
#define GC_GPIO_MASKLOWBYTE_7F0_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7F4_OFFSET 0x7f4
#define GC_GPIO_MASKLOWBYTE_7F4_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7F8_OFFSET 0x7f8
#define GC_GPIO_MASKLOWBYTE_7F8_DEFAULT 0x0
#define GC_GPIO_MASKLOWBYTE_7FC_OFFSET 0x7fc
#define GC_GPIO_MASKLOWBYTE_7FC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_800_OFFSET 0x800
#define GC_GPIO_MASKHIGHBYTE_800_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_804_OFFSET 0x804
#define GC_GPIO_MASKHIGHBYTE_804_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_808_OFFSET 0x808
#define GC_GPIO_MASKHIGHBYTE_808_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_80C_OFFSET 0x80c
#define GC_GPIO_MASKHIGHBYTE_80C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_810_OFFSET 0x810
#define GC_GPIO_MASKHIGHBYTE_810_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_814_OFFSET 0x814
#define GC_GPIO_MASKHIGHBYTE_814_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_818_OFFSET 0x818
#define GC_GPIO_MASKHIGHBYTE_818_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_81C_OFFSET 0x81c
#define GC_GPIO_MASKHIGHBYTE_81C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_820_OFFSET 0x820
#define GC_GPIO_MASKHIGHBYTE_820_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_824_OFFSET 0x824
#define GC_GPIO_MASKHIGHBYTE_824_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_828_OFFSET 0x828
#define GC_GPIO_MASKHIGHBYTE_828_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_82C_OFFSET 0x82c
#define GC_GPIO_MASKHIGHBYTE_82C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_830_OFFSET 0x830
#define GC_GPIO_MASKHIGHBYTE_830_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_834_OFFSET 0x834
#define GC_GPIO_MASKHIGHBYTE_834_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_838_OFFSET 0x838
#define GC_GPIO_MASKHIGHBYTE_838_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_83C_OFFSET 0x83c
#define GC_GPIO_MASKHIGHBYTE_83C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_840_OFFSET 0x840
#define GC_GPIO_MASKHIGHBYTE_840_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_844_OFFSET 0x844
#define GC_GPIO_MASKHIGHBYTE_844_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_848_OFFSET 0x848
#define GC_GPIO_MASKHIGHBYTE_848_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_84C_OFFSET 0x84c
#define GC_GPIO_MASKHIGHBYTE_84C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_850_OFFSET 0x850
#define GC_GPIO_MASKHIGHBYTE_850_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_854_OFFSET 0x854
#define GC_GPIO_MASKHIGHBYTE_854_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_858_OFFSET 0x858
#define GC_GPIO_MASKHIGHBYTE_858_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_85C_OFFSET 0x85c
#define GC_GPIO_MASKHIGHBYTE_85C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_860_OFFSET 0x860
#define GC_GPIO_MASKHIGHBYTE_860_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_864_OFFSET 0x864
#define GC_GPIO_MASKHIGHBYTE_864_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_868_OFFSET 0x868
#define GC_GPIO_MASKHIGHBYTE_868_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_86C_OFFSET 0x86c
#define GC_GPIO_MASKHIGHBYTE_86C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_870_OFFSET 0x870
#define GC_GPIO_MASKHIGHBYTE_870_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_874_OFFSET 0x874
#define GC_GPIO_MASKHIGHBYTE_874_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_878_OFFSET 0x878
#define GC_GPIO_MASKHIGHBYTE_878_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_87C_OFFSET 0x87c
#define GC_GPIO_MASKHIGHBYTE_87C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_880_OFFSET 0x880
#define GC_GPIO_MASKHIGHBYTE_880_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_884_OFFSET 0x884
#define GC_GPIO_MASKHIGHBYTE_884_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_888_OFFSET 0x888
#define GC_GPIO_MASKHIGHBYTE_888_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_88C_OFFSET 0x88c
#define GC_GPIO_MASKHIGHBYTE_88C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_890_OFFSET 0x890
#define GC_GPIO_MASKHIGHBYTE_890_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_894_OFFSET 0x894
#define GC_GPIO_MASKHIGHBYTE_894_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_898_OFFSET 0x898
#define GC_GPIO_MASKHIGHBYTE_898_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_89C_OFFSET 0x89c
#define GC_GPIO_MASKHIGHBYTE_89C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8A0_OFFSET 0x8a0
#define GC_GPIO_MASKHIGHBYTE_8A0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8A4_OFFSET 0x8a4
#define GC_GPIO_MASKHIGHBYTE_8A4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8A8_OFFSET 0x8a8
#define GC_GPIO_MASKHIGHBYTE_8A8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8AC_OFFSET 0x8ac
#define GC_GPIO_MASKHIGHBYTE_8AC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8B0_OFFSET 0x8b0
#define GC_GPIO_MASKHIGHBYTE_8B0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8B4_OFFSET 0x8b4
#define GC_GPIO_MASKHIGHBYTE_8B4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8B8_OFFSET 0x8b8
#define GC_GPIO_MASKHIGHBYTE_8B8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8BC_OFFSET 0x8bc
#define GC_GPIO_MASKHIGHBYTE_8BC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8C0_OFFSET 0x8c0
#define GC_GPIO_MASKHIGHBYTE_8C0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8C4_OFFSET 0x8c4
#define GC_GPIO_MASKHIGHBYTE_8C4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8C8_OFFSET 0x8c8
#define GC_GPIO_MASKHIGHBYTE_8C8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8CC_OFFSET 0x8cc
#define GC_GPIO_MASKHIGHBYTE_8CC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8D0_OFFSET 0x8d0
#define GC_GPIO_MASKHIGHBYTE_8D0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8D4_OFFSET 0x8d4
#define GC_GPIO_MASKHIGHBYTE_8D4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8D8_OFFSET 0x8d8
#define GC_GPIO_MASKHIGHBYTE_8D8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8DC_OFFSET 0x8dc
#define GC_GPIO_MASKHIGHBYTE_8DC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8E0_OFFSET 0x8e0
#define GC_GPIO_MASKHIGHBYTE_8E0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8E4_OFFSET 0x8e4
#define GC_GPIO_MASKHIGHBYTE_8E4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8E8_OFFSET 0x8e8
#define GC_GPIO_MASKHIGHBYTE_8E8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8EC_OFFSET 0x8ec
#define GC_GPIO_MASKHIGHBYTE_8EC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8F0_OFFSET 0x8f0
#define GC_GPIO_MASKHIGHBYTE_8F0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8F4_OFFSET 0x8f4
#define GC_GPIO_MASKHIGHBYTE_8F4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8F8_OFFSET 0x8f8
#define GC_GPIO_MASKHIGHBYTE_8F8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_8FC_OFFSET 0x8fc
#define GC_GPIO_MASKHIGHBYTE_8FC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_900_OFFSET 0x900
#define GC_GPIO_MASKHIGHBYTE_900_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_904_OFFSET 0x904
#define GC_GPIO_MASKHIGHBYTE_904_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_908_OFFSET 0x908
#define GC_GPIO_MASKHIGHBYTE_908_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_90C_OFFSET 0x90c
#define GC_GPIO_MASKHIGHBYTE_90C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_910_OFFSET 0x910
#define GC_GPIO_MASKHIGHBYTE_910_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_914_OFFSET 0x914
#define GC_GPIO_MASKHIGHBYTE_914_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_918_OFFSET 0x918
#define GC_GPIO_MASKHIGHBYTE_918_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_91C_OFFSET 0x91c
#define GC_GPIO_MASKHIGHBYTE_91C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_920_OFFSET 0x920
#define GC_GPIO_MASKHIGHBYTE_920_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_924_OFFSET 0x924
#define GC_GPIO_MASKHIGHBYTE_924_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_928_OFFSET 0x928
#define GC_GPIO_MASKHIGHBYTE_928_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_92C_OFFSET 0x92c
#define GC_GPIO_MASKHIGHBYTE_92C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_930_OFFSET 0x930
#define GC_GPIO_MASKHIGHBYTE_930_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_934_OFFSET 0x934
#define GC_GPIO_MASKHIGHBYTE_934_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_938_OFFSET 0x938
#define GC_GPIO_MASKHIGHBYTE_938_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_93C_OFFSET 0x93c
#define GC_GPIO_MASKHIGHBYTE_93C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_940_OFFSET 0x940
#define GC_GPIO_MASKHIGHBYTE_940_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_944_OFFSET 0x944
#define GC_GPIO_MASKHIGHBYTE_944_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_948_OFFSET 0x948
#define GC_GPIO_MASKHIGHBYTE_948_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_94C_OFFSET 0x94c
#define GC_GPIO_MASKHIGHBYTE_94C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_950_OFFSET 0x950
#define GC_GPIO_MASKHIGHBYTE_950_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_954_OFFSET 0x954
#define GC_GPIO_MASKHIGHBYTE_954_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_958_OFFSET 0x958
#define GC_GPIO_MASKHIGHBYTE_958_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_95C_OFFSET 0x95c
#define GC_GPIO_MASKHIGHBYTE_95C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_960_OFFSET 0x960
#define GC_GPIO_MASKHIGHBYTE_960_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_964_OFFSET 0x964
#define GC_GPIO_MASKHIGHBYTE_964_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_968_OFFSET 0x968
#define GC_GPIO_MASKHIGHBYTE_968_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_96C_OFFSET 0x96c
#define GC_GPIO_MASKHIGHBYTE_96C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_970_OFFSET 0x970
#define GC_GPIO_MASKHIGHBYTE_970_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_974_OFFSET 0x974
#define GC_GPIO_MASKHIGHBYTE_974_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_978_OFFSET 0x978
#define GC_GPIO_MASKHIGHBYTE_978_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_97C_OFFSET 0x97c
#define GC_GPIO_MASKHIGHBYTE_97C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_980_OFFSET 0x980
#define GC_GPIO_MASKHIGHBYTE_980_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_984_OFFSET 0x984
#define GC_GPIO_MASKHIGHBYTE_984_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_988_OFFSET 0x988
#define GC_GPIO_MASKHIGHBYTE_988_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_98C_OFFSET 0x98c
#define GC_GPIO_MASKHIGHBYTE_98C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_990_OFFSET 0x990
#define GC_GPIO_MASKHIGHBYTE_990_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_994_OFFSET 0x994
#define GC_GPIO_MASKHIGHBYTE_994_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_998_OFFSET 0x998
#define GC_GPIO_MASKHIGHBYTE_998_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_99C_OFFSET 0x99c
#define GC_GPIO_MASKHIGHBYTE_99C_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9A0_OFFSET 0x9a0
#define GC_GPIO_MASKHIGHBYTE_9A0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9A4_OFFSET 0x9a4
#define GC_GPIO_MASKHIGHBYTE_9A4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9A8_OFFSET 0x9a8
#define GC_GPIO_MASKHIGHBYTE_9A8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9AC_OFFSET 0x9ac
#define GC_GPIO_MASKHIGHBYTE_9AC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9B0_OFFSET 0x9b0
#define GC_GPIO_MASKHIGHBYTE_9B0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9B4_OFFSET 0x9b4
#define GC_GPIO_MASKHIGHBYTE_9B4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9B8_OFFSET 0x9b8
#define GC_GPIO_MASKHIGHBYTE_9B8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9BC_OFFSET 0x9bc
#define GC_GPIO_MASKHIGHBYTE_9BC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9C0_OFFSET 0x9c0
#define GC_GPIO_MASKHIGHBYTE_9C0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9C4_OFFSET 0x9c4
#define GC_GPIO_MASKHIGHBYTE_9C4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9C8_OFFSET 0x9c8
#define GC_GPIO_MASKHIGHBYTE_9C8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9CC_OFFSET 0x9cc
#define GC_GPIO_MASKHIGHBYTE_9CC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9D0_OFFSET 0x9d0
#define GC_GPIO_MASKHIGHBYTE_9D0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9D4_OFFSET 0x9d4
#define GC_GPIO_MASKHIGHBYTE_9D4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9D8_OFFSET 0x9d8
#define GC_GPIO_MASKHIGHBYTE_9D8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9DC_OFFSET 0x9dc
#define GC_GPIO_MASKHIGHBYTE_9DC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9E0_OFFSET 0x9e0
#define GC_GPIO_MASKHIGHBYTE_9E0_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9E4_OFFSET 0x9e4
#define GC_GPIO_MASKHIGHBYTE_9E4_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9E8_OFFSET 0x9e8
#define GC_GPIO_MASKHIGHBYTE_9E8_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9EC_OFFSET 0x9ec
#define GC_GPIO_MASKHIGHBYTE_9EC_DEFAULT 0x0
#define GC_GPIO_MASKHIGHBYTE_9F0_OFFSET 0x9f0
#define GC_GPIO_MASKHIGHBYTE_9F0_DEFAULT 0x0
#define GC_GPIO_MASKHIG