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  1. /* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
  2. * Use of this source code is governed by a BSD-style license that can be
  3. * found in the LICENSE file.
  4. */
  5. /*
  6. * config.h - Top-level configuration Chrome EC
  7. *
  8. * All configuration settings (CONFIG_*) are defined in this file or in a
  9. * sub-configuration file (config_chip.h, board.h, etc.) included by this file.
  10. *
  11. * Note that this file is included by assembly (.S) files. Any C-isms such as
  12. * struct definitions or enums in a sub-configuration file MUST be guarded with
  13. * #ifndef __ASSEMBLER__ to prevent those C-isms from being evaluated by the
  14. * assembler.
  15. */
  16. #ifndef __CROS_EC_CONFIG_H
  17. #define __CROS_EC_CONFIG_H
  18. /*
  19. * All config options are listed alphabetically and described here.
  20. *
  21. * If you add a new config option somewhere in the code, you must add a
  22. * default value here and describe what it does.
  23. *
  24. * To get a list current list, run this command:
  25. * git grep " CONFIG_" | grep -o "CONFIG_[A-Za-z0-9_]\+" | sort | uniq
  26. *
  27. * Some options are #defined here to enable them by default. Chips or boards
  28. * may override this by #undef'ing them in config_chip.h or board.h,
  29. * respectively.
  30. *
  31. * TODO(crosbug.com/p/23758): Describe all of these. Also describe the
  32. * HAS_TASK_* macro and how/when it should be used vs. a config define. And
  33. * BOARD_*, CHIP_*, and CHIP_FAMILY_*.
  34. */
  35. /* Enable accelerometer interrupts. */
  36. #undef CONFIG_ACCEL_INTERRUPTS
  37. /* Add support for sensor FIFO:
  38. * define the size of the global fifo, must be a power of 2. */
  39. #undef CONFIG_ACCEL_FIFO
  40. /* The amount of free entries that trigger an interrupt to the AP. */
  41. #undef CONFIG_ACCEL_FIFO_THRES
  42. /* Specify type of accelerometers attached. */
  43. #undef CONFIG_ACCEL_KXCJ9
  44. #undef CONFIG_ACCELGYRO_LSM6DS0
  45. #undef CONFIG_ACCELGYRO_BMI160
  46. /* Compile chip support for analog-to-digital convertor */
  47. #undef CONFIG_ADC
  48. /* ADC sample time selection. The value is chip-dependent. */
  49. #undef CONFIG_ADC_SAMPLE_TIME
  50. /* Include the ADC analog watchdog feature in the ADC code */
  51. #define CONFIG_ADC_WATCHDOG
  52. /*
  53. * Some ALS modules may be connected to the EC. We need the command, and
  54. * specific drivers for each module.
  55. */
  56. #undef CONFIG_ALS
  57. #undef CONFIG_ALS_ISL29035
  58. #undef CONFIG_ALS_OPT3001
  59. /* Support AP hang detection host command and state machine */
  60. #undef CONFIG_AP_HANG_DETECT
  61. /* Support AP Warm reset Interrupt. */
  62. #undef CONFIG_AP_WARM_RESET_INTERRUPT
  63. /*
  64. * Support controlling the display backlight based on the state of the lid
  65. * switch. The EC will disable the backlight when the lid is closed.
  66. */
  67. #undef CONFIG_BACKLIGHT_LID
  68. /*
  69. * If defined, EC will enable the backlight signal only if this GPIO is
  70. * asserted AND the lid is open. This supports passing the backlight-enable
  71. * signal from the AP through EC.
  72. */
  73. #undef CONFIG_BACKLIGHT_REQ_GPIO
  74. /*****************************************************************************/
  75. /* Battery config */
  76. /* Support a simple battery. */
  77. #undef CONFIG_BATTERY
  78. /*
  79. * Compile battery-specific code.
  80. *
  81. * Note that some boards have their own unique battery constants / functions.
  82. * In this case, those are provided in board/(boardname)/battery.c, and none of
  83. * these are defined.
  84. */
  85. #undef CONFIG_BATTERY_BQ20Z453
  86. #undef CONFIG_BATTERY_BQ27541
  87. #undef CONFIG_BATTERY_BQ27621
  88. #undef CONFIG_BATTERY_RYU
  89. #undef CONFIG_BATTERY_SAMUS
  90. /* Compile mock battery support; used by tests. */
  91. #undef CONFIG_BATTERY_MOCK
  92. /*
  93. * Charger should call battery_override_params() to limit/correct the voltage
  94. * and current requested by the battery pack before acting on the request.
  95. *
  96. * This is valid with CONFIG_CHARGER_V1 only.
  97. */
  98. #undef CONFIG_BATTERY_OVERRIDE_PARAMS
  99. /*
  100. * If defined, the charger will check for battery presence before attempting
  101. * to communicate with it. This avoids the 30 second delay when booting
  102. * without a battery present. Do not use with CONFIG_BATTERY_PRESENT_GPIO.
  103. *
  104. * Replace the default battery_is_present() function with a board-specific
  105. * implementation in board.c
  106. */
  107. #undef CONFIG_BATTERY_PRESENT_CUSTOM
  108. /*
  109. * If defined, GPIO which is driven low when battery is present.
  110. * Charger will check for battery presence before attempting to communicate
  111. * with it. This avoids the 30 second delay when booting without a battery
  112. * present. Do not use with CONFIG_BATTERY_PRESENT_CUSTOM.
  113. */
  114. #undef CONFIG_BATTERY_PRESENT_GPIO
  115. /*
  116. * Compile smart battery support
  117. *
  118. * For batteries which support this specification:
  119. * http://sbs-forum.org/specs/sbdat110.pdf)
  120. */
  121. #undef CONFIG_BATTERY_SMART
  122. /*
  123. * Critical battery shutdown timeout (seconds)
  124. *
  125. * If the battery is at extremely low charge (and discharging) or extremely
  126. * high temperature, the EC will shut itself down. This defines the timeout
  127. * period in seconds between the critical condition being detected and the
  128. * EC shutting itself down. Note that if the critical condition is corrected
  129. * before the timeout expiration, the EC will not shut itself down.
  130. *
  131. */
  132. #define CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT 30
  133. /*
  134. * Support battery cut-off as host command and console command.
  135. *
  136. * Once defined, you have to implement a board_cut_off_battery() function
  137. * in board/???/battery.c file.
  138. */
  139. #undef CONFIG_BATTERY_CUT_OFF
  140. /*
  141. * The default delay is 1 second. Define this if a board prefers
  142. * different delay.
  143. */
  144. #undef CONFIG_BATTERY_CUTOFF_DELAY_US
  145. /*
  146. * The board-specific battery.c implements get and set functions to read and
  147. * write arbirary vendor-specific parameters stored in the battery.
  148. * See include/battery.h for prototypes.
  149. */
  150. #undef CONFIG_BATTERY_VENDOR_PARAM
  151. /*
  152. * TODO(crosbug.com/p/29467): allows charging of a dead battery that
  153. * requests nil for current and voltage. Remove this workaround when
  154. * possible.
  155. */
  156. #undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
  157. /*
  158. * Check for battery in disconnect state (similar to cut-off state). If this
  159. * battery is found to be in disconnect state, take it out of this state by
  160. * force-applying a charge current.
  161. */
  162. #undef CONFIG_BATTERY_REVIVE_DISCONNECT
  163. /* Boot header storage offset. */
  164. #undef CONFIG_BOOT_HEADER_STORAGE_OFF
  165. /* Size of boot header in storage. */
  166. #undef CONFIG_BOOT_HEADER_STORAGE_SIZE
  167. /*****************************************************************************/
  168. /*
  169. * Call board_config_post_gpio_init() after GPIOs are initialized. See
  170. * include/board_config.h for more information.
  171. */
  172. #undef CONFIG_BOARD_POST_GPIO_INIT
  173. /*
  174. * Call board_config_pre_init() before any inits are called. See
  175. * include/board_config.h for more information.
  176. */
  177. #undef CONFIG_BOARD_PRE_INIT
  178. /* EC has GPIOs attached to board version stuffing resistors */
  179. #undef CONFIG_BOARD_VERSION
  180. /* Permanent LM4 boot configuration */
  181. #undef CONFIG_BOOTCFG_VALUE
  182. /******************************************************************************/
  183. /* Oak Board Revisions */
  184. #undef CONFIG_BOARD_OAK_REV_1
  185. #undef CONFIG_BOARD_OAK_REV_2
  186. #undef CONFIG_BOARD_OAK_REV_3
  187. /*****************************************************************************/
  188. /* Modify the default behavior to make system bringup easier. */
  189. #undef CONFIG_BRINGUP
  190. /*
  191. * Enable debug prints / asserts that may helpful for debugging board bring-up,
  192. * but probably shouldn't be enabled for production for performance reasons.
  193. */
  194. #undef CONFIG_DEBUG_BRINGUP
  195. /*****************************************************************************/
  196. /*
  197. * Number of extra buttons not on the keyboard scan matrix. Doesn't include
  198. * the power button, which has its own handler.
  199. */
  200. #undef CONFIG_BUTTON_COUNT
  201. /*
  202. * Enable case close debug (CCD) mode.
  203. */
  204. #undef CONFIG_CASE_CLOSED_DEBUG
  205. /*
  206. * Capsense chip has buttons, too.
  207. */
  208. #undef CONFIG_CAPSENSE
  209. /*****************************************************************************/
  210. /* Compile charge manager */
  211. #undef CONFIG_CHARGE_MANAGER
  212. /* Compile input current ramping support */
  213. #undef CONFIG_CHARGE_RAMP
  214. /* The hardware has some input current ramping/back-off mechanism */
  215. #undef CONFIG_CHARGE_RAMP_HW
  216. /*****************************************************************************/
  217. /* Charger config */
  218. /* Compile common charge state code. You must pick an implementation. */
  219. #undef CONFIG_CHARGER
  220. #undef CONFIG_CHARGER_V1
  221. #undef CONFIG_CHARGER_V2
  222. /* Compile charger-specific code for these chargers (pick at most one) */
  223. #undef CONFIG_CHARGER_BQ24707A
  224. #undef CONFIG_CHARGER_BQ24715
  225. #undef CONFIG_CHARGER_BQ24725
  226. #undef CONFIG_CHARGER_BQ24735
  227. #undef CONFIG_CHARGER_BQ24738
  228. #undef CONFIG_CHARGER_BQ24770
  229. #undef CONFIG_CHARGER_BQ24773
  230. #undef CONFIG_CHARGER_BQ25890
  231. #undef CONFIG_CHARGER_BQ25892
  232. #undef CONFIG_CHARGER_BQ25895
  233. #undef CONFIG_CHARGER_ISL9237
  234. #undef CONFIG_CHARGER_TPS65090 /* Note: does not use CONFIG_CHARGER */
  235. /*
  236. * BQ2589x IR Compensation settings.
  237. * Should be the combination of BQ2589X_IR_TREG_xxxC, BQ2589X_IR_VCLAMP_yyyMV
  238. * and BQ2589X_IR_BAT_COMP_zzzMOHM.
  239. */
  240. #undef CONFIG_CHARGER_BQ2589X_IR_COMP
  241. /*
  242. * BQ2589x 5V boost current limit and voltage.
  243. * Should be the combination of BQ2589X_BOOSTV_MV(voltage) and
  244. * BQ2589X_BOOST_LIM_xxxMA.
  245. */
  246. #undef CONFIG_CHARGER_BQ2589X_BOOST
  247. /*
  248. * Board specific charging current limit, in mA. If defined, the charge state
  249. * machine will not allow the battery to request more current than this.
  250. */
  251. #undef CONFIG_CHARGER_CURRENT_LIMIT
  252. /*
  253. * Board supports discharge mode. In this mode, the battery will discharge
  254. * even if AC is present. Used for testing.
  255. */
  256. #undef CONFIG_CHARGER_DISCHARGE_ON_AC
  257. /* Board has a custom discharge mode. */
  258. #undef CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
  259. /*
  260. * Board specific flag used to disable external ILIM pin used to determine input
  261. * current limit. When defined, the input current limit is decided only by
  262. * the software register value.
  263. */
  264. #undef CONFIG_CHARGER_ILIM_PIN_DISABLED
  265. /*
  266. * Default input current for the board, in mA.
  267. *
  268. * This value should depend on external power adapter, designed charging
  269. * voltage, and the maximum power of the running system. For type-C chargers,
  270. * this should be set to 512 mA in order to not brown-out low-current USB
  271. * charge ports.
  272. */
  273. #undef CONFIG_CHARGER_INPUT_CURRENT
  274. /*
  275. * Board specific maximum input current limit, in mA.
  276. */
  277. #undef CONFIG_CHARGER_MAX_INPUT_CURRENT
  278. /* Minimum battery percentage for power on */
  279. #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
  280. /*
  281. * Equivalent of CONFIG_BATTERY_OVERRIDE_PARAMS for use with
  282. * CONFIG_CHARGER_V2
  283. */
  284. #undef CONFIG_CHARGER_PROFILE_OVERRIDE
  285. /* Value of the charge sense resistor, in mOhms */
  286. #undef CONFIG_CHARGER_SENSE_RESISTOR
  287. /* Value of the input current sense resistor, in mOhms */
  288. #undef CONFIG_CHARGER_SENSE_RESISTOR_AC
  289. /*
  290. * Maximum time to charge the battery, in hours.
  291. *
  292. * If this timeout is reached, the charger will enter force-idle state.
  293. * If not defined, charger will provide current until the battery asks it to
  294. * stop.
  295. */
  296. #undef CONFIG_CHARGER_TIMEOUT_HOURS
  297. /*
  298. * Board has an GPIO pin to enable or disable charging.
  299. *
  300. * This GPIO should be named GPIO_CHARGER_EN, if active high. Or
  301. * GPIO_CHARGER_EN_L if active low.
  302. */
  303. #undef CONFIG_CHARGER_EN_GPIO
  304. /* Charger enable GPIO is active low */
  305. #undef CONFIG_CHARGER_EN_ACTIVE_LOW
  306. /*****************************************************************************/
  307. /* Chipset config */
  308. /* AP chipset support; pick at most one */
  309. #undef CONFIG_CHIPSET_BAYTRAIL /* Intel Bay Trail (x86) */
  310. #undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */
  311. #undef CONFIG_CHIPSET_ECDRIVEN /* Dummy power module */
  312. #undef CONFIG_CHIPSET_GAIA /* Gaia and Ares (ARM) */
  313. #undef CONFIG_CHIPSET_HASWELL /* Intel Haswell (x86) */
  314. #undef CONFIG_CHIPSET_MEDIATEK /* MediaTek MT81xx */
  315. #undef CONFIG_CHIPSET_ROCKCHIP /* Rockchip rk32xx */
  316. #undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */
  317. #undef CONFIG_CHIPSET_TEGRA /* nVidia Tegra 5 */
  318. /* Support chipset throttling */
  319. #undef CONFIG_CHIPSET_CAN_THROTTLE
  320. /* Enable additional chipset debugging */
  321. #undef CONFIG_CHIPSET_DEBUG
  322. /* Support power rail control */
  323. #define CONFIG_CHIPSET_HAS_PP1350
  324. #define CONFIG_CHIPSET_HAS_PP5000
  325. /*****************************************************************************/
  326. /*
  327. * Chip config for clock circuitry
  328. * define = crystal / undef = oscillator
  329. */
  330. #undef CONFIG_CLOCK_CRYSTAL
  331. /*****************************************************************************/
  332. /* PMIC config */
  333. /* Support firmware long press power-off timer */
  334. #undef CONFIG_PMIC_FW_LONG_PRESS_TIMER
  335. /* Support PMIC power control */
  336. #undef CONFIG_PMIC
  337. /*****************************************************************************/
  338. /*
  339. * Optional console commands
  340. *
  341. * Defining these options will enable the corresponding command on the EC
  342. * console.
  343. */
  344. #undef CONFIG_CMD_ACCELS
  345. #undef CONFIG_CMD_ACCEL_INFO
  346. #undef CONFIG_CMD_BATDEBUG
  347. #define CONFIG_CMD_CHARGER
  348. #undef CONFIG_CMD_CHGRAMP
  349. #undef CONFIG_CMD_CLOCKGATES
  350. #undef CONFIG_CMD_COMXTEST
  351. #undef CONFIG_CMD_ECTEMP
  352. #define CONFIG_CMD_FASTCHARGE
  353. #undef CONFIG_CMD_FLASH
  354. #undef CONFIG_CMD_FORCETIME
  355. #undef CONFIG_CMD_GSV
  356. #define CONFIG_CMD_HASH
  357. #undef CONFIG_CMD_HOSTCMD
  358. #define CONFIG_CMD_I2C_SCAN
  359. #define CONFIG_CMD_I2C_XFER
  360. #undef CONFIG_CMD_I2CWEDGE
  361. #define CONFIG_CMD_IDLE_STATS
  362. #undef CONFIG_CMD_ILIM
  363. #define CONFIG_CMD_INA
  364. #define CONFIG_CMD_REGULATOR
  365. #undef CONFIG_CMD_JUMPTAGS
  366. #undef CONFIG_CMD_LID_ANGLE
  367. #undef CONFIG_CMD_MCDP
  368. #define CONFIG_CMD_PD
  369. #undef CONFIG_CMD_PD_DEV_DUMP_INFO
  370. #undef CONFIG_CMD_PD_FLASH
  371. #undef CONFIG_CMD_PLL
  372. #undef CONFIG_CMD_PMU
  373. #define CONFIG_CMD_POWER_AP
  374. #define CONFIG_CMD_POWERINDEBUG
  375. #undef CONFIG_CMD_POWERLED
  376. #undef CONFIG_CMD_RTC_ALARM
  377. #undef CONFIG_CMD_SCRATCHPAD
  378. #define CONFIG_CMD_SHMEM
  379. #undef CONFIG_CMD_SLEEP
  380. #undef CONFIG_CMD_SPI_FLASH
  381. #undef CONFIG_CMD_STACKOVERFLOW
  382. #undef CONFIG_CMD_TASKREADY
  383. #define CONFIG_CMD_TEMP_SENSOR
  384. #define CONFIG_CMD_TIMERINFO
  385. #define CONFIG_CMD_TYPEC
  386. #undef CONFIG_CMD_USB_PD_PE
  387. #define CONFIG_CMD_USBMUX
  388. /*****************************************************************************/
  389. /* Support Code RAM architecture (run code in RAM). */
  390. #undef CONFIG_CODERAM_ARCH
  391. /* Base address of Code RAM. */
  392. #undef CONFIG_CDRAM_BASE
  393. /* Size of Code RAM. */
  394. #undef CONFIG_CDRAM_SIZE
  395. /* Provide common core code to output panic information without interrupts. */
  396. #define CONFIG_COMMON_PANIC_OUTPUT
  397. /*
  398. * Store a panic log and halt the system for a software-related reasons, such as
  399. * stack overflow or assertion failure.
  400. */
  401. #undef CONFIG_SOFTWARE_PANIC
  402. /*
  403. * Provide the default GPIO abstraction layer.
  404. * You want this unless you are doing a really tiny firmware.
  405. */
  406. #define CONFIG_COMMON_GPIO
  407. /*
  408. * Provides smaller GPIO names to reduce flash size. Instead of the 'name'
  409. * field in GPIO macro it will concat 'port' and 'pin' to reduce flash size.
  410. */
  411. #undef CONFIG_COMMON_GPIO_SHORTNAMES
  412. /*
  413. * Provide common runtime layer code (tasks, hooks ...)
  414. * You want this unless you are doing a really tiny firmware.
  415. */
  416. #define CONFIG_COMMON_RUNTIME
  417. /* Provide common core code to handle the operating system timers. */
  418. #define CONFIG_COMMON_TIMER
  419. /*****************************************************************************/
  420. /*
  421. * Provide additional help on console commands, such as the supported
  422. * options/usage.
  423. *
  424. * Boards may #undef this to reduce image size.
  425. */
  426. #define CONFIG_CONSOLE_CMDHELP
  427. /*
  428. * Number of entries in console history buffer.
  429. *
  430. * Boards may #undef this to reduce memory usage.
  431. */
  432. #define CONFIG_CONSOLE_HISTORY 8
  433. /* Max length of a single line of input */
  434. #define CONFIG_CONSOLE_INPUT_LINE_SIZE 80
  435. /*
  436. * Disable EC console input if the system is locked. This is needed for
  437. * security on platforms where the EC console is accessible from outside the
  438. * case - for example, via a special USB dongle.
  439. */
  440. #undef CONFIG_CONSOLE_RESTRICTED_INPUT
  441. /* Include CRC-8 utility function */
  442. #undef CONFIG_CRC8
  443. /*****************************************************************************/
  444. /*
  445. * Debugging config
  446. *
  447. * Note that these options are enabled by default, because they're really
  448. * handy for debugging systems during bringup and even at factory time.
  449. *
  450. * A board may undefine any or all of these to reduce image size and RAM usage,
  451. * at the cost of debuggability.
  452. */
  453. /*
  454. * ASSERT() macros are checked at runtime. See CONFIG_DEBUG_ASSERT_REBOOTS
  455. * to see what happens if one fails.
  456. *
  457. * Boards may #undef this to reduce image size.
  458. */
  459. #define CONFIG_DEBUG_ASSERT
  460. /*
  461. * Prints a message and reboots if an ASSERT() macro fails at runtime. When
  462. * enabled, an ASSERT() which fails will produce a message of the form:
  463. *
  464. * ASSERTION FAILURE '<expr>' in function() at file:line
  465. *
  466. * If this is not defined, failing ASSERT() will trigger a BKPT instruction
  467. * instead.
  468. *
  469. * Ignored if CONFIG_DEBUG_ASSERT is not defined.
  470. *
  471. * Boards may #undef this to reduce image size.
  472. */
  473. #define CONFIG_DEBUG_ASSERT_REBOOTS
  474. /*
  475. * On assertion failure, prints only the file name and the line number.
  476. *
  477. * Ignored if CONFIG_DEBUG_ASSERT_REBOOTS is not defined.
  478. *
  479. * Boards may define this to reduce image size.
  480. */
  481. #undef CONFIG_DEBUG_ASSERT_BRIEF
  482. /*
  483. * Disable the write buffer used for default memory map accesses.
  484. * This turns "Imprecise data bus errors" into "Precise" errors
  485. * in exception traces at the cost of some performance.
  486. * This may help identify the offending instruction causing an
  487. * exception. Supported on cortex-m.
  488. */
  489. #undef CONFIG_DEBUG_DISABLE_WRITE_BUFFER
  490. /*
  491. * Print additional information when exceptions are triggered, such as the
  492. * fault address, here shown as bfar. This shows the reason for the fault
  493. * and may help to determine the cause.
  494. *
  495. * === EXCEPTION: 03 ====== xPSR: 01000000 ===========
  496. * r0 :0000000b r1 :00000047 r2 :60000000 r3 :200013dd
  497. * r4 :00000000 r5 :080053f4 r6 :200013d0 r7 :00000002
  498. * r8 :00000000 r9 :200013de r10:00000000 r11:00000000
  499. * r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a
  500. * Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000
  501. * mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008
  502. *
  503. * If this is not defined, only a register dump will be printed.
  504. *
  505. * Boards may #undef this to reduce image size.
  506. */
  507. #define CONFIG_DEBUG_EXCEPTIONS
  508. /* Support Synchronous UART debug printf. */
  509. #undef CONFIG_DEBUG_PRINTF
  510. /* Check for stack overflows on every context switch */
  511. #define CONFIG_DEBUG_STACK_OVERFLOW
  512. /*****************************************************************************/
  513. /* Support DMA transfers inside the EC */
  514. #undef CONFIG_DMA
  515. /* Use the common interrupt handlers for DMA IRQs */
  516. #define CONFIG_DMA_DEFAULT_HANDLERS
  517. /* Compile extra debugging and tests for the DMA module */
  518. #undef CONFIG_DMA_HELP
  519. /* Support EC to Internal bus bridge. */
  520. #undef CONFIG_EC2I
  521. /* Support EC chip internal data EEPROM */
  522. #undef CONFIG_EEPROM
  523. /*
  524. * Compile the eoption module, which provides a higher-level interface to
  525. * options stored in internal data EEPROM.
  526. */
  527. #undef CONFIG_EOPTION
  528. /* Include code for handling external power */
  529. #define CONFIG_EXTPOWER
  530. /* Support detecting external power presence via a GPIO */
  531. #undef CONFIG_EXTPOWER_GPIO
  532. /*****************************************************************************/
  533. /* Number of cooling fans. Undef if none. */
  534. #undef CONFIG_FANS
  535. /*
  536. * Replace the default fan_percent_to_rpm() function with a board-specific
  537. * implementation in board.c
  538. */
  539. #undef CONFIG_FAN_RPM_CUSTOM
  540. /*
  541. * We normally check and update the fans once per second (HOOK_SECOND). If this
  542. * is #defined to a postive integer N, we will only update the fans every N
  543. * seconds instead.
  544. */
  545. #undef CONFIG_FAN_UPDATE_PERIOD
  546. /*****************************************************************************/
  547. /* Flash configuration */
  548. /* Support programming on-chip flash */
  549. #define CONFIG_FLASH
  550. #undef CONFIG_FLASH_BANK_SIZE
  551. #undef CONFIG_FLASH_BASE
  552. #undef CONFIG_FLASH_ERASED_VALUE32
  553. #undef CONFIG_FLASH_ERASE_SIZE
  554. /*
  555. * Flash is directly mapped into the EC's address space. If this is not
  556. * defined, the flash driver must implement flash_physical_read().
  557. */
  558. #define CONFIG_FLASH_MAPPED
  559. #undef CONFIG_FLASH_PHYSICAL_SIZE
  560. #undef CONFIG_FLASH_PROTECT_NEXT_BOOT
  561. /*
  562. * Store persistent write protect for the flash inside the flash data itself.
  563. * This allows ECs with internal flash to emulate something closer to a SPI
  564. * flash write protect register. If this is not defined, write protect state
  565. * is maintained solely by the physical flash driver.
  566. */
  567. #define CONFIG_FLASH_PSTATE
  568. /*
  569. * Store the pstate data in its own dedicated bank of flash. This allows
  570. * disabling the protect-RO-at-boot flag without rewriting the RO firmware,
  571. * but costs a bank of flash.
  572. *
  573. * If this is not defined, the pstate data is stored inside the RO firmware
  574. * image itself. This is more space-efficient, but the only way to clear the
  575. * flag once it's set is to rewrite the RO firmware (after removing the WP
  576. * screw, of course).
  577. */
  578. #define CONFIG_FLASH_PSTATE_BANK
  579. #undef CONFIG_FLASH_SIZE
  580. #undef CONFIG_FLASH_WRITE_IDEAL_SIZE
  581. #undef CONFIG_FLASH_WRITE_SIZE
  582. /* Base address of SPI Flash. */
  583. #undef CONFIG_FLASH_BASE_SPI
  584. /*****************************************************************************/
  585. /* Include a flashmap in the compiled firmware image */
  586. #define CONFIG_FMAP
  587. /* Allow EC serial console input to wake up the EC from STOP mode */
  588. #undef CONFIG_FORCE_CONSOLE_RESUME
  589. /* Enable support for floating point unit */
  590. #undef CONFIG_FPU
  591. /*****************************************************************************/
  592. /* Firmware region configuration */
  593. #undef CONFIG_FW_IMAGE_SIZE
  594. #undef CONFIG_FW_PSTATE_OFF
  595. #undef CONFIG_FW_PSTATE_SIZE
  596. /*
  597. * Read-only / read-write image configuration.
  598. * Images may reside on storage (ex. external or internal SPI) at a different
  599. * offset than when copied to program memory. Hence, two sets of offsets,
  600. * for STORAGE and for MEMORY.
  601. */
  602. #undef CONFIG_RO_MEM_OFF
  603. #undef CONFIG_RO_STORAGE_OFF
  604. #undef CONFIG_RO_SIZE
  605. #undef CONFIG_RW_MEM_OFF
  606. #undef CONFIG_RW_STORAGE_OFF
  607. #undef CONFIG_RW_SIZE
  608. /*
  609. * Write protect region offset / size. This region normally encompasses the
  610. * RO image, but may also contain additional images or data.
  611. */
  612. #undef CONFIG_WP_OFF
  613. #undef CONFIG_WP_SIZE
  614. /*
  615. * Board Image ec.bin contains a RO firmware. If not defined, the image will
  616. * only contain the RW firmware. The RO firmware comes from another board.
  617. */
  618. #define CONFIG_FW_INCLUDE_RO
  619. /* If defined, another image (RW) exists with more features */
  620. #undef CONFIG_FW_LIMITED_IMAGE
  621. /*
  622. * If defined, we can use system_get_fw_reset_vector function to decide
  623. * reset vector of RO/RW firmware for sysjump.
  624. */
  625. #undef CONFIG_FW_RESET_VECTOR
  626. /*****************************************************************************/
  627. /* Motion sensor based gesture recognition information */
  628. /* These all require HAS_TASK_MOTIONSENSE to work */
  629. /* Do we want to detect gestures? */
  630. #undef CONFIG_GESTURE_DETECTION
  631. /* Which sensor to look for gesture recognition */
  632. #undef CONFIG_GESTURE_SENSOR_BATTERY_TAP
  633. /* Sensor sampling interval for gesture recognition */
  634. #undef CONFIG_GESTURE_SAMPLING_INTERVAL_MS
  635. /*
  636. * Double tap detection parameters
  637. * Double tap works by looking for two isolated Z-axis accelerometer impulses
  638. * preceded and followed by relatively calm periods of accelerometer motion.
  639. *
  640. * Define an outer and inner window. The inner window specifies how
  641. * long the tap impulse is expected to last. The outer window specifies the
  642. * period before the initial tap impluse and after the final tap impulse for
  643. * which to check for relatively calm periods. In between the two impulses
  644. * there is a minimum and maximum interstice time allowed.
  645. */
  646. #undef CONFIG_GESTURE_TAP_OUTER_WINDOW_T
  647. #undef CONFIG_GESTURE_TAP_INNER_WINDOW_T
  648. #undef CONFIG_GESTURE_TAP_MIN_INTERSTICE_T
  649. #undef CONFIG_GESTURE_TAP_MAX_INTERSTICE_T
  650. /* Do we want to detect the lid angle? */
  651. #undef CONFIG_LID_ANGLE
  652. /* Which sensor is located on the base? */
  653. #undef CONFIG_LID_ANGLE_SENSOR_BASE
  654. /* Which sensor is located on the lid? */
  655. #undef CONFIG_LID_ANGLE_SENSOR_LID
  656. /*
  657. * Allows using the lid angle measurement to determine if key scanning should
  658. * be enabled or disabled when chipset is suspended.
  659. */
  660. #undef CONFIG_LID_ANGLE_KEY_SCAN
  661. /* Define which index in motion_sensors is in the base. */
  662. #undef CONFIG_SENSOR_BASE
  663. /* Define which index in motion_sensors is in the lid. */
  664. #undef CONFIG_SENSOR_LID
  665. /******************************************************************************/
  666. /* Host to RAM (H2RAM) Memory Mapping */
  667. /* H2RAM Base memory address */
  668. #undef CONFIG_H2RAM_BASE
  669. /* H2RAM Size */
  670. #undef CONFIG_H2RAM_SIZE
  671. /* H2RAM Host LPC I/O base memory address */
  672. #undef CONFIG_H2RAM_HOST_LPC_IO_BASE
  673. /*****************************************************************************/
  674. /*
  675. * Support the host asking the EC about the status of the most recent host
  676. * command.
  677. *
  678. * When the AP is attached to the EC via a serialized bus such as I2C or SPI,
  679. * it needs a way to minimize the length of time an EC command will tie up the
  680. * bus (and the kernel driver on the AP). If this config is defined, the EC
  681. * may return an in-progress result code for slow commands such as flash
  682. * erase/write instead of stalling until the command finishes processing, and
  683. * the AP may then inquire the status of the current command and/or the result
  684. * of the previous command.
  685. */
  686. #undef CONFIG_HOST_COMMAND_STATUS
  687. /* If we have host command task, assume we also are using host events. */
  688. #ifdef HAS_TASK_HOSTCMD
  689. #define CONFIG_HOSTCMD_EVENTS
  690. #else
  691. #undef CONFIG_HOSTCMD_EVENTS
  692. #endif
  693. /*
  694. * For ECs where the host command interface is I2C, slave
  695. * address which the EC will respond to.
  696. */
  697. #undef CONFIG_HOSTCMD_I2C_SLAVE_ADDR
  698. /*
  699. * Accept EC host commands over the SPI slave (SPS) interface.
  700. */
  701. #undef CONFIG_HOSTCMD_SPS
  702. /*
  703. * Host command rate limiting assures EC will have time to process lower
  704. * priority tasks even if the AP is hammering the EC with host commands.
  705. * If there is less than CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST between
  706. * host commands for CONFIG_HOSTCMD_RATE_LIMITING_PERIOD, then a
  707. * recess period of CONFIG_HOSTCMD_RATE_LIMITING_RECESS will be
  708. * enforced.
  709. */
  710. #define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC)
  711. #define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC)
  712. #define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC)
  713. /* PD MCU supports host commands */
  714. #undef CONFIG_HOSTCMD_PD
  715. /*
  716. * Use if PD MCU controls charging (selecting charging port and input
  717. * current limit).
  718. */
  719. #undef CONFIG_HOSTCMD_PD_CHG_CTRL
  720. /* Panic when status of PD MCU reflects that it has crashed */
  721. #undef CONFIG_HOSTCMD_PD_PANIC
  722. /*****************************************************************************/
  723. /* Enable debugging and profiling statistics for hook functions */
  724. #undef CONFIG_HOOK_DEBUG
  725. /*****************************************************************************/
  726. /* CRC configuration */
  727. /* Enable the hardware accelerator for CRC computation */
  728. #undef CONFIG_HW_CRC
  729. /* Enable the software routine for CRC computation */
  730. #undef CONFIG_SW_CRC
  731. /*****************************************************************************/
  732. /* Enable system hibernate */
  733. #define CONFIG_HIBERNATE
  734. /* Default delay after shutting down before hibernating */
  735. #define CONFIG_HIBERNATE_DELAY_SEC 3600
  736. /*
  737. * Use to define going in to hibernate early if low on battery.
  738. * CONFIG_HIBERNATE_BATT_PCT specifies the low battery threshold
  739. * for going into hibernate early, and CONFIG_HIBERNATE_BATT_SEC defines
  740. * the minimum amount of time to stay in G3 before checking for low
  741. * battery hibernate.
  742. */
  743. #undef CONFIG_HIBERNATE_BATT_PCT
  744. #undef CONFIG_HIBERNATE_BATT_SEC
  745. /*
  746. * Perform a system reset on wake from hibernate. This is the default behavior,
  747. * and the only chip-supported behavior for certain ECs.
  748. */
  749. #define CONFIG_HIBERNATE_RESET_ON_WAKE
  750. /* For ECs with multiple wakeup pins, define enabled wakeup pins */
  751. #undef CONFIG_HIBERNATE_WAKEUP_PINS
  752. /* Use a hardware specific udelay(). */
  753. #undef CONFIG_HW_SPECIFIC_UDELAY
  754. /*****************************************************************************/
  755. /* I2C configuration */
  756. #undef CONFIG_I2C
  757. #undef CONFIG_I2C_ARBITRATION
  758. #undef CONFIG_I2C_DEBUG
  759. #undef CONFIG_I2C_DEBUG_PASSTHRU
  760. #undef CONFIG_I2C_PASSTHROUGH
  761. #undef CONFIG_I2C_PASSTHRU_RESTRICTED
  762. /* Defines I2C operation retry count when slave nack'd(EC_ERROR_BUSY) */
  763. #define CONFIG_I2C_NACK_RETRY_COUNT 0
  764. /*
  765. * I2C SCL gating.
  766. *
  767. * If CONFIG_I2C_SCL_GATE_ADDR/PORT is defined, whenever the defined address
  768. * is addressed, CONFIG_I2C_SCL_GATE_GPIO is set to high. When the I2C
  769. * transaction is done, the pin is set back to low.
  770. */
  771. #undef CONFIG_I2C_SCL_GATE_PORT
  772. #undef CONFIG_I2C_SCL_GATE_ADDR
  773. #undef CONFIG_I2C_SCL_GATE_GPIO
  774. /*
  775. * I2C multi-port controller.
  776. *
  777. * If CONFIG_I2C_MULTI_PORT_CONTROLLER is defined, a single on-chip I2C
  778. * controller may have multiple I2C ports attached. Therefore, I2c operations
  779. * must lock the controller (not just the port) to prevent hardware access
  780. * conflicts.
  781. */
  782. #undef CONFIG_I2C_MULTI_PORT_CONTROLLER
  783. /*****************************************************************************/
  784. /* Current/Power monitor */
  785. /*
  786. * Compile driver for INA219 or INA231. These two flags may not be both
  787. * defined.
  788. */
  789. #undef CONFIG_INA219
  790. #undef CONFIG_INA231
  791. /*****************************************************************************/
  792. /* Inductive charging */
  793. /* Enable inductive charging support */
  794. #undef CONFIG_INDUCTIVE_CHARGING
  795. /******************************************************************************/
  796. /* Support NXP PCA9534 I/O expander. */
  797. #undef CONFIG_IO_EXPANDER_PCA9534
  798. /*****************************************************************************/
  799. /* Number of IRQs supported on the EC chip */
  800. #undef CONFIG_IRQ_COUNT
  801. /*
  802. * This is the block size of the ILM on the it839x chip.
  803. * The ILM for static code cache, CPU fetch instruction from
  804. * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled.
  805. */
  806. #undef CONFIG_IT83XX_ILM_BLOCK_SIZE
  807. /* Enable Wake-up control interrupt from KSI */
  808. #undef CONFIG_IT83XX_KEYBOARD_KSI_WUC_INT
  809. /* Interrupt for PECI module. (IT839X series and IT838X DX only) */
  810. #undef CONFIG_IT83XX_PECI_WITH_INTERRUPT
  811. /* To define it, if I2C channel C and PECI used at the same time. */
  812. #undef CONFIG_IT83XX_SMCLK2_ON_GPC7
  813. /* Use SSPI Chip Enable 1. */
  814. #undef CONFIG_IT83XX_SPI_USE_CS1
  815. /*****************************************************************************/
  816. /* Keyboard config */
  817. /*
  818. * The Silego reset chip sits in between the EC and the physical keyboard on
  819. * column 2. To save power in low-power modes, some Silego variants require
  820. * the signal to be inverted so that the open-drain output from the EC isn't
  821. * costing power due to the pull-up resistor in the Silego.
  822. */
  823. #undef CONFIG_KEYBOARD_COL2_INVERTED
  824. /*
  825. * Config KSO to start from a different KSO pin. This is to allow some chips
  826. * to use alternate functions on KSO pins.
  827. */
  828. #define CONFIG_KEYBOARD_KSO_BASE 0
  829. /* Enable extra debugging output from keyboard modules */
  830. #undef CONFIG_KEYBOARD_DEBUG
  831. /* The board uses a negative edge-triggered GPIO for keyboard interrupts. */
  832. #undef CONFIG_KEYBOARD_IRQ_GPIO
  833. /* Compile code for 8042 keyboard protocol */
  834. #undef CONFIG_KEYBOARD_PROTOCOL_8042
  835. /* Compile code for MKBP keyboard protocol */
  836. #undef CONFIG_KEYBOARD_PROTOCOL_MKBP
  837. /*
  838. * Keyboard config (struct keyboard_scan_config) is in board.c. If this is
  839. * not defined, default values from common/keyboard_scan.c will be used.
  840. */
  841. #undef CONFIG_KEYBOARD_BOARD_CONFIG
  842. /*
  843. * Minimum CPU clocks between scans. This ensures that keyboard scanning
  844. * doesn't starve the other EC tasks of CPU when running at a decreased system
  845. * clock.
  846. */
  847. #undef CONFIG_KEYBOARD_POST_SCAN_CLOCKS
  848. /*
  849. * Call board-supplied keyboard_suppress_noise() function when the debounced
  850. * keyboard state changes. Some boards use this to send a signal to the audio
  851. * codec to suppress typing noise picked up by the microphone.
  852. */
  853. #undef CONFIG_KEYBOARD_SUPPRESS_NOISE
  854. /*
  855. * Enable keyboard testing functionality. This enables a message which receives
  856. * a list of keyscan events from the AP and processes them. This will cause
  857. * keypresses to appear on the AP through the same mechanism as a normal
  858. * keyboard press.
  859. *
  860. * This can be used to spoof keyboard events, so is not normally defined,
  861. * except during internal testing.
  862. */
  863. #undef CONFIG_KEYBOARD_TEST
  864. /*****************************************************************************/
  865. /* Support common LED interface */
  866. #undef CONFIG_LED_COMMON
  867. /* Standard LED behavior according to spec given that we have a red-green
  868. * bicolor led for charging and one power led
  869. */
  870. #undef CONFIG_LED_POLICY_STD
  871. /*
  872. * LEDs for LED_POLICY STD may be inverted. In this case they are active low
  873. * and the GPIO names will be GPIO_LED..._L.
  874. */
  875. #undef CONFIG_LED_BAT_ACTIVE_LOW
  876. #undef CONFIG_LED_POWER_ACTIVE_LOW
  877. /* Support for LED driver chip(s) */
  878. #undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */
  879. #undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */
  880. /* Offset in flash where little firmware will live. */
  881. #undef CONFIG_LFW_OFFSET
  882. /*
  883. * Compile lid switch support.
  884. *
  885. * This is enabled by default because all boards other than reference boards
  886. * are for laptops with lid switchs. Reference boards #undef it.
  887. */
  888. #define CONFIG_LID_SWITCH
  889. /*
  890. * GPIOs to use to detect that the lid is opened.
  891. *
  892. * This is a X-macro composed of a list of LID_OPEN(GPIO_xxx) elements defining
  893. * all the GPIOs to check to find whether the lid is currently opened.
  894. * If not defined, it is using GPIO_LID_OPEN.
  895. */
  896. #undef CONFIG_LID_SWITCH_GPIO_LIST
  897. /*
  898. * Support for turning the lightbar power rails on briefly when the AP is off.
  899. * Enabling this requires implementing the board-specific lb_power() function
  900. * to do it (see lb_common.h).
  901. */
  902. #undef CONFIG_LIGHTBAR_POWER_RAILS
  903. /*
  904. * For tap sequence, show the last segment in dim to give a better idea of
  905. * battery percentage.
  906. */
  907. #undef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
  908. /* Program memory offset for little firmware loader. */
  909. #undef CONFIG_LOADER_MEM_OFF
  910. /* Size of little firmware loader. */
  911. #undef CONFIG_LOADER_SIZE
  912. /* Little firmware loader storage offset. */
  913. #undef CONFIG_LOADER_STORAGE_OFF
  914. /*
  915. * Low power idle options. These are disabled by default and all boards that
  916. * want to use low power idle must define it. When using the LFIOSC, the low
  917. * frequency clock will be used to conserve even more power when possible.
  918. *
  919. * GPIOs which need to trigger interrupts in low power idle must specify the
  920. * GPIO_INT_DSLEEP flag in gpio_list[].
  921. *
  922. * Note that for some processors (e.g. LM4), an active JTAG connection will
  923. * prevent the EC from using low-power idle.
  924. */
  925. #undef CONFIG_LOW_POWER_IDLE
  926. #undef CONFIG_LOW_POWER_USE_LFIOSC
  927. /*
  928. * Enable Pseudo G3 (power removed from EC)
  929. * This requires board specific implementation.
  930. */
  931. #undef CONFIG_LOW_POWER_PSEUDO_G3
  932. /*
  933. * Enable deep sleep during S0 (ignores SLEEP_MASK_AP_RUN).
  934. */
  935. #undef CONFIG_LOW_POWER_S0
  936. /* Support G3 sleep mode */
  937. #undef CONFIG_G3_SLEEP
  938. /* Support LPC interface */
  939. #undef CONFIG_LPC
  940. /* Base address of low power RAM. */
  941. #undef CONFIG_LPRAM_BASE
  942. /* Size of low power RAM. */
  943. #undef CONFIG_LPRAM_SIZE
  944. /* Use Link-Time Optimizations to try to reduce the firmware code size */
  945. #undef CONFIG_LTO
  946. /* Need for a math library */
  947. #undef CONFIG_MATH_UTIL
  948. /* Presence of a Bosh Sensortec BMM150 magnetometer behind a BMI160. */
  949. #undef CONFIG_MAG_BMI160_BMM150
  950. /* Microchip EC SRAM start address */
  951. #undef CONFIG_MEC_SRAM_BASE_START
  952. /* Microchip EC SRAM end address */
  953. #undef CONFIG_MEC_SRAM_BASE_END
  954. /* Microchip EC SRAM size */
  955. #undef CONFIG_MEC_SRAM_SIZE
  956. /*
  957. * Define Megachips DisplayPort to HDMI protocol converter/level shifter serial
  958. * interface.
  959. */
  960. #undef CONFIG_MCDP28X0
  961. /* Define clock input to MFT module. */
  962. #undef CONFIG_MFT_INPUT_LFCLK
  963. /* Support MKBP event */
  964. #undef CONFIG_MKBP_EVENT
  965. /* Support memory protection unit (MPU) */
  966. #undef CONFIG_MPU
  967. /* Support one-wire interface */
  968. #undef CONFIG_ONEWIRE
  969. /* Support PECI interface to x86 processor */
  970. #undef CONFIG_PECI
  971. /*
  972. * Maximum operating temperature in degrees Celcius used on some x86
  973. * processors. CPU chip temperature is reported relative to this value and
  974. * is never reported greater than this value. Processor asserts PROCHOT#
  975. * and starts throttling frequency and voltage at this temp. Operation may
  976. * become unreliable if temperature exceeds this limit.
  977. */
  978. #undef CONFIG_PECI_TJMAX
  979. /*****************************************************************************/
  980. /* PMU config */
  981. /*
  982. * Enable hard-resetting the PMU from the EC. The implementation is rather
  983. * hacky; it simply shorts out the 3.3V rail to force the PMIC to panic. We
  984. * need this unfortunate hack because it's the only way to reset the I2C engine
  985. * inside the PMU.
  986. */
  987. #undef CONFIG_PMU_HARD_RESET
  988. /* Support TPS65090 PMU */
  989. #undef CONFIG_PMU_TPS65090
  990. /* Suport TPS65090 PMU charging LED. */
  991. #undef CONFIG_PMU_TPS65090_CHARGING_LED
  992. /*
  993. * Support PMU powerinfo host and console commands. Note that the
  994. * implementation is currently specific to the Pit board, so don't blindly
  995. * enable this for another board without fixing that first.
  996. */
  997. #undef CONFIG_PMU_POWERINFO
  998. /*****************************************************************************/
  999. /*
  1000. * Enable polling at boot by port 80 task.
  1001. * Ignored if port 80 is handled by interrupt
  1002. */
  1003. #undef CONFIG_PORT80_TASK_EN
  1004. /*****************************************************************************/
  1005. /* Compile common code to support power button debouncing */
  1006. #undef CONFIG_POWER_BUTTON
  1007. /* Force the active state of the power button : 0(default if unset) or 1 */
  1008. #undef CONFIG_POWER_BUTTON_ACTIVE_STATE
  1009. /* Allow the power button to send events while the lid is closed */
  1010. #undef CONFIG_POWER_BUTTON_IGNORE_LID
  1011. /* Support sending the power button signal to x86 chipsets */
  1012. #undef CONFIG_POWER_BUTTON_X86
  1013. /* Compile common code for AP power state machine */
  1014. #undef CONFIG_POWER_COMMON
  1015. /* Disable the power-on transition when the lid is opened */
  1016. #undef CONFIG_POWER_IGNORE_LID_OPEN
  1017. /* Support stopping in S5 on shutdown */
  1018. #undef CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
  1019. /* Use part of the EC's data EEPROM to hold persistent storage for the AP. */
  1020. #undef CONFIG_PSTORE
  1021. /*****************************************************************************/
  1022. /* Support PWM control */
  1023. #undef CONFIG_PWM
  1024. /* Support PWM control while in low-power idle */
  1025. #undef CONFIG_PWM_DSLEEP
  1026. /* Define clock input to PWM module. */
  1027. #undef CONFIG_PWM_INPUT_LFCLK
  1028. /*****************************************************************************/
  1029. /* Support PWM output to keyboard backlight */
  1030. #undef CONFIG_PWM_KBLIGHT
  1031. /* Base address of RAM for the chip */
  1032. #undef CONFIG_RAM_BASE
  1033. /* Base address of RAM for RO/RW. */
  1034. #undef CONFIG_RAM_BASE_RORW
  1035. /* Size of RAM available on the chip, in bytes */
  1036. #undef CONFIG_RAM_SIZE
  1037. /* Size of RAM for loader */
  1038. #undef CONFIG_RAM_SIZE_LOADER
  1039. /* Size of RAM for RO/RW */
  1040. #undef CONFIG_RAM_SIZE_RORW
  1041. /* Size of RAM for RO/RW & loader */
  1042. #undef CONFIG_RAM_SIZE_TOTAL
  1043. /* Support IR357x Link voltage regulator debugging / reprogramming */
  1044. #undef CONFIG_REGULATOR_IR357X
  1045. /* Support verifying 2048-bit RSA signature */
  1046. #undef CONFIG_RSA
  1047. /* Define the RSA key size. */
  1048. #undef CONFIG_RSA_KEY_SIZE
  1049. /* Flash address of the RO image. */
  1050. #undef CONFIG_RO_IMAGE_FLASHADDR
  1051. /* Flash address of the RW image. */
  1052. #undef CONFIG_RW_IMAGE_FLASHADDR
  1053. /*
  1054. * Verify the RW firmware using the RSA signature.
  1055. * (for accessories without software sync)
  1056. */
  1057. #undef CONFIG_RWSIG
  1058. /****************************************************************************/
  1059. /* Shared objects library. */
  1060. /* Support shared objects library between RO and RW. */
  1061. #undef CONFIG_SHAREDLIB
  1062. /* Size of shared objects library. */
  1063. #undef CONFIG_SHAREDLIB_SIZE
  1064. /* Program memory offset of shared objects library. */
  1065. #undef CONFIG_SHAREDLIB_MEM_OFF
  1066. /* Storage offset of sharedobjects library. */
  1067. #undef CONFIG_SHAREDLIB_STORAGE_OFF
  1068. /*
  1069. * If defined, the hash module will save its last computed hash when jumping
  1070. * between EC images.
  1071. */
  1072. #undef CONFIG_SAVE_VBOOT_HASH
  1073. /* Enable smart battery firmware update driver */
  1074. #undef CONFIG_SB_FIRMWARE_UPDATE
  1075. /* Allow the board to use a GPIO for the SCI# signal. */
  1076. #undef CONFIG_SCI_GPIO
  1077. /* Support computing SHA-1 hash */
  1078. #undef CONFIG_SHA1
  1079. /* Support computing SHA-256 hash (without the VBOOT code) */
  1080. #undef CONFIG_SHA256
  1081. /* Emulate the CLZ (Count Leading Zeros) in software for CPU lacking support */
  1082. #undef CONFIG_SOFTWARE_CLZ
  1083. /* Support smbus interface */
  1084. #undef CONFIG_SMBUS
  1085. /* Support SPI interfaces */
  1086. #undef CONFIG_SPI
  1087. /*
  1088. * Support SPI Slave interfaces. The first board supporting this is cr50 and
  1089. * in its parlance SPI_SLAVE is called SPS. This convention might be
  1090. * reconsidered later, and the use of "SPI" in different config options needs
  1091. * to be cleand up. (crbug.com/512613).
  1092. */
  1093. #undef CONFIG_SPS
  1094. /* Support SPI flash */
  1095. #undef CONFIG_SPI_FLASH
  1096. /* Define the SPI port to use to access the flash */
  1097. #undef CONFIG_SPI_FLASH_PORT
  1098. /* Support W25Q64 SPI flash */
  1099. #undef CONFIG_SPI_FLASH_W25Q64
  1100. /* Support W25X40 SPI flash */
  1101. #undef CONFIG_SPI_FLASH_W25X40
  1102. /* SPI flash part supports SR2 register */
  1103. #undef CONFIG_SPI_FLASH_HAS_SR2
  1104. /* Size (bytes) of SPI flash memory */
  1105. #undef CONFIG_SPI_FLASH_SIZE
  1106. /* SPI master feature */
  1107. #undef CONFIG_SPI_MASTER
  1108. /* Support testing SPI slave controller driver. */
  1109. #undef CONFIG_SPS_TEST
  1110. /* Default stack size to use for tasks, in bytes */
  1111. #undef CONFIG_STACK_SIZE
  1112. /* Use 32-bit timer for clock source on stm32. */
  1113. #undef CONFIG_STM_HWTIMER32
  1114. /* Fake hibernate mode */
  1115. #undef CONFIG_STM32L_FAKE_HIBERNATE
  1116. /*
  1117. * Compile common code to handle simple switch inputs such as the recovery
  1118. * button input from the servo debug interface.
  1119. */
  1120. #undef CONFIG_SWITCH
  1121. /* Support dedicated recovery signal from servo board */
  1122. #undef CONFIG_SWITCH_DEDICATED_RECOVERY
  1123. /*
  1124. * System should remain unlocked even if write protect is enabled.
  1125. *
  1126. * NOTE: This should ONLY be defined during bringup, and should never be
  1127. * defined on a shipping / released platform.
  1128. */
  1129. #undef CONFIG_SYSTEM_UNLOCKED
  1130. /*****************************************************************************/
  1131. /* Task config */
  1132. /*
  1133. * List of enabled tasks in ascending priority order. This is normally
  1134. * defined in each board's ec.tasklist file.
  1135. *
  1136. * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
  1137. * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
  1138. * where :
  1139. * 'n' is the name of the task
  1140. * 'r' is the main routine of the task
  1141. * 'd' is an opaque parameter passed to the routine at startup
  1142. * 's' is the stack size in bytes; must be a multiple of 8
  1143. */
  1144. #undef CONFIG_TASK_LIST
  1145. /*
  1146. * List of test tasks. Same format as CONFIG_TASK_LIST, but used to define
  1147. * additional tasks for a unit test. Normally defined in
  1148. * test/{testname}.tasklist.
  1149. */
  1150. #undef CONFIG_TEST_TASK_LIST
  1151. /*
  1152. * Enable task profiling.
  1153. *
  1154. * Boards may #undef this to reduce image size and RAM usage.
  1155. */
  1156. #define CONFIG_TASK_PROFILING
  1157. /*****************************************************************************/
  1158. /* Temperature sensor config */
  1159. /* Compile common code for temperature sensor support */
  1160. #undef CONFIG_TEMP_SENSOR
  1161. /* Support particular temperature sensor chips */
  1162. #undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */
  1163. #undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */
  1164. #undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */
  1165. /*
  1166. * If defined, active-high GPIO which indicates temperature sensor chips are
  1167. * powered. If not defined, temperature sensors are assumed to be always
  1168. * powered.
  1169. */
  1170. #undef CONFIG_TEMP_SENSOR_POWER_GPIO
  1171. /*****************************************************************************/
  1172. /* TPM-like configuration */
  1173. /* Speak the TPM SPI Hardware Protocol on the SPI slave interface */
  1174. #undef CONFIG_TPM_SPS
  1175. /*****************************************************************************/
  1176. /* USART stream config */
  1177. #undef CONFIG_STREAM_USART
  1178. /*
  1179. * Each USART stream can be individually enabled and accessible using the
  1180. * stream interface provided in the usart_config struct.
  1181. */
  1182. #undef CONFIG_STREAM_USART1
  1183. #undef CONFIG_STREAM_USART2
  1184. #undef CONFIG_STREAM_USART3
  1185. #undef CONFIG_STREAM_USART4
  1186. /*****************************************************************************/
  1187. /* USB stream config */
  1188. #undef CONFIG_STREAM_USB
  1189. /*****************************************************************************/
  1190. /* UART config */
  1191. /* Baud rate for UARTs */
  1192. #define CONFIG_UART_BAUD_RATE 115200
  1193. /* UART index (number) for EC console */
  1194. #undef CONFIG_UART_CONSOLE
  1195. /* UART index (number) for host UART, if present */
  1196. #undef CONFIG_UART_HOST
  1197. /* Use uart_input_filter() to filter UART input. See prototype in uart.h */
  1198. #undef CONFIG_UART_INPUT_FILTER
  1199. /*
  1200. * UART receive buffer size in bytes. Must be a power of 2 for macros in
  1201. * common/uart_buffering.c to work properly. Must be larger than
  1202. * CONFIG_CONSOLE_INPUT_LINE_SIZE to copy and paste scripts.
  1203. */
  1204. #define CONFIG_UART_RX_BUF_SIZE 128
  1205. /* Use DMA for UART input */
  1206. #undef CONFIG_UART_RX_DMA
  1207. /*
  1208. * On some platforms, UART receive DMA can't trigger an interrupt when a single
  1209. * character is received. Those platforms poll for characters every HOOK_TICK.
  1210. * When a character is received, make this many additional checks between then
  1211. * and the next HOOK_TICK, to increase responsiveness of the console to input.
  1212. */
  1213. #define CONFIG_UART_RX_DMA_RECHECKS 5
  1214. /*
  1215. * UART transmit buffer size in bytes. Must be a power of 2 for macros in
  1216. * common/uart_buffering.c to work properly.
  1217. */
  1218. #define CONFIG_UART_TX_BUF_SIZE 512
  1219. /* Use DMA for UART output */
  1220. #undef CONFIG_UART_TX_DMA
  1221. /* The DMA channel for UART. If not defined, default to UART1. */
  1222. #undef CONFIG_UART_TX_DMA_CH
  1223. #undef CONFIG_UART_RX_DMA_CH
  1224. /*****************************************************************************/
  1225. /* USB PD config */
  1226. /* Include all USB Power Delivery modules */
  1227. #undef CONFIG_USB_POWER_DELIVERY
  1228. /* Support for USB PD alternate mode */
  1229. #undef CONFIG_USB_PD_ALT_MODE
  1230. /* Support for USB PD alternate mode of Downward Facing Port */
  1231. #undef CONFIG_USB_PD_ALT_MODE_DFP
  1232. /* Check if max voltage request is allowed before each request */
  1233. #undef CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
  1234. /* Default state of PD communication enabled flag */
  1235. #define CONFIG_USB_PD_COMM_ENABLED 1
  1236. /* Respond to custom vendor-defined messages over PD */
  1237. #undef CONFIG_USB_PD_CUSTOM_VDM
  1238. /* Default USB data role when a USB PD debug accessory is seen */
  1239. #define CONFIG_USB_PD_DEBUG_DR PD_ROLE_DFP
  1240. /* Define if this board can act as a dual-role PD port (source and sink) */
  1241. #undef CONFIG_USB_PD_DUAL_ROLE
  1242. /* Dynamic USB PD source capability */
  1243. #undef CONFIG_USB_PD_DYNAMIC_SRC_CAP
  1244. /* Support USB PD flash. */
  1245. #undef CONFIG_USB_PD_FLASH
  1246. /* Check whether PD is the sole power source before flash erase operation */
  1247. #undef CONFIG_USB_PD_FLASH_ERASE_CHECK
  1248. /* Major and Minor ChromeOS specific PD device Hardware IDs. */
  1249. #undef CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR
  1250. #undef CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR
  1251. /* HW & SW version for alternate mode discover identity response (4bits each) */
  1252. #undef CONFIG_USB_PD_IDENTITY_HW_VERS
  1253. #undef CONFIG_USB_PD_IDENTITY_SW_VERS
  1254. /* USB PD MCU slave address for host commands */
  1255. #define CONFIG_USB_PD_I2C_SLAVE_ADDR 0x3c
  1256. /* Define if using internal comparator for PD receive */
  1257. #undef CONFIG_USB_PD_INTERNAL_COMP
  1258. /* Record main PD events in a circular buffer */
  1259. #undef CONFIG_USB_PD_LOGGING
  1260. /* The size in bytes of the FIFO used for PD events logging */
  1261. #undef CONFIG_USB_PD_LOG_SIZE
  1262. /* Define if USB-PD device has no way of detecting USB VBUS */
  1263. #undef CONFIG_USB_PD_NO_VBUS_DETECT
  1264. /* Number of USB PD ports */
  1265. #undef CONFIG_USB_PD_PORT_COUNT
  1266. /* Simple DFP, such as power adapter, will not send discovery VDM on connect */
  1267. #undef CONFIG_USB_PD_SIMPLE_DFP
  1268. /* Use comparator module for PD RX interrupt */
  1269. #define CONFIG_USB_PD_RX_COMP_IRQ
  1270. /* Use TCPC module (type-C port controller) */
  1271. #undef CONFIG_USB_PD_TCPC
  1272. /*
  1273. * Choose one of the following TCPMs (type-C port manager) to manage TCPC. The
  1274. * TCPM stub is used to make direct function calls to TCPC when TCPC is on
  1275. * the same MCU. The TCPCI TCPM uses the standard TCPCI i2c interface to TCPC.
  1276. */
  1277. #undef CONFIG_USB_PD_TCPM_STUB
  1278. #undef CONFIG_USB_PD_TCPM_TCPCI
  1279. /* Define the type-c port controller I2C base address. */
  1280. #undef CONFIG_TCPC_I2C_BASE_ADDR
  1281. /* Use this option to enable Try.SRC mode for Dual Role devices */
  1282. #undef CONFIG_USB_PD_TRY_SRC
  1283. /* Alternative configuration keeping only the TX part of PHY */
  1284. #undef CONFIG_USB_PD_TX_PHY_ONLY
  1285. /* Use DAC as reference for comparator at 850mV. */
  1286. #undef CONFIG_PD_USE_DAC_AS_REF
  1287. /* USB Product ID. */
  1288. #undef CONFIG_USB_PID
  1289. /* Support for USB type-c superspeed mux */
  1290. #undef CONFIG_USBC_SS_MUX
  1291. /*
  1292. * Only configure USB type-c superspeed mux when DFP (for chipsets that
  1293. * don't support being a UFP)
  1294. */
  1295. #undef CONFIG_USBC_SS_MUX_DFP_ONLY
  1296. /* Support v1.1 type-C connection state machine */
  1297. #undef CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
  1298. /* Support for USB type-c vconn. Not needed for captive cables. */
  1299. #undef CONFIG_USBC_VCONN
  1300. /* Support VCONN swap */
  1301. #undef CONFIG_USBC_VCONN_SWAP
  1302. /* USB Binary device Object Store support */
  1303. #undef CONFIG_USB_BOS
  1304. /* USB Device version of product */
  1305. #undef CONFIG_USB_BCD_DEV
  1306. /*****************************************************************************/
  1307. /* Compile chip support for the USB device controller */
  1308. #undef CONFIG_USB
  1309. /* Support USB blob handler. */
  1310. #undef CONFIG_USB_BLOB
  1311. /* Common USB / BC1.2 charger task */
  1312. #undef CONFIG_USB_CHARGER
  1313. /* Enable USB serial console module. */
  1314. #undef CONFIG_USB_CONSOLE
  1315. /* Support USB HID interface. */
  1316. #undef CONFIG_USB_HID
  1317. /* USB device buffers and descriptors */
  1318. #undef CONFIG_USB_RAM_ACCESS_SIZE
  1319. #undef CONFIG_USB_RAM_ACCESS_TYPE
  1320. #undef CONFIG_USB_RAM_BASE
  1321. #undef CONFIG_USB_RAM_SIZE
  1322. /* Disable automatic connection of USB peripheral */
  1323. #undef CONFIG_USB_INHIBIT_CONNECT
  1324. /* Disable automatic initialization of USB peripheral */
  1325. #undef CONFIG_USB_INHIBIT_INIT
  1326. /* Support simple control of power to the device's USB ports */
  1327. #undef CONFIG_USB_PORT_POWER_DUMB
  1328. /*
  1329. * Support supplying USB power in S3, if the host leaves the port enabled when
  1330. * entering S3.
  1331. */
  1332. #undef CONFIG_USB_PORT_POWER_IN_S3
  1333. /*
  1334. * Support smart power control to the device's USB ports, using
  1335. * dedicated power control chips. This potentially enables automatic
  1336. * negotiation of supplying more power to peripherals.
  1337. */
  1338. #undef CONFIG_USB_PORT_POWER_SMART
  1339. /*
  1340. * Override the default charging mode for USB smart power control.
  1341. * Value is selected from usb_charge_mode in include/usb_charge.h
  1342. */
  1343. #undef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
  1344. /*
  1345. * Smart USB power control can use a full set of control signals to the USB
  1346. * port power chip, or a reduced set. If this is defined, use the reduced set.
  1347. */
  1348. #undef CONFIG_USB_PORT_POWER_SMART_SIMPLE
  1349. /*
  1350. * Smart USB power control current limit pins may be inverted. In this case
  1351. * they are active low and the GPIO names will be GPIO_USBn_ILIM_SEL_L.
  1352. */
  1353. #undef CONFIG_USB_PORT_POWER_SMART_INVERTED
  1354. /******************************************************************************/
  1355. /* USB port switch */
  1356. /* 8-bit USB type-C switch I2C addresses */
  1357. #undef CONFIG_USB_SWITCH_I2C_ADDRS
  1358. /* Support the TSU6721 I2C smart switch */
  1359. #undef CONFIG_USB_SWITCH_TSU6721
  1360. /* Support the Pericom PI3USB9281 I2C USB switch */
  1361. #undef CONFIG_USB_SWITCH_PI3USB9281
  1362. /* Number of Pericom PI3USB9281 chips present in system */
  1363. #undef CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT
  1364. /* Support the Pericom PI3USB30532 USB3.0/DP1.2 Matrix Switch */
  1365. #undef CONFIG_USB_MUX_PI3USB30532
  1366. /* Support the Parade PS8740 Type-C Redriving Switch */
  1367. #undef CONFIG_USB_MUX_PS8740
  1368. /*****************************************************************************/
  1369. /* USB GPIO config */
  1370. #undef CONFIG_USB_GPIO
  1371. /*****************************************************************************/
  1372. /* USB SPI config */
  1373. #undef CONFIG_USB_SPI
  1374. /*****************************************************************************/
  1375. /* Support computing hash of code for verified boot */
  1376. #undef CONFIG_VBOOT_HASH
  1377. /*****************************************************************************/
  1378. /* Watchdog config */
  1379. /*
  1380. * Compile watchdog timer support. The watchdog timer will reboot the system
  1381. * if the hook task (which is the lowest-priority task on the system) gets
  1382. * starved for CPU time and isn't able to fire its HOOK_TICK event.
  1383. */
  1384. #define CONFIG_WATCHDOG
  1385. /*
  1386. * Try to detect a watchdog that is about to fire, and print a trace. This is
  1387. * required on chips such as STM32 where the watchdog timer simply reboots the
  1388. * system without any early warning.
  1389. */
  1390. #undef CONFIG_WATCHDOG_HELP
  1391. /* Watchdog period in ms; see also AUX_TIMER_PERIOD_MS */
  1392. #define CONFIG_WATCHDOG_PERIOD_MS 1600
  1393. /*
  1394. * Fire auxiliary timer 500ms before watchdog timer expires. This leaves
  1395. * some time for debug trace to be printed.
  1396. */
  1397. #define CONFIG_AUX_TIMER_PERIOD_MS (CONFIG_WATCHDOG_PERIOD_MS - 500)
  1398. /*****************************************************************************/
  1399. /*
  1400. * Support controlling power to WiFi, WWAN (3G/LTE), and/or bluetooth modules.
  1401. */
  1402. #undef CONFIG_WIRELESS
  1403. /*
  1404. * Support for WiFi devices that must remain powered in suspend. Set to the
  1405. * combination of EC_WIRELESS_SWITCH flags (from ec_commands.h) which should
  1406. * be set in suspend.
  1407. */
  1408. #undef CONFIG_WIRELESS_SUSPEND
  1409. /*
  1410. * Write protect signal is active-high. If this is defined, there must be a
  1411. * GPIO named GPIO_WP; if not defined, there must be a GPIO names GPIO_WP_L.
  1412. */
  1413. #undef CONFIG_WP_ACTIVE_HIGH
  1414. /*
  1415. * The write protect signal is always asserted,
  1416. * independantly of the GPIO existence or current value.
  1417. */
  1418. #undef CONFIG_WP_ALWAYS
  1419. /*****************************************************************************/
  1420. /*
  1421. * Include board and core configs, since those hold the CONFIG_ constants for a
  1422. * given configuration. This guarantees they get included everywhere, and
  1423. * fixes a fairly common bug where we gate out code with #ifndef
  1424. * CONFIG_SOMETHING and but forget to include both of these.
  1425. *
  1426. * Board is included after chip, so that chip defaults can be overridden on a
  1427. * per-board basis as needed.
  1428. */
  1429. #ifdef __CROS_EC_CONFIG_CHIP_H
  1430. #error Include config.h instead of config_chip.h!
  1431. #endif
  1432. #ifdef __BOARD_H
  1433. #error Include config.h instead of board.h!
  1434. #endif
  1435. #include "config_chip.h"
  1436. #include "board.h"
  1437. /*****************************************************************************/
  1438. /*
  1439. * Handle task-dependent configs.
  1440. *
  1441. * This prevent sub-modules from being compiled when the task and parent module
  1442. * are not present.
  1443. */
  1444. #ifndef HAS_TASK_CHIPSET
  1445. #undef CONFIG_CHIPSET_BAYTRAIL
  1446. #undef CONFIG_CHIPSET_BRASWELL
  1447. #undef CONFIG_CHIPSET_GAIA
  1448. #undef CONFIG_CHIPSET_HASWELL
  1449. #undef CONFIG_CHIPSET_MEDIATEK
  1450. #undef CONFIG_CHIPSET_ROCKCHIP
  1451. #undef CONFIG_CHIPSET_TEGRA
  1452. #undef CONFIG_POWER_COMMON
  1453. #endif
  1454. #ifndef HAS_TASK_KEYPROTO
  1455. #undef CONFIG_KEYBOARD_PROTOCOL_8042
  1456. /*
  1457. * Note that we don't undef CONFIG_KEYBOARD_PROTOCOL_MKBP, because it doesn't
  1458. * have its own task.
  1459. */
  1460. #endif
  1461. #ifndef HAS_TASK_KEYSCAN
  1462. #undef CONFIG_KEYBOARD_PROTOCOL_8042
  1463. #undef CONFIG_KEYBOARD_PROTOCOL_MKBP
  1464. #endif
  1465. /*****************************************************************************/
  1466. /*
  1467. * Apply test config overrides last, since tests need to override some of the
  1468. * config flags in non-standard ways to mock only parts of the system.
  1469. */
  1470. #include "test_config.h"
  1471. /*
  1472. * Sanity checks to make sure some of the configs above make sense.
  1473. */
  1474. #if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS) * 2)
  1475. #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS"
  1476. #endif
  1477. #endif /* __CROS_EC_CONFIG_H */