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  1. /* Copyright (c) 2014 The Chromium OS Authors. All rights reserved.
  2. * Use of this source code is governed by a BSD-style license that can be
  3. * found in the LICENSE file.
  4. */
  5. /*
  6. * config.h - Top-level configuration Chrome EC
  7. *
  8. * All configuration settings (CONFIG_*) are defined in this file or in a
  9. * sub-configuration file (config_chip.h, board.h, etc.) included by this file.
  10. *
  11. * Note that this file is included by assembly (.S) files. Any C-isms such as
  12. * struct definitions or enums in a sub-configuration file MUST be guarded with
  13. * #ifndef __ASSEMBLER__ to prevent those C-isms from being evaluated by the
  14. * assembler.
  15. */
  16. #ifndef __CROS_EC_CONFIG_H
  17. #define __CROS_EC_CONFIG_H
  18. /*
  19. * All config options are listed alphabetically and described here.
  20. *
  21. * If you add a new config option somewhere in the code, you must add a
  22. * default value here and describe what it does.
  23. *
  24. * To get a list current list, run this command:
  25. * git grep " CONFIG_" | grep -o "CONFIG_[A-Za-z0-9_]\+" | sort | uniq
  26. *
  27. * Some options are #defined here to enable them by default. Chips or boards
  28. * may override this by #undef'ing them in config_chip.h or board.h,
  29. * respectively.
  30. *
  31. * TODO(crosbug.com/p/23758): Describe all of these. Also describe the
  32. * HAS_TASK_* macro and how/when it should be used vs. a config define. And
  33. * BOARD_*, CHIP_*, and CHIP_FAMILY_*.
  34. */
  35. /* Enable accelerometer interrupts. */
  36. #undef CONFIG_ACCEL_INTERRUPTS
  37. /* Add support for sensor FIFO:
  38. * define the size of the global fifo, must be a power of 2. */
  39. #undef CONFIG_ACCEL_FIFO
  40. /* The amount of free entries that trigger an interrupt to the AP. */
  41. #undef CONFIG_ACCEL_FIFO_THRES
  42. /* Specify type of accelerometers attached. */
  43. #undef CONFIG_ACCEL_KXCJ9
  44. #undef CONFIG_ACCELGYRO_LSM6DS0
  45. #undef CONFIG_ACCELGYRO_BMI160
  46. /*
  47. * Define the event to raise when BMI160 interrupt.
  48. * Must be within TASK_EVENT_MOTION_INTERRUPT_MASK.
  49. */
  50. #undef CONFIG_ACCELGYRO_BMI160_INT_EVENT
  51. /* Compile chip support for analog-to-digital convertor */
  52. #undef CONFIG_ADC
  53. /* ADC sample time selection. The value is chip-dependent. */
  54. #undef CONFIG_ADC_SAMPLE_TIME
  55. /* Include the ADC analog watchdog feature in the ADC code */
  56. #define CONFIG_ADC_WATCHDOG
  57. /*
  58. * Some ALS modules may be connected to the EC. We need the command, and
  59. * specific drivers for each module.
  60. */
  61. #undef CONFIG_ALS
  62. #undef CONFIG_ALS_ISL29035
  63. #undef CONFIG_ALS_OPT3001
  64. /* Define the exact model ID present on the board: SI1141 = 41, SI1142 = 42, */
  65. #undef CONFIG_ALS_SI114X
  66. /* Check if the device revision is supported */
  67. #undef CONFIG_ALS_SI114X_CHECK_REVISION
  68. /*
  69. * Define the event to raise when BMI160 interrupt.
  70. * Must be within TASK_EVENT_MOTION_INTERRUPT_MASK.
  71. */
  72. #undef CONFIG_ALS_SI114X_INT_EVENT
  73. /* Support AP hang detection host command and state machine */
  74. #undef CONFIG_AP_HANG_DETECT
  75. /* Support AP Warm reset Interrupt. */
  76. #undef CONFIG_AP_WARM_RESET_INTERRUPT
  77. /*
  78. * Support controlling the display backlight based on the state of the lid
  79. * switch. The EC will disable the backlight when the lid is closed.
  80. */
  81. #undef CONFIG_BACKLIGHT_LID
  82. /*
  83. * If defined, EC will enable the backlight signal only if this GPIO is
  84. * asserted AND the lid is open. This supports passing the backlight-enable
  85. * signal from the AP through EC.
  86. */
  87. #undef CONFIG_BACKLIGHT_REQ_GPIO
  88. /*****************************************************************************/
  89. /* Battery config */
  90. /* Support a simple battery. */
  91. #undef CONFIG_BATTERY
  92. /*
  93. * Compile battery-specific code.
  94. *
  95. * Note that some boards have their own unique battery constants / functions.
  96. * In this case, those are provided in board/(boardname)/battery.c, and none of
  97. * these are defined.
  98. */
  99. #undef CONFIG_BATTERY_BQ20Z453
  100. #undef CONFIG_BATTERY_BQ27541
  101. #undef CONFIG_BATTERY_BQ27621
  102. #undef CONFIG_BATTERY_RYU
  103. #undef CONFIG_BATTERY_SAMUS
  104. /* Compile mock battery support; used by tests. */
  105. #undef CONFIG_BATTERY_MOCK
  106. /*
  107. * Charger should call battery_override_params() to limit/correct the voltage
  108. * and current requested by the battery pack before acting on the request.
  109. *
  110. * This is valid with CONFIG_CHARGER_V1 only.
  111. */
  112. #undef CONFIG_BATTERY_OVERRIDE_PARAMS
  113. /*
  114. * If defined, the charger will check for battery presence before attempting
  115. * to communicate with it. This avoids the 30 second delay when booting
  116. * without a battery present. Do not use with CONFIG_BATTERY_PRESENT_GPIO.
  117. *
  118. * Replace the default battery_is_present() function with a board-specific
  119. * implementation in board.c
  120. */
  121. #undef CONFIG_BATTERY_PRESENT_CUSTOM
  122. /*
  123. * If defined, GPIO which is driven low when battery is present.
  124. * Charger will check for battery presence before attempting to communicate
  125. * with it. This avoids the 30 second delay when booting without a battery
  126. * present. Do not use with CONFIG_BATTERY_PRESENT_CUSTOM.
  127. */
  128. #undef CONFIG_BATTERY_PRESENT_GPIO
  129. /*
  130. * Compile smart battery support
  131. *
  132. * For batteries which support this specification:
  133. * http://sbs-forum.org/specs/sbdat110.pdf)
  134. */
  135. #undef CONFIG_BATTERY_SMART
  136. /*
  137. * Critical battery shutdown timeout (seconds)
  138. *
  139. * If the battery is at extremely low charge (and discharging) or extremely
  140. * high temperature, the EC will shut itself down. This defines the timeout
  141. * period in seconds between the critical condition being detected and the
  142. * EC shutting itself down. Note that if the critical condition is corrected
  143. * before the timeout expiration, the EC will not shut itself down.
  144. *
  145. */
  146. #define CONFIG_BATTERY_CRITICAL_SHUTDOWN_TIMEOUT 30
  147. /*
  148. * Support battery cut-off as host command and console command.
  149. *
  150. * Once defined, you have to implement a board_cut_off_battery() function
  151. * in board/???/battery.c file.
  152. */
  153. #undef CONFIG_BATTERY_CUT_OFF
  154. /*
  155. * The default delay is 1 second. Define this if a board prefers
  156. * different delay.
  157. */
  158. #undef CONFIG_BATTERY_CUTOFF_DELAY_US
  159. /*
  160. * The board-specific battery.c implements get and set functions to read and
  161. * write arbirary vendor-specific parameters stored in the battery.
  162. * See include/battery.h for prototypes.
  163. */
  164. #undef CONFIG_BATTERY_VENDOR_PARAM
  165. /*
  166. * TODO(crosbug.com/p/29467): allows charging of a dead battery that
  167. * requests nil for current and voltage. Remove this workaround when
  168. * possible.
  169. */
  170. #undef CONFIG_BATTERY_REQUESTS_NIL_WHEN_DEAD
  171. /*
  172. * Check for battery in disconnect state (similar to cut-off state). If this
  173. * battery is found to be in disconnect state, take it out of this state by
  174. * force-applying a charge current.
  175. */
  176. #undef CONFIG_BATTERY_REVIVE_DISCONNECT
  177. /* Boot header storage offset. */
  178. #undef CONFIG_BOOT_HEADER_STORAGE_OFF
  179. /* Size of boot header in storage. */
  180. #undef CONFIG_BOOT_HEADER_STORAGE_SIZE
  181. /*****************************************************************************/
  182. /*
  183. * Call board_config_post_gpio_init() after GPIOs are initialized. See
  184. * include/board_config.h for more information.
  185. */
  186. #undef CONFIG_BOARD_POST_GPIO_INIT
  187. /*
  188. * Call board_config_pre_init() before any inits are called. See
  189. * include/board_config.h for more information.
  190. */
  191. #undef CONFIG_BOARD_PRE_INIT
  192. /* EC has GPIOs attached to board version stuffing resistors */
  193. #undef CONFIG_BOARD_VERSION
  194. /* Permanent LM4 boot configuration */
  195. #undef CONFIG_BOOTCFG_VALUE
  196. /*****************************************************************************/
  197. /* Modify the default behavior to make system bringup easier. */
  198. #undef CONFIG_BRINGUP
  199. /*
  200. * Enable debug prints / asserts that may helpful for debugging board bring-up,
  201. * but probably shouldn't be enabled for production for performance reasons.
  202. */
  203. #undef CONFIG_DEBUG_BRINGUP
  204. /*****************************************************************************/
  205. /*
  206. * Number of extra buttons not on the keyboard scan matrix. Doesn't include
  207. * the power button, which has its own handler.
  208. */
  209. #undef CONFIG_BUTTON_COUNT
  210. /*
  211. * Enable case close debug (CCD) mode.
  212. */
  213. #undef CONFIG_CASE_CLOSED_DEBUG
  214. /*
  215. * Capsense chip has buttons, too.
  216. */
  217. #undef CONFIG_CAPSENSE
  218. /*****************************************************************************/
  219. /* Compile charge manager */
  220. #undef CONFIG_CHARGE_MANAGER
  221. /* Handle the external power limit host command in charge manager */
  222. #undef CONFIG_CHARGE_MANAGER_EXTERNAL_POWER_LIMIT
  223. /* Compile input current ramping support */
  224. #undef CONFIG_CHARGE_RAMP
  225. /* The hardware has some input current ramping/back-off mechanism */
  226. #undef CONFIG_CHARGE_RAMP_HW
  227. /*****************************************************************************/
  228. /* Charger config */
  229. /* Compile common charge state code. You must pick an implementation. */
  230. #undef CONFIG_CHARGER
  231. #undef CONFIG_CHARGER_V1
  232. #undef CONFIG_CHARGER_V2
  233. /* Enable charger AMON_BMON ADC current detection */
  234. #undef CONFIG_CHARGER_ADC_AMON_BMON
  235. /* Compile charger-specific code for these chargers (pick at most one) */
  236. #undef CONFIG_CHARGER_BQ24707A
  237. #undef CONFIG_CHARGER_BQ24715
  238. #undef CONFIG_CHARGER_BQ24725
  239. #undef CONFIG_CHARGER_BQ24735
  240. #undef CONFIG_CHARGER_BQ24738
  241. #undef CONFIG_CHARGER_BQ24770
  242. #undef CONFIG_CHARGER_BQ24773
  243. #undef CONFIG_CHARGER_BQ25890
  244. #undef CONFIG_CHARGER_BQ25892
  245. #undef CONFIG_CHARGER_BQ25895
  246. #undef CONFIG_CHARGER_ISL9237
  247. #undef CONFIG_CHARGER_TPS65090 /* Note: does not use CONFIG_CHARGER */
  248. /*
  249. * BQ2589x IR Compensation settings.
  250. * Should be the combination of BQ2589X_IR_TREG_xxxC, BQ2589X_IR_VCLAMP_yyyMV
  251. * and BQ2589X_IR_BAT_COMP_zzzMOHM.
  252. */
  253. #undef CONFIG_CHARGER_BQ2589X_IR_COMP
  254. /*
  255. * BQ2589x 5V boost current limit and voltage.
  256. * Should be the combination of BQ2589X_BOOSTV_MV(voltage) and
  257. * BQ2589X_BOOST_LIM_xxxMA.
  258. */
  259. #undef CONFIG_CHARGER_BQ2589X_BOOST
  260. /*
  261. * Board specific charging current limit, in mA. If defined, the charge state
  262. * machine will not allow the battery to request more current than this.
  263. */
  264. #undef CONFIG_CHARGER_CURRENT_LIMIT
  265. /*
  266. * Board specific charging current termination limit, in mA. If defined and
  267. * charger supports setting termination current it should be set during charger
  268. * init.
  269. *
  270. * TODO(tbroch): Only valid for bq2589x currently. Configure defaults for other
  271. * charger ICs that support termination currents.
  272. */
  273. #undef CONFIG_CHARGER_TERM_CURRENT_LIMIT
  274. /*
  275. * Board supports discharge mode. In this mode, the battery will discharge
  276. * even if AC is present. Used for testing.
  277. */
  278. #undef CONFIG_CHARGER_DISCHARGE_ON_AC
  279. /* Board has a custom discharge mode. */
  280. #undef CONFIG_CHARGER_DISCHARGE_ON_AC_CUSTOM
  281. /*
  282. * Board specific flag used to disable external ILIM pin used to determine input
  283. * current limit. When defined, the input current limit is decided only by
  284. * the software register value.
  285. */
  286. #undef CONFIG_CHARGER_ILIM_PIN_DISABLED
  287. /*
  288. * Default input current for the board, in mA.
  289. *
  290. * This value should depend on external power adapter, designed charging
  291. * voltage, and the maximum power of the running system. For type-C chargers,
  292. * this should be set to 512 mA in order to not brown-out low-current USB
  293. * charge ports.
  294. */
  295. #undef CONFIG_CHARGER_INPUT_CURRENT
  296. /*
  297. * Board specific maximum input current limit, in mA.
  298. */
  299. #undef CONFIG_CHARGER_MAX_INPUT_CURRENT
  300. /* Minimum battery percentage for power on */
  301. #undef CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON
  302. /*
  303. * Equivalent of CONFIG_BATTERY_OVERRIDE_PARAMS for use with
  304. * CONFIG_CHARGER_V2
  305. */
  306. #undef CONFIG_CHARGER_PROFILE_OVERRIDE
  307. /* Value of the charge sense resistor, in mOhms */
  308. #undef CONFIG_CHARGER_SENSE_RESISTOR
  309. /* Value of the input current sense resistor, in mOhms */
  310. #undef CONFIG_CHARGER_SENSE_RESISTOR_AC
  311. /*
  312. * Maximum time to charge the battery, in hours.
  313. *
  314. * If this timeout is reached, the charger will enter force-idle state.
  315. * If not defined, charger will provide current until the battery asks it to
  316. * stop.
  317. */
  318. #undef CONFIG_CHARGER_TIMEOUT_HOURS
  319. /*
  320. * Board has an GPIO pin to enable or disable charging.
  321. *
  322. * This GPIO should be named GPIO_CHARGER_EN, if active high. Or
  323. * GPIO_CHARGER_EN_L if active low.
  324. */
  325. #undef CONFIG_CHARGER_EN_GPIO
  326. /* Charger enable GPIO is active low */
  327. #undef CONFIG_CHARGER_EN_ACTIVE_LOW
  328. /*****************************************************************************/
  329. /* Chipset config */
  330. /* AP chipset support; pick at most one */
  331. #undef CONFIG_CHIPSET_BAYTRAIL /* Intel Bay Trail (x86) */
  332. #undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */
  333. #undef CONFIG_CHIPSET_ECDRIVEN /* Dummy power module */
  334. #undef CONFIG_CHIPSET_GAIA /* Gaia and Ares (ARM) */
  335. #undef CONFIG_CHIPSET_HASWELL /* Intel Haswell (x86) */
  336. #undef CONFIG_CHIPSET_MEDIATEK /* MediaTek MT81xx */
  337. #undef CONFIG_CHIPSET_ROCKCHIP /* Rockchip rk32xx */
  338. #undef CONFIG_CHIPSET_SKYLAKE /* Intel Skylake (x86) */
  339. #undef CONFIG_CHIPSET_TEGRA /* nVidia Tegra 5 */
  340. /* Support chipset throttling */
  341. #undef CONFIG_CHIPSET_CAN_THROTTLE
  342. /* Enable additional chipset debugging */
  343. #undef CONFIG_CHIPSET_DEBUG
  344. /* Support power rail control */
  345. #define CONFIG_CHIPSET_HAS_PP1350
  346. #define CONFIG_CHIPSET_HAS_PP5000
  347. /*****************************************************************************/
  348. /*
  349. * Chip config for clock circuitry
  350. * define = crystal / undef = oscillator
  351. */
  352. #undef CONFIG_CLOCK_CRYSTAL
  353. /*****************************************************************************/
  354. /* PMIC config */
  355. /* Support firmware long press power-off timer */
  356. #undef CONFIG_PMIC_FW_LONG_PRESS_TIMER
  357. /* Support PMIC power control */
  358. #undef CONFIG_PMIC
  359. /*****************************************************************************/
  360. /*
  361. * Optional console commands
  362. *
  363. * Defining these options will enable the corresponding command on the EC
  364. * console.
  365. */
  366. #undef CONFIG_CMD_ACCELS
  367. #undef CONFIG_CMD_ACCEL_INFO
  368. #undef CONFIG_CMD_BATDEBUG
  369. #define CONFIG_CMD_CHARGER
  370. #undef CONFIG_CMD_CHGRAMP
  371. #undef CONFIG_CMD_CLOCKGATES
  372. #undef CONFIG_CMD_COMXTEST
  373. #undef CONFIG_CMD_ECTEMP
  374. #define CONFIG_CMD_FASTCHARGE
  375. #undef CONFIG_CMD_FLASH
  376. #undef CONFIG_CMD_FORCETIME
  377. #undef CONFIG_CMD_GSV
  378. #define CONFIG_CMD_HASH
  379. #undef CONFIG_CMD_HOSTCMD
  380. #define CONFIG_CMD_I2C_SCAN
  381. #define CONFIG_CMD_I2C_XFER
  382. #undef CONFIG_CMD_I2CWEDGE
  383. #define CONFIG_CMD_IDLE_STATS
  384. #define CONFIG_CMD_KEYBOARD
  385. #undef CONFIG_CMD_ILIM
  386. #define CONFIG_CMD_INA
  387. #define CONFIG_CMD_REGULATOR
  388. #undef CONFIG_CMD_JUMPTAGS
  389. #undef CONFIG_CMD_LID_ANGLE
  390. #undef CONFIG_CMD_MCDP
  391. #define CONFIG_CMD_PD
  392. #undef CONFIG_CMD_PD_DEV_DUMP_INFO
  393. #undef CONFIG_CMD_PD_FLASH
  394. #undef CONFIG_CMD_PLL
  395. #undef CONFIG_CMD_PMU
  396. #define CONFIG_CMD_POWER_AP
  397. #define CONFIG_CMD_POWERINDEBUG
  398. #undef CONFIG_CMD_POWERLED
  399. #undef CONFIG_CMD_RTC_ALARM
  400. #undef CONFIG_CMD_SCRATCHPAD
  401. #define CONFIG_CMD_SHMEM
  402. #undef CONFIG_CMD_SLEEP
  403. #undef CONFIG_CMD_SPI_FLASH
  404. #undef CONFIG_CMD_STACKOVERFLOW
  405. #undef CONFIG_CMD_TASKREADY
  406. #define CONFIG_CMD_TEMP_SENSOR
  407. #define CONFIG_CMD_TIMERINFO
  408. #define CONFIG_CMD_TYPEC
  409. #undef CONFIG_CMD_USART_INFO
  410. #undef CONFIG_CMD_USB_PD_PE
  411. #define CONFIG_CMD_USBMUX
  412. /*****************************************************************************/
  413. /* Support Code RAM architecture (run code in RAM). */
  414. #undef CONFIG_CODERAM_ARCH
  415. /* Base address of Code RAM. */
  416. #undef CONFIG_CDRAM_BASE
  417. /* Size of Code RAM. */
  418. #undef CONFIG_CDRAM_SIZE
  419. /* Provide common core code to output panic information without interrupts. */
  420. #define CONFIG_COMMON_PANIC_OUTPUT
  421. /*
  422. * Store a panic log and halt the system for a software-related reasons, such as
  423. * stack overflow or assertion failure.
  424. */
  425. #undef CONFIG_SOFTWARE_PANIC
  426. /*
  427. * Provide the default GPIO abstraction layer.
  428. * You want this unless you are doing a really tiny firmware.
  429. */
  430. #define CONFIG_COMMON_GPIO
  431. /*
  432. * Provides smaller GPIO names to reduce flash size. Instead of the 'name'
  433. * field in GPIO macro it will concat 'port' and 'pin' to reduce flash size.
  434. */
  435. #undef CONFIG_COMMON_GPIO_SHORTNAMES
  436. /*
  437. * Provide common runtime layer code (tasks, hooks ...)
  438. * You want this unless you are doing a really tiny firmware.
  439. */
  440. #define CONFIG_COMMON_RUNTIME
  441. /* Provide common core code to handle the operating system timers. */
  442. #define CONFIG_COMMON_TIMER
  443. /*****************************************************************************/
  444. /*
  445. * Provide additional help on console commands, such as the supported
  446. * options/usage.
  447. *
  448. * Boards may #undef this to reduce image size.
  449. */
  450. #define CONFIG_CONSOLE_CMDHELP
  451. /*
  452. * Number of entries in console history buffer.
  453. *
  454. * Boards may #undef this to reduce memory usage.
  455. */
  456. #define CONFIG_CONSOLE_HISTORY 8
  457. /* Max length of a single line of input */
  458. #define CONFIG_CONSOLE_INPUT_LINE_SIZE 80
  459. /*
  460. * Disable EC console input if the system is locked. This is needed for
  461. * security on platforms where the EC console is accessible from outside the
  462. * case - for example, via a special USB dongle.
  463. */
  464. #undef CONFIG_CONSOLE_RESTRICTED_INPUT
  465. /* Include CRC-8 utility function */
  466. #undef CONFIG_CRC8
  467. /*****************************************************************************/
  468. /*
  469. * Debugging config
  470. *
  471. * Note that these options are enabled by default, because they're really
  472. * handy for debugging systems during bringup and even at factory time.
  473. *
  474. * A board may undefine any or all of these to reduce image size and RAM usage,
  475. * at the cost of debuggability.
  476. */
  477. /*
  478. * ASSERT() macros are checked at runtime. See CONFIG_DEBUG_ASSERT_REBOOTS
  479. * to see what happens if one fails.
  480. *
  481. * Boards may #undef this to reduce image size.
  482. */
  483. #define CONFIG_DEBUG_ASSERT
  484. /*
  485. * Prints a message and reboots if an ASSERT() macro fails at runtime. When
  486. * enabled, an ASSERT() which fails will produce a message of the form:
  487. *
  488. * ASSERTION FAILURE '<expr>' in function() at file:line
  489. *
  490. * If this is not defined, failing ASSERT() will trigger a BKPT instruction
  491. * instead.
  492. *
  493. * Ignored if CONFIG_DEBUG_ASSERT is not defined.
  494. *
  495. * Boards may #undef this to reduce image size.
  496. */
  497. #define CONFIG_DEBUG_ASSERT_REBOOTS
  498. /*
  499. * On assertion failure, prints only the file name and the line number.
  500. *
  501. * Ignored if CONFIG_DEBUG_ASSERT_REBOOTS is not defined.
  502. *
  503. * Boards may define this to reduce image size.
  504. */
  505. #undef CONFIG_DEBUG_ASSERT_BRIEF
  506. /*
  507. * Disable the write buffer used for default memory map accesses.
  508. * This turns "Imprecise data bus errors" into "Precise" errors
  509. * in exception traces at the cost of some performance.
  510. * This may help identify the offending instruction causing an
  511. * exception. Supported on cortex-m.
  512. */
  513. #undef CONFIG_DEBUG_DISABLE_WRITE_BUFFER
  514. /*
  515. * Print additional information when exceptions are triggered, such as the
  516. * fault address, here shown as bfar. This shows the reason for the fault
  517. * and may help to determine the cause.
  518. *
  519. * === EXCEPTION: 03 ====== xPSR: 01000000 ===========
  520. * r0 :0000000b r1 :00000047 r2 :60000000 r3 :200013dd
  521. * r4 :00000000 r5 :080053f4 r6 :200013d0 r7 :00000002
  522. * r8 :00000000 r9 :200013de r10:00000000 r11:00000000
  523. * r12:00000000 sp :200009a0 lr :08002b85 pc :08003a8a
  524. * Precise data bus error, Forced hard fault, Vector catch, bfar = 60000000
  525. * mmfs = 00008200, shcsr = 00000000, hfsr = 40000000, dfsr = 00000008
  526. *
  527. * If this is not defined, only a register dump will be printed.
  528. *
  529. * Boards may #undef this to reduce image size.
  530. */
  531. #define CONFIG_DEBUG_EXCEPTIONS
  532. /* Support Synchronous UART debug printf. */
  533. #undef CONFIG_DEBUG_PRINTF
  534. /* Check for stack overflows on every context switch */
  535. #define CONFIG_DEBUG_STACK_OVERFLOW
  536. /*****************************************************************************/
  537. /* Support DMA transfers inside the EC */
  538. #undef CONFIG_DMA
  539. /* Use the common interrupt handlers for DMA IRQs */
  540. #define CONFIG_DMA_DEFAULT_HANDLERS
  541. /* Compile extra debugging and tests for the DMA module */
  542. #undef CONFIG_DMA_HELP
  543. /* Support EC to Internal bus bridge. */
  544. #undef CONFIG_EC2I
  545. /* Support EC chip internal data EEPROM */
  546. #undef CONFIG_EEPROM
  547. /*
  548. * Compile the eoption module, which provides a higher-level interface to
  549. * options stored in internal data EEPROM.
  550. */
  551. #undef CONFIG_EOPTION
  552. /* Include code for handling external power */
  553. #define CONFIG_EXTPOWER
  554. /* Support detecting external power presence via a GPIO */
  555. #undef CONFIG_EXTPOWER_GPIO
  556. /*****************************************************************************/
  557. /* Number of cooling fans. Undef if none. */
  558. #undef CONFIG_FANS
  559. /*
  560. * Replace the default fan_percent_to_rpm() function with a board-specific
  561. * implementation in board.c
  562. */
  563. #undef CONFIG_FAN_RPM_CUSTOM
  564. /*
  565. * We normally check and update the fans once per second (HOOK_SECOND). If this
  566. * is #defined to a postive integer N, we will only update the fans every N
  567. * seconds instead.
  568. */
  569. #undef CONFIG_FAN_UPDATE_PERIOD
  570. /*****************************************************************************/
  571. /* Flash configuration */
  572. /* Support programming on-chip flash */
  573. #define CONFIG_FLASH
  574. #undef CONFIG_FLASH_BANK_SIZE
  575. #undef CONFIG_FLASH_BASE
  576. #undef CONFIG_FLASH_ERASED_VALUE32
  577. #undef CONFIG_FLASH_ERASE_SIZE
  578. /*
  579. * Flash is directly mapped into the EC's address space. If this is not
  580. * defined, the flash driver must implement flash_physical_read().
  581. */
  582. #define CONFIG_FLASH_MAPPED
  583. #undef CONFIG_FLASH_PHYSICAL_SIZE
  584. #undef CONFIG_FLASH_PROTECT_NEXT_BOOT
  585. /*
  586. * Store persistent write protect for the flash inside the flash data itself.
  587. * This allows ECs with internal flash to emulate something closer to a SPI
  588. * flash write protect register. If this is not defined, write protect state
  589. * is maintained solely by the physical flash driver.
  590. */
  591. #define CONFIG_FLASH_PSTATE
  592. /*
  593. * Store the pstate data in its own dedicated bank of flash. This allows
  594. * disabling the protect-RO-at-boot flag without rewriting the RO firmware,
  595. * but costs a bank of flash.
  596. *
  597. * If this is not defined, the pstate data is stored inside the RO firmware
  598. * image itself. This is more space-efficient, but the only way to clear the
  599. * flag once it's set is to rewrite the RO firmware (after removing the WP
  600. * screw, of course).
  601. */
  602. #define CONFIG_FLASH_PSTATE_BANK
  603. #undef CONFIG_FLASH_SIZE
  604. #undef CONFIG_FLASH_WRITE_IDEAL_SIZE
  605. #undef CONFIG_FLASH_WRITE_SIZE
  606. /* Base address of SPI Flash. */
  607. #undef CONFIG_FLASH_BASE_SPI
  608. /*****************************************************************************/
  609. /* Include a flashmap in the compiled firmware image */
  610. #define CONFIG_FMAP
  611. /* Allow EC serial console input to wake up the EC from STOP mode */
  612. #undef CONFIG_FORCE_CONSOLE_RESUME
  613. /* Enable support for floating point unit */
  614. #undef CONFIG_FPU
  615. /*****************************************************************************/
  616. /* Firmware region configuration */
  617. #undef CONFIG_FW_IMAGE_SIZE
  618. #undef CONFIG_FW_PSTATE_OFF
  619. #undef CONFIG_FW_PSTATE_SIZE
  620. /*
  621. * Read-only / read-write image configuration.
  622. * Images may reside on storage (ex. external or internal SPI) at a different
  623. * offset than when copied to program memory. Hence, two sets of offsets,
  624. * for STORAGE and for MEMORY.
  625. */
  626. #undef CONFIG_RO_MEM_OFF
  627. #undef CONFIG_RO_STORAGE_OFF
  628. #undef CONFIG_RO_SIZE
  629. #undef CONFIG_RW_MEM_OFF
  630. #undef CONFIG_RW_STORAGE_OFF
  631. #undef CONFIG_RW_SIZE
  632. /*
  633. * Write protect region offset / size. This region normally encompasses the
  634. * RO image, but may also contain additional images or data.
  635. */
  636. #undef CONFIG_WP_OFF
  637. #undef CONFIG_WP_SIZE
  638. /*
  639. * Board Image ec.bin contains a RO firmware. If not defined, the image will
  640. * only contain the RW firmware. The RO firmware comes from another board.
  641. */
  642. #define CONFIG_FW_INCLUDE_RO
  643. /* If defined, another image (RW) exists with more features */
  644. #undef CONFIG_FW_LIMITED_IMAGE
  645. /*
  646. * If defined, we can use system_get_fw_reset_vector function to decide
  647. * reset vector of RO/RW firmware for sysjump.
  648. */
  649. #undef CONFIG_FW_RESET_VECTOR
  650. /*****************************************************************************/
  651. /* Motion sensor based gesture recognition information */
  652. /* These all require HAS_TASK_MOTIONSENSE to work */
  653. /* Do we want to detect gestures? */
  654. #undef CONFIG_GESTURE_DETECTION
  655. /* Which sensor to look for gesture recognition */
  656. #undef CONFIG_GESTURE_SENSOR_BATTERY_TAP
  657. /* Sensor sampling interval for gesture recognition */
  658. #undef CONFIG_GESTURE_SAMPLING_INTERVAL_MS
  659. /*
  660. * Double tap detection parameters
  661. * Double tap works by looking for two isolated Z-axis accelerometer impulses
  662. * preceded and followed by relatively calm periods of accelerometer motion.
  663. *
  664. * Define an outer and inner window. The inner window specifies how
  665. * long the tap impulse is expected to last. The outer window specifies the
  666. * period before the initial tap impluse and after the final tap impulse for
  667. * which to check for relatively calm periods. In between the two impulses
  668. * there is a minimum and maximum interstice time allowed.
  669. */
  670. #undef CONFIG_GESTURE_TAP_OUTER_WINDOW_T
  671. #undef CONFIG_GESTURE_TAP_INNER_WINDOW_T
  672. #undef CONFIG_GESTURE_TAP_MIN_INTERSTICE_T
  673. #undef CONFIG_GESTURE_TAP_MAX_INTERSTICE_T
  674. /* Do we want to detect the lid angle? */
  675. #undef CONFIG_LID_ANGLE
  676. /* Which sensor is located on the base? */
  677. #undef CONFIG_LID_ANGLE_SENSOR_BASE
  678. /* Which sensor is located on the lid? */
  679. #undef CONFIG_LID_ANGLE_SENSOR_LID
  680. /*
  681. * Allows using the lid angle measurement to determine if peripheral devices
  682. * should be enabled or disabled, like key scanning, trackpad interrupt.
  683. */
  684. #undef CONFIG_LID_ANGLE_UPDATE
  685. /* Define which index in motion_sensors is in the base. */
  686. #undef CONFIG_SENSOR_BASE
  687. /* Define which index in motion_sensors is in the lid. */
  688. #undef CONFIG_SENSOR_LID
  689. /******************************************************************************/
  690. /* Host to RAM (H2RAM) Memory Mapping */
  691. /* H2RAM Base memory address */
  692. #undef CONFIG_H2RAM_BASE
  693. /* H2RAM Size */
  694. #undef CONFIG_H2RAM_SIZE
  695. /* H2RAM Host LPC I/O base memory address */
  696. #undef CONFIG_H2RAM_HOST_LPC_IO_BASE
  697. /*****************************************************************************/
  698. /*
  699. * Support the host asking the EC about the status of the most recent host
  700. * command.
  701. *
  702. * When the AP is attached to the EC via a serialized bus such as I2C or SPI,
  703. * it needs a way to minimize the length of time an EC command will tie up the
  704. * bus (and the kernel driver on the AP). If this config is defined, the EC
  705. * may return an in-progress result code for slow commands such as flash
  706. * erase/write instead of stalling until the command finishes processing, and
  707. * the AP may then inquire the status of the current command and/or the result
  708. * of the previous command.
  709. */
  710. #undef CONFIG_HOST_COMMAND_STATUS
  711. /* If we have host command task, assume we also are using host events. */
  712. #ifdef HAS_TASK_HOSTCMD
  713. #define CONFIG_HOSTCMD_EVENTS
  714. #else
  715. #undef CONFIG_HOSTCMD_EVENTS
  716. #endif
  717. /*
  718. * For ECs where the host command interface is I2C, slave
  719. * address which the EC will respond to.
  720. */
  721. #undef CONFIG_HOSTCMD_I2C_SLAVE_ADDR
  722. /*
  723. * Accept EC host commands over the SPI slave (SPS) interface.
  724. */
  725. #undef CONFIG_HOSTCMD_SPS
  726. /*
  727. * Host command rate limiting assures EC will have time to process lower
  728. * priority tasks even if the AP is hammering the EC with host commands.
  729. * If there is less than CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST between
  730. * host commands for CONFIG_HOSTCMD_RATE_LIMITING_PERIOD, then a
  731. * recess period of CONFIG_HOSTCMD_RATE_LIMITING_RECESS will be
  732. * enforced.
  733. */
  734. #define CONFIG_HOSTCMD_RATE_LIMITING_PERIOD (500 * MSEC)
  735. #define CONFIG_HOSTCMD_RATE_LIMITING_MIN_REST (3 * MSEC)
  736. #define CONFIG_HOSTCMD_RATE_LIMITING_RECESS (20 * MSEC)
  737. /* PD MCU supports host commands */
  738. #undef CONFIG_HOSTCMD_PD
  739. /*
  740. * Use if PD MCU controls charging (selecting charging port and input
  741. * current limit).
  742. */
  743. #undef CONFIG_HOSTCMD_PD_CHG_CTRL
  744. /* Panic when status of PD MCU reflects that it has crashed */
  745. #undef CONFIG_HOSTCMD_PD_PANIC
  746. /*****************************************************************************/
  747. /* Enable debugging and profiling statistics for hook functions */
  748. #undef CONFIG_HOOK_DEBUG
  749. /*****************************************************************************/
  750. /* CRC configuration */
  751. /* Enable the hardware accelerator for CRC computation */
  752. #undef CONFIG_HW_CRC
  753. /* Enable the software routine for CRC computation */
  754. #undef CONFIG_SW_CRC
  755. /*****************************************************************************/
  756. /* Enable system hibernate */
  757. #define CONFIG_HIBERNATE
  758. /* Default delay after shutting down before hibernating */
  759. #define CONFIG_HIBERNATE_DELAY_SEC 3600
  760. /*
  761. * Use to define going in to hibernate early if low on battery.
  762. * CONFIG_HIBERNATE_BATT_PCT specifies the low battery threshold
  763. * for going into hibernate early, and CONFIG_HIBERNATE_BATT_SEC defines
  764. * the minimum amount of time to stay in G3 before checking for low
  765. * battery hibernate.
  766. */
  767. #undef CONFIG_HIBERNATE_BATT_PCT
  768. #undef CONFIG_HIBERNATE_BATT_SEC
  769. /*
  770. * Perform a system reset on wake from hibernate. This is the default behavior,
  771. * and the only chip-supported behavior for certain ECs.
  772. */
  773. #define CONFIG_HIBERNATE_RESET_ON_WAKE
  774. /* For ECs with multiple wakeup pins, define enabled wakeup pins */
  775. #undef CONFIG_HIBERNATE_WAKEUP_PINS
  776. /* Use a hardware specific udelay(). */
  777. #undef CONFIG_HW_SPECIFIC_UDELAY
  778. /*****************************************************************************/
  779. /* I2C configuration */
  780. #undef CONFIG_I2C
  781. #undef CONFIG_I2C_ARBITRATION
  782. #undef CONFIG_I2C_DEBUG
  783. #undef CONFIG_I2C_DEBUG_PASSTHRU
  784. #undef CONFIG_I2C_PASSTHROUGH
  785. #undef CONFIG_I2C_PASSTHRU_RESTRICTED
  786. /* Defines I2C operation retry count when slave nack'd(EC_ERROR_BUSY) */
  787. #define CONFIG_I2C_NACK_RETRY_COUNT 0
  788. /*
  789. * I2C SCL gating.
  790. *
  791. * If CONFIG_I2C_SCL_GATE_ADDR/PORT is defined, whenever the defined address
  792. * is addressed, CONFIG_I2C_SCL_GATE_GPIO is set to high. When the I2C
  793. * transaction is done, the pin is set back to low.
  794. */
  795. #undef CONFIG_I2C_SCL_GATE_PORT
  796. #undef CONFIG_I2C_SCL_GATE_ADDR
  797. #undef CONFIG_I2C_SCL_GATE_GPIO
  798. /*
  799. * I2C multi-port controller.
  800. *
  801. * If CONFIG_I2C_MULTI_PORT_CONTROLLER is defined, a single on-chip I2C
  802. * controller may have multiple I2C ports attached. Therefore, I2c operations
  803. * must lock the controller (not just the port) to prevent hardware access
  804. * conflicts.
  805. */
  806. #undef CONFIG_I2C_MULTI_PORT_CONTROLLER
  807. /*****************************************************************************/
  808. /* Current/Power monitor */
  809. /*
  810. * Compile driver for INA219 or INA231. These two flags may not be both
  811. * defined.
  812. */
  813. #undef CONFIG_INA219
  814. #undef CONFIG_INA231
  815. /*****************************************************************************/
  816. /* Inductive charging */
  817. /* Enable inductive charging support */
  818. #undef CONFIG_INDUCTIVE_CHARGING
  819. /******************************************************************************/
  820. /* Support NXP PCA9534 I/O expander. */
  821. #undef CONFIG_IO_EXPANDER_PCA9534
  822. /*****************************************************************************/
  823. /* Number of IRQs supported on the EC chip */
  824. #undef CONFIG_IRQ_COUNT
  825. /*
  826. * This is the block size of the ILM on the it839x chip.
  827. * The ILM for static code cache, CPU fetch instruction from
  828. * ILM(ILM -> CPU)instead of flash(flash -> IMMU -> CPU) if enabled.
  829. */
  830. #undef CONFIG_IT83XX_ILM_BLOCK_SIZE
  831. /* Enable Wake-up control interrupt from KSI */
  832. #undef CONFIG_IT83XX_KEYBOARD_KSI_WUC_INT
  833. /* Interrupt for PECI module. (IT839X series and IT838X DX only) */
  834. #undef CONFIG_IT83XX_PECI_WITH_INTERRUPT
  835. /* To define it, if I2C channel C and PECI used at the same time. */
  836. #undef CONFIG_IT83XX_SMCLK2_ON_GPC7
  837. /*****************************************************************************/
  838. /* Keyboard config */
  839. /*
  840. * The Silego reset chip sits in between the EC and the physical keyboard on
  841. * column 2. To save power in low-power modes, some Silego variants require
  842. * the signal to be inverted so that the open-drain output from the EC isn't
  843. * costing power due to the pull-up resistor in the Silego.
  844. */
  845. #undef CONFIG_KEYBOARD_COL2_INVERTED
  846. /*
  847. * Config KSO to start from a different KSO pin. This is to allow some chips
  848. * to use alternate functions on KSO pins.
  849. */
  850. #define CONFIG_KEYBOARD_KSO_BASE 0
  851. /* Enable extra debugging output from keyboard modules */
  852. #undef CONFIG_KEYBOARD_DEBUG
  853. /* The board uses a negative edge-triggered GPIO for keyboard interrupts. */
  854. #undef CONFIG_KEYBOARD_IRQ_GPIO
  855. /* Compile code for 8042 keyboard protocol */
  856. #undef CONFIG_KEYBOARD_PROTOCOL_8042
  857. /* Compile code for MKBP keyboard protocol */
  858. #undef CONFIG_KEYBOARD_PROTOCOL_MKBP
  859. /*
  860. * Keyboard config (struct keyboard_scan_config) is in board.c. If this is
  861. * not defined, default values from common/keyboard_scan.c will be used.
  862. */
  863. #undef CONFIG_KEYBOARD_BOARD_CONFIG
  864. /*
  865. * Minimum CPU clocks between scans. This ensures that keyboard scanning
  866. * doesn't starve the other EC tasks of CPU when running at a decreased system
  867. * clock.
  868. */
  869. #undef CONFIG_KEYBOARD_POST_SCAN_CLOCKS
  870. /*
  871. * Call board-supplied keyboard_suppress_noise() function when the debounced
  872. * keyboard state changes. Some boards use this to send a signal to the audio
  873. * codec to suppress typing noise picked up by the microphone.
  874. */
  875. #undef CONFIG_KEYBOARD_SUPPRESS_NOISE
  876. /*
  877. * Enable keyboard testing functionality. This enables a message which receives
  878. * a list of keyscan events from the AP and processes them. This will cause
  879. * keypresses to appear on the AP through the same mechanism as a normal
  880. * keyboard press.
  881. *
  882. * This can be used to spoof keyboard events, so is not normally defined,
  883. * except during internal testing.
  884. */
  885. #undef CONFIG_KEYBOARD_TEST
  886. /*****************************************************************************/
  887. /* Support common LED interface */
  888. #undef CONFIG_LED_COMMON
  889. /* Standard LED behavior according to spec given that we have a red-green
  890. * bicolor led for charging and one power led
  891. */
  892. #undef CONFIG_LED_POLICY_STD
  893. /*
  894. * LEDs for LED_POLICY STD may be inverted. In this case they are active low
  895. * and the GPIO names will be GPIO_LED..._L.
  896. */
  897. #undef CONFIG_LED_BAT_ACTIVE_LOW
  898. #undef CONFIG_LED_POWER_ACTIVE_LOW
  899. /* Support for LED driver chip(s) */
  900. #undef CONFIG_LED_DRIVER_DS2413 /* Maxim DS2413, on one-wire interface */
  901. #undef CONFIG_LED_DRIVER_LP5562 /* LP5562, on I2C interface */
  902. /* Offset in flash where little firmware will live. */
  903. #undef CONFIG_LFW_OFFSET
  904. /*
  905. * Compile lid switch support.
  906. *
  907. * This is enabled by default because all boards other than reference boards
  908. * are for laptops with lid switchs. Reference boards #undef it.
  909. */
  910. #define CONFIG_LID_SWITCH
  911. /*
  912. * GPIOs to use to detect that the lid is opened.
  913. *
  914. * This is a X-macro composed of a list of LID_OPEN(GPIO_xxx) elements defining
  915. * all the GPIOs to check to find whether the lid is currently opened.
  916. * If not defined, it is using GPIO_LID_OPEN.
  917. */
  918. #undef CONFIG_LID_SWITCH_GPIO_LIST
  919. /*
  920. * Support for turning the lightbar power rails on briefly when the AP is off.
  921. * Enabling this requires implementing the board-specific lb_power() function
  922. * to do it (see lb_common.h).
  923. */
  924. #undef CONFIG_LIGHTBAR_POWER_RAILS
  925. /*
  926. * For tap sequence, show the last segment in dim to give a better idea of
  927. * battery percentage.
  928. */
  929. #undef CONFIG_LIGHTBAR_TAP_DIM_LAST_SEGMENT
  930. /* Program memory offset for little firmware loader. */
  931. #undef CONFIG_LOADER_MEM_OFF
  932. /* Size of little firmware loader. */
  933. #undef CONFIG_LOADER_SIZE
  934. /* Little firmware loader storage offset. */
  935. #undef CONFIG_LOADER_STORAGE_OFF
  936. /*
  937. * Low power idle options. These are disabled by default and all boards that
  938. * want to use low power idle must define it. When using the LFIOSC, the low
  939. * frequency clock will be used to conserve even more power when possible.
  940. *
  941. * GPIOs which need to trigger interrupts in low power idle must specify the
  942. * GPIO_INT_DSLEEP flag in gpio_list[].
  943. *
  944. * Note that for some processors (e.g. LM4), an active JTAG connection will
  945. * prevent the EC from using low-power idle.
  946. */
  947. #undef CONFIG_LOW_POWER_IDLE
  948. #undef CONFIG_LOW_POWER_USE_LFIOSC
  949. /*
  950. * Enable Pseudo G3 (power removed from EC)
  951. * This requires board specific implementation.
  952. */
  953. #undef CONFIG_LOW_POWER_PSEUDO_G3
  954. /*
  955. * Enable deep sleep during S0 (ignores SLEEP_MASK_AP_RUN).
  956. */
  957. #undef CONFIG_LOW_POWER_S0
  958. /* Support LPC interface */
  959. #undef CONFIG_LPC
  960. /* Base address of low power RAM. */
  961. #undef CONFIG_LPRAM_BASE
  962. /* Size of low power RAM. */
  963. #undef CONFIG_LPRAM_SIZE
  964. /* Use Link-Time Optimizations to try to reduce the firmware code size */
  965. #undef CONFIG_LTO
  966. /* Need for a math library */
  967. #undef CONFIG_MATH_UTIL
  968. /* Presence of a Bosh Sensortec BMM150 magnetometer behind a BMI160. */
  969. #undef CONFIG_MAG_BMI160_BMM150
  970. /* Microchip EC SRAM start address */
  971. #undef CONFIG_MEC_SRAM_BASE_START
  972. /* Microchip EC SRAM end address */
  973. #undef CONFIG_MEC_SRAM_BASE_END
  974. /* Microchip EC SRAM size */
  975. #undef CONFIG_MEC_SRAM_SIZE
  976. /*
  977. * Define Megachips DisplayPort to HDMI protocol converter/level shifter serial
  978. * interface.
  979. */
  980. #undef CONFIG_MCDP28X0
  981. /* Define clock input to MFT module. */
  982. #undef CONFIG_MFT_INPUT_LFCLK
  983. /* Support MKBP event */
  984. #undef CONFIG_MKBP_EVENT
  985. /* Support memory protection unit (MPU) */
  986. #undef CONFIG_MPU
  987. /* Support one-wire interface */
  988. #undef CONFIG_ONEWIRE
  989. /* Support PECI interface to x86 processor */
  990. #undef CONFIG_PECI
  991. /*
  992. * Maximum operating temperature in degrees Celcius used on some x86
  993. * processors. CPU chip temperature is reported relative to this value and
  994. * is never reported greater than this value. Processor asserts PROCHOT#
  995. * and starts throttling frequency and voltage at this temp. Operation may
  996. * become unreliable if temperature exceeds this limit.
  997. */
  998. #undef CONFIG_PECI_TJMAX
  999. /*****************************************************************************/
  1000. /* PMU config */
  1001. /*
  1002. * Enable hard-resetting the PMU from the EC. The implementation is rather
  1003. * hacky; it simply shorts out the 3.3V rail to force the PMIC to panic. We
  1004. * need this unfortunate hack because it's the only way to reset the I2C engine
  1005. * inside the PMU.
  1006. */
  1007. #undef CONFIG_PMU_HARD_RESET
  1008. /* Support TPS65090 PMU */
  1009. #undef CONFIG_PMU_TPS65090
  1010. /* Suport TPS65090 PMU charging LED. */
  1011. #undef CONFIG_PMU_TPS65090_CHARGING_LED
  1012. /*
  1013. * Support PMU powerinfo host and console commands. Note that the
  1014. * implementation is currently specific to the Pit board, so don't blindly
  1015. * enable this for another board without fixing that first.
  1016. */
  1017. #undef CONFIG_PMU_POWERINFO
  1018. /*
  1019. * Enable this config to make console UART self sufficient (no other
  1020. * initialization required before uart_init(), no interrupts, uart_tx_char()
  1021. * does not exit until character finished transmitting).
  1022. *
  1023. * This is useful during early hardware bringup, each platform needs to
  1024. * implement its own code to support this.
  1025. */
  1026. #undef CONFIG_POLLING_UART
  1027. /*****************************************************************************/
  1028. /*
  1029. * Enable polling at boot by port 80 task.
  1030. * Ignored if port 80 is handled by interrupt
  1031. */
  1032. #undef CONFIG_PORT80_TASK_EN
  1033. /*****************************************************************************/
  1034. /* Compile common code to support power button debouncing */
  1035. #undef CONFIG_POWER_BUTTON
  1036. /* Force the active state of the power button : 0(default if unset) or 1 */
  1037. #undef CONFIG_POWER_BUTTON_ACTIVE_STATE
  1038. /* Allow the power button to send events while the lid is closed */
  1039. #undef CONFIG_POWER_BUTTON_IGNORE_LID
  1040. /* Support sending the power button signal to x86 chipsets */
  1041. #undef CONFIG_POWER_BUTTON_X86
  1042. /* Compile common code for AP power state machine */
  1043. #undef CONFIG_POWER_COMMON
  1044. /* Disable the power-on transition when the lid is opened */
  1045. #undef CONFIG_POWER_IGNORE_LID_OPEN
  1046. /* Support stopping in S5 on shutdown */
  1047. #undef CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
  1048. /* Use part of the EC's data EEPROM to hold persistent storage for the AP. */
  1049. #undef CONFIG_PSTORE
  1050. /*****************************************************************************/
  1051. /* Support PWM control */
  1052. #undef CONFIG_PWM
  1053. /* Support PWM control while in low-power idle */
  1054. #undef CONFIG_PWM_DSLEEP
  1055. /* Define clock input to PWM module. */
  1056. #undef CONFIG_PWM_INPUT_LFCLK
  1057. /*****************************************************************************/
  1058. /* Support PWM output to keyboard backlight */
  1059. #undef CONFIG_PWM_KBLIGHT
  1060. /* Base address of RAM for the chip */
  1061. #undef CONFIG_RAM_BASE
  1062. /* Base address of RAM for RO/RW. */
  1063. #undef CONFIG_RAM_BASE_RORW
  1064. /* Size of RAM available on the chip, in bytes */
  1065. #undef CONFIG_RAM_SIZE
  1066. /* Size of RAM for loader */
  1067. #undef CONFIG_RAM_SIZE_LOADER
  1068. /* Size of RAM for RO/RW */
  1069. #undef CONFIG_RAM_SIZE_RORW
  1070. /* Size of RAM for RO/RW & loader */
  1071. #undef CONFIG_RAM_SIZE_TOTAL
  1072. /* Support IR357x Link voltage regulator debugging / reprogramming */
  1073. #undef CONFIG_REGULATOR_IR357X
  1074. /* Support verifying 2048-bit RSA signature */
  1075. #undef CONFIG_RSA
  1076. /* Define the RSA key size. */
  1077. #undef CONFIG_RSA_KEY_SIZE
  1078. /* Flash address of the RO image. */
  1079. #undef CONFIG_RO_IMAGE_FLASHADDR
  1080. /* Flash address of the RW image. */
  1081. #undef CONFIG_RW_IMAGE_FLASHADDR
  1082. /*
  1083. * Verify the RW firmware using the RSA signature.
  1084. * (for accessories without software sync)
  1085. */
  1086. #undef CONFIG_RWSIG
  1087. /****************************************************************************/
  1088. /* Shared objects library. */
  1089. /* Support shared objects library between RO and RW. */
  1090. #undef CONFIG_SHAREDLIB
  1091. /* Size of shared objects library. */
  1092. #undef CONFIG_SHAREDLIB_SIZE
  1093. /* Program memory offset of shared objects library. */
  1094. #undef CONFIG_SHAREDLIB_MEM_OFF
  1095. /* Storage offset of sharedobjects library. */
  1096. #undef CONFIG_SHAREDLIB_STORAGE_OFF
  1097. /*
  1098. * If defined, the hash module will save its last computed hash when jumping
  1099. * between EC images.
  1100. */
  1101. #undef CONFIG_SAVE_VBOOT_HASH
  1102. /* Enable smart battery firmware update driver */
  1103. #undef CONFIG_SB_FIRMWARE_UPDATE
  1104. /* Allow the board to use a GPIO for the SCI# signal. */
  1105. #undef CONFIG_SCI_GPIO
  1106. /* Support computing SHA-1 hash */
  1107. #undef CONFIG_SHA1
  1108. /* Support computing SHA-256 hash (without the VBOOT code) */
  1109. #undef CONFIG_SHA256
  1110. /* Emulate the CLZ (Count Leading Zeros) in software for CPU lacking support */
  1111. #undef CONFIG_SOFTWARE_CLZ
  1112. /* Support smbus interface */
  1113. #undef CONFIG_SMBUS
  1114. /* Support SPI interfaces */
  1115. #undef CONFIG_SPI
  1116. /* Support deprecated SPI protocol version 2. */
  1117. #undef CONFIG_SPI_PROTOCOL_V2
  1118. /*
  1119. * Support SPI Slave interfaces. The first board supporting this is cr50 and
  1120. * in its parlance SPI_SLAVE is called SPS. This convention might be
  1121. * reconsidered later, and the use of "SPI" in different config options needs
  1122. * to be cleand up. (crbug.com/512613).
  1123. */
  1124. #undef CONFIG_SPS
  1125. /* Define the SPI port to use to access SPI accelerometer */
  1126. #undef CONFIG_SPI_ACCEL_PORT
  1127. /* Support SPI flash */
  1128. #undef CONFIG_SPI_FLASH
  1129. /* Define the SPI port to use to access the flash */
  1130. #undef CONFIG_SPI_FLASH_PORT
  1131. /* Support W25Q64 SPI flash */
  1132. #undef CONFIG_SPI_FLASH_W25Q64
  1133. /* Support W25X40 SPI flash */
  1134. #undef CONFIG_SPI_FLASH_W25X40
  1135. /* SPI flash part supports SR2 register */
  1136. #undef CONFIG_SPI_FLASH_HAS_SR2
  1137. /* Size (bytes) of SPI flash memory */
  1138. #undef CONFIG_SPI_FLASH_SIZE
  1139. /* SPI master feature */
  1140. #undef CONFIG_SPI_MASTER
  1141. /* Support testing SPI slave controller driver. */
  1142. #undef CONFIG_SPS_TEST
  1143. /* Default stack size to use for tasks, in bytes */
  1144. #undef CONFIG_STACK_SIZE
  1145. /* Use 32-bit timer for clock source on stm32. */
  1146. #undef CONFIG_STM_HWTIMER32
  1147. /* Fake hibernate mode */
  1148. #undef CONFIG_STM32L_FAKE_HIBERNATE
  1149. /*
  1150. * Compile common code to handle simple switch inputs such as the recovery
  1151. * button input from the servo debug interface.
  1152. */
  1153. #undef CONFIG_SWITCH
  1154. /* Support dedicated recovery signal from servo board */
  1155. #undef CONFIG_SWITCH_DEDICATED_RECOVERY
  1156. /*
  1157. * System should remain unlocked even if write protect is enabled.
  1158. *
  1159. * NOTE: This should ONLY be defined during bringup, and should never be
  1160. * defined on a shipping / released platform.
  1161. */
  1162. #undef CONFIG_SYSTEM_UNLOCKED
  1163. /*****************************************************************************/
  1164. /* Task config */
  1165. /*
  1166. * List of enabled tasks in ascending priority order. This is normally
  1167. * defined in each board's ec.tasklist file.
  1168. *
  1169. * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
  1170. * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
  1171. * where :
  1172. * 'n' is the name of the task
  1173. * 'r' is the main routine of the task
  1174. * 'd' is an opaque parameter passed to the routine at startup
  1175. * 's' is the stack size in bytes; must be a multiple of 8
  1176. */
  1177. #undef CONFIG_TASK_LIST
  1178. /*
  1179. * List of test tasks. Same format as CONFIG_TASK_LIST, but used to define
  1180. * additional tasks for a unit test. Normally defined in
  1181. * test/{testname}.tasklist.
  1182. */
  1183. #undef CONFIG_TEST_TASK_LIST
  1184. /*
  1185. * Enable task profiling.
  1186. *
  1187. * Boards may #undef this to reduce image size and RAM usage.
  1188. */
  1189. #define CONFIG_TASK_PROFILING
  1190. /*****************************************************************************/
  1191. /* Temperature sensor config */
  1192. /* Compile common code for temperature sensor support */
  1193. #undef CONFIG_TEMP_SENSOR
  1194. /* Support particular temperature sensor chips */
  1195. #undef CONFIG_TEMP_SENSOR_BD99992GW /* BD99992GW PMIC, on I2C bus */
  1196. #undef CONFIG_TEMP_SENSOR_G781 /* G781 sensor, on I2C bus */
  1197. #undef CONFIG_TEMP_SENSOR_TMP006 /* TI TMP006 sensor, on I2C bus */
  1198. #undef CONFIG_TEMP_SENSOR_TMP432 /* TI TMP432 sensor, on I2C bus */
  1199. /*
  1200. * If defined, active-high GPIO which indicates temperature sensor chips are
  1201. * powered. If not defined, temperature sensors are assumed to be always
  1202. * powered.
  1203. */
  1204. #undef CONFIG_TEMP_SENSOR_POWER_GPIO
  1205. /*****************************************************************************/
  1206. /* TPM-like configuration */
  1207. /* Speak the TPM SPI Hardware Protocol on the SPI slave interface */
  1208. #undef CONFIG_TPM_SPS
  1209. /*****************************************************************************/
  1210. /* USART stream config */
  1211. #undef CONFIG_STREAM_USART
  1212. /*
  1213. * Each USART stream can be individually enabled and accessible using the
  1214. * stream interface provided in the usart_config struct.
  1215. */
  1216. #undef CONFIG_STREAM_USART1
  1217. #undef CONFIG_STREAM_USART2
  1218. #undef CONFIG_STREAM_USART3
  1219. #undef CONFIG_STREAM_USART4
  1220. /*****************************************************************************/
  1221. /* USB stream config */
  1222. #undef CONFIG_STREAM_USB
  1223. /*****************************************************************************/
  1224. /* UART config */
  1225. /* Baud rate for UARTs */
  1226. #define CONFIG_UART_BAUD_RATE 115200
  1227. /* UART index (number) for EC console */
  1228. #undef CONFIG_UART_CONSOLE
  1229. /* UART index (number) for host UART, if present */
  1230. #undef CONFIG_UART_HOST
  1231. /* Use uart_input_filter() to filter UART input. See prototype in uart.h */
  1232. #undef CONFIG_UART_INPUT_FILTER
  1233. /*
  1234. * UART receive buffer size in bytes. Must be a power of 2 for macros in
  1235. * common/uart_buffering.c to work properly. Must be larger than
  1236. * CONFIG_CONSOLE_INPUT_LINE_SIZE to copy and paste scripts.
  1237. */
  1238. #define CONFIG_UART_RX_BUF_SIZE 128
  1239. /* Use DMA for UART input */
  1240. #undef CONFIG_UART_RX_DMA
  1241. /*
  1242. * On some platforms, UART receive DMA can't trigger an interrupt when a single
  1243. * character is received. Those platforms poll for characters every HOOK_TICK.
  1244. * When a character is received, make this many additional checks between then
  1245. * and the next HOOK_TICK, to increase responsiveness of the console to input.
  1246. */
  1247. #define CONFIG_UART_RX_DMA_RECHECKS 5
  1248. /*
  1249. * UART transmit buffer size in bytes. Must be a power of 2 for macros in
  1250. * common/uart_buffering.c to work properly.
  1251. */
  1252. #define CONFIG_UART_TX_BUF_SIZE 512
  1253. /* Use DMA for UART output */
  1254. #undef CONFIG_UART_TX_DMA
  1255. /* The DMA channel for UART. If not defined, default to UART1. */
  1256. #undef CONFIG_UART_TX_DMA_CH
  1257. #undef CONFIG_UART_RX_DMA_CH
  1258. /*****************************************************************************/
  1259. /* USB PD config */
  1260. /* Include all USB Power Delivery modules */
  1261. #undef CONFIG_USB_POWER_DELIVERY
  1262. /* Support for USB PD alternate mode */
  1263. #undef CONFIG_USB_PD_ALT_MODE
  1264. /* Support for USB PD alternate mode of Downward Facing Port */
  1265. #undef CONFIG_USB_PD_ALT_MODE_DFP
  1266. /* Check if max voltage request is allowed before each request */
  1267. #undef CONFIG_USB_PD_CHECK_MAX_REQUEST_ALLOWED
  1268. /* Default state of PD communication enabled flag */
  1269. #define CONFIG_USB_PD_COMM_ENABLED 1
  1270. /* Respond to custom vendor-defined messages over PD */
  1271. #undef CONFIG_USB_PD_CUSTOM_VDM
  1272. /* Default USB data role when a USB PD debug accessory is seen */
  1273. #define CONFIG_USB_PD_DEBUG_DR PD_ROLE_DFP
  1274. /* Define if this board can act as a dual-role PD port (source and sink) */
  1275. #undef CONFIG_USB_PD_DUAL_ROLE
  1276. /* Dynamic USB PD source capability */
  1277. #undef CONFIG_USB_PD_DYNAMIC_SRC_CAP
  1278. /* Support USB PD flash. */
  1279. #undef CONFIG_USB_PD_FLASH
  1280. /* Check whether PD is the sole power source before flash erase operation */
  1281. #undef CONFIG_USB_PD_FLASH_ERASE_CHECK
  1282. /* Major and Minor ChromeOS specific PD device Hardware IDs. */
  1283. #undef CONFIG_USB_PD_HW_DEV_ID_BOARD_MAJOR
  1284. #undef CONFIG_USB_PD_HW_DEV_ID_BOARD_MINOR
  1285. /* HW & SW version for alternate mode discover identity response (4bits each) */
  1286. #undef CONFIG_USB_PD_IDENTITY_HW_VERS
  1287. #undef CONFIG_USB_PD_IDENTITY_SW_VERS
  1288. /* USB PD MCU slave address for host commands */
  1289. #define CONFIG_USB_PD_I2C_SLAVE_ADDR 0x3c
  1290. /* Define if using internal comparator for PD receive */
  1291. #undef CONFIG_USB_PD_INTERNAL_COMP
  1292. /* Record main PD events in a circular buffer */
  1293. #undef CONFIG_USB_PD_LOGGING
  1294. /* The size in bytes of the FIFO used for PD events logging */
  1295. #undef CONFIG_USB_PD_LOG_SIZE
  1296. /* Define if USB-PD device has no way of detecting USB VBUS */
  1297. #undef CONFIG_USB_PD_NO_VBUS_DETECT
  1298. /* Number of USB PD ports */
  1299. #undef CONFIG_USB_PD_PORT_COUNT
  1300. /* Simple DFP, such as power adapter, will not send discovery VDM on connect */
  1301. #undef CONFIG_USB_PD_SIMPLE_DFP
  1302. /* Use comparator module for PD RX interrupt */
  1303. #define CONFIG_USB_PD_RX_COMP_IRQ
  1304. /* Use TCPC module (type-C port controller) */
  1305. #undef CONFIG_USB_PD_TCPC
  1306. /*
  1307. * Choose one of the following TCPMs (type-C port manager) to manage TCPC. The
  1308. * TCPM stub is used to make direct function calls to TCPC when TCPC is on
  1309. * the same MCU. The TCPCI TCPM uses the standard TCPCI i2c interface to TCPC.
  1310. */
  1311. #undef CONFIG_USB_PD_TCPM_STUB
  1312. #undef CONFIG_USB_PD_TCPM_TCPCI
  1313. /*
  1314. * Use this option if the TCPC port controller is on a seperate chip from
  1315. * the TCPM layer and if VUBS detect GPIO is not available on the TCPM
  1316. * mcu.
  1317. */
  1318. #undef CONFIG_USB_PD_TCPM_VBUS
  1319. /* Define the type-c port controller I2C base address. */
  1320. #undef CONFIG_TCPC_I2C_BASE_ADDR
  1321. /* Use this option to enable Try.SRC mode for Dual Role devices */
  1322. #undef CONFIG_USB_PD_TRY_SRC
  1323. /* Set the default minimum battery percentage for Try.Src to be enabled */
  1324. #define CONFIG_USB_PD_TRY_SRC_MIN_BATT_SOC 1
  1325. /* Alternative configuration keeping only the TX part of PHY */
  1326. #undef CONFIG_USB_PD_TX_PHY_ONLY
  1327. /* Use DAC as reference for comparator at 850mV. */
  1328. #undef CONFIG_PD_USE_DAC_AS_REF
  1329. /* USB Product ID. */
  1330. #undef CONFIG_USB_PID
  1331. /* Support for USB type-c superspeed mux */
  1332. #undef CONFIG_USBC_SS_MUX
  1333. /*
  1334. * Only configure USB type-c superspeed mux when DFP (for chipsets that
  1335. * don't support being a UFP)
  1336. */
  1337. #undef CONFIG_USBC_SS_MUX_DFP_ONLY
  1338. /* Sniffer header version
  1339. * Version 1: [timestamp:2B, sequence number:2B]
  1340. * Version 2: [timestamp:2B, sequence number:2B,
  1341. * Vbus value: 2B, vbus timestamp offset: 2B]
  1342. */
  1343. #undef CONFIG_USBC_SNIFFER_HEADER_V1
  1344. #undef CONFIG_USBC_SNIFFER_HEADER_V2
  1345. /* Support v1.1 type-C connection state machine */
  1346. #undef CONFIG_USBC_BACKWARDS_COMPATIBLE_DFP
  1347. /* Support for USB type-c vconn. Not needed for captive cables. */
  1348. #undef CONFIG_USBC_VCONN
  1349. /* Support VCONN swap */
  1350. #undef CONFIG_USBC_VCONN_SWAP
  1351. /* USB Binary device Object Store support */
  1352. #undef CONFIG_USB_BOS
  1353. /* USB Device version of product */
  1354. #undef CONFIG_USB_BCD_DEV
  1355. /*****************************************************************************/
  1356. /* Compile chip support for the USB device controller */
  1357. #undef CONFIG_USB
  1358. /* Support USB blob handler. */
  1359. #undef CONFIG_USB_BLOB
  1360. /* Common USB / BC1.2 charger task */
  1361. #undef CONFIG_USB_CHARGER
  1362. /* Enable USB serial console module. */
  1363. #undef CONFIG_USB_CONSOLE
  1364. /* Support USB HID interface. */
  1365. #undef CONFIG_USB_HID
  1366. /* USB device buffers and descriptors */
  1367. #undef CONFIG_USB_RAM_ACCESS_SIZE
  1368. #undef CONFIG_USB_RAM_ACCESS_TYPE
  1369. #undef CONFIG_USB_RAM_BASE
  1370. #undef CONFIG_USB_RAM_SIZE
  1371. /* Disable automatic connection of USB peripheral */
  1372. #undef CONFIG_USB_INHIBIT_CONNECT
  1373. /* Disable automatic initialization of USB peripheral */
  1374. #undef CONFIG_USB_INHIBIT_INIT
  1375. /* Support simple control of power to the device's USB ports */
  1376. #undef CONFIG_USB_PORT_POWER_DUMB
  1377. /*
  1378. * Support supplying USB power in S3, if the host leaves the port enabled when
  1379. * entering S3.
  1380. */
  1381. #undef CONFIG_USB_PORT_POWER_IN_S3
  1382. /*
  1383. * Support smart power control to the device's USB ports, using
  1384. * dedicated power control chips. This potentially enables automatic
  1385. * negotiation of supplying more power to peripherals.
  1386. */
  1387. #undef CONFIG_USB_PORT_POWER_SMART
  1388. /*
  1389. * Override the default charging mode for USB smart power control.
  1390. * Value is selected from usb_charge_mode in include/usb_charge.h
  1391. */
  1392. #undef CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE
  1393. /*
  1394. * Smart USB power control can use a full set of control signals to the USB
  1395. * port power chip, or a reduced set. If this is defined, use the reduced set.
  1396. */
  1397. #undef CONFIG_USB_PORT_POWER_SMART_SIMPLE
  1398. /*
  1399. * Smart USB power control current limit pins may be inverted. In this case
  1400. * they are active low and the GPIO names will be GPIO_USBn_ILIM_SEL_L.
  1401. */
  1402. #undef CONFIG_USB_PORT_POWER_SMART_INVERTED
  1403. /******************************************************************************/
  1404. /* USB port switch */
  1405. /* 8-bit USB type-C switch I2C addresses */
  1406. #undef CONFIG_USB_SWITCH_I2C_ADDRS
  1407. /* Support the TSU6721 I2C smart switch */
  1408. #undef CONFIG_USB_SWITCH_TSU6721
  1409. /* Support the Pericom PI3USB9281 I2C USB switch */
  1410. #undef CONFIG_USB_SWITCH_PI3USB9281
  1411. /* Number of Pericom PI3USB9281 chips present in system */
  1412. #undef CONFIG_USB_SWITCH_PI3USB9281_CHIP_COUNT
  1413. /* Support the Pericom PI3USB30532 USB3.0/DP1.2 Matrix Switch */
  1414. #undef CONFIG_USB_MUX_PI3USB30532
  1415. /* Support the Parade PS8740 Type-C Redriving Switch */
  1416. #undef CONFIG_USB_MUX_PS8740
  1417. /*****************************************************************************/
  1418. /* USB GPIO config */
  1419. #undef CONFIG_USB_GPIO
  1420. /*****************************************************************************/
  1421. /* USB SPI config */
  1422. #undef CONFIG_USB_SPI
  1423. /*****************************************************************************/
  1424. /* Support computing hash of code for verified boot */
  1425. #undef CONFIG_VBOOT_HASH
  1426. /*****************************************************************************/
  1427. /* Watchdog config */
  1428. /*
  1429. * Compile watchdog timer support. The watchdog timer will reboot the system
  1430. * if the hook task (which is the lowest-priority task on the system) gets
  1431. * starved for CPU time and isn't able to fire its HOOK_TICK event.
  1432. */
  1433. #define CONFIG_WATCHDOG
  1434. /*
  1435. * Try to detect a watchdog that is about to fire, and print a trace. This is
  1436. * required on chips such as STM32 where the watchdog timer simply reboots the
  1437. * system without any early warning.
  1438. */
  1439. #undef CONFIG_WATCHDOG_HELP
  1440. /* Watchdog period in ms; see also AUX_TIMER_PERIOD_MS */
  1441. #define CONFIG_WATCHDOG_PERIOD_MS 1600
  1442. /*
  1443. * Fire auxiliary timer 500ms before watchdog timer expires. This leaves
  1444. * some time for debug trace to be printed.
  1445. */
  1446. #define CONFIG_AUX_TIMER_PERIOD_MS (CONFIG_WATCHDOG_PERIOD_MS - 500)
  1447. /*****************************************************************************/
  1448. /*
  1449. * Support controlling power to WiFi, WWAN (3G/LTE), and/or bluetooth modules.
  1450. */
  1451. #undef CONFIG_WIRELESS
  1452. /*
  1453. * Support for WiFi devices that must remain powered in suspend. Set to the
  1454. * combination of EC_WIRELESS_SWITCH flags (from ec_commands.h) which should
  1455. * be set in suspend.
  1456. */
  1457. #undef CONFIG_WIRELESS_SUSPEND
  1458. /*
  1459. * Write protect signal is active-high. If this is defined, there must be a
  1460. * GPIO named GPIO_WP; if not defined, there must be a GPIO names GPIO_WP_L.
  1461. */
  1462. #undef CONFIG_WP_ACTIVE_HIGH
  1463. /*
  1464. * The write protect signal is always asserted,
  1465. * independantly of the GPIO existence or current value.
  1466. */
  1467. #undef CONFIG_WP_ALWAYS
  1468. /*
  1469. * If needed to allocate some free space in the base of the RO section of the
  1470. * image, define this to be equal the required size of the free space.
  1471. */
  1472. #undef CONFIG_RO_HEAD_ROOM
  1473. /*****************************************************************************/
  1474. /*
  1475. * Include board and core configs, since those hold the CONFIG_ constants for a
  1476. * given configuration. This guarantees they get included everywhere, and
  1477. * fixes a fairly common bug where we gate out code with #ifndef
  1478. * CONFIG_SOMETHING and but forget to include both of these.
  1479. *
  1480. * Board is included after chip, so that chip defaults can be overridden on a
  1481. * per-board basis as needed.
  1482. */
  1483. #ifdef __CROS_EC_CONFIG_CHIP_H
  1484. #error Include config.h instead of config_chip.h!
  1485. #endif
  1486. #ifdef __BOARD_H
  1487. #error Include config.h instead of board.h!
  1488. #endif
  1489. #include "config_chip.h"
  1490. #include "board.h"
  1491. /*****************************************************************************/
  1492. /*
  1493. * Handle task-dependent configs.
  1494. *
  1495. * This prevent sub-modules from being compiled when the task and parent module
  1496. * are not present.
  1497. */
  1498. #ifndef HAS_TASK_CHIPSET
  1499. #undef CONFIG_CHIPSET_BAYTRAIL
  1500. #undef CONFIG_CHIPSET_BRASWELL
  1501. #undef CONFIG_CHIPSET_GAIA
  1502. #undef CONFIG_CHIPSET_HASWELL
  1503. #undef CONFIG_CHIPSET_MEDIATEK
  1504. #undef CONFIG_CHIPSET_ROCKCHIP
  1505. #undef CONFIG_CHIPSET_SKYLAKE
  1506. #undef CONFIG_CHIPSET_TEGRA
  1507. #undef CONFIG_POWER_COMMON
  1508. #endif
  1509. #ifndef HAS_TASK_KEYPROTO
  1510. #undef CONFIG_KEYBOARD_PROTOCOL_8042
  1511. /*
  1512. * Note that we don't undef CONFIG_KEYBOARD_PROTOCOL_MKBP, because it doesn't
  1513. * have its own task.
  1514. */
  1515. #endif
  1516. #ifndef HAS_TASK_KEYSCAN
  1517. #undef CONFIG_KEYBOARD_PROTOCOL_8042
  1518. #undef CONFIG_KEYBOARD_PROTOCOL_MKBP
  1519. #endif
  1520. /*****************************************************************************/
  1521. /*
  1522. * Apply test config overrides last, since tests need to override some of the
  1523. * config flags in non-standard ways to mock only parts of the system.
  1524. */
  1525. #include "test_config.h"
  1526. /*
  1527. * Sanity checks to make sure some of the configs above make sense.
  1528. */
  1529. #if (CONFIG_AUX_TIMER_PERIOD_MS) < ((HOOK_TICK_INTERVAL_MS) * 2)
  1530. #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS"
  1531. #endif
  1532. #endif /* __CROS_EC_CONFIG_H */