slippy: Add second NVRAM bank and define some fields
We don't use a lot of CMOS but it is useful for me
to have quick access to some of the debug data that
is stored in there.
BUG=chrome-os-partner:19980
BRANCH=none
TEST=manual: tested on falco
> mosys nvram dump
LPSS0 CMOS Bank 0 (128 bytes)
00000000 31 27 04 23 23 22 90 11 06 13 26 02 50 80 00 00 |1'.##"....&.P...|
00000010 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00000020 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00000030 00 00 00 00 70 00 00 00 00 00 00 00 00 00 00 00 |....p...........|
00000040 00 00 00 20 00 00 00 00 00 00 00 00 00 00 00 00 |... ............|
00000050 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00000060 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
00000070 80 f8 fd 00 00 00 00 00 00 00 00 00 00 00 00 00 |................|
LPSS1 CMOS Bank 1 (128 bytes)
00000000 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000010 42 43 05 00 00 00 b8 bc ff ff ff ff ff ff ff ff |BC..............|
00000020 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000030 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000040 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000050 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000060 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
00000070 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
> mosys nvram list
LPSS0 | Post Code Bank | 0x80
LPSS0 | Post Code Bank 0 | 0xf8
LPSS0 | Post Code Bank 1 | 0xfd
LPSS0 | Post Extra Bank 0 | 0x0
LPSS0 | Post Extra Bank 1 | 0x0
LPSS1 | Boot Count | 0x5
Change-Id: I852c82ccda743c2e219a6c28b9a529be459c77e8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58253
Reviewed-by: David Hendricks <dhendrix@chromium.org>
diff --git a/platform/experimental/slippy/nvram.c b/platform/experimental/slippy/nvram.c
index add7b35..a529fc2 100644
--- a/platform/experimental/slippy/nvram.c
+++ b/platform/experimental/slippy/nvram.c
@@ -48,20 +48,41 @@
CMOS_DEVICE_PCH,
};
+struct cmos_var_map {
+ uint8_t offset;
+ uint8_t length;
+ char *desc;
+};
+
struct cmos_map {
enum cmos_device type;
const char *device;
int bank;
int length;
int clear_start; /* first bytes are usually reserved for RTC */
- struct valstr *var_list;
+ struct cmos_var_map *var_list;
+};
+
+static struct cmos_var_map coreboot_cmos_bank0_vars[] = {
+ { 0x70, 1, "Post Code Bank" },
+ { 0x71, 1, "Post Code Bank 0" },
+ { 0x72, 1, "Post Code Bank 1" },
+ { 0x73, 4, "Post Extra Bank 0" },
+ { 0x77, 4, "Post Extra Bank 1" },
+ { 0 }
+};
+
+static struct cmos_var_map coreboot_cmos_bank1_vars[] = {
+ { 0x12, 4, "Boot Count" }, /* 0x92 */
+ { 0 }
};
struct cmos_map slippy_cmos_map[] = {
- { CMOS_DEVICE_PCH, "LPSS", 0, 128, 0x29, NULL },
+ { CMOS_DEVICE_PCH, "LPSS0", 0, 128, 0x29, coreboot_cmos_bank0_vars },
+ { CMOS_DEVICE_PCH, "LPSS1", 1, 128, 0x00, coreboot_cmos_bank1_vars },
};
-static const uint16_t slippy_cmos_port[] = { 0x70 };
+static const uint16_t slippy_cmos_port[] = { 0x70, 0x72 };
static uint8_t slippy_read_cmos(struct platform_intf *intf,
int addr, int reg)
@@ -79,6 +100,47 @@
io_write8(intf, slippy_cmos_port[addr] + 1, val);
}
+static int slippy_nvram_list_bank(struct platform_intf *intf,
+ struct cmos_map *map)
+{
+ struct cmos_var_map *var;
+ int i;
+
+ /* handle each cmos bank */
+ for (var = map->var_list; var && var->desc; var++) {
+ struct kv_pair *kv = kv_pair_new();
+ uint32_t val = 0;
+
+ switch (map->type) {
+ case CMOS_DEVICE_PCH:
+ for (i = 0; i < var->length; i++)
+ val |= slippy_read_cmos(
+ intf, map->bank,
+ var->offset + i) << (i*8);
+ break;
+ }
+
+ kv_pair_add(kv, "device", map->device);
+ kv_pair_add(kv, "name", var->desc);
+ kv_pair_fmt(kv, "value", "0x%x", val);
+ kv_pair_print(kv);
+ kv_pair_free(kv);
+ }
+
+ return 0;
+}
+
+static int slippy_nvram_list(struct platform_intf *intf)
+{
+ int dev, rc = 0;
+
+ /* handle each cmos bank */
+ for (dev = 0; dev < ARRAY_SIZE(slippy_cmos_map); dev++)
+ rc |= slippy_nvram_list_bank(intf, &slippy_cmos_map[dev]);
+
+ return rc;
+}
+
static int slippy_nvram_dump(struct platform_intf *intf)
{
struct cmos_map *map;
@@ -86,10 +148,7 @@
uint8_t cmos_data[128];
/* handle each cmos bank */
- for (dev = 0;
- dev < sizeof(slippy_cmos_map) /
- sizeof(slippy_cmos_map[0]);
- dev++) {
+ for (dev = 0; dev < ARRAY_SIZE(slippy_cmos_map); dev++) {
map = &slippy_cmos_map[dev];
if (map->length > sizeof(cmos_data))
@@ -137,6 +196,7 @@
}
struct nvram_cb slippy_nvram_cb = {
+ .list = slippy_nvram_list,
.dump = slippy_nvram_dump,
.clear = slippy_nvram_clear,
};