nonspd: Get memory type from SMBIOS table
For the non-SPD memories, this change reads the memory type from
SMBIOS table for any memory part that does not match the list of
memories that mosys knows about. The memory type needs to be
translated from SMBIOS type to SPD type for rest of the functions to
work properly.
With this change, it is no longer necessary to add support for every
non-SPD memory type in mosys. We do lose some information
e.g. Manufacturer id/name, device width, ranks and list of different
speeds supported by the memory part. But none of these are interesting
from any uses cases / tests that we have.
If a memory has table in mosys, the output of "mosys memory spd print
all" looks something like:
0 | LPDDR4
1 | LPDDR4
2 | LPDDR4
3 | LPDDR4
0 | 1-44: Micron Technology | 00000000 | MT53B256M32D1NP
1 | 1-44: Micron Technology | 00000000 | MT53B256M32D1NP
2 | 1-44: Micron Technology | 00000000 | MT53B256M32D1NP
3 | 1-44: Micron Technology | 00000000 | MT53B256M32D1NP
0 | 1024 | 1 | 32
1 | 1024 | 1 | 32
2 | 1024 | 1 | 32
3 | 1024 | 1 | 32
0 | LPDDR4-1333, LPDDR4-1600, LPDDR4-1866, LPDDR4-2133, LPDDR4-2400
1 | LPDDR4-1333, LPDDR4-1600, LPDDR4-1866, LPDDR4-2133, LPDDR4-2400
2 | LPDDR4-1333, LPDDR4-1600, LPDDR4-1866, LPDDR4-2133, LPDDR4-2400
3 | LPDDR4-1333, LPDDR4-1600, LPDDR4-1866, LPDDR4-2133, LPDDR4-2400
Without the entry in mosys, following is the output based on
information in SMBIOS:
0 | LPDDR4
1 | LPDDR4
2 | LPDDR4
3 | LPDDR4
0 | 1-0 | 00000000 | MT53B256M32D1NP
1 | 1-0 | 00000000 | MT53B256M32D1NP
2 | 1-0 | 00000000 | MT53B256M32D1NP
3 | 1-0 | 00000000 | MT53B256M32D1NP
0 | 1024 | 0 | 0
1 | 1024 | 0 | 0
2 | 1024 | 0 | 0
3 | 1024 | 0 | 0
0 | LPDDR4-2400
1 | LPDDR4-2400
2 | LPDDR4-2400
3 | LPDDR4-2400
BUG=b:117711313,b:120183640
BRANCH=None
TEST=Verified that memory type gets reported correctly. Also, verified
that platform_MemCheck is successful.
Change-Id: I352904263fae1e24bbf53d7fdec5e966e36095df
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1356300
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
diff --git a/include/lib/smbios_tables.h b/include/lib/smbios_tables.h
index a692db4..bafad84 100644
--- a/include/lib/smbios_tables.h
+++ b/include/lib/smbios_tables.h
@@ -272,6 +272,7 @@
SMBIOS_MEMORY_TYPE_DDR2_FBDIMM = 0x14,
SMBIOS_MEMORY_TYPE_DDR3 = 0x18,
SMBIOS_MEMORY_TYPE_DDR4 = 0x1A,
+ SMBIOS_MEMORY_TYPE_LPDDR4 = 0x1E,
};
/* memory device type details (bitmask) */
diff --git a/lib/spd/nonspd_modules.c b/lib/spd/nonspd_modules.c
index 6897452..ccfa2f9 100644
--- a/lib/spd/nonspd_modules.c
+++ b/lib/spd/nonspd_modules.c
@@ -831,6 +831,28 @@
return -1;
}
+enum spd_dram_type map_smbios_mem_type_to_spd(struct smbios_table *table)
+{
+ switch (table->data.mem_device.type) {
+ case SMBIOS_MEMORY_TYPE_DDR:
+ return SPD_DRAM_TYPE_DDR;
+ case SMBIOS_MEMORY_TYPE_DDR2:
+ return SPD_DRAM_TYPE_DDR2;
+ case SMBIOS_MEMORY_TYPE_DDR2_FBDIMM:
+ return SPD_DRAM_TYPE_FBDIMM;
+ case SMBIOS_MEMORY_TYPE_DDR3:
+ return SPD_DRAM_TYPE_DDR3;
+ case SMBIOS_MEMORY_TYPE_DDR4:
+ return SPD_DRAM_TYPE_DDR4;
+ case SMBIOS_MEMORY_TYPE_LPDDR4:
+ return SPD_DRAM_TYPE_LPDDR4;
+ default:
+ lprintf(LOG_ERR, "%s: Unknown SMBIOS memory type: %d\n",
+ __func__, table->data.mem_device.type);
+ return 0;
+ }
+}
+
static int extract_mem_info_from_smbios(
struct smbios_table *table,
struct nonspd_mem_info *info)
@@ -857,6 +879,9 @@
(table->data.mem_device.size & 0x8000 ? size * 1024 : size);
strncpy((char *)info->part_num, smbios_part_num, max_part_num_len);
+
+ info->dram_type = map_smbios_mem_type_to_spd(table);
+
return transfer_speed_from_smbios_to_nonspd_mem_info(table, info);
}
