slippy: Add second NVRAM bank and define some fields

We don't use a lot of CMOS but it is useful for me
to have quick access to some of the debug data that
is stored in there.

BUG=chrome-os-partner:19980
BRANCH=none
TEST=manual: tested on falco

> mosys nvram dump
LPSS0 CMOS Bank 0 (128 bytes)
00000000  31 27 04 23 23 22 90 11  06 13 26 02 50 80 00 00  |1'.##"....&.P...|
00000010  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000020  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 70 00 00 00  00 00 00 00 00 00 00 00  |....p...........|
00000040  00 00 00 20 00 00 00 00  00 00 00 00 00 00 00 00  |... ............|
00000050  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000060  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000070  80 f8 fd 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|

LPSS1 CMOS Bank 1 (128 bytes)
00000000  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
00000010  42 43 05 00 00 00 b8 bc  ff ff ff ff ff ff ff ff  |BC..............|
00000020  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
00000030  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
00000040  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
00000050  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
00000060  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|
00000070  ff ff ff ff ff ff ff ff  ff ff ff ff ff ff ff ff  |................|

> mosys nvram list
LPSS0 | Post Code Bank | 0x80
LPSS0 | Post Code Bank 0 | 0xf8
LPSS0 | Post Code Bank 1 | 0xfd
LPSS0 | Post Extra Bank 0 | 0x0
LPSS0 | Post Extra Bank 1 | 0x0
LPSS1 | Boot Count | 0x5

Change-Id: I852c82ccda743c2e219a6c28b9a529be459c77e8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58253
Reviewed-by: David Hendricks <dhendrix@chromium.org>
1 file changed