imports: Make imports/ follow Chromium flashrom
This commit makes ap_wpsr follow the Chromium flashrom instead of
following the upstream flashrom database. This addresses inconsistencies
between the ap_wpsr and flashrom databases, which have led to issues
like the one described in b/340421736 in nissa factory branch.
This change simplifies development and reduces the risk of introducing
regressions when updating the flashrom databases, especially for factory
branches.
This change is intended to affect the main branch only, there will be
further changes related to modify the ap_wpsr imports/ in other factory
branches.
Imported from flashrom snapshot: b243d7fffc9885d18072f3e27ec2ebbd662101ba
BUG=b:362686439
TEST=change to ToT, diff the ap_wpsr and flashrom databases.
Cq-Depend: chromium:5808523
Cq-Depend: chromium:6017465
Cq-Depend: chromium:6017466
Cq-Depend: chromium:6005886
Cq-Depend: chromium:6011519
Cq-Depend: chromium:6022541
Change-Id: I888b4e21a900175be41f191c6c8f6dbe8399702e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/ap_wpsr/+/6096941
Tested-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-by: Jian-Jia Su <jjsu@chromium.org>
Commit-Queue: Hsuan Ting Chen <roccochen@chromium.org>
diff --git a/imports/flashchips.c b/imports/flashchips.c
index e6b4761..0e83200 100644
--- a/imports/flashchips.c
+++ b/imports/flashchips.c
@@ -6186,6 +6186,50 @@
{
.vendor = "Fudan",
+ .name = "FM25Q04",
+ .bustype = BUS_SPI,
+ .manufacture_id = FUDAN_ID_NOPREFIX,
+ .model_id = FUDAN_FM25Q04,
+ .total_size = 512,
+ .page_size = 256,
+ /* supports SFDP */
+ /* QPI enable 0x38, disable 0xFF */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+ .tested = TEST_UNTESTED,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
+ /* 128 * 4KB sectors */
+ .eraseblocks = { {4 * 1024, 128} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ /* 16 * 32KB blocks */
+ .eraseblocks = { {32 * 1024, 16} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ /* 8 * 64KB blocks */
+ .eraseblocks = { {64 * 1024, 8} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ /* Full chip erase (0x60) */
+ .eraseblocks = { {512 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ /* Full chip erase (0xC7) */
+ .eraseblocks = { {512 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ },
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Fudan",
.name = "FM25Q08",
.bustype = BUS_SPI,
.manufacture_id = FUDAN_ID_NOPREFIX,
@@ -6196,7 +6240,7 @@
/* OTP: 1024B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
/* QPI enable 0x38, disable 0xFF */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
- .tested = TEST_UNTESTED,
+ .tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers = {
@@ -6305,6 +6349,94 @@
},
{
+ .vendor = "Fudan",
+ .name = "FM25Q64",
+ .bustype = BUS_SPI,
+ .manufacture_id = FUDAN_ID_NOPREFIX,
+ .model_id = FUDAN_FM25Q64,
+ .total_size = 8192,
+ .page_size = 256,
+ /* supports SFDP */
+ /* QPI enable 0x38, disable 0xFF */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+ .tested = TEST_UNTESTED,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
+ /* 2048 * 4KB sectors */
+ .eraseblocks = { {4 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ /* 256 * 32KB blocks */
+ .eraseblocks = { {32 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ /* 128 * 64KB blocks */
+ .eraseblocks = { {64 * 1024, 128} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ /* Full chip erase (0x60) */
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ /* Full chip erase (0xC7) */
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ },
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, /* bit6 selects size of protected blocks; TODO: SR2 */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
+ .vendor = "Fudan",
+ .name = "FM25Q128",
+ .bustype = BUS_SPI,
+ .manufacture_id = FUDAN_ID_NOPREFIX,
+ .model_id = FUDAN_FM25Q128,
+ .total_size = 16384,
+ .page_size = 256,
+ /* supports SFDP */
+ /* QPI enable 0x38, disable 0xFF */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+ .tested = TEST_OK_PR,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers = {
+ {
+ /* 4096 * 4KB sectors */
+ .eraseblocks = { {4 * 1024, 4096} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ /* 512 * 32KB blocks */
+ .eraseblocks = { {32 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ /* 256 * 64KB blocks */
+ .eraseblocks = { {64 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ /* Full chip erase (0x60) */
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ /* Full chip erase (0xC7) */
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ },
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP2_TB_BPL, /* bit6 selects size of protected blocks; TODO: SR2 */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP2_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ },
+
+ {
.vendor = "Fujitsu",
.name = "MBM29F004BC",
.bustype = BUS_PARALLEL,
@@ -6644,6 +6776,62 @@
{
.vendor = "GigaDevice",
+ .name = "GD25LF512MF",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25LF512MF,
+ .total_size = 65536,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR_EXT2 | FEATURE_4BA,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_5C,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {1695, 1950},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
+ .srl = {STATUS2, 0, RW},
+ .cmp = {STATUS2, 6, RW},
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
+ .vendor = "GigaDevice",
.name = "GD25LQ128E/GD25LB128E/GD25LR128E/GD25LQ128D/GD25LQ128C",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
@@ -7217,7 +7405,7 @@
{
.vendor = "GigaDevice",
- .name = "GD25Q127C/GD25Q128E",
+ .name = "GD25Q128E/GD25B128E/GD25R128E/GD25Q127C",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25Q128,
@@ -7395,14 +7583,13 @@
{
.vendor = "GigaDevice",
- .name = "GD25Q256D/GD25Q256E",
+ .name = "GD25Q256E/GD25B256E/GD25R256E/GD25Q256D",
.bustype = BUS_SPI,
.manufacture_id = GIGADEVICE_ID,
.model_id = GIGADEVICE_GD25Q256D,
.total_size = 32768,
.page_size = 256,
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA |
- FEATURE_WRSR_EXT2 | FEATURE_WRSR2 | FEATURE_WRSR3,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2 | FEATURE_WRSR3,
.tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
@@ -7434,8 +7621,8 @@
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
- .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
- .unlock = SPI_DISABLE_BLOCKPROTECT,
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ,
.voltage = {2700, 3600},
@@ -7444,7 +7631,63 @@
.srp = {STATUS1, 7, RW},
.srl = {STATUS2, 6, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
- .tb = {STATUS1, 6, RW},
+ .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+{
+ .vendor = "GigaDevice",
+ .name = "GD25B512MF/GD25R512MF",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25B512MF,
+ .total_size = 65536,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3 | FEATURE_4BA,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_5C,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 6, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
+ .cmp = {STATUS3, 3, RW},
},
.decode_range = DECODE_RANGE_SPI25,
},
@@ -7896,6 +8139,153 @@
.voltage = {2300, 3600},
},
+{
+ .vendor = "GigaDevice",
+ .name = "GD25F64F",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25F64F,
+ .total_size = 8192,
+ .page_size = 256,
+ /* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 128} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {8 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW}, /* Called BP3 in datasheet, acts like TB */
+ .sec = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like SEC */
+ .cmp = {STATUS3, 4, RW},
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+{
+ .vendor = "GigaDevice",
+ .name = "GD25F128F",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25F128F,
+ .total_size = 16384,
+ .page_size = 256,
+ /* OTP: 3x2048B; read 0x48; write 0x42, erase 0x44 */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 4096} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 256} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {16 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
+ {
+ .vendor = "GigaDevice",
+ .name = "GD25F256F",
+ .bustype = BUS_SPI,
+ .manufacture_id = GIGADEVICE_ID,
+ .model_id = GIGADEVICE_GD25F256F,
+ .total_size = 32768,
+ .page_size = 256,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2 | FEATURE_WRSR3 | FEATURE_4BA,
+ .tested = TEST_OK_PREWB,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 8192} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_5C,
+ }, {
+ .eraseblocks = { {32 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { {64 * 1024, 512} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {32 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT_BP4_SRWD,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {2700, 3600},
+ .reg_bits =
+ {
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW}, /* Called BP4 in datasheet, acts like TB */
+ },
+ .decode_range = DECODE_RANGE_SPI25,
+ },
+
{
.vendor = "GigaDevice",
.name = "GD25WQ80E",
@@ -18775,7 +19165,7 @@
/* 4 x 256B Security Region (OTP) */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_WRSR_EXT3 | FEATURE_OTP |
FEATURE_4BA_ENTER | FEATURE_4BA_NATIVE,
- .tested = TEST_UNTESTED,
+ .tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
@@ -19984,6 +20374,52 @@
{
.vendor = "Winbond",
+ .name = "W25R512NW/W74M51NW",
+ .bustype = BUS_SPI,
+ .manufacture_id = WINBOND_NEX_ID,
+ .model_id = WINBOND_NEX_W25R512NW,
+ .total_size = 65536,
+ .page_size = 256,
+ /* supports SFDP */
+ /* OTP: 3X256B; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
+ .tested = TEST_OK_PREW,
+ .probe = PROBE_SPI_RDID,
+ .probe_timing = TIMING_ZERO,
+ .block_erasers =
+ {
+ {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_21,
+ }, {
+ .eraseblocks = { {4 * 1024, 16384} },
+ .block_erase = SPI_BLOCK_ERASE_20,
+ }, {
+ .eraseblocks = { {32 * 1024, 2048} },
+ .block_erase = SPI_BLOCK_ERASE_52,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_DC,
+ }, {
+ .eraseblocks = { {64 * 1024, 1024} },
+ .block_erase = SPI_BLOCK_ERASE_D8,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_60,
+ }, {
+ .eraseblocks = { {64 * 1024 * 1024, 1} },
+ .block_erase = SPI_BLOCK_ERASE_C7,
+ }
+ },
+ .printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD,
+ .unlock = SPI_DISABLE_BLOCKPROTECT,
+ .write = SPI_CHIP_WRITE256,
+ .read = SPI_CHIP_READ,
+ .voltage = {1700, 1950},
+ },
+
+ {
+ .vendor = "Winbond",
.name = "W25Q256JW_DTR",
.bustype = BUS_SPI,
.manufacture_id = WINBOND_NEX_ID,
@@ -22443,14 +22879,14 @@
{
.vendor = "XMC",
- .name = "XM25QU64C",
+ .name = "XM25QU64C/XM25LU64C",
.bustype = BUS_SPI,
.manufacture_id = ST_ID,
.model_id = XMC_XM25QU64C,
.total_size = 8192,
.page_size = 256,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
- .tested = TEST_UNTESTED,
+ .tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
@@ -23086,7 +23522,7 @@
/* We present our own "report this" text hence we do not */
/* want the default "This flash part has status UNTESTED..." */
/* text to be printed. */
- .tested = TEST_OK_PREW,
+ .tested = { .probe = OK, .read = OK, .erase = OK, .write = OK, .wp = NA },
.probe = PROBE_SPI_SFDP,
.block_erasers = {}, /* set by probing function */
.unlock = SPI_DISABLE_BLOCKPROTECT, /* is this safe? */
diff --git a/imports/include/flash.h b/imports/include/flash.h
index aa89409..aa29da6 100644
--- a/imports/include/flash.h
+++ b/imports/include/flash.h
@@ -148,6 +148,14 @@
* other flash chips, such as the ENE KB9012 internal flash, work the opposite way.
*/
#define FEATURE_ERASED_ZERO (1 << 18)
+/*
+ * Feature indicates that the chip does not require erase before writing:
+ * write operations can set any bit to any value without first doing an erase,
+ * but bulk erase operations may still be supported.
+ *
+ * EEPROMs usually behave this way (compare to Flash, which requires erase),
+ * for example the ST M95M02.
+ */
#define FEATURE_NO_ERASE (1 << 19)
#define FEATURE_WRSR_EXT2 (1 << 20)
@@ -266,16 +274,10 @@
WRITE_82802AB,
WRITE_EN29LV640B,
EDI_CHIP_WRITE,
-#ifdef FLASHROM_TEST
TEST_WRITE_INJECTOR, /* special case must come last. */
-#endif
};
typedef int (write_func_t)(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
-#ifdef FLASHROM_TEST
-extern write_func_t *g_test_write_injector;
-#endif
-
enum read_func {
NO_READ_FUNC = 0, /* 0 indicates no read function set. */
SPI_CHIP_READ = 1,
@@ -284,17 +286,11 @@
EDI_CHIP_READ,
SPI_READ_AT45DB,
SPI_READ_AT45DB_E8,
-#ifdef FLASHROM_TEST
TEST_READ_INJECTOR, /* special case must come last. */
-#endif
};
typedef int (read_func_t)(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
int read_flash(struct flashctx *flash, uint8_t *buf, unsigned int start, unsigned int len);
-#ifdef FLASHROM_TEST
-extern read_func_t *g_test_read_injector;
-#endif
-
enum block_erase_func {
NO_BLOCK_ERASE_FUNC = 0, /* 0 indicates no block erase function set. */
SPI_BLOCK_ERASE_EMULATION = 1,
@@ -331,21 +327,10 @@
ERASE_SECTOR_49LFXXXC,
STM50_SECTOR_ERASE,
EDI_CHIP_BLOCK_ERASE,
-#ifdef FLASHROM_TEST
- /* special cases must come last. */
- TEST_ERASE_INJECTOR_1,
- TEST_ERASE_INJECTOR_2,
- TEST_ERASE_INJECTOR_3,
- TEST_ERASE_INJECTOR_4,
- TEST_ERASE_INJECTOR_5,
-#endif
+ CROS_EC_BLOCK_ERASE,
+ TEST_ERASE_INJECTOR, /* special case must come last. */
};
-#ifdef FLASHROM_TEST
-#define NUM_TEST_ERASE_INJECTORS 5
-extern erasefunc_t *g_test_erase_injector[NUM_TEST_ERASE_INJECTORS];
-#endif
-
enum blockprotect_func {
NO_BLOCKPROTECT_FUNC = 0, /* 0 indicates no unlock function set. */
SPI_DISABLE_BLOCKPROTECT,
@@ -629,6 +614,9 @@
size_t strnlen(const char *str, size_t n);
#endif
+/* flashchips_crosbl.c */
+bool is_chipname_duplicate(const struct flashchip *chip);
+
/* flashrom.c */
extern const char flashrom_version[];
char *flashbuses_to_text(enum chipbustype bustype);
@@ -657,6 +645,8 @@
unsigned int get_next_write(const uint8_t *have, const uint8_t *want, unsigned int len, unsigned int *first_start, enum write_granularity gran);
int write_flash(struct flashctx *flash, const uint8_t *buf, unsigned int start, unsigned int len);
+erasefunc_t *lookup_erase_func_ptr(const struct block_eraser *const eraser);
+
/* Something happened that shouldn't happen, but we can go on. */
#define ERROR_FLASHROM_NONFATAL 0x100
diff --git a/imports/include/flashchips.h b/imports/include/flashchips.h
index d5c0027..0fea690 100644
--- a/imports/include/flashchips.h
+++ b/imports/include/flashchips.h
@@ -344,9 +344,12 @@
#define FUDAN_FM25F01 0x3111
#define FUDAN_FM25F02 0x3112 /* Same as FM25F02A */
#define FUDAN_FM25F04 0x3113 /* Same as FM25F04A */
+#define FUDAN_FM25Q04 0x4013
#define FUDAN_FM25Q08 0x4014
#define FUDAN_FM25Q16 0x4015
#define FUDAN_FM25Q32 0x4016
+#define FUDAN_FM25Q64 0x4017
+#define FUDAN_FM25Q128 0x4018
#define FUJITSU_ID 0x04 /* Fujitsu */
#define FUJITSU_MBM29DL400BC 0x0F
@@ -391,12 +394,16 @@
#define GIGADEVICE_GD25Q16 0x4015 /* Same as GD25Q16B (which has OTP) */
#define GIGADEVICE_GD25Q32 0x4016 /* Same as GD25Q32B */
#define GIGADEVICE_GD25Q64 0x4017 /* Same as GD25Q64B */
-#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C, and GD25Q128E, can be distinguished by SFDP */
-#define GIGADEVICE_GD25Q256D 0x4019
+#define GIGADEVICE_GD25Q128 0x4018 /* Same as GD25Q128B, GD25Q127C, GD25Q128C,and GD25Q128E, GD25B128E, GD25R128E can be distinguished by SFDP */
+#define GIGADEVICE_GD25Q256D 0x4019 /* Same as GD25B256E, GD25Q256E, GD25R256E */
+#define GIGADEVICE_GD25B512MF 0x401A /* Same as GD25R512MF */
#define GIGADEVICE_GD25VQ21B 0x4212
#define GIGADEVICE_GD25VQ41B 0x4213 /* Same as GD25VQ40C, can be distinguished by SFDP */
#define GIGADEVICE_GD25VQ80C 0x4214
#define GIGADEVICE_GD25VQ16C 0x4215
+#define GIGADEVICE_GD25F64F 0x4317
+#define GIGADEVICE_GD25F128F 0x4318
+#define GIGADEVICE_GD25F256F 0x4319
#define GIGADEVICE_GD25LQ40 0x6013
#define GIGADEVICE_GD25LQ80 0x6014
#define GIGADEVICE_GD25LQ16 0x6015
@@ -407,6 +414,7 @@
#define GIGADEVICE_GD25LB512MF 0x601A /* Same as GD25LR512MF */
#define GIGADEVICE_GD25LF128E 0x6318
#define GIGADEVICE_GD25LF256F 0x6319
+#define GIGADEVICE_GD25LF512MF 0x631A
#define GIGADEVICE_GD25LR256E 0x6719
#define GIGADEVICE_GD25LR512ME 0x671A /* Same as GD25LB512ME */
#define GIGADEVICE_GD25WQ80E 0x6514
@@ -849,7 +857,7 @@
#define ST_M45PE80 0x4014 /* Same as XM25QH80B */
#define ST_M45PE16 0x4015
#define XMC_XM25QH64C 0x4017 /* Same as XM25QH64D */
-#define XMC_XM25QU64C 0x4117
+#define XMC_XM25QU64C 0x4117 /* Same as XM25LU64C */
#define XMC_XM25QU80B 0x5014
#define XMC_XM25QH16C 0x4015 /* Same as XM25QH16D */
#define XMC_XM25QU16C 0x5015
@@ -1019,6 +1027,7 @@
#define WINBOND_NEX_W25Q64_W 0x6017 /* W25Q64DW; W25Q64FV in QPI mode */
#define WINBOND_NEX_W25Q128_W 0x6018 /* W25Q128FW; W25Q128FV in QPI mode */
#define WINBOND_NEX_W25Q256_W 0x6019 /* W25Q256JW */
+#define WINBOND_NEX_W25R512NW 0x6020 /* W25R512NW/W74M51NW */
#define WINBOND_NEX_W25Q16JV_M 0x7015 /* W25Q16JV_M (QE=0) */
#define WINBOND_NEX_W25Q32JV_M 0x7016 /* W25Q32JV_M (QE=0) */
#define WINBOND_NEX_W25Q64JV 0x7017 /* W25Q64JV */
diff --git a/imports/include/libflashrom.h b/imports/include/libflashrom.h
index e87776b..2c664ff 100644
--- a/imports/include/libflashrom.h
+++ b/imports/include/libflashrom.h
@@ -115,6 +115,8 @@
struct flashrom_flashchip_info {
const char *vendor;
const char *name;
+ uint32_t manufacture_id;
+ uint32_t model_id;
unsigned int total_size;
struct flashrom_tested {
enum flashrom_test_state probe;
@@ -230,6 +232,13 @@
*/
size_t flashrom_flash_getsize(const struct flashrom_flashctx *flashctx);
/**
+ * @brief Returns the info of the specified flash chip within the flashctx.
+ *
+ * @param flashctx The queried flash context.
+ * @param[out] A reference of flashchip_info structure is provided to be filled.
+ */
+void flashrom_flash_getinfo(const struct flashrom_flashctx *const flashctx, struct flashrom_flashchip_info *info);
+/**
* @brief Erase the specified ROM chip.
*
* If a layout is set in the given flash context, only included regions
diff --git a/imports/include/programmer.h b/imports/include/programmer.h
index a90624b..bedf0e2 100644
--- a/imports/include/programmer.h
+++ b/imports/include/programmer.h
@@ -25,6 +25,13 @@
#include "flash.h" /* for chipaddr and flashctx */
+
+/*
+ * This function returns 'true' if current flashrom invocation is programming
+ * the EC.
+ */
+bool programming_ec(void);
+
enum programmer_type {
PCI = 1, /* to detect uninitialized values */
USB,
@@ -101,6 +108,8 @@
extern const struct programmer_entry programmer_usbblaster_spi;
extern const struct programmer_entry programmer_dirtyjtag_spi;
+extern const struct programmer_entry programmer_cros_ec;
+
int programmer_init(const struct programmer_entry *prog, const char *param);
int programmer_shutdown(void);
@@ -274,6 +283,7 @@
void probe_superio(void);
int register_superio(struct superio s);
extern enum chipbustype internal_buses_supported;
+int internal_init(const struct programmer_cfg *cfg);
#endif
/* bitbang_spi.c */
@@ -357,6 +367,7 @@
CHIPSET_400_SERIES_COMET_POINT,
CHIPSET_500_SERIES_TIGER_POINT,
CHIPSET_600_SERIES_ALDER_POINT,
+ CHIPSET_700_SERIES_RAPTOR_POINT,
CHIPSET_APOLLO_LAKE,
CHIPSET_GEMINI_LAKE,
CHIPSET_JASPER_LAKE,
@@ -472,6 +483,18 @@
#define SER_INV_FD -1
#endif
+/* cros_ec.c */
+/**
+ * Probe the Google Chrome OS EC device
+ *
+ * @return 0 if found correct, non-zero if not found or error
+ */
+int cros_ec_need_2nd_pass(void);
+bool cros_ec_erasure_failed(void);
+int cros_ec_finish(void);
+int cros_ec_prepare(struct flashctx *flash, const uint8_t *const image, uint32_t flash_size);
+int cros_ec_block_erase(struct flashctx *flash, unsigned int blockaddr, unsigned int len);
+
void sp_flush_incoming(void);
fdtype sp_openserport(char *dev, int baud);
extern fdtype sp_fd;
diff --git a/imports/writeprotect.c b/imports/writeprotect.c
index 411089d..964c311 100644
--- a/imports/writeprotect.c
+++ b/imports/writeprotect.c
@@ -482,7 +482,7 @@
case FLASHROM_WP_MODE_HARDWARE:
if (!bits->srp_bit_present)
- return FLASHROM_WP_ERR_CHIP_UNSUPPORTED;
+ return FLASHROM_WP_ERR_MODE_UNSUPPORTED;
bits->srl = 0;
bits->srp = 1;
