Merge changes from topic "ar/cvereorder" into integration
* changes:
chore(cpus): rearrange the errata and cve in order in Cortex-X4
chore(cpus): rearrange the errata and cve in order in Neoverse-V3
diff --git a/docs/components/activity-monitors.rst b/docs/components/activity-monitors.rst
index 4c33d42..d25fcb1 100644
--- a/docs/components/activity-monitors.rst
+++ b/docs/components/activity-monitors.rst
@@ -21,7 +21,9 @@
As a security precaution, Trusted Firmware-A does not enable these by default.
Instead, platforms must configure their auxiliary counters through the
-``plat_amu_aux_enables`` platform hook.
+``plat_amu_aux_enables`` platform hook. This is a per-core array indexed with
+``plat_my_core_pos()``. A core's value will be written verbatim into
+``AMCNTENSET1_EL0``.
--------------
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 67fdead..3707520 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -697,6 +697,7 @@
#define MDCR_TDOSA_BIT (ULL(1) << 10)
#define MDCR_TDA_BIT (ULL(1) << 9)
#define MDCR_TPM_BIT (ULL(1) << 6)
+#define MDCR_RLTE_BIT (ULL(1) << 0)
#define MDCR_EL3_RESET_VAL MDCR_MTPME_BIT
/* MDCR_EL2 definitions */
diff --git a/lib/aarch64/misc_helpers.S b/lib/aarch64/misc_helpers.S
index 93771df..f95fb6e 100644
--- a/lib/aarch64/misc_helpers.S
+++ b/lib/aarch64/misc_helpers.S
@@ -21,10 +21,6 @@
.globl disable_mmu_icache_el1
.globl disable_mmu_icache_el3
.globl fixup_gdt_reloc
-#if SUPPORT_VFP
- .globl enable_vfp
-#endif
-
func smc
smc #0
endfunc smc
@@ -456,24 +452,6 @@
endfunc disable_mmu_icache_el1
/* ---------------------------------------------------------------------------
- * Enable the use of VFP at EL3
- * ---------------------------------------------------------------------------
- */
-#if SUPPORT_VFP
-func enable_vfp
- mrs x0, cpacr_el1
- orr x0, x0, #CPACR_VFP_BITS
- msr cpacr_el1, x0
- mrs x0, cptr_el3
- mov x1, #AARCH64_CPTR_TFP
- bic x0, x0, x1
- msr cptr_el3, x0
- isb
- ret
-endfunc enable_vfp
-#endif
-
-/* ---------------------------------------------------------------------------
* Helper to fixup Global Descriptor table (GDT) and dynamic relocations
* (.rela.dyn) at runtime.
*
diff --git a/lib/extensions/trf/aarch64/trf.c b/lib/extensions/trf/aarch64/trf.c
index d36853a..dbafca1 100644
--- a/lib/extensions/trf/aarch64/trf.c
+++ b/lib/extensions/trf/aarch64/trf.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2024, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2025, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,8 +22,12 @@
* MDCR_EL3.TTRF = b0
* Allow access of trace filter control registers from NS-EL2
* and NS-EL1 when NS-EL2 is implemented but not used
+ *
+ * MDCR_EL3.RLTE = b0
+ * Trace prohibited in Realm state, unless overridden by the
+ * IMPLEMENTATION DEFINED authentication interface.
*/
- mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT);
+ mdcr_el3_val &= ~(MDCR_STE_BIT | MDCR_TTRF_BIT | MDCR_RLTE_BIT);
write_ctx_reg(state, CTX_MDCR_EL3, mdcr_el3_val);
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
index 1ddd0e4..c587a55 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdv3/platform.mk
@@ -178,5 +178,6 @@
ifeq (${SPD},spmd)
ifeq (${SPMD_SPM_AT_SEL2},1)
override CTX_INCLUDE_SVE_REGS := 0
+override CTX_INCLUDE_FPREGS := 0
endif
endif
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
index 5ffd9ef..849e38a 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.c
@@ -1,6 +1,6 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
- * Copyright (c) 2022-2023, Advanced Micro Devices, Inc. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -123,7 +123,7 @@
.name = "qspi0",
.regval = 0x02,
.group_base = PINCTRL_GRP_QSPI0_0,
- .group_size = PINCTRL_GRP_QSPI0_0 - PINCTRL_GRP_QSPI0_0 + 1U,
+ .group_size = PINCTRL_GRP_QSPI0_1 - PINCTRL_GRP_QSPI0_0 + 1U,
},
[PINCTRL_FUNC_QSPI_FBCLK] = {
.name = "qspi_fbclk",
@@ -135,7 +135,7 @@
.name = "qspi_ss",
.regval = 0x02,
.group_base = PINCTRL_GRP_QSPI_SS,
- .group_size = PINCTRL_GRP_QSPI_SS - PINCTRL_GRP_QSPI_SS + 1U,
+ .group_size = PINCTRL_GRP_QSPI_SS_1 - PINCTRL_GRP_QSPI_SS + 1U,
},
[PINCTRL_FUNC_SPI0] = {
.name = "spi0",
@@ -383,6 +383,7 @@
[PINCTRL_PIN_0] = {
.groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0,
+ PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0,
@@ -401,6 +402,7 @@
[PINCTRL_PIN_1] = {
.groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0,
+ PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0,
@@ -419,6 +421,7 @@
[PINCTRL_PIN_2] = {
.groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0,
+ PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0,
@@ -437,6 +440,7 @@
[PINCTRL_PIN_3] = {
.groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0,
+ PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0,
@@ -455,6 +459,7 @@
[PINCTRL_PIN_4] = {
.groups = &((uint16_t []) {
PINCTRL_GRP_QSPI0_0,
+ PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0,
@@ -473,6 +478,7 @@
[PINCTRL_PIN_5] = {
.groups = &((uint16_t []) {
PINCTRL_GRP_QSPI_SS,
+ PINCTRL_GRP_QSPI_SS_1,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_RESERVED,
PINCTRL_GRP_TESTSCAN0_0,
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
index 277af4b..cb3b62e 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_pinctrl.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2018-2020, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -184,7 +185,9 @@
PINCTRL_GRP_MDIO2_0,
PINCTRL_GRP_MDIO3_0,
PINCTRL_GRP_QSPI0_0,
+ PINCTRL_GRP_QSPI0_1,
PINCTRL_GRP_QSPI_SS,
+ PINCTRL_GRP_QSPI_SS_1,
PINCTRL_GRP_QSPI_FBCLK,
PINCTRL_GRP_SPI0_0,
PINCTRL_GRP_SPI0_1,
