UPSTREAM: arch/riscv: Show fault PC and load address on load access faults
Change-Id: Ib0535bf25ce25550cc17f64177f804a70aa13fb3
Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15286
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/356718
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index ff3be56..5b4d0b1 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -122,6 +122,8 @@
break;
case 5:
printk(BIOS_DEBUG, "Trap: Load access fault\n");
+ printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
+ printk(BIOS_DEBUG, "Load Address: %p\n", badAddr);
break;
case 6:
printk(BIOS_DEBUG, "Trap: Store address misaligned\n");
