UPSTREAM: mb/google/fatcat: Create kinmen variant
Create the kinmen variant of the fatcat reference board by copying
the fatcat files to a new directory named for the variant.
BUG=b:409148565
TEST=1. util/abuild/abuild -p none -t google/fatcat -x -a
make sure the build includes GOOGLE_KINMEN
2. Run part_id_gen tool without any errors
(cherry picked from commit ee5256bfe5b73560a5503a8028c12357f7338543)
Original-Change-Id: I51e388e61f102216f6ce9233c87c1915596602be
Original-Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/87317
Original-Reviewed-by: Bob Moragues <moragues@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Derek Huang <derekhuang@google.com>
Original-Reviewed-by: YH Lin <yueherngl@google.com>
Original-Reviewed-by: Subrata Banik <subratabanik@google.com>
Original-Reviewed-by: Jayvik Desai <jayvik@google.com>
GitOrigin-RevId: ee5256bfe5b73560a5503a8028c12357f7338543
Cr-Build-Id: 8717233198884905137
Cr-Build-Url: https://cr-buildbucket.appspot.com/build/8717233198884905137
Copybot-Job-Name: coreboot-main-copybot-downstream
Change-Id: I4763f318dcc13b3a51cefc9fe26b88d59f3c45ae
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/6472762
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Commit-Queue: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Bot-Commit: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index d24f3c0..b5f649c 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -91,6 +91,9 @@
select BOARD_GOOGLE_BASEBOARD_FATCAT
select HAVE_SLP_S0_GATE
+config BOARD_GOOGLE_KINMEN
+ select BOARD_GOOGLE_BASEBOARD_FATCAT
+
if BOARD_GOOGLE_FATCAT_COMMON
config BASEBOARD_DIR
@@ -127,6 +130,7 @@
default 0x03 if BOARD_GOOGLE_MODEL_FATCAT
default 0x01 if BOARD_GOOGLE_FRANCKA
default 0x01 if BOARD_GOOGLE_FELINO
+ default 0x03 if BOARD_GOOGLE_KINMEN
config HAVE_SLP_S0_GATE
def_bool n
@@ -145,6 +149,7 @@
default "Fatcatnuvo" if BOARD_GOOGLE_FATCATNUVO
default "Francka" if BOARD_GOOGLE_FRANCKA
default "Felino" if BOARD_GOOGLE_FELINO
+ default "Kinmen" if BOARD_GOOGLE_KINMEN
config MEMORY_SOLDERDOWN
def_bool n
@@ -156,6 +161,7 @@
default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15)
default 79 if BOARD_GOOGLE_FELINO # GPE0_DW2_15 (GPP_F15)
default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_11 (GPP_H11)
+ default 47 if BOARD_GOOGLE_KINMEN # GPE0_DW1_15 (GPP_D15)
# FIXME: update as per board schematics
config UART_FOR_CONSOLE
@@ -170,6 +176,7 @@
default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT
default "francka" if BOARD_GOOGLE_FRANCKA
default "felino" if BOARD_GOOGLE_FELINO
+ default "kinmen" if BOARD_GOOGLE_KINMEN
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
diff --git a/src/mainboard/google/fatcat/Kconfig.name b/src/mainboard/google/fatcat/Kconfig.name
index 7c6cb89..786c0e7 100644
--- a/src/mainboard/google/fatcat/Kconfig.name
+++ b/src/mainboard/google/fatcat/Kconfig.name
@@ -19,3 +19,6 @@
config BOARD_GOOGLE_FRANCKA
bool "-> Francka"
+
+config BOARD_GOOGLE_KINMEN
+ bool "-> Kinmen"
diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
index 067c361..6934bf1 100644
--- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
+++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h
@@ -30,6 +30,10 @@
#define GPIO_PCH_WP 0 /* TODO */
/* Used to gate SoC's SLP_S0# signal */
#define GPIO_SLP_S0_GATE GPP_D03
+#elif CONFIG(BOARD_GOOGLE_KINMEN)
+ #define EC_SYNC_IRQ GPP_E07_IRQ
+ #define GPIO_PCH_WP GPP_D02
+#define GPIO_SLP_S0_GATE 0 /* Not Connected */
#endif
#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
new file mode 100644
index 0000000..4c33dad
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/Makefile.mk
@@ -0,0 +1,6 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+romstage-y += memory.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/fatcat/variants/kinmen/gpio.c b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
new file mode 100644
index 0000000..ede819d
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/gpio.c
@@ -0,0 +1,423 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <soc/gpio.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+ /* GPP_A00: ESPI_IO0_EC_R */
+ /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */
+
+ /* GPP_A01: ESPI_IO1_EC_R */
+ /* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */
+
+ /* GPP_A02: ESPI_IO2_EC_R */
+ /* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */
+
+ /* GPP_A03: ESPI_IO3_EC_R */
+ /* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */
+
+ /* GPP_A04: ESPI_CS0_EC_R_N */
+ /* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */
+
+ /* GPP_A05: ESPI_CLK_EC_R */
+ /* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */
+
+ /* GPP_A06: ESPI_RST_EC_R_N */
+ /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */
+
+ /* GPP_A09: M.2_WWAN_FCP_OFF_N */
+ PAD_CFG_GPO(GPP_A09, 1, PLTRST),
+ /* GPP_A10: M.2_WWAN_DISABLE_N */
+ PAD_CFG_GPO(GPP_A10, 1, PLTRST),
+ /* GPP_A11: WLAN_RST_N */
+ PAD_CFG_GPO(GPP_A11, 1, PLTRST),
+ /* GPP_A12: WIFI_WAKE_N */
+ PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL),
+ /* GPP_A15: GPP_A15_DNX_FORCE_RELOAD */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* GPP_A16: BT_RF_KILL_N */
+ PAD_CFG_GPO(GPP_A16, 1, DEEP),
+ /* GPP_A17: WIFI_RF_KILL_N */
+ PAD_CFG_GPO(GPP_A17, 1, DEEP),
+
+ /* GPP_B00: USBC_SML_CLK_PD */
+ PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1),
+ /* GPP_B01: USBC_SML_DATA_PD */
+ PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1),
+ /* GPP_B02: ISH_I2C0_SDA_SNSR_HDR */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3),
+ /* GPP_B03: ISH_I2C0_SCL_SNSR_HDR */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3),
+ /* GPP_B04: ISH_GP_0_SNSR_HDR */
+ PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4),
+ /* GPP_B05: ISH_GP_1_SNSR_HDR */
+ PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4),
+ /* GPP_B06: ISH_GP_2_SNSR_HDR */
+ PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4),
+ /* GPP_B07: ISH_GP_3_SNSR_HDR */
+ PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4),
+ /* GPP_B08: ISH_GP_4_SNSR_HDR */
+ PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4),
+ /* GPP_B09: M2_GEN4_SSD_RESET_N */
+ PAD_CFG_GPO(GPP_B09, 1, PLTRST),
+ /* GPP_B10: GEN4_SSD_PWREN */
+ PAD_CFG_GPO(GPP_B10, 1, PLTRST),
+ /* GPP_B11: MOD_TCSS1_DISP_HPD3 */
+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2),
+ /* GPP_B12: PM_SLP_S0_N */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* GPP_B13: PLT_RST_N */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* GPP_B14: MOD_TCSS2_DISP_HPD4 */
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2),
+ /* GPP_B15: MOD_TCSS_USB_TYP_A_OC3_N */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+ /* GPP_B16: GEN5_SSD_PWREN */
+ PAD_CFG_GPO(GPP_B16, 1, PLTRST),
+ /* GPP_B17: Not used */
+ PAD_NC(GPP_B17, NONE),
+ /* GPP_B18: ISH_I2C2_SDA_SNSR_HDR */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B18, NONE, DEEP, NF1),
+ /* GPP_B19: ISH_I2C2_SCL_SNSR_HDR */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B19, NONE, DEEP, NF1),
+ /* GPP_B20: M.2_WWAN_RST_N */
+ PAD_CFG_GPO(GPP_B20, 1, PLTRST),
+ /* GPP_B21: TCP_RETIMER_FORCE_PWR */
+ PAD_CFG_GPO(GPP_B21, 0, DEEP),
+ /* GPP_B22: ISH_GP_5_SNSR_HDR */
+ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4),
+ /* GPP_B23: ISH_GP_6_SNSR_HDR */
+ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4),
+ /* GPP_B24: ESPI_ALERT0_EC_R_N */
+ PAD_NC(GPP_B24, NONE),
+
+ /* GPP_C00: GPP_C0_SMBCLK */
+ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+ /* GPP_C01: GPP_C1_SMBDATA */
+ PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+ /* GPP_C02: Not used */
+ PAD_NC(GPP_C02, NONE),
+ /* GPP_C03: TCP_LAN_SML0_SCL_R */
+ PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
+ /* GPP_C04: TCP_LAN_SML0_SDA_R */
+ PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+ /* GPP_C06: SML1_CLK */
+ PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1),
+ /* GPP_C07: SML1_DATA */
+ PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1),
+ /* GPP_C09: CLKREQ0_X8_GEN5_DT_CEM_SLOT_N */
+ PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1),
+ /* GPP_C10: CLKREQ1_X4_GEN5_M2_SSD_N */
+ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
+ /* GPP_C11: CLKREQ2_X1_GEN4_DT_CEM_SLOT_N */
+ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
+ /* GPP_C12: CLKREQ3_X1_GEN1_GBE_LAN_N */
+ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+ /* GPP_C13: CLKREQ4_X1_GEN4_M2_WLAN_N */
+ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
+ /* GPP_C14: CLKREQ5_X1_GEN4_M2_WWAN_N */
+ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1),
+ /* GPP_C16: TBT_LSX0_TXD */
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
+ /* GPP_C17: TBT_LSX0_RXD */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
+ /* GPP_C18: TBT_LSX1_TXD */
+ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+ /* GPP_C19: TBT_LSX1_RXD */
+ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+ /* GPP_C20: MOD_TCSS1_LS_TX_DDC_SCL */
+ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+ /* GPP_C21: MOD_TCSS1_LS_RX_DDC_SDA */
+ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+ /* GPP_C22: MOD_TCSS2_LS_TX_DDC_SCL */
+ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF2),
+ /* GPP_C23: MOD_TCSS2_LS_RX_DDC_SDA */
+ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF2),
+
+ /* GPP_D00: IMGCLKOUT_1 */
+ PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1),
+ /* GPP_D02: Not used */
+ PAD_NC(GPP_D02, NONE),
+ /* GPP_D03: M.2_WWAN_PERST_GPIO_N */
+ PAD_CFG_GPO(GPP_D03, 1, PLTRST),
+ /* GPP_D04: IMGCLKOUT_0 */
+ PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1),
+ /* GPP_D05: disable ISH_UART0_RXD */
+ PAD_NC(GPP_D05, NONE),
+ /* GPP_D07: NC */
+ PAD_NC(GPP_D07, NONE),
+ /* GPP_D08: NC */
+ PAD_NC(GPP_D08, NONE),
+ /* GPP_D09: PEG_SLOT_RST_N */
+ PAD_CFG_GPO(GPP_D09, 1, PLTRST),
+ /* GPP_D10: HDA_BCLK */
+ PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1),
+ /* GPP_D11: HDA_SYNC */
+ PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1),
+ /* GPP_D12: HDA_SDO */
+ PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1),
+ /* GPP_D13: HDA_SDI0 */
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ /* GPP_D14: COINLESS_MODE_SELECT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D14, NONE, PLTRST, LEVEL, ACPI),
+ /* GPP_D15: SPI_TPM_INT_N */
+ PAD_CFG_GPI_APIC_LOCK(GPP_D15, NONE, LEVEL, INVERT, LOCK_CONFIG),
+ /* GPP_D16: HDA_RST_N_HDR */
+ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1),
+ /* GPP_D17: HDA_SDI1_HDR */
+ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+ /* GPP_D18: CLKREQ6_X4_GEN4_M2_SSD_N */
+ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+ /* GPP_D20: CSE_EARLY_SW */
+ PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL),
+ /* GPP_D21: NC */
+ PAD_NC(GPP_D21, NONE),
+ /* GPP_D22: BPKI3C_SDA */
+ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1),
+ /* GPP_D23: BPKI3C_SCL */
+ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+ /* GPP_D24: PEG_SLOT_WAKE_N */
+ PAD_CFG_GPI_SCI_LOW(GPP_D24, NONE, DEEP, LEVEL),
+ /* GPP_D25: X4_SLOT_WAKE_N */
+ PAD_CFG_GPI_SCI_LOW(GPP_D25, NONE, DEEP, LEVEL),
+
+ /* GPP_E01: CRD2_RST_N */
+ PAD_CFG_GPO(GPP_E01, 1, PLTRST),
+ /* GPP_E02: WWAN_WAKE_GPIO_N */
+ PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL),
+ /* GPP_E03: M2_GEN5_SSD_RESET_N */
+ PAD_CFG_GPO(GPP_E03, 1, PLTRST),
+ /* GPP_E06: SECURE_CAM_SW */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI),
+ /* GPP_E07 : [] ==> EC_SOC_INT_ODL */
+ PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG),
+ /* GPP_E08: Not used */
+ PAD_NC(GPP_E08, NONE),
+ /* GPP_E09: USB_RD_FP_CONN_12_OC0_N */
+ PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1),
+ /* GPP_E10: CRD1_RST_N */
+ PAD_CFG_GPO(GPP_E10, 1, PLTRST),
+ /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF3),
+ /* GPP_E12: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF3),
+ /* GPP_E13: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF3),
+ /* GPP_E14: THC0_SPI1_IO_2_TCH_PNL1 */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF3),
+ /* GPP_E15: THC0_SPI1_IO_3_TCH_PNL1 */
+ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF3),
+ /* GPP_E16: THC0_SPI1_RST_N_TCH_PNL1 */
+ /* THC NOTE: use GPO instead of GPO for THC0 Rst */
+ PAD_CFG_GPO(GPP_E16, 1, DEEP),
+ /* GPP_E18: THC0_SPI1_INT_N_TCH_PNL1 */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF3),
+ /* GPP_E21: I2C_PMC_PD_INT_N */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+ /* GPP_E22: THC0_SPI1_DSYNC */
+ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF3),
+
+ /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1),
+ /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1),
+ /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1),
+ /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1),
+ /* GPP_F04: CNV_RF_RESET_R_N */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1),
+ /* GPP_F05: CRF_CLKREQ_R */
+ /* NOTE: IOSSTAGE: 'Ignore' for S0ix */
+ PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3),
+ /* GPP_F06: WLAN_WWAN_COEX3 */
+ PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1),
+ /* GPP_F07: IMGCLKOUT_2 */
+ PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2),
+ /* GPP_F08: TCH_PNL1_PWR_EN */
+ PAD_CFG_GPO(GPP_F08, 1, PLTRST),
+ /* GPP_F09: NC */
+ PAD_NC(GPP_F09, NONE),
+ /* GPP_F10: PEG_SLOT_PWR_EN_N */
+ PAD_CFG_GPO(GPP_F10, 0, PLTRST),
+ /* GPP_F11: MOD_TCSS2_TYP_A_VBUS_EN */
+ PAD_CFG_GPO(GPP_F11, 1, DEEP),
+ /* GPP_F12: THC_I2C1_SCL_TCH_PAD */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8),
+ /* GPP_F13: THC_I2C1_SDA_TCH_PAD */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8),
+ /* GPP_F17: Not used */
+ PAD_CFG_GPI_INT(GPP_F17, NONE, PLTRST, EDGE_BOTH),
+ /* GPP_F18: TCH_PAD_INT_N */
+ /* NOTE: require rework to switch from GPP_A13 to GPP_F18 */
+ PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, LEVEL, INVERT),
+ /* GPP_F19: GPP_PRIVACY_LED_CAM2 */
+ PAD_CFG_GPO(GPP_F19, 0, PLTRST),
+ /* GPP_F20: GPP_PRIVACY_LED_CAM1_CVS_HST_WAKE */
+ PAD_CFG_GPO(GPP_F20, 0, PLTRST),
+ /* GPP_F22: THC1_SPI2_DSYNC */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF3),
+
+ /* GPP_H00: Not used */
+ PAD_NC(GPP_H00, NONE),
+ /* GPP_H01: CRD_CAM_STROBE */
+ PAD_CFG_GPO(GPP_H01, 0, PLTRST),
+ /* GPP_H02: DEBUG_TRACE_PNP */
+ PAD_CFG_GPO(GPP_H02, 1, PLTRST),
+ /* GPP_H03: MIC MUTE */
+ PAD_CFG_NF(GPP_H03, NONE, DEEP, NF1),
+ /* GPP_H04: I2C2_SDA_CAM_FLSH */
+ PAD_CFG_NF(GPP_H04, NONE, DEEP, NF1),
+ /* GPP_H05: I2C2_SCL_CAM_FLSH */
+ PAD_CFG_NF(GPP_H05, NONE, DEEP, NF1),
+ /* GPP_H06: I2C3_SDA_PSS */
+ PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+ /* GPP_H07: I2C3_SCL_PSS */
+ PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+ /* GPP_H08: UART0_BUF_RXD */
+ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+ /* GPP_H09: UART0_BUF_TXD */
+ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+ /* GPP_H10: UART0_BUF_RTS */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
+ /* GPP_H11: UART0_BUF_CTS */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1),
+ /* GPP_H13: CPU_C10_GATE_N_R */
+ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
+ /* GPP_H14: NC */
+ PAD_NC(GPP_H14, NONE),
+ /* GPP_H15: NC */
+ PAD_NC(GPP_H15, NONE),
+ /* GPP_H16: WWAN_PWREN */
+ PAD_CFG_GPO(GPP_H16, 1, PLTRST),
+ /* GPP_H17: MIC MUTE LED */
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ /* GPP_H19: I3C0_SDA_HDR */
+ PAD_CFG_NF(GPP_H19, NONE, DEEP, NF2),
+ /* GPP_H20: I3C0_SCL_HDR */
+ PAD_CFG_NF(GPP_H20, NONE, DEEP, NF2),
+ /* GPP_H21: I2C1_SDA_I3C1_SDA_CAM_FLSH_CVS */
+ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+ /* GPP_H22: I2C1_SCL_I3C1_SCL_CAM_FLSH_CVS */
+ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+
+ /* GPP_S00: SNDW3_CLK_CODEC */
+ PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1),
+ /* GPP_S01: SNDW3_DATA0_CODEC */
+ PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1),
+ /* GPP_S02: SNDW3_DATA1_CODEC */
+ PAD_CFG_NF(GPP_S02, NONE, DEEP, NF1),
+ /* GPP_S03: SNDW3_DATA2_CODEC */
+ PAD_CFG_NF(GPP_S03, NONE, DEEP, NF1),
+ /* GPP_S04: SNDW2_CLK */
+ PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2),
+ /* GPP_S05: SNDW2_DATA0 */
+ PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2),
+ /* GPP_S06: SNDW1_CLK */
+ PAD_CFG_NF(GPP_S06, NONE, DEEP, NF3),
+ /* GPP_S07: SNDW1_DATA0 */
+ PAD_CFG_NF(GPP_S07, NONE, DEEP, NF3),
+
+ /* GPP_V00: PM_BATLOW_N */
+ PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1),
+ /* GPP_V01: BC_ACOK_MCP */
+ PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1),
+ /* GPP_V02: LANWAKE_N_R */
+ PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1),
+ /* GPP_V03: PWRBTN_MCP_N */
+ PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1),
+ /* GPP_V04: PM_SLP_S3_N */
+ PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1),
+ /* GPP_V05: PM_SLP_S4_N */
+ PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1),
+ /* GPP_V06: PM_SLP_A_N */
+ PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1),
+ /* GPP_V07: Not used */
+ PAD_NC(GPP_V07, NONE),
+ /* GPP_V08: SLP_WLAN_N */
+ PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1),
+ /* GPP_V09: PM_SLP_S5_N */
+ PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1),
+ /* GPP_V10: LANPHYPC_R_N */
+ PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1),
+ /* GPP_V11: PM_SLP_LAN_N */
+ PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1),
+ /* GPP_V12: WAKE_N */
+ PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1),
+ /* GPP_V13: GPP_V13_CATERR_N */
+ PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1),
+ /* GPP_V14: GPP_V14_FORCEPR_N */
+ PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1),
+ /* GPP_V15: GPP_V15_THERMTRIP_N */
+ PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1),
+ /* GPP_V16: GPP_V16_VCCST_EN */
+ PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1),
+ /* GPP_V17: TCP_RT_S0IX_ENTRY_EXIT_N */
+ PAD_CFG_GPO(GPP_V17, 1, DEEP),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+ /* GPP_H08: UART0_BUF_RXD */
+ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1),
+ /* GPP_H09: UART0_BUF_TXD */
+ PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),
+
+ /* GPP_H06: I2C3_SDA_PSS */
+ PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
+ /* GPP_H07: I2C3_SCL_PSS */
+ PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
+ /* GPP_D15: SPI_TPM_INT_N */
+ PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+};
+
+/* Pad configuration in romstage */
+static const struct pad_config romstage_gpio_table[] = {
+ /* GPP_A08: X1_PCIE_SLOT_PWR_EN */
+ PAD_CFG_GPO(GPP_A08, 0, PLTRST),
+ /* GPP_C00: GPP_C0_SMBCLK */
+ PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1),
+ /* GPP_C01: GPP_C1_SMBDATA */
+ PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1),
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+/* Create the stub for romstage gpio, typically use for power sequence */
+const struct pad_config *variant_romstage_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(romstage_gpio_table);
+ return romstage_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME),
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME),
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME),
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE4_NAME),
+};
+
+DECLARE_CROS_GPIOS(cros_gpios);
diff --git a/src/mainboard/google/fatcat/variants/kinmen/hda_verb.c b/src/mainboard/google/fatcat/variants/kinmen/hda_verb.c
new file mode 100644
index 0000000..2f703b7
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/hda_verb.c
@@ -0,0 +1,126 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */
+ 0x10ec12ac, /* Subsystem ID */
+ 0x00000013, /* Number of jacks (NID entries) */
+
+ AZALIA_RESET(0x1),
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table */
+ AZALIA_SUBVENDOR(0, 0x10ec12ac),
+
+ /* Pin Widget Verb Table */
+ /*
+ * DMIC
+ * Requirement is to use PCH DMIC. Hence,
+ * commented out codec's Internal DMIC.
+ * AZALIA_PIN_CFG(0, 0x12, 0x90A60130),
+ * AZALIA_PIN_CFG(0, 0x13, 0x40000000),
+ */
+ /* Pin widget 0x14 - Front (Port-D) */
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ /* Pin widget 0x18 - NPC */
+ AZALIA_PIN_CFG(0, 0x18, 0x411111F0),
+ /* Pin widget 0x19 - MIC2 (Port-F) */
+ AZALIA_PIN_CFG(0, 0x19, 0x04A11040),
+ /* Pin widget 0x1A - LINE1 (Port-C) */
+ AZALIA_PIN_CFG(0, 0x1a, 0x411111F0),
+ /* Pin widget 0x1B - NPC */
+ AZALIA_PIN_CFG(0, 0x1b, 0x411111F0),
+ /* Pin widget 0x1D - BEEP-IN */
+ AZALIA_PIN_CFG(0, 0x1d, 0x40610041),
+ /* Pin widget 0x1E - NPC */
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111F0),
+ /* Pin widget 0x21 - HP1-OUT (Port-I) */
+ AZALIA_PIN_CFG(0, 0x21, 0x04211020),
+ /*
+ * Widget node 0x20 - 1
+ * Codec hidden reset and speaker power 2W/4ohm
+ */
+ 0x0205001A,
+ 0x0204C003,
+ 0x02050038,
+ 0x02047901,
+ /*
+ * Widget node 0x20 - 2
+ * Class D power on Reset
+ */
+ 0x0205003C,
+ 0x02040354,
+ 0x0205003C,
+ 0x02040314,
+ /*
+ * Widget node 0x20 - 3
+ * Disable AGC and set AGC limit to -1.5dB
+ */
+ 0x02050016,
+ 0x02040C50,
+ 0x02050012,
+ 0x0204EBC1,
+ /*
+ * Widget node 0x20 - 4
+ * Set AGC Post gain +1.5dB then Enable AGC
+ */
+ 0x02050013,
+ 0x02044023,
+ 0x02050016,
+ 0x02040E50,
+ /*
+ * Widget node 0x20 - 5
+ * Silence detector enabling + Set EAPD to verb control
+ */
+ 0x02050037,
+ 0x0204FE15,
+ 0x02050010,
+ 0x02040020,
+ /*
+ * Widget node 0x20 - 6
+ * Silence data mode Threshold (-90dB)
+ */
+ 0x02050030,
+ 0x0204A000,
+ 0x0205001B,
+ 0x02040A4B,
+ /*
+ * Widget node 0x20 - 7
+ * Default setting-1
+ */
+ 0x05750003,
+ 0x05740DA3,
+ 0x02050046,
+ 0x02040004,
+ /*
+ * Widget node 0x20 - 8
+ * support 1 pin detect two port
+ */
+ 0x02050009,
+ 0x0204E003,
+ 0x0205000A,
+ 0x02047770,
+ /*
+ * Widget node 0x20 - 9
+ * To set LDO1/LDO2 as default
+ */
+ 0x02050008,
+ 0x02046A0C,
+ 0x02050008,
+ 0x02046A0C,
+};
+
+const u32 pc_beep_verbs[] = {
+ /* Dos beep path - 1 */
+ 0x01470C00,
+ 0x02050036,
+ 0x02047151,
+ 0x01470740,
+ /* Dos beep path - 2 */
+ 0x0143b000,
+ 0x01470C02,
+ 0x01470C02,
+ 0x01470C02,
+};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/google/fatcat/variants/kinmen/include/variant/ec.h b/src/mainboard/google/fatcat/variants/kinmen/include/variant/ec.h
new file mode 100644
index 0000000..4fc0622
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/include/variant/ec.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <baseboard/ec.h>
+
+#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/google/fatcat/variants/kinmen/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/kinmen/include/variant/gpio.h
new file mode 100644
index 0000000..cced668
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/include/variant/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_GPIO_H__
+#define __MAINBOARD_GPIO_H__
+
+#include <baseboard/gpio.h>
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+#endif /* __MAINBOARD_GPIO_H__ */
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory.c b/src/mainboard/google/fatcat/variants/kinmen/memory.c
new file mode 100644
index 0000000..e0908ad
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory.c
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+#include <soc/meminit.h>
+
+static const struct mb_cfg lp5_mem_config = {
+ .type = MEM_TYPE_LP5X,
+
+ .lpx_dq_map = {
+ .ddr0 = {
+ .dq0 = { 13, 14, 12, 15, 11, 10, 8, 9, },
+ .dq1 = { 7, 5, 4, 6, 0, 3, 1, 2 },
+ },
+ .ddr1 = {
+ .dq0 = { 1, 3, 0, 2, 7, 4, 6, 5, },
+ .dq1 = { 12, 13, 14, 15, 11, 10, 9, 8 },
+ },
+ .ddr2 = {
+ .dq0 = { 0, 2, 1, 3, 6, 4, 7, 5 },
+ .dq1 = { 14, 13, 15, 12, 8, 11, 10, 9, },
+ },
+ .ddr3 = {
+ .dq0 = { 6, 5, 7, 4, 2, 3, 1, 0, },
+ .dq1 = { 10, 8, 11, 9, 12, 15, 13, 14 },
+ },
+ .ddr4 = {
+ .dq0 = { 2, 1, 3, 0, 4, 7, 5, 6 },
+ .dq1 = { 15, 14, 12, 13, 9, 11, 10, 8, },
+ },
+ .ddr5 = {
+ .dq0 = { 6, 5, 7, 4, 3, 1, 0, 2, },
+ .dq1 = { 10, 9, 11, 8, 13, 14, 12, 15 },
+ },
+ .ddr6 = {
+ .dq0 = { 9, 10, 11, 8, 14, 12, 13, 15, },
+ .dq1 = { 0, 1, 2, 3, 5, 7, 4, 6 },
+ },
+ .ddr7 = {
+ .dq0 = { 0, 1, 2, 3, 7, 5, 6, 4, },
+ .dq1 = { 14, 13, 15, 12, 10, 8, 11, 9 },
+ },
+ },
+
+ .lpx_dqs_map = {
+ .ddr0 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr1 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr5 = { .dqs0 = 0, .dqs1 = 1 },
+ .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
+ .ddr7 = { .dqs0 = 0, .dqs1 = 1 }
+ },
+
+ .ect = true, /* Early Command Training */
+
+ .lp_ddr_dq_dqs_re_training = 1,
+
+ .user_bd = BOARD_TYPE_ULT_ULX,
+
+ .lp5x_config = {
+ .ccc_config = 0xFF,
+ },
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+ return &lp5_mem_config;
+}
+
+void variant_get_spd_info(struct mem_spd *spd_info)
+{
+ spd_info->topo = MEM_TOPO_MEMORY_DOWN;
+ spd_info->cbfs_index = 0;
+}
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
new file mode 100644
index 0000000..8fccc97
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/Makefile.mk
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/kinmen/memory src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
+
+SPD_SOURCES =
+SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 0(0b0000) Parts = H58G56BK7BX068
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
new file mode 100644
index 0000000..15fcc5c
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/dram_id.generated.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# This is an auto-generated file. Do not edit!!
+# Generated by:
+# ./util/spd_tools/bin/part_id_gen PTL lp5 src/mainboard/google/fatcat/variants/kinmen/memory src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
+
+DRAM Part Name ID to assign
+H58G56BK7BX068 0 (0000)
diff --git a/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
new file mode 100644
index 0000000..17ee7ef
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/memory/mem_parts_used.txt
@@ -0,0 +1,12 @@
+# This is a CSV file containing a list of memory parts used by this variant.
+# One part per line with an optional fixed ID in column 2.
+# Only include a fixed ID if it is required for legacy reasons!
+# Generated IDs are dependent on the order of parts in this file,
+# so new parts must always be added at the end of the file!
+#
+# Generate an updated Makefile.mk and dram_id.generated.txt by running the
+# part_id_gen tool from util/spd_tools.
+# See util/spd_tools/README.md for more details and instructions.
+
+# Part Name
+H58G56BK7BX068
diff --git a/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
new file mode 100644
index 0000000..bfd637a
--- /dev/null
+++ b/src/mainboard/google/fatcat/variants/kinmen/overridetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/pantherlake
+
+ device domain 0 on
+ end
+end
