| ## |
| ## This file is part of the coreboot project. |
| ## |
| ## Copyright (C) 2010 Google Inc. |
| ## |
| ## This program is free software; you can redistribute it and/or modify |
| ## it under the terms of the GNU General Public License as published by |
| ## the Free Software Foundation; version 2 of the License. |
| ## |
| ## This program is distributed in the hope that it will be useful, |
| ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| ## GNU General Public License for more details. |
| ## |
| ## You should have received a copy of the GNU General Public License |
| ## along with this program; if not, write to the Free Software |
| ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| ## |
| |
| config NORTHBRIDGE_INTEL_HASWELL |
| bool |
| select CACHE_MRC_BIN |
| select CPU_INTEL_HASWELL |
| select REQUIRES_BLOB |
| select MMCONF_SUPPORT_DEFAULT |
| select INTEL_DDI |
| select INTEL_DP |
| |
| if NORTHBRIDGE_INTEL_HASWELL |
| |
| config BOOTBLOCK_NORTHBRIDGE_INIT |
| string |
| default "northbridge/intel/haswell/bootblock.c" |
| |
| config VGA_BIOS_ID |
| string |
| default "8086,0166" |
| |
| config EXTERNAL_MRC_BLOB |
| bool |
| default n |
| |
| config CACHE_MRC_SIZE_KB |
| int |
| default 512 |
| |
| # FIXME: build from rom size |
| config MRC_CACHE_BASE |
| hex |
| default 0xff800000 |
| |
| config MRC_CACHE_LOCATION |
| hex |
| depends on !CHROMEOS |
| default 0x370000 |
| |
| config MRC_CACHE_SIZE |
| hex |
| depends on !CHROMEOS |
| default 0x10000 |
| |
| config DCACHE_RAM_BASE |
| hex |
| default 0xff7c0000 |
| |
| config DCACHE_RAM_SIZE |
| hex |
| default 0x10000 |
| help |
| The size of the cache-as-ram region required during bootblock |
| and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE |
| must add up to a power of 2. |
| |
| config DCACHE_RAM_MRC_VAR_SIZE |
| hex |
| default 0x30000 |
| help |
| The amount of cache-as-ram region required by the reference code. |
| |
| config DCACHE_RAM_ROMSTAGE_STACK_SIZE |
| hex |
| default 0x2000 |
| help |
| The amount of anticipated stack usage from the data cache |
| during pre-ram rom stage execution. |
| |
| config HAVE_MRC |
| bool "Add a System Agent binary" |
| help |
| Select this option to add a System Agent binary to |
| the resulting coreboot image. |
| |
| Note: Without this binary coreboot will not work |
| |
| config MRC_FILE |
| string "Intel System Agent path and filename" |
| depends on HAVE_MRC |
| default "mrc.bin" |
| help |
| The path and filename of the file to use as System Agent |
| binary. |
| |
| config CBFS_SIZE |
| hex "Size of CBFS filesystem in ROM" |
| default 0x100000 |
| help |
| On Haswell systems the firmware image has to store a lot more |
| than just coreboot, including: |
| - a firmware descriptor |
| - Intel Management Engine firmware |
| - MRC cache information |
| This option allows to limit the size of the CBFS portion in the |
| firmware image. |
| |
| config PRE_GRAPHICS_DELAY |
| int "Graphics initialization delay in ms" |
| default 0 |
| help |
| On some systems, coreboot boots so fast that connected monitors |
| (mostly TVs) won't be able to wake up fast enough to talk to the |
| VBIOS. On those systems we need to wait for a bit before executing |
| the VBIOS. |
| |
| endif |