| /* |
| * This file is part of the coreboot project. |
| * |
| * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| * Copyright (C) 2009 coresystems GmbH |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License as published by |
| * the Free Software Foundation; version 2 of the License. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| */ |
| |
| #include <stdint.h> |
| #include <delay.h> |
| #include <arch/cpu.h> |
| #include <cpu/x86/msr.h> |
| #include <cpu/x86/lapic.h> |
| |
| /* NOTE: This code uses global variables, so it can not be used during |
| * memory init. |
| */ |
| |
| static u32 timer_fsb = 0; |
| |
| static int set_timer_fsb(void) |
| { |
| struct cpuinfo_x86 c; |
| int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 }; |
| int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 }; |
| |
| get_fms(&c, cpuid_eax(1)); |
| if (c.x86 != 6) |
| return -1; |
| |
| switch (c.x86_model) { |
| case 0xe: /* Core Solo/Duo */ |
| case 0x1c: /* Atom */ |
| timer_fsb = core_fsb[rdmsr(0xcd).lo & 7]; |
| break; |
| case 0xf: /* Core 2*/ |
| case 0x17: /* Enhanced Core */ |
| timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7]; |
| break; |
| case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/ |
| case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/ |
| timer_fsb = 100; |
| break; |
| default: |
| timer_fsb = 200; |
| break; |
| } |
| |
| return 0; |
| } |
| |
| void init_timer(void) |
| { |
| /* Set the apic timer to no interrupts and periodic mode */ |
| lapic_write(LAPIC_LVTT, (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)); |
| |
| /* Set the divider to 1, no divider */ |
| lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1); |
| |
| /* Set the initial counter to 0xffffffff */ |
| lapic_write(LAPIC_TMICT, 0xffffffff); |
| |
| /* Set FSB frequency to a reasonable value */ |
| set_timer_fsb(); |
| } |
| |
| void udelay(u32 usecs) |
| { |
| u32 start, value, ticks; |
| |
| if (!timer_fsb || (lapic_read(LAPIC_LVTT) & |
| (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) != |
| (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) |
| init_timer(); |
| |
| /* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */ |
| ticks = usecs * timer_fsb; |
| start = lapic_read(LAPIC_TMCCT); |
| do { |
| value = lapic_read(LAPIC_TMCCT); |
| } while((start - value) < ticks); |
| } |