UPSTREAM: cpu/x86/mtrr: Replace CONFIG_CPU_ADDR_BITS with cpu_phys_address_size()

This patch helps to generate correct MTRR mask value while
using set_var_mtrr().

set_var_mtrr(1, 0x99000000, 16*MiB, WP)

without CL :
0x0000000099000005: PHYBASE2: Address = 0x0000000099000000, WP
0x0000000fff000800: PHYMASK2: Length  = 0x0000007001000000, Valid

with CL :
0x0000000099000005: PHYBASE1: Address = 0x0000000099000000, WP
0x0000007fff000800: PHYMASK1: Length  = 0x0000000001000000, Valid


Change-Id: I4fc447140e35f9c3b0282f56bda32a28d17d72fd
Signed-off-by: Patrick Georgi <>
Original-Commit-Id: 6c8a040ec5e52a2032055c0e59dd68a8851d4bbc
Original-Change-Id: Ie3185dd8d4af73ec0605e19e9aa4223f2c2ad462
Original-Signed-off-by: Subrata Banik <>
Original-Reviewed-by: V Sowmya <>
Original-Reviewed-by: Furquan Shaikh <>
Original-Tested-by: build bot (Jenkins) <>
Reviewed-by: Patrick Georgi <>
Commit-Queue: Patrick Georgi <>
Tested-by: Patrick Georgi <>
1 file changed
tree: f2ee54125e83ec03250b02dad0c8b36e0089a5dc
  1. .checkpatch.conf
  2. .clang-format
  3. .gitignore
  4. .gitmodules
  5. .gitreview
  9. Documentation/
  11. Makefile
  13. PRESUBMIT.cfg
  15. configs/
  16. gnat.adc
  17. payloads/
  18. src/
  20. util/

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.


After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)


  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

You can contact us directly on the coreboot mailing list:

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.