UPSTREAM: soc/intel/common: Add Lunar Lake IAA and TBTRP3 device IDs
Reference:
Lunar Lake External Design Specification Volume 1 (734362)
BUG=b:329787286
TEST=verified on Lunar Lake RVP board (lnlrvp).
(cherry picked from commit 47e7240ffc6a8f479bedc065376fb59cd040c7c7)
Original-Change-Id: I92b65c946682387cbb841d558c6f0a7cb0fcd4ac
Original-Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/81850
Original-Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Original-Reviewed-by: Eric Lai <ericllai@google.com>
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GitOrigin-RevId: 47e7240ffc6a8f479bedc065376fb59cd040c7c7
Change-Id: Ic272f6606454355be40276f4837ac9ee302f3266
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/5539056
Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com>
Reviewed-by: Brett Brotherton <bbrotherton@google.com>
Commit-Queue: Brett Brotherton <bbrotherton@google.com>
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 5500d27..e349d27 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -4599,6 +4599,7 @@
#define PCI_DID_INTEL_LNL_TBT_RP0 0xa84e
#define PCI_DID_INTEL_LNL_TBT_RP1 0xa84f
#define PCI_DID_INTEL_LNL_TBT_RP2 0xa860
+#define PCI_DID_INTEL_LNL_TBT_RP3 0xa837
#define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833
#define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834
@@ -4706,6 +4707,9 @@
#define PCI_DID_INTEL_LNL_PSE1 0xa863
#define PCI_DID_INTEL_LNL_PSE2 0xa864
+/* In-memory Analytics Accelerator device IDs */
+#define PCI_DID_INTEL_LNL_IAA 0x642d
+
/* Intel Crashlog */
#define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM 0x9a0d
#define PCI_DID_INTEL_ADL_CPU_CRASHLOG_SRAM 0x467d
