publish butterfly firmware
This is a snapshot from:
https://chrome-internal.googlesource.com/chromeos/third_party/coreboot
at git sha1:
ff1f4757e4bd35a6b72018d0982b5e2bec89a1bb
All files in the 3rdparty/ subdir have been stripped.
BUG=None
TEST=compiled internal repo & public repo and compared disassembled files
Change-Id: I3e78b91813138eb48db8f93e81a18eff59da08c3
Reviewed-on: https://chromium-review.googlesource.com/195360
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Mike Frysinger <vapier@chromium.org>
diff --git a/.gitignore b/.gitignore
index 8e259c7..0afef54 100644
--- a/.gitignore
+++ b/.gitignore
@@ -34,7 +34,6 @@
*.out
*.\#
*.swp
-*.bin
util/ectool/ectool
util/inteltool/.dependencies
util/inteltool/inteltool
diff --git a/Makefile.inc b/Makefile.inc
index 176ff67..7a6f028 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -19,7 +19,7 @@
#######################################################################
# misleadingly named, this is the coreboot version
-export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "`which git`" ]; then git describe --dirty; else echo unknown; fi)
+export KERNELVERSION := $(shell if [ -d "$(top)/.git" -a -f "`which git`" ]; then git describe --dirty; else echo 4.0$(KERNELREVISION); fi)
#######################################################################
# Basic component discovery
@@ -30,7 +30,7 @@
## Final build results, which CBFSTOOL uses to create the final
## rom image file, are placed under $(objcbfs).
## These typically have suffixes .debug .elf .bin and .map
-export objcbfs := $(obj)/cbfs/$(CONFIG_CBFS_PREFIX)
+export objcbfs := $(obj)/cbfs/$(call strip_quotes,$(CONFIG_CBFS_PREFIX))
## Based on the active configuration, Makefile conditionally collects
## the required assembly includes and saves them in a file.
@@ -67,6 +67,9 @@
ramstage-c-ccopts:= -finstrument-functions
endif
+ifneq ($(CONFIG_CHROMEOS),y)
+# In the ChromeOS build system we keep the 3rdparty binaries in the same
+# repository.
ifeq ($(CONFIG_USE_BLOBS),y)
forgetthis:=$(shell git submodule update --init --checkout 3rdparty)
else
@@ -74,6 +77,7 @@
$(error Your current configuration requires binary-only components, but you did not choose to use them)
endif
endif
+endif
smm-c-ccopts:=-D__SMM__
smm-S-ccopts:=-D__SMM__
@@ -178,6 +182,10 @@
printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht
printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht
+ printf "#define COREBOOT_BUILD_YEAR `LANG= date +"%-y"`\n" >> $(obj)/build.ht
+ printf "#define COREBOOT_BUILD_MONTH `LANG= date +"%-m"` \n" >> $(obj)/build.ht
+ printf "#define COREBOOT_BUILD_DAY `LANG= date +"%-d"`\n" >> $(obj)/build.ht
+ printf "#define COREBOOT_BUILD_WEEKDAY `LANG= date +"%-u"`\n" >> $(obj)/build.ht
printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht
printf "\n" >> $(obj)/build.ht
printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht
@@ -228,6 +236,7 @@
$(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR)
ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c
+romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c
$(objutil)/%.o: $(objutil)/%.c
@printf " HOSTCC $(subst $(objutil)/,,$(@))\n"
@@ -237,6 +246,10 @@
@printf " CC $(subst $(obj)/,,$(@))\n"
$(CC) -MMD $(CFLAGS) -c -o $@ $<
+$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
+ @printf " CC $(subst $(obj)/,,$(@))\n"
+ $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $<
+
#######################################################################
# Clean up rules
clean-abuild:
diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg
new file mode 100644
index 0000000..b9a7fca
--- /dev/null
+++ b/PRESUBMIT.cfg
@@ -0,0 +1,10 @@
+# This config file disables some of the ChromiumOS source style checks for
+# coreboot as they are directly conflicting with the coreboot coding
+# guidelines.
+
+[Hook Overrides]
+#stray_whitespace_check: false
+#long_line_check: false
+cros_license_check: false
+tab_check: false
+
diff --git a/configs/config.butterfly b/configs/config.butterfly
new file mode 100644
index 0000000..46e81e4
--- /dev/null
+++ b/configs/config.butterfly
@@ -0,0 +1,412 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version:
+# Sun Sep 9 20:24:03 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_USE_BLOBS=y
+CONFIG_REQUIRES_BLOB=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAL is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+CONFIG_VENDOR_GOOGLE=y
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="google/butterfly"
+CONFIG_MAINBOARD_PART_NUMBER="Butterfly"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="Hewlett-Packard"
+CONFIG_MAX_CPUS=8
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,0106"
+CONFIG_STACK_SIZE=0x8000
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xff7e0000
+CONFIG_DCACHE_RAM_SIZE=0x20000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/google/butterfly/snm_2130_coreboot.bin"
+CONFIG_BOARD_HAS_FADT=y
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1ae0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xc000
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_BOARD_GOOGLE_BUTTERFLY=y
+# CONFIG_BOARD_GOOGLE_PARROT is not set
+# CONFIG_BOARD_GOOGLE_LINK is not set
+# CONFIG_BOARD_GOOGLE_STOUT is not set
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_CACHE_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_PCI_CONF2 is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_306AX=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax"
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_MICROCODE_IN_CBFS=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE=y
+CONFIG_CACHE_MRC_SIZE_KB=512
+CONFIG_MRC_CACHE_BASE=0xff800000
+CONFIG_EXTERNAL_MRC_BLOB=y
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_HAVE_MRC=y
+CONFIG_MRC_FILE="/build/butterfly/firmware/mrc.bin"
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_C216=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+CONFIG_SERIRQ_CONTINUOUS_MODE=y
+
+#
+# Super I/O
+#
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_QUANTA_ENE_KB3940Q=y
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SMM=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_ELOG=y
+# CONFIG_ELOG_DEBUG is not set
+CONFIG_ELOG_FLASH_BASE=0x0
+CONFIG_ELOG_AREA_SIZE=0x1000
+CONFIG_ELOG_FULL_THRESHOLD=0xC00
+CONFIG_ELOG_SHRINK_SIZE=0x400
+# CONFIG_ELOG_CBMEM is not set
+CONFIG_ELOG_GSMI=y
+CONFIG_ELOG_BOOT_COUNT=y
+CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x117
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_CHROMEOS=y
+
+#
+# ChromeOS
+#
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
+CONFIG_FLASHMAP_OFFSET=0x00610000
diff --git a/configs/config.emeraldlake2 b/configs/config.emeraldlake2
new file mode 100644
index 0000000..04b275d
--- /dev/null
+++ b/configs/config.emeraldlake2
@@ -0,0 +1,394 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version:
+# Sun Sep 9 20:26:57 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_USE_BLOBS=y
+CONFIG_REQUIRES_BLOB=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAL is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+CONFIG_VENDOR_INTEL=y
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="intel/emeraldlake2"
+CONFIG_MAINBOARD_PART_NUMBER="EMERALD LAKE 2"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="Intel"
+CONFIG_MAX_CPUS=16
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,0166"
+CONFIG_STACK_SIZE=0x8000
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xff7e0000
+CONFIG_DCACHE_RAM_SIZE=0x20000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/intel/emeraldlake2/snm_2120.dat"
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_BOARD_INTEL_D810E2CB is not set
+# CONFIG_BOARD_INTEL_D945GCLF is not set
+# CONFIG_BOARD_INTEL_EAGLEHEIGHTS is not set
+CONFIG_BOARD_INTEL_EMERALDLAKE2=y
+# CONFIG_BOARD_INTEL_JARRELL is not set
+# CONFIG_BOARD_INTEL_MTARVON is not set
+# CONFIG_BOARD_INTEL_TRUXTON is not set
+# CONFIG_BOARD_INTEL_XE7501DEVKIT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_CACHE_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_PCI_CONF2 is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_306AX=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax"
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+# CONFIG_CACHE_ROM is not set
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_MICROCODE_IN_CBFS=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE=y
+CONFIG_CACHE_MRC_SIZE_KB=512
+CONFIG_MRC_CACHE_BASE=0xff800000
+CONFIG_MRC_CACHE_LOCATION=0x370000
+CONFIG_MRC_CACHE_SIZE=0x10000
+CONFIG_EXTERNAL_MRC_BLOB=y
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_HAVE_MRC=y
+CONFIG_MRC_FILE="/build/emeraldlake2/firmware/mrc.bin"
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_C216=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+# CONFIG_SERIRQ_CONTINUOUS_MODE is not set
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_SMSC_SIO1007=y
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_SMM is not set
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+# CONFIG_ELOG is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+# CONFIG_TPM is not set
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x114
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80
+# CONFIG_CHROMEOS is not set
diff --git a/configs/config.link b/configs/config.link
new file mode 100644
index 0000000..fd14193
--- /dev/null
+++ b/configs/config.link
@@ -0,0 +1,409 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version:
+# Sun Sep 9 20:23:51 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_USE_BLOBS=y
+CONFIG_REQUIRES_BLOB=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAL is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+CONFIG_VENDOR_GOOGLE=y
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="google/link"
+CONFIG_MAINBOARD_PART_NUMBER="Link"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="GOOGLE"
+CONFIG_MAX_CPUS=8
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,0166"
+CONFIG_STACK_SIZE=0x8000
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xff7e0000
+CONFIG_DCACHE_RAM_SIZE=0x20000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/google/link/snm_2137.dat"
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
+# CONFIG_BOARD_GOOGLE_PARROT is not set
+CONFIG_BOARD_GOOGLE_LINK=y
+# CONFIG_BOARD_GOOGLE_STOUT is not set
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_CACHE_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_PCI_CONF2 is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_306AX=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax"
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_MICROCODE_IN_CBFS=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE=y
+CONFIG_CACHE_MRC_SIZE_KB=512
+CONFIG_MRC_CACHE_BASE=0xff800000
+CONFIG_EXTERNAL_MRC_BLOB=y
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_HAVE_MRC=y
+CONFIG_MRC_FILE="/build/link/firmware/mrc.bin"
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_C216=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+CONFIG_SERIRQ_CONTINUOUS_MODE=y
+
+#
+# Super I/O
+#
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_GOOGLE_CHROMEEC=y
+CONFIG_EC_GOOGLE_API_ROOT="/build/link/usr/include"
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SMM=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+CONFIG_ELOG=y
+# CONFIG_ELOG_DEBUG is not set
+CONFIG_ELOG_FLASH_BASE=0x0
+CONFIG_ELOG_AREA_SIZE=0x1000
+CONFIG_ELOG_FULL_THRESHOLD=0xC00
+CONFIG_ELOG_SHRINK_SIZE=0x400
+CONFIG_ELOG_GSMI=y
+CONFIG_ELOG_BOOT_COUNT=y
+CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x161
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_CHROMEOS=y
+
+#
+# ChromeOS
+#
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
+CONFIG_FLASHMAP_OFFSET=0x00610000
diff --git a/configs/config.lumpy b/configs/config.lumpy
new file mode 100644
index 0000000..8131b03
--- /dev/null
+++ b/configs/config.lumpy
@@ -0,0 +1,401 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version:
+# Sun Sep 9 20:26:23 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_USE_BLOBS=y
+CONFIG_REQUIRES_BLOB=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAL is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+CONFIG_VENDOR_SAMSUNG=y
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="samsung/lumpy"
+CONFIG_MAINBOARD_PART_NUMBER="Lumpy"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="SAMSUNG"
+CONFIG_MAX_CPUS=8
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,0106"
+CONFIG_STACK_SIZE=0x8000
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xff7f0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/samsung/lumpy/snm_2130_coreboot.bin"
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is not set
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_SAMSUNG_LUMPY=y
+# CONFIG_BOARD_SAMSUNG_STUMPY is not set
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_CACHE_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_PCI_CONF2 is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_206AX=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax"
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_MICROCODE_IN_CBFS=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
+CONFIG_CACHE_MRC_SIZE_KB=256
+CONFIG_MRC_CACHE_BASE=0xff800000
+CONFIG_EXTERNAL_MRC_BLOB=y
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_HAVE_MRC=y
+CONFIG_MRC_FILE="/build/lumpy/firmware/mrc.bin"
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+# CONFIG_SERIRQ_CONTINUOUS_MODE is not set
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_SMSC_MEC1308=y
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_SMSC_MEC1308=y
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_SMM is not set
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+# CONFIG_ELOG is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x114
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+CONFIG_DEBUG_ACPI=y
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_INTEL_ME is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_CHROMEOS=y
+
+#
+# ChromeOS
+#
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
+CONFIG_FLASHMAP_OFFSET=0x00670000
diff --git a/configs/config.parrot b/configs/config.parrot
new file mode 100644
index 0000000..dc049002
--- /dev/null
+++ b/configs/config.parrot
@@ -0,0 +1,410 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version:
+# Sun Sep 9 20:23:34 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_USE_BLOBS=y
+CONFIG_REQUIRES_BLOB=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAL is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+CONFIG_VENDOR_GOOGLE=y
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="google/parrot"
+CONFIG_MAINBOARD_PART_NUMBER="Parrot"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="GOOGLE"
+CONFIG_MAX_CPUS=8
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,0106"
+CONFIG_STACK_SIZE=0x8000
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xff7e0000
+CONFIG_DCACHE_RAM_SIZE=0x20000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/google/parrot/snm_2130_coreboot.bin"
+CONFIG_BOARD_HAS_FADT=y
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1ae0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xc000
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
+CONFIG_BOARD_GOOGLE_PARROT=y
+# CONFIG_BOARD_GOOGLE_LINK is not set
+# CONFIG_BOARD_GOOGLE_STOUT is not set
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_CACHE_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_PCI_CONF2 is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_306AX=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax"
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_MICROCODE_IN_CBFS=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE=y
+CONFIG_CACHE_MRC_SIZE_KB=512
+CONFIG_MRC_CACHE_BASE=0xff800000
+CONFIG_EXTERNAL_MRC_BLOB=y
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_HAVE_MRC=y
+CONFIG_MRC_FILE="/build/parrot/firmware/mrc.bin"
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_C216=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+CONFIG_SERIRQ_CONTINUOUS_MODE=y
+
+#
+# Super I/O
+#
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_COMPAL_ENE932=y
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SMM=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+CONFIG_ELOG=y
+# CONFIG_ELOG_DEBUG is not set
+CONFIG_ELOG_FLASH_BASE=0x0
+CONFIG_ELOG_AREA_SIZE=0x1000
+CONFIG_ELOG_FULL_THRESHOLD=0xC00
+CONFIG_ELOG_SHRINK_SIZE=0x400
+CONFIG_ELOG_GSMI=y
+CONFIG_ELOG_BOOT_COUNT=y
+CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET=144
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x117
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_CHROMEOS=y
+
+#
+# ChromeOS
+#
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
+CONFIG_FLASHMAP_OFFSET=0x00610000
diff --git a/configs/config.stout b/configs/config.stout
new file mode 100644
index 0000000..156e551
--- /dev/null
+++ b/configs/config.stout
@@ -0,0 +1,402 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version:
+# Sun Sep 9 20:24:29 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_USE_BLOBS=y
+CONFIG_REQUIRES_BLOB=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAL is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+CONFIG_VENDOR_GOOGLE=y
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="google/stout"
+CONFIG_MAINBOARD_PART_NUMBER="Stout"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="GOOGLE"
+CONFIG_MAX_CPUS=8
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,0106"
+CONFIG_STACK_SIZE=0x8000
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xff7e0000
+CONFIG_DCACHE_RAM_SIZE=0x20000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/google/stout/snm_2137.dat"
+CONFIG_BOARD_HAS_FADT=y
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1ae0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xc000
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
+# CONFIG_BOARD_GOOGLE_PARROT is not set
+# CONFIG_BOARD_GOOGLE_LINK is not set
+CONFIG_BOARD_GOOGLE_STOUT=y
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_CACHE_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_PCI_CONF2 is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_306AX=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax"
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_MICROCODE_IN_CBFS=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE=y
+CONFIG_CACHE_MRC_SIZE_KB=512
+CONFIG_MRC_CACHE_BASE=0xff800000
+CONFIG_EXTERNAL_MRC_BLOB=y
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_HAVE_MRC=y
+CONFIG_MRC_FILE="/build/stout/firmware/mrc.bin"
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_C216=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+# CONFIG_SERIRQ_CONTINUOUS_MODE is not set
+
+#
+# Super I/O
+#
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_QUANTA_IT8518=y
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_SMM=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+# CONFIG_ELOG is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x117
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_CHROMEOS=y
+
+#
+# ChromeOS
+#
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
+CONFIG_FLASHMAP_OFFSET=0x00610000
diff --git a/configs/config.stumpy b/configs/config.stumpy
new file mode 100644
index 0000000..136bbfc
--- /dev/null
+++ b/configs/config.stumpy
@@ -0,0 +1,400 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version:
+# Sun Sep 9 20:26:41 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+CONFIG_USE_BLOBS=y
+CONFIG_REQUIRES_BLOB=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_AAEON is not set
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANSUS is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTECGROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AVALUE is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIFFEROS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAL is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DIGITALLOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+CONFIG_VENDOR_SAMSUNG=y
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="samsung/stumpy"
+CONFIG_MAINBOARD_PART_NUMBER="Stumpy"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="SAMSUNG"
+CONFIG_MAX_CPUS=8
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+CONFIG_VGA_BIOS_ID="8086,0106"
+CONFIG_STACK_SIZE=0x8000
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS=y
+# CONFIG_CONSOLE_POST is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_UDELAY_IO is not set
+CONFIG_DCACHE_RAM_BASE=0xff7f0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_VGA_BIOS_FILE="3rdparty/mainboard/samsung/stumpy/snm_2124_coreboot.bin"
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is not set
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+# CONFIG_BOARD_SAMSUNG_LUMPY is not set
+CONFIG_BOARD_SAMSUNG_STUMPY=y
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_64 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_CACHE_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+# CONFIG_AP_IN_SIPI_WAIT is not set
+# CONFIG_SIPI_VECTOR_IN_ROM is not set
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+CONFIG_IOAPIC_INTERRUPTS_ON_FSB=y
+# CONFIG_IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS is not set
+# CONFIG_PCI_CONF2 is not set
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_CPU_SPECIFIC_OPTIONS=y
+# CONFIG_CPU_AMD_AGESA is not set
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_HIGH_SCRATCH_MEMORY_SIZE=0x0
+CONFIG_CPU_INTEL_MODEL_206AX=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_MICROCODE_INCLUDE_PATH="src/cpu/intel/model_206ax"
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_UDELAY_TIMER2 is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+# CONFIG_TSC_SYNC_LFENCE is not set
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_AP_SIPI_VECTOR=0xfffff000
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_MICROCODE_IN_CBFS=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+# CONFIG_NORTHBRIDGE_AMD_AGESA is not set
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_AMD_NB_CIMX is not set
+# CONFIG_NORTHBRIDGE_AMD_CIMX_RD890 is not set
+CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
+CONFIG_CACHE_MRC_SIZE_KB=256
+CONFIG_MRC_CACHE_BASE=0xff800000
+CONFIG_EXTERNAL_MRC_BLOB=y
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_HAVE_MRC=y
+CONFIG_MRC_FILE="/build/stumpy/firmware/mrc.bin"
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+# CONFIG_AMD_SB_CIMX is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 is not set
+# CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900 is not set
+CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
+# CONFIG_SERIRQ_CONTINUOUS_MODE is not set
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_ITE_IT8772F=y
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_SPI_FLASH=y
+# CONFIG_SPI_FLASH_SMM is not set
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_NO_FAST_READ=y
+# CONFIG_ELOG is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+CONFIG_POST_PORT=0x80
+CONFIG_CMOS_POST=y
+CONFIG_CMOS_POST_OFFSET=0x70
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x114
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_ACPI is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_INTEL_ME is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_TRACE is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_ID_SECTION_OFFSET=0x80
+CONFIG_CHROMEOS=y
+
+#
+# ChromeOS
+#
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
+CONFIG_FLASHMAP_OFFSET=0x00670000
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 5486bb1..ec2b330 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -34,6 +34,12 @@
OPTION_TABLE_H:=$(obj)/option_table.h
endif
+ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
+cbfs-files-y += microcode_blob.bin
+microcode_blob.bin-file = $(obj)/microcode_blob.bin
+microcode_blob.bin-type = 0x53
+endif
+
#######################################################################
# Build the final rom image
COREBOOT_ROM_DEPENDENCIES:=
@@ -319,6 +325,10 @@
$(objcbfs)/romstage_null.debug: $$(romstage-objs) $(objgenerated)/romstage_null.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/romstage_null.ld $(romstage-objs)
+ $(NM) $@ | grep -q " [DdBb] "; if [ $$? -eq 0 ]; then \
+ echo "Forbidden global variables in romstage:"; \
+ $(NM) $@ | grep " [DdBb] "; test "$(CONFIG_CPU_AMD_AGESA)" == y; \
+ else true; fi
$(objcbfs)/romstage_xip.debug: $$(romstage-objs) $(objgenerated)/romstage_xip.ld
@printf " LINK $(subst $(obj)/,,$(@))\n"
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 6932208..20bd725 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -32,6 +32,7 @@
#include <device/pci.h>
#include <cbmem.h>
#include <cpu/x86/lapic_def.h>
+#include <cpu/cpu.h>
#if CONFIG_COLLECT_TIMESTAMPS
#include <timestamp.h>
#endif
@@ -135,7 +136,7 @@
unsigned long acpi_create_madt_lapics(unsigned long current)
{
device_t cpu;
- int cpu_index = 0;
+ int index = 0;
for (cpu = all_devices; cpu; cpu = cpu->next) {
if ((cpu->path.type != DEVICE_PATH_APIC) ||
@@ -145,8 +146,8 @@
if (!cpu->enabled)
continue;
current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current,
- cpu_index, cpu->path.apic.apic_id);
- cpu_index++;
+ index, cpu->path.apic.apic_id);
+ index++;
}
return current;
@@ -558,9 +559,19 @@
/* If we happen to be resuming find wakeup vector and jump to OS. */
wake_vec = acpi_find_wakeup_vector();
if (wake_vec) {
+ u32 *gnvs_address = cbmem_find(CBMEM_ID_ACPI_GNVS);
+
+ /* Restore GNVS pointer in SMM if found */
+ if (gnvs_address && *gnvs_address) {
+ printk(BIOS_DEBUG, "Restore GNVS pointer to 0x%08x\n",
+ *gnvs_address);
+ smm_setup_structures((void *)*gnvs_address, NULL, NULL);
+ }
+
/* Call mainboard resume handler first, if defined. */
if (mainboard_suspend_resume)
mainboard_suspend_resume();
+ post_code(POST_OS_RESUME);
acpi_jump_to_wakeup(wake_vec);
}
}
@@ -700,3 +711,10 @@
HIGH_MEMORY_SAVE);
}
#endif
+
+void acpi_save_gnvs(u32 gnvs_address)
+{
+ u32 *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+ if (gnvs)
+ *gnvs = gnvs_address;
+}
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index e7a297d..bec47fe 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -394,6 +394,32 @@
return len;
}
+/* generates a func with max supported P states */
+int acpigen_write_PPC_NVS(void)
+{
+/*
+ Method (_PPC, 0, NotSerialized)
+ {
+ Return (PPCM)
+ }
+*/
+ int len;
+ /* method op */
+ acpigen_emit_byte(0x14);
+ len = acpigen_write_len_f();
+ len += acpigen_emit_namestring("_PPC");
+ /* no fnarg */
+ acpigen_emit_byte(0x00);
+ /* return */
+ acpigen_emit_byte(0xa4);
+ /* arg */
+ len += acpigen_emit_namestring("PPCM");
+ /* add all single bytes */
+ len += 3;
+ acpigen_patch_len(len - 1);
+ return len;
+}
+
int acpigen_write_TPC(const char *gnvs_tpc_limit)
{
/*
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index f39bf04..313b680 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -29,6 +29,7 @@
#include <cpu/x86/name.h>
#include <cbfs_core.h>
#include <arch/byteorder.h>
+#include <elog.h>
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/gnvs.h>
#endif
@@ -296,6 +297,9 @@
len += smbios_write_type1(¤t, handle++);
len += smbios_write_type3(¤t, handle++);
len += smbios_write_type4(¤t, handle++);
+#if CONFIG_ELOG
+ len += elog_smbios_write_type15(¤t, handle++);
+#endif
len += smbios_write_type32(¤t, handle++);
len += smbios_walk_device_tree(all_devices, &handle, ¤t);
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 9f790cc..97afa1b 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -500,6 +500,7 @@
void *acpi_find_wakeup_vector(void);
void *acpi_get_wakeup_rsdp(void);
void acpi_jump_to_wakeup(void *wakeup_addr);
+void acpi_save_gnvs(u32 gnvs_address);
int acpi_get_sleep_type(void);
#else /* CONFIG_HAVE_ACPI_RESUME */
@@ -519,8 +520,4 @@
#endif /* CONFIG_GENERATE_ACPI_TABLES */
-#if CONFIG_CHROMEOS
-void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size);
-#endif /* CONFIG_CHROMEOS */
-
#endif /* __ASM_ACPI_H */
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index aebf508..5297aff 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -42,6 +42,7 @@
int acpigen_write_name_byte(const char *name, uint8_t val);
int acpigen_write_scope(const char *name);
int acpigen_write_PPC(u8 nr);
+int acpigen_write_PPC_NVS(void);
int acpigen_write_empty_PCT(void);
int acpigen_write_empty_PTC(void);
int acpigen_write_TPC(const char *gnvs_tpc_limit);
diff --git a/src/arch/x86/include/arch/cbfs.h b/src/arch/x86/include/arch/cbfs.h
index 635ff10..8a61d6e 100644
--- a/src/arch/x86/include/arch/cbfs.h
+++ b/src/arch/x86/include/arch/cbfs.h
@@ -1,3 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __INCLUDE_ARCH_CBFS__
+#define __INCLUDE_ARCH_CBFS__
+
static void *walkcbfs(char *target)
{
void *entry;
@@ -23,4 +45,4 @@
{
asm volatile ("jmp *%0\n\t" : : "r" (addr), "a" (bist));
}
-
+#endif
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 0dc92fb..aa0412f 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -160,7 +160,7 @@
struct cpu_info {
device_t cpu;
- unsigned long index;
+ unsigned int index;
};
static inline struct cpu_info *cpu_info(void)
diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h
index 955ccd3..eca9390 100644
--- a/src/arch/x86/include/arch/pci_ops.h
+++ b/src/arch/x86/include/arch/pci_ops.h
@@ -2,12 +2,18 @@
#define ARCH_I386_PCI_OPS_H
extern const struct pci_bus_operations pci_cf8_conf1;
-extern const struct pci_bus_operations pci_cf8_conf2;
#if CONFIG_MMCONF_SUPPORT
extern const struct pci_bus_operations pci_ops_mmconf;
#endif
-void pci_set_method(device_t dev);
+static inline const struct pci_bus_operations *pci_config_default(void)
+{
+ return &pci_cf8_conf1;
+}
+static inline void pci_set_method(device_t dev)
+{
+ dev->ops->ops_pci_bus = pci_config_default();
+}
#endif /* ARCH_I386_PCI_OPS_H */
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index bd19682..c9674f4 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -34,3 +34,27 @@
}
}
#endif
+
+#if CONFIG_CMOS_POST
+#include <pc80/mc146818rtc.h>
+
+static void cmos_post_init(void)
+{
+ u8 magic = CMOS_POST_BANK_0_MAGIC;
+
+ /* Switch to the other bank */
+ switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
+ case CMOS_POST_BANK_1_MAGIC:
+ break;
+ case CMOS_POST_BANK_0_MAGIC:
+ magic = CMOS_POST_BANK_1_MAGIC;
+ break;
+ default:
+ /* Initialize to zero */
+ cmos_write(0, CMOS_POST_BANK_0_OFFSET);
+ cmos_write(0, CMOS_POST_BANK_1_OFFSET);
+ }
+
+ cmos_write(magic, CMOS_POST_BANK_OFFSET);
+}
+#endif
diff --git a/src/arch/x86/include/stddef.h b/src/arch/x86/include/stddef.h
index e4fc019..fc89de5 100644
--- a/src/arch/x86/include/stddef.h
+++ b/src/arch/x86/include/stddef.h
@@ -2,7 +2,10 @@
#define I386_STDDEF_H
typedef long ptrdiff_t;
-typedef unsigned long size_t;
+#ifndef __SIZE_TYPE__
+#define __SIZE_TYPE__ unsigned long
+#endif
+typedef __SIZE_TYPE__ size_t;
typedef long ssize_t;
typedef int wchar_t;
@@ -12,4 +15,10 @@
#define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
+#ifdef __PRE_RAM__
+#define ROMSTAGE_CONST const
+#else
+#define ROMSTAGE_CONST
+#endif
+
#endif /* I386_STDDEF_H */
diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index ca4e820..7245794 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -53,5 +53,4 @@
}
_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
- _bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_CPU_AMD_AGESA, "Do not use global variables in romstage");
}
diff --git a/src/arch/x86/init/bootblock_simple.c b/src/arch/x86/init/bootblock_simple.c
index 41f73b4..fd9ba22 100644
--- a/src/arch/x86/init/bootblock_simple.c
+++ b/src/arch/x86/init/bootblock_simple.c
@@ -10,6 +10,9 @@
#if CONFIG_USE_OPTION_TABLE
sanitize_cmos();
#endif
+#if CONFIG_CMOS_POST
+ cmos_post_init();
+#endif
}
const char* target1 = "fallback/romstage";
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 4375952..2186072 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -3,7 +3,6 @@
ramstage-y += pci_ops_conf1.c
ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
-ramstage-y += pci_ops_auto.c
ramstage-y += exception.c
ramstage-$(CONFIG_IOAPIC) += ioapic.c
ramstage-y += memset.c
diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S
index 005ac33..7ac94a9 100644
--- a/src/arch/x86/lib/c_start.S
+++ b/src/arch/x86/lib/c_start.S
@@ -16,17 +16,19 @@
post_code(POST_ENTRY_C_START) /* post 13 */
- /** clear stack */
+ /** poison the stack. Code should not count on the
+ * stack being full of zeros.
+ */
cld
leal _stack, %edi
movl $_estack, %ecx
subl %edi, %ecx
shrl $2, %ecx /* it is 32 bit aligned, right? */
- xorl %eax, %eax
+ movl $0xDEADBEEF, %eax
rep
stosl
- /** clear bss */
+ /** clear bss, which is zero by definition */
leal _bss, %edi
movl $_ebss, %ecx
subl %edi, %ecx
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 98ede06..be8e38d 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -234,7 +234,7 @@
cpu->ops = driver ? driver->ops : NULL;
}
-void cpu_initialize(void)
+void cpu_initialize(unsigned int index)
{
/* Because we busy wait at the printk spinlock.
* It is important to keep the number of printed messages
@@ -247,7 +247,7 @@
info = cpu_info();
- printk(BIOS_INFO, "Initializing CPU #%ld\n", info->index);
+ printk(BIOS_INFO, "Initializing CPU #%d\n", index);
cpu = info->cpu;
if (!cpu) {
@@ -284,7 +284,7 @@
cpu->ops->init(cpu);
}
- printk(BIOS_INFO, "CPU #%ld initialized\n", info->index);
+ printk(BIOS_INFO, "CPU #%d initialized\n", index);
return;
}
diff --git a/src/arch/x86/lib/pci_ops_auto.c b/src/arch/x86/lib/pci_ops_auto.c
deleted file mode 100644
index 58e098b..0000000
--- a/src/arch/x86/lib/pci_ops_auto.c
+++ /dev/null
@@ -1,107 +0,0 @@
-#include <stddef.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pciconf.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-
-#if CONFIG_PCI_CONF2
-/*
- * Before we decide to use direct hardware access mechanisms, we try to do some
- * trivial checks to ensure it at least _seems_ to be working -- we just test
- * whether bus 00 contains a host bridge (this is similar to checking
- * techniques used in XFree86, but ours should be more reliable since we
- * attempt to make use of direct access hints provided by the PCI BIOS).
- *
- * This should be close to trivial, but it isn't, because there are buggy
- * chipsets (yes, you guessed it, by Intel and Compaq) that have no class ID.
- */
-static int pci_sanity_check(const struct pci_bus_operations *o)
-{
- uint16_t class, vendor;
- unsigned bus;
- int devfn;
- struct bus pbus; /* Dummy device */
-#define PCI_CLASS_BRIDGE_HOST 0x0600
-#define PCI_CLASS_DISPLAY_VGA 0x0300
-#define PCI_VENDOR_ID_COMPAQ 0x0e11
-#define PCI_VENDOR_ID_INTEL 0x8086
-#define PCI_VENDOR_ID_MOTOROLA 0x1057
-
- for (bus = 0, devfn = 0; devfn < 0x100; devfn++) {
- class = o->read16(&pbus, bus, devfn, PCI_CLASS_DEVICE);
- vendor = o->read16(&pbus, bus, devfn, PCI_VENDOR_ID);
- if (((class == PCI_CLASS_BRIDGE_HOST) || (class == PCI_CLASS_DISPLAY_VGA)) ||
- ((vendor == PCI_VENDOR_ID_INTEL) || (vendor == PCI_VENDOR_ID_COMPAQ) ||
- (vendor == PCI_VENDOR_ID_MOTOROLA))) {
- return 1;
- }
- }
- printk(BIOS_ERR, "PCI: Sanity check failed\n");
- return 0;
-}
-
-static struct pci_bus_operations *pci_bus_fallback_ops = NULL;
-
-static const struct pci_bus_operations *pci_check_direct(void)
-{
- unsigned int tmp;
-
- /*
- * Check if configuration type 1 works.
- */
- {
- outb(0x01, 0xCFB);
- tmp = inl(0xCF8);
- outl(0x80000000, 0xCF8);
- if ((inl(0xCF8) == 0x80000000) &&
- pci_sanity_check(&pci_cf8_conf1))
- {
- outl(tmp, 0xCF8);
- printk(BIOS_DEBUG, "PCI: Using configuration type 1\n");
- return &pci_cf8_conf1;
- }
- outl(tmp, 0xCF8);
- }
-
- /*
- * Check if configuration type 2 works.
- */
- {
- outb(0x00, 0xCFB);
- outb(0x00, 0xCF8);
- outb(0x00, 0xCFA);
- if ((inb(0xCF8) == 0x00 && inb(0xCFA) == 0x00) &&
- pci_sanity_check(&pci_cf8_conf2))
- {
- printk(BIOS_DEBUG, "PCI: Using configuration type 2\n");
- return &pci_cf8_conf2;
- }
- }
-
- die("pci_check_direct failed\n");
- return NULL;
-}
-
-const struct pci_bus_operations *pci_remember_direct(void)
-{
- if (!pci_bus_fallback_ops)
- pci_bus_fallback_ops = (struct pci_bus_operations *)pci_check_direct();
- return pci_bus_fallback_ops;
-}
-#else
-const struct pci_bus_operations *pci_remember_direct(void)
-{
- return &pci_cf8_conf1;
-}
-#endif
-
-/** Set the method to be used for PCI, type I or type II
- */
-void pci_set_method(device_t dev)
-{
- printk(BIOS_INFO, "Finding PCI configuration type.\n");
- dev->ops->ops_pci_bus = pci_remember_direct();
- post_code(0x5f);
-}
diff --git a/src/arch/x86/lib/pci_ops_conf2.c b/src/arch/x86/lib/pci_ops_conf2.c
deleted file mode 100644
index e89c933..0000000
--- a/src/arch/x86/lib/pci_ops_conf2.c
+++ /dev/null
@@ -1,80 +0,0 @@
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pciconf.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-/*
- * Functions for accessing PCI configuration space with type 2 accesses
- */
-
-#define IOADDR(devfn, where) ((0xC000 | ((devfn & 0x78) << 5)) + where)
-#define FUNC(devfn) (((devfn & 7) << 1) | 0xf0)
-#define SET(bus,devfn) outb(FUNC(devfn), 0xCF8); outb(bus, 0xCFA);
-
-static uint8_t pci_conf2_read_config8(struct bus *pbus, int bus, int devfn,
- int where)
-{
- uint8_t value;
- SET(bus, devfn);
- value = inb(IOADDR(devfn, where));
- outb(0, 0xCF8);
- return value;
-}
-
-static uint16_t pci_conf2_read_config16(struct bus *pbus, int bus, int devfn,
- int where)
-{
- uint16_t value;
- SET(bus, devfn);
- value = inw(IOADDR(devfn, where));
- outb(0, 0xCF8);
- return value;
-}
-
-static uint32_t pci_conf2_read_config32(struct bus *pbus, int bus, int devfn,
- int where)
-{
- uint32_t value;
- SET(bus, devfn);
- value = inl(IOADDR(devfn, where));
- outb(0, 0xCF8);
- return value;
-}
-
-static void pci_conf2_write_config8(struct bus *pbus, int bus, int devfn,
- int where, uint8_t value)
-{
- SET(bus, devfn);
- outb(value, IOADDR(devfn, where));
- outb(0, 0xCF8);
-}
-
-static void pci_conf2_write_config16(struct bus *pbus, int bus, int devfn,
- int where, uint16_t value)
-{
- SET(bus, devfn);
- outw(value, IOADDR(devfn, where));
- outb(0, 0xCF8);
-}
-
-static void pci_conf2_write_config32(struct bus *pbus, int bus, int devfn,
- int where, uint32_t value)
-{
- SET(bus, devfn);
- outl(value, IOADDR(devfn, where));
- outb(0, 0xCF8);
-}
-
-#undef SET
-#undef IOADDR
-#undef FUNC
-
-const struct pci_bus_operations pci_cf8_conf2 = {
- .read8 = pci_conf2_read_config8,
- .read16 = pci_conf2_read_config16,
- .read32 = pci_conf2_read_config32,
- .write8 = pci_conf2_write_config8,
- .write16 = pci_conf2_write_config16,
- .write32 = pci_conf2_write_config32,
-};
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index 25eda9b..78a8aec 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -29,7 +29,7 @@
#include <console/ne2k.h>
#endif
-static void console_tx_byte(unsigned char byte)
+void console_tx_byte(unsigned char byte)
{
if (byte == '\n')
console_tx_byte('\r');
@@ -54,7 +54,7 @@
#endif
}
-static void console_tx_flush(void)
+void console_tx_flush(void)
{
#if CONFIG_CONSOLE_SERIAL8250MEM
uart8250_mem_tx_flush(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000);
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index d78b859..27edc1a 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -35,6 +35,7 @@
#include <boot/tables.h>
#include <boot/elf.h>
#include <cbfs.h>
+#include <lib.h>
#if CONFIG_HAVE_ACPI_RESUME
#include <arch/acpi.h>
#endif
@@ -101,13 +102,14 @@
#endif
/* Now actually enable devices on the bus */
dev_enable();
+ post_code(POST_DEVICES_ENABLED);
#if CONFIG_COLLECT_TIMESTAMPS
timestamps[4] = rdtsc();
#endif
/* And of course initialize devices on the bus */
dev_initialize();
- post_code(POST_DEVICES_ENABLED);
+ post_code(POST_DEVICES_INITIALIZED);
#if CONFIG_COLLECT_TIMESTAMPS
timestamps[5] = rdtsc();
@@ -143,7 +145,19 @@
lb_mem = write_tables();
timestamp_add_now(TS_LOAD_PAYLOAD);
- cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
- printk(BIOS_ERR, "Boot failed.\n");
+
+ void *payload;
+ payload = cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
+ if (! payload)
+ die("Could not find a payload\n");
+
+ printk(BIOS_DEBUG, "Got a payload\n");
+ /* Before we go off to run the payload, see if
+ * we stayed within our bounds.
+ */
+ checkstack(&_estack, 0);
+
+ selfboot(lb_mem, payload);
+ printk(BIOS_EMERG, "Boot failed");
}
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index 3c31023..fd5b382 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -494,7 +494,7 @@
return 1;
}
-static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
+int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
{
u32 entry=0;
struct segment head;
@@ -532,13 +532,7 @@
struct cbfs_payload *payload;
payload = (struct cbfs_payload *)cbfs_find_file(name, CBFS_TYPE_PAYLOAD);
- if (payload == NULL)
- return (void *) -1;
- printk(BIOS_DEBUG, "Got a payload\n");
- selfboot(lb_mem, payload);
- printk(BIOS_EMERG, "SELFBOOT RETURNED!\n");
-
- return (void *) -1;
+ return payload;
}
diff --git a/src/console/Kconfig b/src/console/Kconfig
index f1129a1..c1c2012 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -373,5 +373,23 @@
usually displayed using a so-called "POST card" ISA/PCI/PCI-E
device) on the debug console.
+config CMOS_POST
+ bool "Store post codes in CMOS for debugging"
+ depends on !NO_POST
+ default n
+ help
+ If enabled, coreboot will store post codes in CMOS and switch between
+ two offsets on each boot so the last post code in the previous boot
+ can be retrieved. This uses 3 bytes of CMOS.
+
+config CMOS_POST_OFFSET
+ hex "Offset into CMOS to store POST codes"
+ depends on CMOS_POST
+ default 0
+ help
+ If CMOS_POST is enabled then an offset into CMOS must be provided.
+ If CONFIG_HAVE_OPTION_TABLE is enabled then it will use the value
+ defined in the mainboard option table.
+
endmenu
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index f3b8758..f8928ad 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -7,6 +7,7 @@
smm-y += printk.c
smm-y += vtxprintf.c
+smm-$(CONFIG_SMM_TSEG) += die.c
romstage-y += vtxprintf.c
romstage-$(CONFIG_CACHE_AS_RAM) += console.c
diff --git a/src/console/post.c b/src/console/post.c
index 08336a2..27f1692 100644
--- a/src/console/post.c
+++ b/src/console/post.c
@@ -21,9 +21,67 @@
#include <arch/io.h>
#include <console/console.h>
+#include <pc80/mc146818rtc.h>
+#include <elog.h>
/* Write POST information */
+/* Some mainboards have very nice features beyond just a simple
+ * display. They can override this function.
+ */
+void __attribute__((weak)) mainboard_post(uint8_t value)
+{
+}
+
+#if CONFIG_CMOS_POST
+
+#if !defined(__PRE_RAM__)
+void cmos_post_log(void)
+{
+ u8 code;
+
+ /* Get post code from other bank */
+ switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
+ case CMOS_POST_BANK_0_MAGIC:
+ code = cmos_read(CMOS_POST_BANK_1_OFFSET);
+ break;
+ case CMOS_POST_BANK_1_MAGIC:
+ code = cmos_read(CMOS_POST_BANK_0_OFFSET);
+ break;
+ default:
+ return;
+ }
+
+ /* Check last post code in previous boot against normal list */
+ switch (code) {
+ case POST_OS_BOOT:
+ case POST_OS_RESUME:
+ case POST_ENTER_ELF_BOOT:
+ case 0:
+ break;
+ default:
+ printk(BIOS_WARNING, "POST: Unexpected post code "
+ "in previous boot: 0x%02x\n", code);
+#if CONFIG_ELOG
+ elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
+#endif
+ }
+}
+#endif /* !__PRE_RAM__ */
+
+static void cmos_post_code(u8 value)
+{
+ switch (cmos_read(CMOS_POST_BANK_OFFSET)) {
+ case CMOS_POST_BANK_0_MAGIC:
+ cmos_write(value, CMOS_POST_BANK_0_OFFSET);
+ break;
+ case CMOS_POST_BANK_1_MAGIC:
+ cmos_write(value, CMOS_POST_BANK_1_OFFSET);
+ break;
+ }
+}
+#endif /* CONFIG_CMOS_POST */
+
void post_code(uint8_t value)
{
#if !CONFIG_NO_POST
@@ -32,6 +90,10 @@
print_emerg_hex8(value);
print_emerg("\n");
#endif
+#if CONFIG_CMOS_POST
+ cmos_post_code(value);
+#endif
outb(value, CONFIG_POST_PORT);
+ mainboard_post(value);
#endif
}
diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c
index 923df99..ed77237 100644
--- a/src/console/uart8250mem_console.c
+++ b/src/console/uart8250mem_console.c
@@ -23,7 +23,7 @@
static u32 uart_bar = 0;
-static void uartmem_init(void)
+void uartmem_init(void)
{
uart_bar = uart_mem_init();
}
diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index a370e5f..28c5a60 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
@@ -170,7 +170,7 @@
/* get the conversion qualifier */
qualifier = -1;
- if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L') {
+ if (*fmt == 'h' || *fmt == 'l' || *fmt == 'L' || *fmt == 'z') {
qualifier = *fmt;
++fmt;
if (*fmt == 'l') {
@@ -218,7 +218,6 @@
field_width, precision, flags);
continue;
-
case 'n':
if (qualifier == 'L') {
long long *ip = va_arg(args, long long *);
@@ -265,6 +264,8 @@
num = va_arg(args, unsigned long long);
} else if (qualifier == 'l') {
num = va_arg(args, unsigned long);
+ } else if (qualifier == 'z') {
+ num = va_arg(args, size_t);
} else if (qualifier == 'h') {
num = (unsigned short) va_arg(args, int);
if (flags & SIGN)
diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig
index acb9bb5..c48ee80 100644
--- a/src/cpu/Kconfig
+++ b/src/cpu/Kconfig
@@ -23,6 +23,7 @@
# yet be dropped completely.
config MAX_PHYSICAL_CPUS
int
+ depends on CPU_AMD_MODEL_10XXX || CPU_AMD_MODEL_FXX || CPU_AMD_AGESA
default 1
config SMP
@@ -68,4 +69,10 @@
Unset this if you don't want the MTRR code to use
subtractive MTRRs
+config MICROCODE_IN_CBFS
+ bool "Look for microcode in CBFS"
+ default n
+ help
+ Send coreboot debug output to a memory mapped serial port console.
+
endif # ARCH_X86
diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig
index 18f74e8..b3f895f 100644
--- a/src/cpu/amd/agesa/Kconfig
+++ b/src/cpu/amd/agesa/Kconfig
@@ -24,6 +24,7 @@
default y if CPU_AMD_AGESA_FAMILY14
default y if CPU_AMD_AGESA_FAMILY15
default n
+ select TSC_SYNC_LFENCE
if CPU_AMD_AGESA
diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c
index 16c959a..cae7e4e 100644
--- a/src/cpu/amd/agesa/s3_resume.c
+++ b/src/cpu/amd/agesa/s3_resume.c
@@ -29,7 +29,9 @@
#endif
#include <device/device.h>
#include <device/pci.h>
+#ifndef __PRE_RAM__
#include <device/pci_ops.h>
+#endif
#include <arch/io.h>
#include <arch/acpi.h>
#include <string.h>
diff --git a/src/cpu/amd/model_10xxx/Kconfig b/src/cpu/amd/model_10xxx/Kconfig
index 221d044..0890771 100644
--- a/src/cpu/amd/model_10xxx/Kconfig
+++ b/src/cpu/amd/model_10xxx/Kconfig
@@ -3,6 +3,7 @@
select SSE
select SSE2
select MMCONF_SUPPORT_DEFAULT
+ select TSC_SYNC_LFENCE
if CPU_AMD_MODEL_10XXX
config CPU_ADDR_BITS
diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig
index e04605b..0afc4b0 100644
--- a/src/cpu/amd/model_fxx/Kconfig
+++ b/src/cpu/amd/model_fxx/Kconfig
@@ -3,6 +3,7 @@
select MMX
select SSE
select SSE2
+ select TSC_SYNC_LFENCE
if CPU_AMD_MODEL_FXX
config UDELAY_IO
diff --git a/src/cpu/intel/microcode/Makefile.inc b/src/cpu/intel/microcode/Makefile.inc
index 6631019..f4d0102 100644
--- a/src/cpu/intel/microcode/Makefile.inc
+++ b/src/cpu/intel/microcode/Makefile.inc
@@ -1 +1,15 @@
ramstage-y += microcode.c
+
+
+ifeq ($(CONFIG_MICROCODE_IN_CBFS),y)
+
+SRC_PATH = src/cpu/intel/microcode
+FLAGS = -I $(CONFIG_MICROCODE_INCLUDE_PATH) -include $(obj)/config.h
+$(obj)/microcode_blob.o: $(SRC_PATH)/microcode_blob.c
+ $(CC) $(FLAGS) -MMD -c -o $@ $<
+
+$(obj)/microcode_blob.bin: $(obj)/microcode_blob.o
+ objcopy -j .data -O binary $< $@
+
+-include $(obj)/microcode_blob.d
+endif
diff --git a/src/cpu/intel/microcode/microcode.c b/src/cpu/intel/microcode/microcode.c
index ec42fb9..e84bad9 100644
--- a/src/cpu/intel/microcode/microcode.c
+++ b/src/cpu/intel/microcode/microcode.c
@@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2000 Ronald G. Minnich
*
* This program is free software; you can redistribute it and/or modify
@@ -27,6 +28,14 @@
#include <cpu/x86/msr.h>
#include <cpu/intel/microcode.h>
+#if CONFIG_MICROCODE_IN_CBFS
+#ifdef __PRE_RAM__
+#include <arch/cbfs.h>
+#else
+#include <cbfs.h>
+#endif
+#endif
+
struct microcode {
u32 hdrver; /* Header Version */
u32 rev; /* Update Revision */
@@ -68,6 +77,9 @@
return msr.hi;
}
+#if CONFIG_MICROCODE_IN_CBFS
+static
+#endif
void intel_update_microcode(const void *microcode_updates)
{
u32 eax;
@@ -115,8 +127,8 @@
#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "microcode: updated to revision "
"0x%x date=%04x-%02x-%02x\n", new_rev,
- m->date & 0xffff, (m->date >> 16) & 0xff,
- (m->date >> 24) & 0xff);
+ m->date & 0xffff, (m->date >> 24) & 0xff,
+ (m->date >> 16) & 0xff);
#endif
break;
}
@@ -131,3 +143,21 @@
}
}
}
+
+#if CONFIG_MICROCODE_IN_CBFS
+
+#define MICROCODE_CBFS_FILE "microcode_blob.bin"
+
+void intel_update_microcode_from_cbfs(void)
+{
+ void *microcode_blob;
+
+#ifdef __PRE_RAM__
+ microcode_blob = walkcbfs((char *) MICROCODE_CBFS_FILE);
+#else
+ microcode_blob = cbfs_find_file(MICROCODE_CBFS_FILE,
+ CBFS_TYPE_MICROCODE);
+#endif
+ intel_update_microcode(microcode_blob);
+}
+#endif
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/cpu/intel/microcode/microcode_blob.c
similarity index 84%
rename from src/mainboard/intel/eagleheights/chip.h
rename to src/cpu/intel/microcode/microcode_blob.c
index 3ae8657..69238a9 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/cpu/intel/microcode/microcode_blob.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
+unsigned microcode[] = {
+#include <microcode_blob.h>
+};
diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index b079922..852c9cd 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -2,3 +2,4 @@
bool
select SMP
select SSE2
+ select TSC_SYNC_MFENCE
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 09449cb..ce4957d 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -4,3 +4,4 @@
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
+ select TSC_SYNC_MFENCE
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
index c11f21a..6635868 100644
--- a/src/cpu/intel/model_206ax/Kconfig
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -12,7 +12,9 @@
select SSE2
select UDELAY_LAPIC
select SMM_TSEG
+ select MICROCODE_IN_CBFS
#select AP_IN_SIPI_WAIT
+ select TSC_SYNC_MFENCE
config BOOTBLOCK_CPU_INIT
string
@@ -26,28 +28,7 @@
hex
default 0x800000
-config ENABLE_VMX
- bool "Enable VMX for virtualization"
- default n
-
-endif
-
-if CPU_INTEL_MODEL_206AX
- config CPU_MODEL_NAME
+config MICROCODE_INCLUDE_PATH
string
- default "Intel SandyBridge CPU"
-
- config CPU_MODEL_INDEX
- hex
- default 0x2a
-endif
-
-if CPU_INTEL_MODEL_306AX
- config CPU_MODEL_NAME
- string
- default "Intel IvyBridge CPU"
-
- config CPU_MODEL_INDEX
- hex
- default 0x3a
+ default "src/cpu/intel/model_206ax"
endif
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
index 1a8ceb7..c8c30a4 100644
--- a/src/cpu/intel/model_206ax/acpi.c
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -44,15 +44,8 @@
if (c.x86 != 6)
return 1;
- switch (c.x86_model) {
- case CONFIG_CPU_MODEL_INDEX:
- result = cpuid_ext(0xb, 1);
- cores = result.ebx & 0xff;
- break;
- default:
- cores = (cpuid_ebx(1) >> 16) & 0xff;
- break;
- }
+ result = cpuid_ext(0xb, 1);
+ cores = result.ebx & 0xff;
return cores;
}
@@ -85,7 +78,7 @@
length += acpigen_write_CST_package_entry(&cstates[c2]);
}
if (c3 > 0) {
- cstates[c2].ctype = 2;
+ cstates[c3].ctype = 3;
length += acpigen_write_CST_package_entry(&cstates[c3]);
}
@@ -235,7 +228,16 @@
/* Get bus ratio limits and calculate clock speeds */
msr = rdmsr(MSR_PLATFORM_INFO);
ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
- ratio_max = (msr.lo >> 8) & 0xff; /* Max Non-Turbo Ratio */
+
+ /* Determine if this CPU has configurable TDP */
+ if (cpu_config_tdp_levels()) {
+ /* Set max ratio to nominal TDP ratio */
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ ratio_max = msr.lo & 0xff;
+ } else {
+ /* Max Non-Turbo Ratio */
+ ratio_max = (msr.lo >> 8) & 0xff;
+ }
clock_max = ratio_max * SANDYBRIDGE_BCLK;
/* Calculate CPU TDP in mW */
@@ -248,7 +250,7 @@
len = acpigen_write_empty_PCT();
/* Write _PPC with no limit on supported P-state */
- len += acpigen_write_PPC(0);
+ len += acpigen_write_PPC_NVS();
/* Write PSD indicating configured coordination type */
len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
@@ -359,5 +361,5 @@
}
struct chip_operations cpu_intel_model_206ax_ops = {
- CHIP_NAME(CONFIG_CPU_MODEL_NAME)
+ CHIP_NAME("Intel SandyBridge/IvyBridge CPU")
};
diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl
index a9d5eeb..558a9d3 100644
--- a/src/cpu/intel/model_206ax/acpi/cpu.asl
+++ b/src/cpu/intel/model_206ax/acpi/cpu.asl
@@ -33,29 +33,40 @@
Method (PNOT)
{
If (LGreaterEqual (\PCNT, 2)) {
- Notify (\_PR.CPU0, 0x80) // _PPC
Notify (\_PR.CPU0, 0x81) // _CST
- Notify (\_PR.CPU1, 0x80) // _PPC
Notify (\_PR.CPU1, 0x81) // _CST
}
If (LGreaterEqual (\PCNT, 4)) {
- Notify (\_PR.CPU2, 0x80) // _PPC
Notify (\_PR.CPU2, 0x81) // _CST
- Notify (\_PR.CPU3, 0x80) // _PPC
Notify (\_PR.CPU3, 0x81) // _CST
}
If (LGreaterEqual (\PCNT, 8)) {
- Notify (\_PR.CPU4, 0x80) // _PPC
Notify (\_PR.CPU4, 0x81) // _CST
- Notify (\_PR.CPU5, 0x80) // _PPC
Notify (\_PR.CPU5, 0x81) // _CST
- Notify (\_PR.CPU6, 0x80) // _PPC
Notify (\_PR.CPU6, 0x81) // _CST
- Notify (\_PR.CPU7, 0x80) // _PPC
Notify (\_PR.CPU7, 0x81) // _CST
}
}
+/* Notify OS to re-read CPU _PPC limit, assuming ^2 CPU count */
+Method (PPCN)
+{
+ If (LGreaterEqual (\PCNT, 2)) {
+ Notify (\_PR.CPU0, 0x80) // _PPC
+ Notify (\_PR.CPU1, 0x80) // _PPC
+ }
+ If (LGreaterEqual (\PCNT, 4)) {
+ Notify (\_PR.CPU2, 0x80) // _PPC
+ Notify (\_PR.CPU3, 0x80) // _PPC
+ }
+ If (LGreaterEqual (\PCNT, 8)) {
+ Notify (\_PR.CPU4, 0x80) // _PPC
+ Notify (\_PR.CPU5, 0x80) // _PPC
+ Notify (\_PR.CPU6, 0x80) // _PPC
+ Notify (\_PR.CPU7, 0x80) // _PPC
+ }
+}
+
/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
Method (TNOT)
{
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
index 9549d23..02958bb 100644
--- a/src/cpu/intel/model_206ax/bootblock.c
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -22,12 +22,18 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
-
-static const uint32_t microcode_updates[] = {
- #include "x06_microcode.h"
-};
+#include <arch/io.h>
+#include <arch/romcc_io.h>
#include <cpu/intel/microcode/microcode.c>
+#include "model_206ax.h"
+
+#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X || CONFIG_SOUTHBRIDGE_INTEL_C216
+/* Needed for RCBA access to set Soft Reset Data register */
+#include <southbridge/intel/bd82x6x/pch.h>
+#else
+#error "CPU must be paired with Intel BD82X6X or C216 southbridge"
+#endif
static void set_var_mtrr(
unsigned reg, unsigned base, unsigned size, unsigned type)
@@ -58,8 +64,60 @@
wrmsr(MTRRdefType_MSR, msr);
}
+static void set_flex_ratio_to_tdp_nominal(void)
+{
+ msr_t flex_ratio, msr;
+ u32 soft_reset;
+ u8 nominal_ratio;
+
+ /* Minimum CPU revision for configurable TDP support */
+ if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
+ return;
+
+ /* Check for Flex Ratio support */
+ flex_ratio = rdmsr(MSR_FLEX_RATIO);
+ if (!(flex_ratio.lo & FLEX_RATIO_EN))
+ return;
+
+ /* Check for >0 configurable TDPs */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if (((msr.hi >> 1) & 3) == 0)
+ return;
+
+ /* Use nominal TDP ratio for flex ratio */
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ nominal_ratio = msr.lo & 0xff;
+
+ /* See if flex ratio is already set to nominal TDP ratio */
+ if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio)
+ return;
+
+ /* Set flex ratio to nominal TDP ratio */
+ flex_ratio.lo &= ~0xff00;
+ flex_ratio.lo |= nominal_ratio << 8;
+ flex_ratio.lo |= FLEX_RATIO_LOCK;
+ wrmsr(MSR_FLEX_RATIO, flex_ratio);
+
+ /* Set flex ratio in soft reset data register bits 11:6.
+ * RCBA region is enabled in southbridge bootblock */
+ soft_reset = RCBA32(SOFT_RESET_DATA);
+ soft_reset &= ~(0x3f << 6);
+ soft_reset |= (nominal_ratio & 0x3f) << 6;
+ RCBA32(SOFT_RESET_DATA) = soft_reset;
+
+ /* Set soft reset control to use register value */
+ RCBA32_OR(SOFT_RESET_CTRL, 1);
+
+ /* Issue warm reset, will be "CPU only" due to soft reset data */
+ outb(0x0, 0xcf9);
+ outb(0x6, 0xcf9);
+ asm("hlt");
+}
+
static void bootblock_cpu_init(void)
{
+ /* Set flex ratio and reset if needed */
+ set_flex_ratio_to_tdp_nominal();
enable_rom_caching();
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
}
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h
index 48e0c89..96b4c5d 100644
--- a/src/cpu/intel/model_206ax/chip.h
+++ b/src/cpu/intel/model_206ax/chip.h
@@ -34,4 +34,6 @@
int c1_acpower; /* ACPI C1 on AC Power */
int c2_acpower; /* ACPI C2 on AC Power */
int c3_acpower; /* ACPI C3 on AC Power */
+
+ int tcc_offset; /* TCC Activation Offset */
};
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
index 9de94c4..4ed5d1e 100644
--- a/src/cpu/intel/model_206ax/finalize.c
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -43,18 +43,30 @@
void intel_model_206ax_finalize_smm(void)
{
- msr_set_bit(IA32_FEATURE_CONTROL, 0);
msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
/* Lock AES-NI only if supported */
if (cpuid_ecx(1) & (1 << 25))
msr_set_bit(MSR_FEATURE_CONFIG, 0);
+#ifdef LOCK_POWER_CONTROL_REGISTERS
+ /*
+ * Lock the power control registers.
+ *
+ * These registers can be left unlocked if modifying power
+ * limits from the OS is desirable. Modifying power limits
+ * from the OS can be especially useful for experimentation
+ * during early phases of system bringup while the thermal
+ * power envelope is being proven.
+ */
+
msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
+#endif
+
msr_set_bit(MSR_MISC_PWR_MGMT, 22);
msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
}
diff --git a/src/cpu/intel/model_206ax/microcode-M12206A7_00000028.h b/src/cpu/intel/model_206ax/microcode-M12206A7_00000028.h
new file mode 100644
index 0000000..8b2550c
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12206A7_00000028.h
@@ -0,0 +1,611 @@
+//+++
+// Copyright (c) <1995-2012>, Intel Corporation.
+// All rights reserved.
+//
+// Redistribution. Redistribution and use in binary form, without modification, are
+// permitted provided that the following conditions are met:
+// .Redistributions must reproduce the above copyright notice and the following
+// disclaimer in the documentation and/or other materials provided with the
+// distribution.
+// .Neither the name of Intel Corporation nor the names of its suppliers may be used
+// to endorse or promote products derived from this software without specific prior
+// written permission.
+// .No reverse engineering, decompilation, or disassembly of this software is
+// permitted.
+// ."Binary form" includes any format commonly used for electronic conveyance
+// which is a reversible, bit-exact translation of binary representation to ASCII or
+// ISO text, for example, "uuencode."
+//
+// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
+// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//---
+/* Wed Jun 6 09:55:27 CST 2012 */
+/* m12206a7_00000028.inc */
+0x00000001, 0x00000028, 0x04242012, 0x000206a7,
+0xf3e9935d, 0x00000001, 0x00000012, 0x000023d0,
+0x00002400, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x000000a1, 0x00020001, 0x00000028,
+0x00000000, 0x00000000, 0x20120423, 0x000008f1,
+0x00000001, 0x000206a7, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x00000000, 0x000008f1, 0x00000000, 0x00000000,
+0x00000000, 0x00000000, 0x00000000, 0x00000000,
+0x52b813ac, 0xdb8994c7, 0x70e9f6bb, 0x9d6db2ff,
+0xf4d70f5d, 0x5b1eccf6, 0xac59106f, 0x0ae2e2c1,
+0x1a7bbeb1, 0x355a1d62, 0x2e7eb594, 0x09f8dea9,
+0x432a49e4, 0xbf520253, 0xdafa4010, 0x893a858a,
+0x766e0efb, 0xd91e196d, 0x838bd2ef, 0xe5146494,
+0xd515f413, 0x29704828, 0xe85598b6, 0xdcbe6c51,
+0x88eabbfa, 0xa1e8909f, 0xd8931721, 0x35386554,
+0x089a78a7, 0xd9914775, 0xd4644748, 0x1556a4dc,
+0xf44448f6, 0xd054d7db, 0xf30f2b7d, 0x5ae223d0,
+0xcbbb48b0, 0x5c8b0383, 0x177de157, 0x9c1e5f73,
+0x2ec28289, 0xd72a7b6c, 0x823b6eb2, 0x35e02171,
+0xba8deae4, 0x06f4d468, 0x13dbafaa, 0x72b419f1,
+0x033385b5, 0x05806920, 0x4c6034cf, 0x9bd117dc,
+0x976e2d04, 0x250330f0, 0x7250b5e1, 0x184980c2,
+0x12a9d7d6, 0x1bc808f9, 0xae79994f, 0xc6f87901,
+0xc0e3132f, 0x671491c5, 0x236cad39, 0x37889d9c,
+0x67f7c3f3, 0x964a6be5, 0xbcced7da, 0x57eeaa6e,
+0x7bca1522, 0x654fee4c, 0x2a1ca5d9, 0xa1803cf3,
+0x00000011, 0x8c316d2c, 0x17603b7e, 0x32e42981,
+0xc26c1400, 0xf0fbccb6, 0xeab6b43a, 0x11d456a5,
+0x5b912d46, 0x15195fe0, 0x542f6db3, 0x0b7f212e,
+0x47718dd9, 0x7c41b108, 0x06c21111, 0x4445d5ea,
+0xb4fb8128, 0xe07404a6, 0x8d503da4, 0x78fc7e44,
+0xb9919656, 0x9968c797, 0x87f26ab0, 0x23bb1af7,
+0x1ec5d761, 0x26f30d2c, 0x7cdb747c, 0xe4d42033,
+0x8a5d4801, 0x768aff57, 0xbcfd5d11, 0x7c853c2d,
+0x231e6207, 0x8b1988a6, 0xd68fdb75, 0x58dcb417,
+0x44422ef9, 0x2a186ebb, 0x7d27e85f, 0x36ac31f7,
+0x1e487e77, 0x2b0b8c37, 0xd8ba682f, 0x2cba791b,
+0xe6d3dece, 0x1b2c2a99, 0x4e5decab, 0xfbd313a3,
+0xdbc78294, 0x5a80cce7, 0x2d8e0f0b, 0xcf564f71,
+0x073d1f37, 0x25162870, 0x96cdb85b, 0x9c553048,
+0x24eba740, 0xfc0f352e, 0x0c83be68, 0x89b5076c,
+0xc39c4355, 0x6a4cf25c, 0x2bbd2682, 0xc524fdb9,
+0x7ea19bae, 0x191ad6f1, 0xd3fbf3bf, 0x21bf77fa,
+0x8f77fec4, 0x0f90f635, 0xe55e165c, 0x868d58c0,
+0x966bc0ad, 0x6c276364, 0x9d8f7eff, 0x4b7925d4,
+0x8b2f9326, 0x4ab7b47e, 0x33a9087c, 0xf31ab949,
+0x69831dfb, 0x4711a215, 0x8128c1fa, 0x8481c213,
+0x7401b01b, 0xfdcfdc50, 0xd6b55266, 0xae9b23ac,
+0xfa2ad275, 0xa225bb45, 0x4dd720c4, 0x760a20e6,
+0x5f1223c9, 0x2f334372, 0x6e1dcdab, 0xe8ee8638,
+0x1c19ba8a, 0xef9341c4, 0x360aaa9d, 0x90452ea9,
+0x65852446, 0xe9398fa3, 0xbba6a631, 0x1a3e90b9,
+0xe2a73a56, 0x6e8c0747, 0x35c7c53d, 0xcc1ac842,
+0x183356af, 0xb6e98608, 0x987b43c2, 0xa8a3cfd2,
+0xc2c5fce0, 0xcc3af64a, 0xd6d3a291, 0xe59ad1f5,
+0x124ca513, 0x9522b50a, 0x25150477, 0xa2eb5797,
+0x7fc63626, 0x648c48e3, 0x9f5797ff, 0x2307b84d,
+0x980625a4, 0xabc05983, 0x24980807, 0x773c4f99,
+0x3407b872, 0x07c3657a, 0xa2cd9e48, 0x49c1e6a8,
+0xa881b84c, 0xf804d72c, 0xb5319d2a, 0x3e39780f,
+0x97518822, 0x0acd54c2, 0x0721a9ff, 0x10e1d2fd,
+0xa7b6db77, 0x845b1a56, 0xef00160e, 0x6b41bfd5,
+0xc994df0d, 0xcf44a5ca, 0x794b36a4, 0xf9fdb127,
+0x922a1366, 0x822aa8a9, 0x4b137bd5, 0x5722a49f,
+0x8933719a, 0x17edc1a9, 0x079d9538, 0x21fae7d5,
+0xe534fd73, 0x9d3038d5, 0x48c3a056, 0x5b22d58a,
+0x6f142866, 0xf1d767cd, 0xb51ad5a6, 0x34a0ef85,
+0x0111703e, 0xca4b3a30, 0xa0f3c34d, 0x9d48775a,
+0x3f2059f9, 0xf2fe2c36, 0x588861a9, 0xed5bd9fe,
+0x8231f7cb, 0x8c115969, 0x3f82ba00, 0x21b3730c,
+0xba757997, 0x3ec0bb2c, 0x16f11def, 0x5d4356c6,
+0xdc2e0bc2, 0x58c1eb6e, 0x313ede0c, 0xb68fcc52,
+0x84d3e1b5, 0xcc6d9201, 0x95046196, 0x276b527b,
+0x80a4a729, 0xe782916d, 0x5cf09e0b, 0x98aaf9fa,
+0x1de6dd43, 0xab4f1962, 0x49ece734, 0x81455488,
+0xc2597b61, 0x5b22af85, 0x646f7b94, 0x09213a1f,
+0x08edf7e4, 0x963d343c, 0x059ba888, 0xb4e804ed,
+0xe7cc826c, 0xf87bafc7, 0xeecaec10, 0x8e60919c,
+0xbf14c996, 0xd3dcaee3, 0xb8fa0b7e, 0x81563c6e,
+0x7f59a258, 0x2f344446, 0x374d8aa6, 0x9b6de5c9,
+0xbf992857, 0xbc5b94fc, 0x28adb080, 0x17e41044,
+0xb87b469e, 0xda504d12, 0xf21bef8b, 0xce75c1e3,
+0xdbd92c83, 0x58bba0af, 0x77b42977, 0x506cfd75,
+0x1139e875, 0x6ce5fe43, 0xc6a5d7b3, 0x87f9e628,
+0x7b5c500b, 0x130066b3, 0x789b611f, 0xec8c1ba9,
+0xb7e6872d, 0xaf828cd6, 0xc28d3316, 0x2a91f6d0,
+0xc725f063, 0x065ac531, 0x4f9ef4b8, 0x2b9d927e,
+0xaf54f3f9, 0x7c924f72, 0xda1d77ad, 0xff00db67,
+0xaf4f03c0, 0xb4f4ee64, 0x169e64e5, 0x04653ac0,
+0xed51cb70, 0xfeaff0e5, 0x51dbf346, 0x072a2407,
+0x23fb74f4, 0x9a906eef, 0x5d6fc3f0, 0xbc3c374c,
+0x1cf9f063, 0x919015d9, 0x5b3e9d07, 0xd6209d8b,
+0xa3710b3d, 0x90ad23b8, 0x420ceedc, 0x58e8371f,
+0x5d419d1f, 0xb8acd13f, 0x7d100d6d, 0x210c10d1,
+0xcd0a697e, 0x5023db4b, 0x33e6d8e7, 0x44bbe6b4,
+0x827e859f, 0x6ca4cc81, 0x661bb2c3, 0x71209ee8,
+0xb8c3ffaf, 0xd1075f51, 0xba1eae10, 0x728b0a6a,
+0xe4af7a2f, 0xca9bcf2e, 0xb249a631, 0xdce6be47,
+0x5c910321, 0x425c3c27, 0x33083e43, 0xdea067ae,
+0xea594a23, 0x41b75c2c, 0x3a401a95, 0xd33cd88a,
+0xc295cad0, 0x67f48045, 0x1dc9ad4c, 0x4bc48864,
+0x53991b6e, 0x7aadde5f, 0x2b0bf775, 0x06ba5380,
+0x9eb874be, 0x2c4b967a, 0x1bcc342f, 0xe875001b,
+0x15b5642d, 0x5be99c9d, 0xcb210ace, 0x1b4924ad,
+0x3793ed81, 0x8b983114, 0x3ec33981, 0x75ec71e7,
+0x8b5b7df3, 0x834756f4, 0x100fad01, 0x70037fdf,
+0x0cef9a36, 0x3d9e3a2d, 0x38b48efd, 0xfc4034b6,
+0xa32e29dd, 0x388944bc, 0xc1c15614, 0x3877e9c7,
+0xa5e733fa, 0xa621bd53, 0x4b651df6, 0xce082970,
+0x85f30d6f, 0x729a5c87, 0x31dd7ba9, 0xdb495828,
+0x7b12c698, 0x953495c9, 0x6b5f99e7, 0x2cc42fa8,
+0x697ac512, 0x1be679de, 0xc116d305, 0x94a36606,
+0x9e5e141e, 0x874affed, 0x58d40b0b, 0x5e3cf5e5,
+0x5d05e9a9, 0x06840efc, 0xd2f98b21, 0xa1e83ab2,
+0x4f726202, 0xa6394535, 0x62a02403, 0x9f2167ec,
+0x4f9fc77b, 0x98073be4, 0x2bc781fa, 0xfc8e4c89,
+0xc7179b97, 0x692cf793, 0x708ff7bb, 0x12ecba93,
+0xacd06e21, 0x202bef76, 0x03852241, 0xe84e02a1,
+0xf1f9ac8d, 0xcee61aef, 0x61a4f235, 0xd22991eb,
+0x67a81345, 0x375a15c6, 0xe8fae8a3, 0xb4ff2b37,
+0x339ee4ea, 0x14ffadc3, 0xf49340dd, 0xf285e568,
+0x00fc6970, 0x369c52d1, 0x4f55368f, 0x3f4d75f1,
+0x6a73b603, 0x963c1f59, 0x171e2bdc, 0x72bac76b,
+0x9e2e5c32, 0x307f7c3f, 0xd3b48637, 0x3a917acf,
+0xea52a65f, 0xecd209fb, 0xf0ad84bf, 0xd4bdea70,
+0xa2647b38, 0xce040b49, 0xc6d5f13d, 0x5d942c52,
+0xf8edc042, 0x798fdefd, 0x4b074246, 0x1cb1873a,
+0x6793c186, 0x23b9c774, 0x77bb0202, 0xc519b3aa,
+0xa30c09a2, 0xe1f6669a, 0xb7eddb8d, 0x7aaa91d6,
+0x076a3789, 0x0ac47791, 0x1e503404, 0x44fe8c54,
+0xf3cbbf49, 0xd3234eef, 0x0d898b3f, 0xe854984b,
+0xe3986de9, 0x923a5c76, 0x2ee9abca, 0x1a9fedbe,
+0xdf76dcd1, 0xea07936b, 0xcdaaf247, 0xe62d98fa,
+0xa99c7f7b, 0x34fc84d4, 0x03a35111, 0xad5675c8,
+0xcc64075b, 0x408203f9, 0x846e1f08, 0xe934019e,
+0x423d1223, 0x2f04f9e3, 0xee1dbf40, 0x65edc60f,
+0x097aa22f, 0x7058a2b7, 0x41c8a0a5, 0xa68aa391,
+0x0f345c40, 0x667517e6, 0x860838ba, 0x6dae933b,
+0x764d5919, 0x6673fa0f, 0xf0a5e97d, 0x4262ebbe,
+0x64b413f2, 0xd2c4145a, 0x0b2c11f3, 0xfdfe9f93,
+0x96c77107, 0x1399fdda, 0xf599f215, 0xb504da5d,
+0xf8a95268, 0x9ed1ef87, 0x9ae33cfb, 0x3b21f1ef,
+0xc6d447c2, 0xe0694d4e, 0x967febab, 0xc13f631d,
+0x8393bfba, 0x37438788, 0x1724194d, 0x8e77a045,
+0x20e2483c, 0xb961c2fc, 0x485cf593, 0xb3462621,
+0xcb2959b8, 0x10307e19, 0xf71fbbfd, 0xdda641e1,
+0x0daf5f66, 0x56d85178, 0x145f6749, 0xebc46ed1,
+0x5593c249, 0x94561f51, 0x534cc654, 0xca7c8814,
+0xb59a578c, 0x40b2b614, 0xeaf3437a, 0x198d5b4e,
+0xf245fa53, 0xfb75e0b0, 0xa363c46d, 0xc43b5468,
+0xdf036413, 0xc59f5a36, 0xd8ff4381, 0xa3af3e36,
+0x7af63462, 0x414526d7, 0x7bdc41c5, 0xa416f1e7,
+0x6987d9ad, 0x472c5499, 0x4f10ee37, 0x47bb7ff7,
+0xc7f2e621, 0x820008f7, 0x33a475db, 0x91ff5d72,
+0x0517401c, 0x73d067c8, 0xe417b69d, 0xb86d9903,
+0x1ac9a032, 0x74bbf582, 0x8b65596e, 0x883be34c,
+0x95dcc26f, 0xe232c646, 0xfae9c19f, 0x35cb5273,
+0x6a94d095, 0xfff6ca91, 0xb9c40eb5, 0xd351dcac,
+0xc90d464f, 0x9b609642, 0x15663b56, 0x15f7f88d,
+0x22499f60, 0x417fd6c5, 0x2dc36fe2, 0x712bf66a,
+0x22f1fba8, 0x531b8092, 0x40d269b6, 0x1d227898,
+0xeb6ff35b, 0x2490ac31, 0xc958ed65, 0x3ce6ffb7,
+0x9338a806, 0x3beadfe2, 0x1c361ac9, 0x53d0e3b0,
+0x91d46102, 0x4d57045f, 0xb5c8afb3, 0xfd2c9e7d,
+0x3d578410, 0x2adb9406, 0x10df7459, 0x90abccfb,
+0xe3f217ed, 0xef5f4e09, 0x74925ce4, 0x169b5879,
+0xfeff4ad5, 0xb300dd1d, 0xc96022ba, 0x72da501b,
+0x1e694296, 0x9efa33cb, 0x0dc3ee6c, 0x0ac4e7ea,
+0x73041130, 0xf0e6a295, 0xc46bdb6a, 0x6a927044,
+0xd217ceca, 0x0b744007, 0xd5a2bafb, 0x4220cd92,
+0x70d3352a, 0x5ee4f661, 0xfa07e5c0, 0x155542d9,
+0x4a39fba0, 0xcec0552d, 0x30c1d8ef, 0xbef9d21e,
+0x183879aa, 0x5b3f30a8, 0x54a06db4, 0xef876e4e,
+0x5e823680, 0x53e2a353, 0xc9aa4112, 0x13a56ee5,
+0x848859fd, 0x0ba2b801, 0xec15260f, 0x7bb22672,
+0x1a097332, 0xb141339f, 0x752a67d9, 0xdae373f3,
+0x3c8cfd49, 0x2dfaf2a9, 0x95820c6c, 0x956b39a2,
+0x1ca0d24e, 0x1312b978, 0x7280e1bd, 0xa7a7c2ff,
+0x0b48e987, 0xb6083e55, 0x4b4b82f4, 0x9c6104ad,
+0xcb93beca, 0xe1c34035, 0x34de740d, 0xbb151baa,
+0x71f5942f, 0x1eaac228, 0x0c68331b, 0x3d2a1dd0,
+0xe7a3d41a, 0x7253acae, 0xfd4de230, 0x79988d80,
+0x4468f19b, 0xac4440fd, 0x6e8a6ef3, 0x5736adf8,
+0xded67716, 0x1f1d5a4b, 0x96c5f451, 0x85bae181,
+0x1293ab28, 0xc2ba53c2, 0x729ff4cf, 0x60218df8,
+0xc2870138, 0x6127d844, 0x89604e9e, 0xd2b9ad4e,
+0x4f6ded9f, 0xdd263849, 0x1633bd92, 0x64b03a24,
+0x96dabd4d, 0x6e85d235, 0x1ab69ad0, 0x9aa80454,
+0x6b9041e0, 0x106c7e9a, 0x8f54812f, 0xa274efe4,
+0xe45d6695, 0xf3aa7bd3, 0x6a5a2a63, 0xe36f3525,
+0x6238fa4b, 0x7d6cb06f, 0x16d3b4a2, 0xf3b04822,
+0x638f1a60, 0x0e1875fa, 0x1c0292b9, 0x6b519ea4,
+0x9faba37b, 0x209341ec, 0x83c9061f, 0x3387dfe8,
+0xc7f12ceb, 0x2bef45d7, 0x8f8acb47, 0x35d9741b,
+0x7009f514, 0xfd003802, 0x6f9489c5, 0xe2ea2504,
+0x910e996a, 0xcc81d016, 0x3280730d, 0xdedfef59,
+0x5a7357cc, 0x8fe8dd39, 0x15543fe5, 0x976c4207,
+0xe41cf62b, 0x0ba6b4b5, 0x5c3b7ced, 0xa6c5b72b,
+0x72ad3b4d, 0xff143181, 0x2b78a157, 0x7fe231a5,
+0x6ff0538a, 0xe58ed1ac, 0x81a311a5, 0xefaa54b8,
+0xf04a797e, 0xce6e69c7, 0xdc810726, 0x7bab7be3,
+0xdd5923e8, 0x5a2413ed, 0x31cef794, 0x73dfd806,
+0x1b9223c1, 0x0c370882, 0x04fa3b68, 0x87c50bc1,
+0x1d78c90f, 0xf4e2cee6, 0xebea941b, 0x73e5838f,
+0xca8d39a6, 0xe004296b, 0x28cf8a0e, 0x7c73e7ef,
+0x26a296c2, 0x789d4c72, 0xd1490265, 0xd9a9e843,
+0xf03504c3, 0xfae6dffb, 0x7a48f00d, 0x51e369c8,
+0xcb3eeee6, 0x0625e936, 0xe93d0d7d, 0xfb15ba6b,
+0xec5c76da, 0x8fdf44f1, 0xa036653a, 0x5730c4a3,
+0xe5bfe6dd, 0x0b8c091f, 0x3b51558c, 0x403748f4,
+0xf4007f86, 0x952b5db6, 0x5524d8ba, 0x8046409a,
+0xe3fc61a9, 0x66f4ea56, 0x5645150b, 0xdb2bec15,
+0x50672218, 0x7f40e87d, 0x2b8359f8, 0x438787dc,
+0x7f221597, 0xf8b1590c, 0x4f468251, 0xff586d05,
+0xb9195380, 0x0ee09e0b, 0x2fa7dbd9, 0xd197b327,
+0xa0dbad58, 0xb485681f, 0x5ef0937c, 0x1e07ebb6,
+0xcb49fe3f, 0xc2427cd9, 0x6c2c5298, 0x4a2e171a,
+0xa7f333a8, 0xb3609ad6, 0x94e374d6, 0x0e1eb64d,
+0x22c3367d, 0xcdf89975, 0x647aceef, 0x16727c9c,
+0xf476ae53, 0x35a1212e, 0x0db768b8, 0xfff8b53d,
+0xbd4fe45e, 0xab28a5a3, 0x59cec0af, 0x28bcd1ef,
+0x6f43ad69, 0x2658a059, 0x27aee0ec, 0x4e8bbd15,
+0xa9fdcf04, 0xc9aa329f, 0x687f010f, 0x5c968a07,
+0xb894e607, 0x0e1cba22, 0x2f00f203, 0xe8e133ac,
+0x494a4746, 0xe8bdff9a, 0xf69791a2, 0x64179ce2,
+0xbfd10dc6, 0xc026f6d8, 0x4871923a, 0x8946b277,
+0x609f49a4, 0x6466df1b, 0xd8c3c131, 0x46ef0291,
+0x0fdce8b6, 0x2b9aedb7, 0x225c4520, 0x72b332cf,
+0x4e220d47, 0xf2f69c36, 0x2c23fad9, 0x57a2a918,
+0xe017409c, 0x490819af, 0xf2121afd, 0x951ff7ff,
+0x40363fcf, 0x5078b94e, 0x9e4be775, 0xee97ef16,
+0xdb3a2390, 0x17d42af9, 0x96f56a51, 0x1b4c2934,
+0xc866315c, 0x2b746f99, 0x9a3b73f6, 0xa1e081fc,
+0xa9d07ebd, 0xa6359fae, 0xdf50d099, 0x55304e01,
+0xfe5aaa81, 0x1e74267d, 0x38b1d2d7, 0x8633e9af,
+0x99b013df, 0x3aa05831, 0x86279736, 0xd2b464e0,
+0xdf036a9f, 0xe8162915, 0x876c0d4f, 0x4beb7d0e,
+0xfec9b170, 0x46bc9df4, 0x46cb88fa, 0x0cb5904d,
+0x2e2961cf, 0x7ea5dc1a, 0x60670df2, 0xf935ca32,
+0x67e6777b, 0x8bacc97a, 0x5cd07248, 0x32e483e6,
+0xfdf09b0d, 0xca57150b, 0x3f432d09, 0xdea2d7db,
+0x9f6a2954, 0x6f07dff3, 0x4133f394, 0x60272f97,
+0x1b98c9ec, 0x2ab648d9, 0xb5df14a8, 0x0d2c38f2,
+0x5dfde2c4, 0x7cb43ca3, 0x8d0c6c01, 0xe80ea41e,
+0x5f58b71e, 0x4ca9fef2, 0xabd201a4, 0x50905c08,
+0xca8ba387, 0x5592922b, 0xfa4e05f5, 0xceb64b14,
+0x0845c5bd, 0x518d369b, 0x727e570c, 0x1daaab31,
+0x801e8b9c, 0xec6568f3, 0xd4c3760f, 0x40a78d22,
+0x38af58b5, 0xc406a76e, 0x8c3a7779, 0x18272c42,
+0x45cf7b70, 0xa6f3c0f3, 0x88021e41, 0xda662504,
+0xe97aa709, 0xe93bafe0, 0x8862ed5f, 0x35bc8268,
+0xf5a41551, 0x3dd3bb21, 0x1af0cf11, 0x08fe1ad7,
+0x53ecae41, 0x01a4a8ae, 0xfed636b7, 0xf09323e6,
+0x73b9b253, 0x7ebd7ce2, 0x7074b4de, 0x21c719b2,
+0x50982743, 0xd23cfd27, 0x136a1f4a, 0x23260f6e,
+0xfad89dcd, 0x57586681, 0xadc4fba5, 0xad0f71b8,
+0x91a3f188, 0x20d62385, 0xfecda9cb, 0x33d67776,
+0x2abb0e6c, 0x0ad16087, 0x486332da, 0x2928d342,
+0xf6d1b174, 0x5e133a4e, 0x72fc0ad4, 0x940578b8,
+0x320a42b1, 0x9cbda7d4, 0xf2a36135, 0x00ab8de3,
+0x5bad9000, 0x5778e633, 0x3952763d, 0xe0e58583,
+0xdfb0bf19, 0xb11914b6, 0xa67da7a1, 0x8d9a9f81,
+0x638cbcf7, 0x83bf931d, 0x8703b0dd, 0xcab30fa4,
+0xd6db2ee6, 0x5cc2e5ac, 0x717e636b, 0xfdcbc760,
+0x563b3b25, 0x0e4df458, 0x9efb8fa7, 0x95aaa7a1,
+0xf05b6680, 0x5e237e59, 0xc884018a, 0x177b5a30,
+0x3ea2c9bc, 0xd0325ee6, 0xb1dae51b, 0x812ee29d,
+0x6d58db21, 0xb787fa68, 0xfd092294, 0x09683dd3,
+0xfe0d6405, 0xfdd99aad, 0x78744a59, 0x936738e6,
+0x6ad6cba7, 0x370f7f8f, 0xd208c214, 0x12239384,
+0xbe71f0e7, 0xfc0ef264, 0xc04e4a49, 0x354f9cf3,
+0xf5d7572c, 0x07839ad0, 0x834a003d, 0x23ba26e2,
+0xf4049ecf, 0x5ff402b2, 0xff9d6769, 0x074ebe6d,
+0xdc829da1, 0xc3d7697d, 0x973efe4f, 0xfc2a9165,
+0x126dc518, 0x0b824ca4, 0xc438fb70, 0xb7b0ee00,
+0xbe56afd9, 0xa3d8defd, 0x971455ae, 0xc11ffde7,
+0x346e619a, 0xb41111a9, 0x6004b62e, 0x896c668d,
+0x738e458c, 0x351f9fdd, 0xe771b2ba, 0xad6d7464,
+0x719b57c2, 0x6f6a4611, 0x8a676f2d, 0xb8db1c43,
+0x3f102641, 0x51bffdbc, 0xb7862565, 0x5d8dd231,
+0x7a79bd39, 0xfa472894, 0x0fd1d2ff, 0x64cf589a,
+0x38234d7a, 0x5c9acefd, 0x8eb0b9f8, 0x761e1c95,
+0xf2fe78fa, 0xe06220d7, 0xaf82a919, 0xf4e196e1,
+0xa17c8935, 0x06d08d16, 0x6bad807b, 0xf410805d,
+0x4ff2bce6, 0x3297c81f, 0x06e35353, 0xbe1f5e1c,
+0x65d1cb92, 0x0dc69b2f, 0xac55d597, 0x636ff24c,
+0xe2e4f2ba, 0x63d64922, 0x4b2e9f71, 0xad2279ec,
+0x5f0b5c0e, 0xac688638, 0x35613358, 0xf5531360,
+0x54a304e8, 0x27ebfe65, 0x977b5a3c, 0x3dc5e10c,
+0x73b32ee9, 0x3a2c9454, 0x30a149c6, 0x31e5b55c,
+0x2c10854f, 0x745cd38a, 0x2853a27b, 0x6629e355,
+0x0bb67e39, 0x5469184d, 0x694a9bb6, 0x0a0ca25f,
+0xa878c5de, 0xee15fd46, 0x23d92ff8, 0x02328404,
+0x1c9402b5, 0xa46b6ce0, 0xefc3e947, 0x0e9312ad,
+0x5830ae9e, 0xe30e32f2, 0x9db8ee81, 0xe8aeebbc,
+0x30675c83, 0x447278c2, 0xab2bad3b, 0x08ba3d0c,
+0x1124e681, 0x3691242d, 0x903c8d2b, 0x3281c312,
+0x22af690f, 0xd69a150c, 0x57622c5b, 0x29313c73,
+0x6ab2d7c6, 0x39b06dad, 0x6e1f9f81, 0x03324986,
+0x53a49093, 0x7654eba3, 0x2527245a, 0x9af596fb,
+0x818ffb3a, 0xa3817173, 0x6a2c4b80, 0xfcc42ad5,
+0xfb1bbb69, 0x3a3720a2, 0x90a89bcf, 0xed80308d,
+0x7753cb1c, 0x1c2654a5, 0xb01ee4af, 0x81091e85,
+0x9067b3f1, 0x2e2b9b5e, 0x9fb0c7d1, 0x78fd9f69,
+0x5771c46d, 0xacdf498d, 0xfd8b8e77, 0x4c15fa61,
+0x607120ce, 0x18a298d8, 0x73716420, 0x65e5e06a,
+0x18c53e04, 0x35b84427, 0xcd82b522, 0x9a7d26bb,
+0xd56b4b74, 0x49b47fe8, 0x63178dc6, 0x0bac0f46,
+0xc8b0755a, 0x9bbaaf1f, 0x18131d2b, 0xcc019330,
+0x0ceb89bb, 0x8808c2d6, 0xfb5bd86c, 0x6c945b71,
+0xdc911924, 0x4ebb8d35, 0x44e46d08, 0xabfee615,
+0xf456931f, 0x7a244955, 0x0bffce7d, 0x5533ca5f,
+0xb1b2c636, 0x4f29075e, 0x64012561, 0x7aa5e7c7,
+0x9c8a0666, 0x9698782d, 0x3481ad8f, 0x21a55b19,
+0x735aa45d, 0x4245b9c4, 0x0d4c3fdc, 0xd1b10966,
+0x7035fcde, 0xc2257947, 0x4a37271a, 0x9da464a9,
+0x228adbf8, 0xbf309e03, 0x096f560a, 0xa2b8ca78,
+0x427702cd, 0x35a99cf5, 0x99811758, 0x6953db58,
+0xec07533e, 0xe95838b9, 0x61c71654, 0xc9cce595,
+0x275af106, 0xc8697af3, 0xb3f27e58, 0x411d8d30,
+0xd0d90ecd, 0x1503b9dc, 0x76bf070e, 0x49f89ef0,
+0x7333b083, 0x53f9c44b, 0x8330c3a2, 0x6a1119c3,
+0xca555f2b, 0x3d51fc6f, 0xac7b3320, 0xf8e42cdf,
+0x053753fe, 0xc122336f, 0x94d289c6, 0x088b5a64,
+0xc3aac7f0, 0x96a76344, 0x2ff05828, 0x9b4f2af3,
+0x46de6a46, 0x4ed29d98, 0xe2ab7634, 0x27481ddc,
+0x300ca71f, 0xce7ac539, 0x88240e09, 0xb1a14e78,
+0x2addd4c5, 0xb3a7f320, 0xe91f549b, 0x6881c45b,
+0x0e381c47, 0x1018feb4, 0x64679650, 0xe62281cc,
+0x670ee6d4, 0x0d226160, 0x947b7f08, 0xbc595a74,
+0x2380c0b3, 0xc0235785, 0x63b41221, 0x80b9cc31,
+0x3231b4ae, 0x33ed5718, 0xf2c5c90f, 0xdd3b03ea,
+0x67dfca08, 0x453e9d29, 0xa2bdecbf, 0x5e9a3181,
+0xad17aea2, 0xff0a8f13, 0xdf946849, 0xcfbbecb7,
+0xb0a602d7, 0xb1a820c6, 0xfe7abbc8, 0x7f70790d,
+0xeb5f8863, 0x266d3cc1, 0xbd552a44, 0xe19b1b3d,
+0x856aefbd, 0x51c11f1e, 0xde661b7f, 0x61c075d2,
+0xd0f6a834, 0xff1d0d37, 0x6793d1c2, 0x70c133a5,
+0x20c4d2cf, 0x8c80d4d3, 0x61ebe382, 0x788b74df,
+0x11c56903, 0x535889ba, 0x0a9c7380, 0xf9de2837,
+0x09437fe7, 0x1627c6b2, 0xb943bdb8, 0x69bc29b2,
+0xee9795a4, 0x83c992e0, 0x95437918, 0x8ce166a2,
+0x56b56b66, 0xb0680941, 0x623d38a9, 0x2add07ad,
+0xe583ba09, 0x96f6532a, 0x3eff4696, 0x2a8a6b0b,
+0x905b913b, 0xafc01673, 0xe871e006, 0x2c2339ad,
+0x248438e5, 0x96d83e53, 0xb3a75d6b, 0x2258cf63,
+0x69ff39bf, 0x95727173, 0xc3ac09d5, 0xea8d2c06,
+0x0e7c0a4b, 0x144fcade, 0x28a9a5a3, 0x97c11ae8,
+0x89865e3d, 0x1640cd32, 0xe3e551f8, 0x1f7ba770,
+0x6d23fb31, 0x11eceae3, 0xc8ccb8ee, 0x46dd0bb0,
+0xd01a46ff, 0x0504adf5, 0xec6e170e, 0x2e3d7ac5,
+0x70f893ac, 0xaf9963db, 0x061e283c, 0xf0ad248f,
+0x2fe97e19, 0x881fd340, 0xc686c9d5, 0x88ea8ba5,
+0x92f05cd7, 0xd6716148, 0x6fc47fc3, 0x2c51d9b9,
+0xd50a7faf, 0x4eccacd1, 0x7c92f802, 0xa63ffc83,
+0x7cb0ab1d, 0x4492e81b, 0x7d906554, 0x43306ba1,
+0x73a5d57a, 0xe57a05d6, 0x6850b964, 0xefed595c,
+0x7754978f, 0x629e8236, 0x62ec4dde, 0x247439ee,
+0x8b9982fa, 0x4eece5c2, 0x48599175, 0x0fdc752c,
+0xecd87b12, 0x94936c75, 0x17a45ea1, 0x80a899ac,
+0x22a39ee7, 0x745730b6, 0x03ea4daf, 0x4a7570d7,
+0x307621fa, 0x7322e0a7, 0x3a8e0316, 0x454e46f7,
+0x08773750, 0x156dcaad, 0x5562bc06, 0xa23a1ee3,
+0x20435211, 0x1d679ea0, 0xb220e205, 0x682cc1a6,
+0xd64a71c7, 0x3ca7f8e3, 0x2e92f253, 0xa7cfdd0b,
+0xd62b4053, 0xf5c5f641, 0xbf72dde1, 0xdcb716c1,
+0xe2f7b05d, 0xa03145ea, 0xc09828d2, 0x7dae7916,
+0x6fb97c79, 0xb3a85204, 0x998a9c7b, 0x5f42ba8c,
+0xd9c628b3, 0x6b17bacb, 0xa889b716, 0x450ff97d,
+0xe9166f3c, 0x2d20777b, 0x82a003ae, 0x2c7ae0aa,
+0x6011a9fe, 0xfeed34be, 0x1328f67e, 0xf61003a3,
+0xfaecdf20, 0xee18c81e, 0x731a0302, 0x11a39e60,
+0x355d78dc, 0x99088f2c, 0xcf253759, 0x97347603,
+0x736f71f1, 0x37e4b395, 0x9cc74540, 0xf7e39994,
+0xf01c5f64, 0xbec519f1, 0xa79c1067, 0x76000d5e,
+0x1ac85b6e, 0x51e5b7a3, 0x62a97ddf, 0x6f20096a,
+0x2af51e77, 0xea5554f6, 0xb4e581da, 0xc1ac4ba8,
+0xc8f22bf7, 0x9e254d3b, 0xd7dd62f6, 0x6461ae3e,
+0x423e1f10, 0xf143e7b9, 0x18c73b04, 0xa43de614,
+0x2da8d02f, 0x9befa706, 0xc01dcd49, 0xa278f1e0,
+0xd85f3177, 0x6b6679fd, 0x1ccef04e, 0x53af9252,
+0x34d751db, 0xc8d32c86, 0x3d725097, 0xa64ed581,
+0xd090c42f, 0x9e92bf3f, 0x6f82b089, 0xd42728eb,
+0x3dd651e0, 0x1985bc52, 0x4b0f4159, 0x0f99bd7f,
+0xe2597023, 0xca0cae4c, 0xce48a894, 0x7249dd88,
+0x8e146632, 0xb4be1d6c, 0x790ae7e5, 0x6747b657,
+0x52143947, 0xa2e42ed3, 0xea359617, 0x6ca01a11,
+0x35c5e2dc, 0xc97b78fc, 0x5db6db2a, 0x80fe3414,
+0x27da19d4, 0xd7431d04, 0xa91e9110, 0x7d8ecb23,
+0x2508700a, 0xc8c71ed9, 0xd28835af, 0x018c2887,
+0x3d0a6fab, 0x3e8523d6, 0xd0688dee, 0xe5c3865c,
+0x838d72e4, 0x6bb73a1d, 0x497a59ca, 0xf77c56de,
+0x38ecb72e, 0xa55e3565, 0x04b12c92, 0x1aec9997,
+0x037c340a, 0xef0d04c3, 0x78f74bd6, 0xdec9b9e8,
+0xd95b61ea, 0x5528e8f5, 0x4ecd325c, 0x88ffdc0b,
+0xb337ac61, 0x899d90e7, 0xb5eeb978, 0x8295d9ae,
+0x1ed8978b, 0xa8849eda, 0x8633b4a3, 0xb8c858b5,
+0xbe3c4375, 0x28b9e84e, 0xb2a26def, 0x22f8f66b,
+0x3a4aed99, 0x0c4914ea, 0xad103249, 0xba5a5eff,
+0x8a052461, 0x26938899, 0x915c6ed7, 0xe6268ad9,
+0x246e8c74, 0x75f3c196, 0xc3e725d6, 0x92e02549,
+0x1f78a5cb, 0xeada57e5, 0x40f14906, 0x0215e49c,
+0x57c06bae, 0xc1896b87, 0x0cd40a63, 0x60741d80,
+0x11a69899, 0x80fed942, 0x0497e115, 0x56697b55,
+0xba89c3d4, 0x27d6b7c5, 0xddff87b0, 0xd3b1ff2f,
+0x3160e528, 0x9cca1286, 0x13b4fdf1, 0x38cdd907,
+0xb50c4597, 0x4c151714, 0x1cab86c7, 0x23126a3e,
+0xe26e9749, 0x289a0d0e, 0xc4004640, 0x9d33928d,
+0x33b691a2, 0x15ed6e6b, 0x6e773980, 0xadd59678,
+0x188ba49f, 0x08da4c6d, 0x6d150d0b, 0x0c6c7b98,
+0xc8e1df7e, 0xb8b1e692, 0x5e89fd35, 0xcb253d24,
+0xfc6ee27c, 0x8013de3d, 0x1d38012b, 0xe50a8f7b,
+0x7d410ff1, 0xceee4e9f, 0x0e8094b6, 0xaa1a5f57,
+0xb395a551, 0xbd62b2ae, 0x5d7b34c8, 0xbd2d6195,
+0x33af4109, 0x0769ff18, 0x9c6cc123, 0x78ee6eb6,
+0x412644e7, 0x70e0c6f4, 0xf45d8fc6, 0x0435f5af,
+0xd43622b7, 0x27409d5b, 0x6dd04e8f, 0x9f02ecf5,
+0xca415f7d, 0xc9f439c2, 0x7198e539, 0x20476b75,
+0x3cdd8dd8, 0xce17fbb0, 0xa5bc115e, 0xb0ee52c1,
+0x0b074cfa, 0xd26d4f99, 0x3b43320b, 0x230b680b,
+0x9908f2d2, 0xcbcb1952, 0xf45a2f53, 0x7b4564c6,
+0xcf2fd983, 0x414fe4b2, 0x55ea7f11, 0x63e8117d,
+0xe8954052, 0x7c2ea344, 0x97a02aaf, 0x6ca874c3,
+0x1ae5b4ee, 0x41754eae, 0x6954abe0, 0x115ddcda,
+0x9a27968b, 0x32a53e65, 0xffe47b2f, 0x4fe7e5a7,
+0x6016dedc, 0xb3c0893e, 0x9626776d, 0x5ec773f9,
+0x1104e01c, 0x1473cfb3, 0x43b2cedf, 0x8ca9d119,
+0x7f1bc844, 0xd8bb7387, 0xba90d2ef, 0x2bb0dcf4,
+0x2340f124, 0xa5bd514c, 0x50afab05, 0x718f5ad5,
+0x7c03fad9, 0x71d00d2d, 0x1c31fdc2, 0x4a938809,
+0x40945ded, 0x437f2a0d, 0x83c10d64, 0xd224c6ab,
+0x0cd44481, 0xb0040966, 0x27fd6e7f, 0x6ff45d4c,
+0xab057ad1, 0x8fa4e5d4, 0xac50270c, 0x6e4926ca,
+0xc5721498, 0x2529b458, 0x40ee2ad5, 0xde5e21f2,
+0xea8964ca, 0x56766e60, 0xdc3b8702, 0xa93528d4,
+0x28d7713d, 0x42edf022, 0x59774dd8, 0x200ff942,
+0xe7a4d769, 0xd8c4ef5e, 0xe177f715, 0xe9d53cd6,
+0xc11270bb, 0xb25977e5, 0xb80867b4, 0xfb48468b,
+0xdbf166a8, 0x49700d85, 0x0f85f98a, 0xa7ca7a75,
+0x109817ce, 0xca243f19, 0x8bed7688, 0x9a1c8231,
+0x94f0ce97, 0xc36309ca, 0x90ecac24, 0x67e7e0de,
+0x86b18d62, 0x18c7b7a5, 0x622f5d3a, 0x47e1e067,
+0xdc96b94d, 0xe4a03beb, 0x59d17692, 0x040abc0d,
+0x44a5ae50, 0x3d3dab7d, 0xc18dfd30, 0x2802b9d9,
+0x6818379f, 0x56db41d7, 0x97cbf039, 0xe41d6a32,
+0x64b5fb01, 0x6506e0b4, 0xd60a3234, 0xdf3573d2,
+0xac148579, 0xe7f46ac0, 0x05e1c763, 0x904a5aa9,
+0xc7ca1ee0, 0xe0c3b047, 0x5e36e1bc, 0x447a9141,
+0xe24654df, 0x9853a49b, 0x6a29cedb, 0x022f00dc,
+0x6df2a7a7, 0x3636da02, 0x72bb9c81, 0x4f0e0918,
+0xd649f4a5, 0xbb0c81f9, 0xc0ba93fd, 0xc1b390f1,
+0xda84e720, 0x1aea0064, 0xf3ee67e1, 0xb874ef4a,
+0x82467ce6, 0x59abf506, 0xafbf145a, 0x9a4cf8a1,
+0x17247c89, 0xd8669398, 0x1796eaf7, 0xbc2d24a9,
+0xcb486570, 0x17a9db23, 0x3e6504f0, 0x08684517,
+0x2723ab28, 0x7081b814, 0x8a265a04, 0x697e6d8b,
+0x69b146dc, 0x6434c182, 0x27ec8101, 0x864405c5,
+0xfff86c9e, 0x3052d8a6, 0x23d283db, 0x492970e8,
+0xbc6c64c3, 0x46d8f98b, 0xe16e7ff3, 0x731e4f82,
+0xbd26b1af, 0x6b30e6c1, 0xff192fce, 0x097e0bba,
+0x49df63a5, 0x2fdc3f01, 0x50aae053, 0x60177b8f,
+0x1949eb85, 0xa46084ce, 0x9658f694, 0xcb951fbc,
+0xc53806d9, 0x63a17d30, 0x3b3f86c2, 0x8a37aa6c,
+0xedf8fe5c, 0x87aee1d3, 0x8c680126, 0xfd8b27a6,
+0x231fa106, 0x69358c25, 0x4502c348, 0xc107861c,
+0x46280e70, 0xcf6067ac, 0xf6a04ff3, 0x3e488677,
+0x6f3fb4c1, 0xeec1f758, 0x560e1c48, 0xb604c06b,
+0x69e34b1e, 0x8ef41dec, 0x854cea22, 0x726581d7,
+0x55ea91f3, 0x38ae4053, 0x5ff7389d, 0x6952cbf6,
+0x09aa0fc1, 0xcccb1d50, 0x5c1a633a, 0xde1eba46,
+0x797212d8, 0xa943fb3d, 0x6063a1a8, 0xbe68ef36,
+0x6ba0d5ba, 0x0dbe2061, 0x47711712, 0x62679807,
+0x6f34009e, 0xe6fe8f18, 0x66a6a64b, 0x3f80f472,
+0xe953d5e0, 0xbcd8196a, 0x086faad0, 0x49da7f16,
+0x7f2199a5, 0x55af4af2, 0x085b4d38, 0x22e634bd,
+0x6cff0416, 0x343466f4, 0xd121a7a6, 0x6caa3942,
+0xe4f365a2, 0xd832eb0c, 0x616728e5, 0xcca4c71a,
+0x4010cdc2, 0xd0f1d1cb, 0x5e695f89, 0x27719206,
+0x0ec92854, 0x76144a1b, 0x49808021, 0x12457a1b,
+0xdde7aa5c, 0x8f1a077f, 0x110a4a5a, 0xb3a5ad31,
+0xaacebf8f, 0x66ff7f33, 0xa2340971, 0xfb4c7e82,
+0x8dd536d7, 0xafd2021a, 0x72aa9c6e, 0x22df6952,
+0x83c4b4fb, 0xba515555, 0x93eee8f0, 0x22d0ed5a,
+0xbec05586, 0x83828f28, 0xe0d7f930, 0xac0f0199,
+0xef6d76f9, 0xf56ebdf8, 0xf67323c9, 0x8b805745,
+0xce5902c0, 0xfa2ce3da, 0x10f836dd, 0xe1ac6d97,
+0xa0e415ea, 0xbb7c32ad, 0xc421f3b0, 0x8166e898,
+0x74e7a73c, 0xf454b82a, 0x631369b1, 0xe30ed23f,
+0xdaa1c75b, 0xe7c9c6a7, 0x5f33c375, 0x99c05187,
+0xf2d6e6ae, 0xcd2045b8, 0x92ff3009, 0x15082015,
+0xd1a1580e, 0xdce25f9b, 0x21984a75, 0xa9be5388,
+0x099a5372, 0x3ab9bcfa, 0xdb9069aa, 0x49a99be6,
+0x42a9ee0b, 0xfe32d832, 0x24e11ad3, 0xd16f596b,
+0xb95982cc, 0x754ab1c8, 0x42ffa128, 0x539e823d,
+0x28e0f976, 0x262ddfc0, 0x2a16e7ad, 0x49b5acd9,
+0x931f3def, 0xdc419b84, 0x8412cc3c, 0x81056cd9,
+0x91933e1f, 0x57710b15, 0xa55d2696, 0x87d88724,
+0xd4fedfdc, 0xcc3825c6, 0x397f382f, 0x80f9b6ba,
+0xcdd6d59f, 0x24b984d8, 0x8f1c5bcf, 0x25bcef1d,
+0x00dc603a, 0x76fd94c2, 0xa267a7dc, 0xa6e90a6a,
+0x5c5916d6, 0x065a52cf, 0xa28d3263, 0x9b17b72d,
+0xb8436b48, 0x1b1c2391, 0x1fda3395, 0xa6cecbcb,
+0xbc4ec502, 0x1766b590, 0x5945fbd6, 0x6a124405,
+0xf92d06f2, 0xe24694b7, 0xf6befd08, 0x8266cf5c,
+0x03ed670a, 0x5f98be62, 0xf27b7e2e, 0x598cf22c,
+0x2e855591, 0x879815fb, 0x153799c6, 0x3820faf6,
+0x3d3a2cc6, 0xdbb6dece, 0x1a3c46b2, 0x5031bdda,
+0x47894c03, 0xe43661fe, 0x7a6ee548, 0xa5ca9779,
+0x6aa9e105, 0xbc8505a3, 0xa03b860a, 0x448faeb9,
+0x367de4a9, 0xc9779c7d, 0x6535ad8c, 0x4b7fcacc,
+0xb2db5c10, 0x0ab41ec6, 0xe528ab90, 0x5e6f03da,
+0x98bc76d3, 0xf38df42e, 0xea59b039, 0x1c2eaa28,
+0xca30dac5, 0xdb0eb8c6, 0x60063860, 0x18823f8d,
+0x164e2f28, 0x7cbbe080, 0x70a12315, 0xb08f44d9,
+0x5fbb9453, 0x4bc62738, 0x9fa15ffc, 0xe4033ca1,
+0xc9dfbc13, 0x58245d7d, 0x588113aa, 0x8f5a6ac8,
+0x92588a60, 0x26330c74, 0xb2aaf0e3, 0x24ada1ea,
+0xa9e973ae, 0x624b73e7, 0x4ef961db, 0x95ede155,
+0xf2bb86ff, 0x96bc79d9, 0x95cd646b, 0x1c3af453,
+0xf60fa711, 0x10905115, 0x0e24b740, 0x169bb227,
+0x34cee6f0, 0x990980db, 0x18d8ace5, 0xd4c87504,
+0x29515d32, 0x2e5d9c04, 0x87dffa60, 0x12e815d1,
+0x021db8e9, 0x2c5a42fd, 0x6e3a1a13, 0x88889ab5,
+0x3bc915a6, 0x608919c5, 0xd310a970, 0xea8f3218,
+0x949f55bc, 0x9ed7aadd, 0x6d990157, 0x181f1c2f,
+0xa940df64, 0xf3be8c39, 0x7ca2e699, 0x7b4f07f9,
+0x89e83fee, 0xe66b9493, 0x54fc3d17, 0xa63d2d46,
+0xd5e835d5, 0x910e0144, 0xecf67025, 0x1fa6a93a,
+0xe692dbca, 0x466af681, 0xc2bc808c, 0xbb4ebd60,
+0x74d5c729, 0xa283ad25, 0x1e66fa23, 0x6d372988,
+0x753c9fcb, 0x1742efdb, 0x5b68cf15, 0x372a0e33,
+0xaa3a7ebd, 0xa0e944d5, 0x95d5cbb4, 0x4fb6020b,
+0xced927b0, 0xb2afea78, 0xd0646b72, 0x1622fad4,
+0x4672c6b6, 0x736ae4f8, 0x8d46a4db, 0x0e6a432e,
+0xe0a30a98, 0x4c2bcf4f, 0xd87acedd, 0x19682d7a,
+0xf97c025c, 0x55d8feb3, 0xbcd4d2ff, 0x236c6f9f,
+0x8ba0246d, 0x42812f73, 0x327636f5, 0xc92cd30a,
+0x08a69d9d, 0xc735a946, 0x82eca01f, 0xda0753a0,
+0x7077b1d1, 0x17b05834, 0xfa24bc02, 0xf49f4473,
+0x8f9ac6b4, 0xa880c630, 0xf7457b4d, 0xd5f829e4,
+0x25c49a99, 0x1176a997, 0xbb2d2009, 0x61d35764,
+0xa322c752, 0x6ef3ae02, 0x5faae6f8, 0x9a52acf1,
+0x19176f43, 0x43843b07, 0x14efc471, 0xee474403,
+0x319c4857, 0xa19adcf0, 0xc0a466e1, 0x02db14ad,
+0xb7f211f3, 0x72aa6ca6, 0x0eb9bffe, 0x48a6d284,
+0x9a93a2ee, 0xac09fc5f, 0x92a62c4f, 0xd34f0271,
+0xffb348c7, 0xf229b6e2, 0xc68ec1ca, 0x19577dbc,
+0x069a10bf, 0xf64ac347, 0xf7c3c848, 0x81975294,
+0x6376e550, 0x93b53440, 0x8bb17daa, 0xc4c64c07,
+0xcaeff293, 0xd51497b0, 0x33da3565, 0xa73d5def,
+0x4bf4dcde, 0xfb470fcd, 0xca7db864, 0x7ef17022,
+0x47567363, 0xd8fb8d74, 0xa68c3c72, 0x8202e4f3,
+0x75bf1798, 0x16a70fd2, 0xcc3b697f, 0xab9a1075,
+0x13f56ef3, 0x269d0302, 0xcb655a43, 0xc9a4de88,
+0xfb8363de, 0xff40f36d, 0xd2555489, 0x647a7995,
+0xfd8eda6e, 0xa3958c9a, 0x20e029b4, 0xbed3e225,
+0xa7df5f17, 0x63bc3c1a, 0x337ecc9d, 0x6c329508,
+0x786aa47e, 0x1db5b093, 0xc0acd73b, 0xf9587237,
+0x243e5d40, 0xd3623c3a, 0x338c4740, 0xb672140e,
+0x43640a9b, 0xb7ef3f6a, 0x44151074, 0x749bcc46,
+0xfa1f103b, 0x0fefb19e, 0x58855538, 0x138ad276,
+0x2641fd80, 0x297d99d0, 0xfaa63ba2, 0x00b6f11a,
+0x3793fb6b, 0x124763a1, 0x8b9419ac, 0x56abf9eb,
+0xdbf83419, 0x43570571, 0x37299cd8, 0x8b201e62,
+0xa4058fa5, 0xb320e91b, 0xbe7d40b7, 0x4eca3b2d,
+0x8519c155, 0xf4b17021, 0x9e4c572a, 0xdc1f9e16,
+0x39a589a3, 0xa6cfc7a8, 0x5b986910, 0x64e150e7,
+0x60b6f2c1, 0x02bacd3f, 0x2f3b5a5c, 0xc6f453a8,
+0x15a87a7e, 0x76104a14, 0xafa2ef63, 0x2cd48dbe,
+0x3c7abddc, 0xd786ea5a, 0x4f65867a, 0x355cda38,
+0x2ae03d9e, 0x4f11f6be, 0xfc0a0034, 0xde4ea602,
+0x21ff83ea, 0x0f12d913, 0xedf4da28, 0xc96d8fd1,
+0xd7e82c3c, 0xfec63bdc, 0x37a456d7, 0x3007e18c,
+0x091a47b6, 0x82f1c641, 0x82219cce, 0x3e7e6993,
+0x7b3a2115, 0x0b8e1a02, 0x40f88213, 0xfa2f9c21,
diff --git a/src/cpu/intel/model_206ax/microcode-M12306A2_00000008.h b/src/cpu/intel/model_206ax/microcode-M12306A2_00000008.h
new file mode 100644
index 0000000..05b0ce2
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12306A2_00000008.h
@@ -0,0 +1,512 @@
+ 0x00000001, 0x00000008, 0x05182011, 0x000306a2,
+ 0xa0e51feb, 0x00000001, 0x00000012, 0x00001fd0,
+ 0x00002000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000a1, 0x00020001, 0x00000008,
+ 0x00000000, 0x00000000, 0x20110517, 0x000007d1,
+ 0x00000001, 0x000306a2, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x94ff6556, 0xcfa79d17, 0xb29f811e, 0x8e4ec2b0,
+ 0xb5beb75c, 0x6c9aaf43, 0xcc4c0bcb, 0x12875d19,
+ 0x5a3401db, 0x42caecce, 0xb4d8e75e, 0xe6dbaf24,
+ 0x7861b35f, 0x6bd717bc, 0x23b9b731, 0x82ec1ac8,
+ 0x20337b64, 0x5396dbf1, 0x59973bff, 0x724bc7e9,
+ 0x5237193b, 0x0b8647c1, 0x6a0d0e16, 0xbf9ddb5b,
+ 0xace2cc1c, 0xad707638, 0x056f102f, 0xa37e60f8,
+ 0x76255642, 0xfb86e030, 0xb8069a40, 0x367795f1,
+ 0x653fb05e, 0xab7f14ad, 0xb6e8a8e1, 0xd2598d20,
+ 0x2eba3f68, 0x78b372f1, 0xba8d13f8, 0x1f1de861,
+ 0x97f951d5, 0x8097c728, 0x27dbf904, 0xb97906a8,
+ 0xffe7a4ac, 0x4b947668, 0xc1dbd726, 0x2adcf777,
+ 0x63b1bcf0, 0x818e2a1b, 0x49aa907b, 0x2faf5e8d,
+ 0xae842352, 0x82707fae, 0x0aa12b41, 0xa0bae11c,
+ 0xb4298c47, 0xd2b4099c, 0x4ff625f2, 0xcd2630d4,
+ 0x79850981, 0x05dbf57d, 0xb05b81a5, 0x56e73ec7,
+ 0x95cb3897, 0xe262bda5, 0xb2c6e288, 0xcb7f8e77,
+ 0x72b8bdd3, 0x3f400494, 0x63ade65b, 0xbc4adc71,
+ 0x00000011, 0xb03d8772, 0xd6a6410f, 0xc3179f60,
+ 0xd049131b, 0x520c95e1, 0xfce4c8db, 0xb512c2eb,
+ 0x71736977, 0x8269157b, 0xcf5c1ee7, 0x8c63bd78,
+ 0x2263191b, 0xbfbf7e8b, 0x8f58e2c2, 0x26b839f1,
+ 0x6931ac98, 0xb03191aa, 0xf863752d, 0x390b30a1,
+ 0x5f67d45b, 0x79b0a425, 0xb1af06e0, 0x2808d62b,
+ 0xbb0a3a45, 0x7946943b, 0xfd63fd33, 0xc9f36fd2,
+ 0x81a5c023, 0x3ab0bef3, 0xcb0971c0, 0xd9274c2e,
+ 0x2ea257c8, 0x1d5b0c47, 0x430a995b, 0xe699699f,
+ 0x308fd8b5, 0x5ca9c648, 0xc5bd5637, 0xd21170dc,
+ 0xf28e5d70, 0x6cf557a6, 0xa468b1a0, 0x733d9a21,
+ 0x0a6361b7, 0x9afba13f, 0xc6742be8, 0xbe117903,
+ 0x0df10451, 0x4ce0b9b4, 0x9358b04d, 0x35b6fe86,
+ 0xd4fe9173, 0x8100695a, 0x027a7905, 0x5e4630ce,
+ 0xc2de9c98, 0xc8a878a4, 0x2bb006a4, 0x70e1c64a,
+ 0x3fefce54, 0x0fe1e5bb, 0xe1e8607e, 0xcf15a032,
+ 0xa89164af, 0x391c6cef, 0x814bd538, 0x3faaa9bc,
+ 0x7178e47b, 0x0784f21a, 0x4de0fd07, 0x4826d856,
+ 0x4fa2919f, 0x68b71ea7, 0x6d173f26, 0xdd964132,
+ 0xa9371aa3, 0x8c17143f, 0x9eb8fbb3, 0x039bd218,
+ 0x49e3c295, 0xbe9b55bf, 0x8ac611a0, 0xcf9ee50b,
+ 0xf4174264, 0x56830a33, 0x6e95f589, 0x203110b7,
+ 0x03220d7d, 0x96fc409d, 0x799627a9, 0x0623d281,
+ 0xfab5c71b, 0x283a9e67, 0x29711a51, 0xa406a081,
+ 0x09dd9197, 0x9ad69ded, 0xab0489e2, 0x2e1a6290,
+ 0x4de2ef22, 0x43d05f21, 0x14723f83, 0x913460f4,
+ 0x327d1438, 0xdffaa8b4, 0xc3476930, 0x938699f0,
+ 0xd83efc42, 0xc42048e0, 0x27007e37, 0x923cedd9,
+ 0x696b16cd, 0xb7b6431d, 0x8ac1ef16, 0x2a999058,
+ 0x651f28ae, 0x2593b094, 0xe5de2961, 0x89eccc60,
+ 0xbb351bae, 0xb389e3db, 0xcfa740d1, 0x862efecc,
+ 0xe3f1ef72, 0xd5925e62, 0x0e42857e, 0xdb437f85,
+ 0x4b78c822, 0xff4f4e61, 0xf87ce802, 0x43deb62c,
+ 0x5d23bcd0, 0x8c9619cd, 0x041fe9cc, 0x2b1f6bf3,
+ 0x38a65285, 0xfa663b8c, 0xb017ce6f, 0x8443a4a1,
+ 0x98871c14, 0x4d1b98a8, 0xa2ef625d, 0xdd0c9c2b,
+ 0xb2b45d98, 0x5795cbbd, 0xe4706ad4, 0x62373590,
+ 0xd98e08db, 0xb40e41cb, 0xb1b46b7d, 0x221d459b,
+ 0x73ca6dd9, 0xfce856ec, 0x65a750a4, 0x11a57c32,
+ 0x5983498d, 0xa8c39e1c, 0xa5a98619, 0xd579c642,
+ 0x6461bebf, 0xbab072de, 0x936e2cec, 0x04960797,
+ 0x6b7c6511, 0xbe6b2ef8, 0x0bdccd98, 0x828616b3,
+ 0xe39628c2, 0x64598833, 0x831279c4, 0x98395550,
+ 0x04679721, 0x9a457c16, 0x8c1683b0, 0x0f8cf077,
+ 0x07efbb31, 0xda2f14ff, 0xaac369ca, 0x7cc9b256,
+ 0x1667a14b, 0xa888067c, 0x9754978a, 0xf6397d5b,
+ 0x73588192, 0x5aa8bb83, 0xe18f1a56, 0x19a4b1d8,
+ 0xaf762b09, 0xccfd08a7, 0xb36e9849, 0x263bffd6,
+ 0xa262c17b, 0xfb64d1e1, 0xe0058700, 0xb2f65b82,
+ 0xbee5145f, 0xf87fa269, 0xea3c80d8, 0xd2893c81,
+ 0xee8a55d0, 0x34dddf88, 0xe2a059b9, 0x09438e94,
+ 0xfa401ed1, 0xee39e712, 0x846b3a45, 0xb97451b8,
+ 0x8c0d3b43, 0x45a1a844, 0x1bb204e9, 0x9146826a,
+ 0xff91a1f9, 0x49a230e9, 0x1b51cc54, 0x60028676,
+ 0xd3568726, 0x5655536c, 0xea1495a8, 0x92373d55,
+ 0x7b4a00cb, 0x4b23f0a2, 0x130f4d04, 0x0e80fa92,
+ 0xd0f93f5c, 0x4dc1db58, 0xdac405e3, 0x4304afa8,
+ 0x5cdaef88, 0xec05bade, 0xf7ac28b1, 0x8d644682,
+ 0x32d4f61f, 0xecfa19e9, 0x793759d7, 0xfa4f4fbf,
+ 0x673fff26, 0x5ce785e3, 0xfa3ae4ec, 0xac6183d1,
+ 0xfdf01f6f, 0x030c9334, 0x52bbc321, 0x5a8c5018,
+ 0x4759ac5f, 0xc546bf93, 0x5f139300, 0x2bee6e97,
+ 0xeb1d150d, 0x7a98804b, 0xace72c17, 0xa0dc5838,
+ 0xdb7070f9, 0x482fc62a, 0x8a1ea5b4, 0x351d9c41,
+ 0x57519edd, 0xeaaa21db, 0x85991fb8, 0x5998ad19,
+ 0xfba37420, 0x7df2156f, 0x2b653fef, 0x2e589698,
+ 0xe9ef8767, 0xa6638ccd, 0x52a04fb9, 0xc5590be2,
+ 0xb4c0e51a, 0xccb1c346, 0xa2e07ae4, 0x01eb9c97,
+ 0x94c58182, 0xbc30d487, 0xf142698e, 0x7700f473,
+ 0xc5151420, 0xeae2f346, 0x07b30428, 0xc77d89fa,
+ 0x56849cb7, 0x681b7f9a, 0x8873f721, 0x57a8400a,
+ 0x6e099ffa, 0x4bec7f09, 0x26839ab5, 0x92518225,
+ 0xa0b0c668, 0x437f75d2, 0x8f409bd0, 0x48e75e72,
+ 0xebe49143, 0x82e94781, 0x183b152f, 0x00b55162,
+ 0x113d9669, 0xf7673ddd, 0xc9acef67, 0x1864cefa,
+ 0x54b1d9f4, 0x276c6a3e, 0xe629ab95, 0x8312d175,
+ 0x097737e5, 0xbb1c8308, 0xeef95191, 0x5edde323,
+ 0xd1877c8b, 0x0f55e271, 0x22359485, 0x6b918644,
+ 0x1f3c258c, 0x1c277c19, 0x037e89da, 0x57b9a00b,
+ 0xf365fbfe, 0xf300e553, 0x0b6352cc, 0x79c58e00,
+ 0x63a35d22, 0x9f9d12fb, 0x3e496970, 0xd2e25746,
+ 0x793cd7c1, 0x1b1992d2, 0x0f4c3126, 0x48f2208a,
+ 0xb362a176, 0x77dd555b, 0x9b9e3ea0, 0x3d076bca,
+ 0xa7ba3c81, 0x4ea97870, 0x49ed147d, 0xdc4d6ed8,
+ 0xb78a03e2, 0x49cae375, 0xe1fa5dd6, 0xb8250134,
+ 0x09b55b81, 0x140f27e7, 0x0c77f5d9, 0xc522ca9a,
+ 0xcade480c, 0x4ff22f3c, 0x05bcfd2a, 0x0aceaf1d,
+ 0xb490be3c, 0xaf8f7bb3, 0x72c33cb8, 0xa68b46e0,
+ 0x11a5dc32, 0x6667023c, 0x380bb3ce, 0x9661fe4c,
+ 0x31babb98, 0x2c2e32e6, 0x5a46cd7b, 0x05fc2598,
+ 0xad69a4e9, 0xec17e594, 0x228a3149, 0x9e3ce0be,
+ 0xf37de385, 0x918a3544, 0x0a49c000, 0x41401ead,
+ 0x889350ef, 0x504019f3, 0xe50d5ada, 0x1a1b9d84,
+ 0xe75c5cad, 0xd7ad4c62, 0xc8b200ef, 0x5039425c,
+ 0x50f1cb8e, 0x68423198, 0xa48c18e7, 0x2eb57a4c,
+ 0x4f4cbde8, 0xe46023dd, 0xe82326f7, 0x86c145ed,
+ 0x391f27f1, 0x6c0728f1, 0x44e69f49, 0x0d4643c2,
+ 0x2a9199b3, 0xfcc19418, 0xf5125acc, 0x6ce054b5,
+ 0xfd59cff7, 0xede79cd0, 0x5d99938f, 0x80e438ad,
+ 0xcba3cf92, 0x8cce29ef, 0xb2efa81c, 0x1806394c,
+ 0x7162e333, 0xa0742075, 0x2d8d47da, 0x8c2da510,
+ 0xa7369ad9, 0x0ddbd050, 0x682f8e72, 0x98c7ae2e,
+ 0x97e05e6f, 0x080f5b96, 0x52ab150e, 0xda83cdad,
+ 0xbb86a3c2, 0x1f07a09b, 0x402724ac, 0xf6682636,
+ 0xeaade001, 0x54221b6d, 0x8dfad0db, 0xe98ff62e,
+ 0xda2c7419, 0xd12c52a2, 0xc10960ad, 0x424b3756,
+ 0x877b7ef7, 0x52517df4, 0x4c27ef34, 0xdb698f6c,
+ 0x2acdc1e7, 0x6c1aad60, 0x20b9115f, 0xe203e9e4,
+ 0x27926d6d, 0xb22e1fcd, 0x2d90815c, 0xa0407863,
+ 0x3c8bf847, 0x3410c5fc, 0x5caf97ad, 0x023d4014,
+ 0xd022ae9a, 0x600bc542, 0x6e3d48df, 0x8f3f125b,
+ 0x307856b8, 0x2d285245, 0x4fb5ec67, 0x689a27c5,
+ 0x0f43ca47, 0xcf81b5f3, 0x82490870, 0x16a8e704,
+ 0x52249e33, 0x04fbf10e, 0xcc18e015, 0x5235f8d2,
+ 0x9442be25, 0xa0423a64, 0x7e20a86e, 0x3a0501fd,
+ 0x0b0525fb, 0x9b5a9d8f, 0x3451e597, 0x05c738b3,
+ 0x07ed1fcd, 0xa1fee521, 0x2a89fdbe, 0xb7d370e8,
+ 0xe9556569, 0xfb0ee802, 0xe536be91, 0x2a728ee9,
+ 0x1b108409, 0x4c347e5b, 0x8db8372c, 0x06be53d1,
+ 0xe92ea058, 0x84de4cb7, 0x1645c7f2, 0x08e6e386,
+ 0x6ee876f4, 0x89340508, 0x95a2ead8, 0xaae14210,
+ 0x3a611fdc, 0x7b7baf87, 0xb17dc84b, 0x8faa05a0,
+ 0x66855ef8, 0x9178fbee, 0xdecd716a, 0x7c2397c8,
+ 0xac7887d0, 0x7ef446db, 0x44089087, 0xab15bf19,
+ 0x101bac0f, 0x8524a2bc, 0x74339af0, 0xb1942522,
+ 0x176eacbe, 0x0ad55197, 0xde787be5, 0xd401c900,
+ 0xb069856f, 0x8e8d777d, 0x5e7a6b14, 0xfe527701,
+ 0x56abefd2, 0x4b41b692, 0xac0d6c79, 0x15bac9f2,
+ 0x07f7aaff, 0x820c1e9e, 0x00094122, 0xf1aa3c70,
+ 0xb8fba13b, 0x790a336e, 0x6d41e3e8, 0x996df919,
+ 0x955fd4aa, 0xceaf238c, 0x031cee79, 0x386e92f9,
+ 0x8e595245, 0x85b11a2a, 0x4fa71496, 0xe85de73e,
+ 0xbfe9d5cf, 0x108c7cfa, 0xdd7d72ec, 0x3a2a6c59,
+ 0x77a50226, 0xc01c70c8, 0xa50c6790, 0x4a07d26f,
+ 0xe5297723, 0xfe8943f9, 0xca4a2956, 0xcb5fe2f0,
+ 0x5e75d892, 0x69abebc9, 0xbfc45600, 0xbdb40208,
+ 0xfb06a5dc, 0xc11af78a, 0x70ee6456, 0x129bccc0,
+ 0x7c952b1f, 0x655bd786, 0x61f05603, 0x2ddfa7b2,
+ 0xd9aebcee, 0x860f2482, 0x6ee642d4, 0xa0f7901c,
+ 0x46fd0f34, 0x0d836566, 0x7090d792, 0x3bb2845b,
+ 0x40216573, 0x89bac49c, 0x1b365e7a, 0xa4e89d88,
+ 0x5b4467f7, 0x16736e9c, 0xc47fe035, 0xc9782676,
+ 0xa1233e8a, 0xc692f38c, 0x49ba9bbb, 0x38b512b2,
+ 0xbe116d78, 0x9b984bc0, 0x64c686d2, 0x966e669e,
+ 0x627d9828, 0x1fe32056, 0x404b2809, 0x8754652c,
+ 0x72602dce, 0x2933251f, 0xfe93dcff, 0x00e74579,
+ 0x0934063e, 0x6ca7246b, 0x135d16dc, 0xad24193f,
+ 0xc4ae209a, 0x4137bdab, 0x412524a9, 0x0b782e9c,
+ 0x559a36c8, 0x8fee5b28, 0x354d5634, 0x1359e536,
+ 0x1f99643e, 0x8ce5d917, 0x64fbd18d, 0xd358834d,
+ 0x6103a887, 0xc41dd6a4, 0x82a4dff6, 0x354cd281,
+ 0xa3cb27af, 0x9523335e, 0xa3e5d6fa, 0x3af3ab9c,
+ 0x1d92f0dc, 0xa9c393d8, 0xa4d58cee, 0x01a80348,
+ 0x3b028340, 0x21292723, 0x2a1063be, 0xfcf4626b,
+ 0x258935d1, 0x0c47874c, 0x370c7eed, 0xb5869f78,
+ 0x142d3148, 0xc34705b5, 0xb3180331, 0x6b870ead,
+ 0x7d372b3a, 0x9b8205ed, 0x97ed2d65, 0xba816031,
+ 0x1ce2d2d2, 0xb5a23cfc, 0x5b0f481d, 0xb9e04a85,
+ 0xaeedb91c, 0x6c5f8f1e, 0x90ac1c0b, 0xf87424d0,
+ 0x5903cbb6, 0x1f241a99, 0xd4fd1d96, 0x5ba9f8f4,
+ 0x06527ea6, 0x25fa5ebe, 0x649c61dc, 0xb2e250f3,
+ 0xa0d74482, 0x4028ff95, 0x51078b1c, 0x7baf1d00,
+ 0xf60a69b4, 0x6543da8a, 0xfb8aaeeb, 0xc79c89a9,
+ 0x764e1b65, 0xd50125d4, 0x302d5abb, 0xe74f0b6b,
+ 0x41526db6, 0x343b79e4, 0x0680e918, 0xe417622f,
+ 0x2137d39d, 0xb34fd1fd, 0xd02ae803, 0xaadfe2d5,
+ 0x1b4648a2, 0xf3be09a3, 0xe02d4747, 0xc7c4e60c,
+ 0x01bfc0d9, 0xcaa2545c, 0x97fa559e, 0x894b2a99,
+ 0x82975bc7, 0x3d7a2db0, 0xb4fa48d9, 0xd601651b,
+ 0xada87426, 0x480dcab1, 0xc834b5cf, 0xbb649872,
+ 0x78217b04, 0x57a68ed8, 0x50f43c86, 0x2369fbf0,
+ 0x4f579983, 0x5c3dc02b, 0x34d3f7b0, 0x727cdffd,
+ 0x32112f46, 0x38ff4006, 0xbe26b403, 0xf8f1f76a,
+ 0x5c954d47, 0x734517d8, 0x19e77599, 0x4c645649,
+ 0x13267038, 0xdd4ccaa5, 0x34525ec5, 0x32357fcd,
+ 0x4ee39656, 0x3a5c5abe, 0xbc53aa1f, 0x0a5b0bba,
+ 0x330e2bc0, 0xc57e3fa1, 0x5cbc4c42, 0xcf97a05a,
+ 0x221c8d8e, 0x27e466ab, 0xf753109c, 0x1d75627e,
+ 0xa194b0d4, 0x6f76d457, 0x3ab323d0, 0x960202be,
+ 0x5f750281, 0x7c66da6b, 0x76eaf698, 0xb3ffea6d,
+ 0x3caa1c15, 0xda40100a, 0xd5eb25f1, 0x19e79d92,
+ 0x07f31866, 0xaa5c7230, 0xbf34a043, 0x266c573c,
+ 0x26f4fc77, 0x49ce60c3, 0x4849bc11, 0xf3cb6d2e,
+ 0x44bf978b, 0x103cb16e, 0xab36cd00, 0x2c88b696,
+ 0x252e310b, 0x5fe44c53, 0x019698a6, 0xdf7c6c6c,
+ 0xb5f9fc55, 0xc02b94ea, 0xcec55282, 0x5c7809fd,
+ 0x7d3b9c22, 0x979a12e7, 0xfbb88d9f, 0x622369cf,
+ 0x9bd48bec, 0xc5f78a5b, 0x43480d02, 0xc8f23cb9,
+ 0xa74fcded, 0x4a57a9f2, 0x742c0fa9, 0x79cf075e,
+ 0x4c3cec0e, 0xf5b57270, 0xd6920751, 0xa68c3a90,
+ 0x85d95209, 0x79598ba4, 0xc7cff1c6, 0xbe13c8ba,
+ 0xef636173, 0xe9448e6c, 0x0abdd206, 0xd587c53f,
+ 0x651d6e28, 0xf655655b, 0xcc8d5f27, 0x0334db5e,
+ 0xed742441, 0x00ec414e, 0x78c215b7, 0x92a17727,
+ 0x94d4de40, 0xa6c89e31, 0xef0e9cb3, 0xcaaf4dfe,
+ 0x62b108a7, 0x1f11d211, 0x8e6d80c2, 0x9019632b,
+ 0x27bb59fc, 0xec670644, 0x9937c4c1, 0xc71ba54a,
+ 0x0d99ce08, 0x0c582524, 0x2ade4596, 0x6c6d19e7,
+ 0x24d5d408, 0x2a774ecf, 0x4783c121, 0x562dd75b,
+ 0x0bf93b88, 0xf02f26bc, 0x55dccf10, 0x97210218,
+ 0x6fb30a5f, 0xb8e289d6, 0x62f4691c, 0xd6a7bb48,
+ 0xcd72b10a, 0x040506df, 0x1b3c97f8, 0xfead0632,
+ 0x3517cbb2, 0x37229acd, 0xde46fba5, 0x44cbfc9f,
+ 0x0e190df1, 0xc0667958, 0xf65111c5, 0x1344f0ad,
+ 0x1bc3063d, 0x5549ee04, 0x58c6e0c8, 0xb3f48cc1,
+ 0x109081b8, 0x20524fca, 0x60f044e3, 0xda4c0b57,
+ 0xbc0b2d01, 0x4258d7dd, 0x235878a6, 0xbe7b8103,
+ 0xc3b9360a, 0x01e63ca6, 0x89ed00b4, 0xfd9f2654,
+ 0x25852e93, 0x409ee6e2, 0xcc548be5, 0xe6139471,
+ 0x93674f7d, 0x39456d64, 0xac347169, 0x9986745e,
+ 0x599a139c, 0x19124870, 0x7402de5d, 0x3a526063,
+ 0xc71cb5db, 0x114e4bba, 0x63cf3a96, 0xde873102,
+ 0x20baaf7c, 0x28230a72, 0x5144dedf, 0x9265313f,
+ 0x0bcda190, 0x77f1fc1e, 0x53f67026, 0x805dc15d,
+ 0xaeb6f6f3, 0xc7db990a, 0x9c19fa42, 0x9afb07d0,
+ 0xa0dbfd20, 0x7657406a, 0xcc279772, 0xb5be41d2,
+ 0x9b7d1568, 0x027075e4, 0x65362117, 0x2a35a675,
+ 0x00fc01f5, 0x85243c1b, 0x052bb326, 0x48564c13,
+ 0x3d49a902, 0xa2719bd0, 0x9634c037, 0xcc61cc93,
+ 0x5ecb40b5, 0x221e6297, 0xeb800e10, 0xdda6c6a1,
+ 0x7c0e7d69, 0xf13e9850, 0x15e4ad94, 0x6d994c59,
+ 0xf7aaad83, 0xbbbddecd, 0x4d08d515, 0x4534557f,
+ 0x88499baa, 0x85642d7d, 0xce057574, 0x7a8fcecf,
+ 0xb1e36024, 0x7bae9b8a, 0xb17795ef, 0x4daad89b,
+ 0x5bd2390b, 0x1358e77e, 0xf0254d35, 0x990a23b3,
+ 0x6fe79940, 0xdc9452ef, 0xd7299274, 0xba28364a,
+ 0x8c33bcf3, 0x5dd8fd27, 0xdc0b7188, 0x20ae1980,
+ 0x10bad203, 0x71207d35, 0x4d4932a6, 0xdde5722b,
+ 0x0d09dc66, 0x166d4e7b, 0xc4048d5b, 0xfe8a18a7,
+ 0xc4bf6c43, 0x33bb066b, 0x4ab6d34e, 0xa6f9191f,
+ 0x4d124cb7, 0x38a55a03, 0xa2904e20, 0x4ea3f407,
+ 0x486e4c24, 0x9261f56d, 0xdaeff698, 0x38feebf5,
+ 0x2b8e50a2, 0x61baa841, 0xe16b0719, 0xcaae5c26,
+ 0x0a33e85a, 0xb954cb72, 0x2e3f4201, 0xc0dd26bd,
+ 0xcdfbff5c, 0x26a1a823, 0x981b0d07, 0x2fee4978,
+ 0xf99b8039, 0x5d25dac2, 0xcd6934c1, 0x066228f6,
+ 0xba7e0704, 0x337a1b20, 0x8c323be3, 0x7ff9c315,
+ 0xf4ac9eb3, 0x5fc1175d, 0xdc296f20, 0x41d498a2,
+ 0xd3d7c30b, 0xe7386b05, 0xdd2dba6d, 0xe2e81592,
+ 0x9ea5b6dd, 0x357be182, 0x83d9c558, 0x28a5717d,
+ 0x54d5b3d9, 0xc0e43744, 0x5f2e7524, 0x09ab2d34,
+ 0x7e6a9707, 0x176caa28, 0x2e82adfc, 0x3b3081da,
+ 0x1c7d7047, 0x791acb94, 0x85554aca, 0xd340db82,
+ 0x17ab8f41, 0x57d4079f, 0x6909bf5f, 0x67926a3f,
+ 0x4699d010, 0x6ab9fd79, 0x5bcfe302, 0xc8331dcc,
+ 0x06438b8d, 0xe4f4a14e, 0x16bdd6a1, 0xbd522605,
+ 0xfdc3f0fd, 0x1519c8d3, 0xc028a731, 0xfa093171,
+ 0xd9e7ad75, 0xf101f517, 0x21fc9f6a, 0xa722aecb,
+ 0x478eb517, 0x531ef72d, 0xc729d08f, 0x1b43148a,
+ 0x57e617d0, 0x327422e5, 0xb7a20ad6, 0xc25ccf5c,
+ 0x9bb93736, 0x0ad5ab2f, 0x16353f25, 0x7e64734c,
+ 0xc1a7c1f1, 0xf8d949ff, 0x31bc7294, 0xfcbdecd7,
+ 0x3b4a5813, 0xffa05a93, 0x8b56f1e8, 0xf1932e6f,
+ 0x188d84d0, 0x0b77acea, 0x6b838d06, 0x307fcbd7,
+ 0x03755582, 0xdd8fccb2, 0xbe2465b1, 0x4cc8e1be,
+ 0xa7673f91, 0x5d22ef2c, 0xf34b5c90, 0xa055faef,
+ 0x23582017, 0x42ad337b, 0x2239da5e, 0x51447628,
+ 0x59d2e16b, 0xd853c1de, 0xffd49bdb, 0xbc334817,
+ 0xb2d18b9b, 0xc8692375, 0xfa851045, 0x82e9cf0b,
+ 0xe377945f, 0x942a7b28, 0xc00f78da, 0xa26cdac0,
+ 0x7b52fc41, 0x3b49aca2, 0xeaf3b2ca, 0x61c6849a,
+ 0xa8d3c24d, 0xc0d80f55, 0x4c77d1d9, 0xe07a7713,
+ 0x24cea55b, 0xf7839272, 0x837a2e88, 0xb6a20e1c,
+ 0x385ba2d6, 0x5d16140f, 0xf755021e, 0x9d588670,
+ 0x81c9e230, 0xf8ce940e, 0xe8f0b292, 0x1656e7b2,
+ 0xa3345b8c, 0x651b48f6, 0xba13d42a, 0x51ff69e7,
+ 0xceeba4df, 0x7c5d1b2b, 0x201ae48c, 0x1f6e6d22,
+ 0x0fa59228, 0x073a3fad, 0x476c7965, 0x6cb62b62,
+ 0xca850d99, 0x659d223d, 0x340fd07f, 0x2c26dace,
+ 0xfd0b441d, 0x2ddca03c, 0x0c3c870f, 0x66f2587e,
+ 0x60b0cc54, 0xe64fff4f, 0x6404437b, 0x131802bb,
+ 0xbdaff5c8, 0x8315c5d8, 0x87a0bf17, 0x6f7cb63a,
+ 0x955d568a, 0x6b6a40af, 0x93902e51, 0x624a8eda,
+ 0xa457e199, 0x33469b2f, 0x79ddd09c, 0x0781d418,
+ 0x8685284d, 0x41257c02, 0x0218e1c8, 0xb8a65398,
+ 0xe2394e17, 0x271966b7, 0x3cdedc6e, 0x97b0d5e7,
+ 0x5ae801bc, 0xd23df137, 0x32a4cc8a, 0xfa675478,
+ 0x27720acb, 0xfd06aa13, 0x1a9563ce, 0xb9ddae63,
+ 0x39e9f560, 0xdcb8c8ea, 0xec327cad, 0xad00bc29,
+ 0x628a204a, 0x010ccda5, 0x4ae1e6b7, 0x7839b974,
+ 0xed8ab90c, 0xd190cf1a, 0x6329a130, 0xbfa3fae2,
+ 0x84e0388a, 0x9cd706b5, 0x98a3f5e9, 0x43dca149,
+ 0x66e49f64, 0xd70bfb71, 0xea5470d3, 0x4620eb99,
+ 0x13b98bf9, 0x66d96da6, 0xd833f53b, 0x940d0cb9,
+ 0xbb440af1, 0x24b1244e, 0x982197ab, 0xe667c0b1,
+ 0x60b6b551, 0x15965925, 0xcd8ab77f, 0x6ffb8611,
+ 0x6c8a292e, 0x10977564, 0xf44663ea, 0x0fe25bd9,
+ 0x80ccfa9d, 0x73048454, 0xd85fe220, 0x17b677f4,
+ 0x65801095, 0xd5d65368, 0xef594093, 0x4f02ed98,
+ 0x3cb19a2b, 0x8cf0abeb, 0xcb3c5f45, 0xec9567e1,
+ 0xac374fee, 0xe83dc258, 0x1af95b60, 0xaf060682,
+ 0x26017849, 0xb2f2e63d, 0x543a16d7, 0x12bd7fe3,
+ 0xc84adc42, 0xa8a6dba9, 0x44e0522a, 0x55d73c6a,
+ 0x7ebd500a, 0xece58173, 0x0b301361, 0xc4f19eca,
+ 0xb19fbffc, 0x14fef202, 0x928def14, 0xf57934af,
+ 0xade67654, 0x1ca5f860, 0x4e29489a, 0x1aa27463,
+ 0xcd05a93a, 0x0ffd7d0b, 0x9623738c, 0xe9b8fe32,
+ 0x61b5f6a6, 0x3121b153, 0xabd3333c, 0x3ca6219d,
+ 0x5ebff047, 0x4aa52427, 0x138b9eaf, 0x5108fade,
+ 0x69ee4246, 0x7037c5d1, 0xf26dae96, 0x1d38eccd,
+ 0x0aa2cd66, 0x96ab1831, 0xb7b276b9, 0x39fced26,
+ 0x13509355, 0xd76ead9f, 0xc98a8245, 0x75ff6c22,
+ 0x3426ed0f, 0xba14d8a1, 0x471f2b07, 0xceb2ff8f,
+ 0x43689aa0, 0xe4730653, 0xbfb95948, 0x4aa28781,
+ 0xe08179e2, 0xd991f3e8, 0x209e5832, 0x9e37da37,
+ 0xdbaf59ad, 0xd3d43c18, 0x089146f7, 0x728562bc,
+ 0x4c945175, 0x3a9de3fe, 0xead91cde, 0x5538f57e,
+ 0x297e2b5d, 0xcfda2ca6, 0x785adb1a, 0xf7540ba4,
+ 0xe1c56896, 0x4c0c1e19, 0xeb21a193, 0x1f1f5309,
+ 0xf449ba96, 0x6c891e2d, 0x0af978ba, 0x3e58e1ec,
+ 0x44bc156c, 0x0a528fcf, 0xad839e9a, 0x7c6c6b9b,
+ 0xa262f8bf, 0xed487cf1, 0x86b340cc, 0xa09a3775,
+ 0xf978cc6f, 0x1dd9e65e, 0x1b88e260, 0x2b0fa5c5,
+ 0x761ce2b0, 0x3f3b2977, 0x25c1c34d, 0x26e3e571,
+ 0xb6802175, 0xf76a96f6, 0x473fb196, 0x70142f84,
+ 0x0abcced3, 0xa21c9323, 0x412ea89f, 0x5a626915,
+ 0xfdf011ab, 0x2ffcab0d, 0x069d494f, 0x1f552fdf,
+ 0x66c8591d, 0x5a7c8b22, 0x8c335ccb, 0x37d379f7,
+ 0x79e16156, 0x7466ee57, 0x127bc692, 0x9400b22a,
+ 0x09364486, 0x0316c196, 0x420c1552, 0x0c1a7abe,
+ 0xc5237341, 0x205a538f, 0xbc5ae40e, 0xabb331d8,
+ 0x5ec3564b, 0x03a9fcad, 0x873e95db, 0xbe00c106,
+ 0xa1e5d4cc, 0x7aebb184, 0x47ce0c74, 0x7fa6e961,
+ 0x773e3b87, 0x0e26bb7d, 0xdcca3728, 0x423b252f,
+ 0x7a42fe7a, 0x1037ece8, 0xbcdb0059, 0x14e57421,
+ 0x6a37ea84, 0xa3793edd, 0xf1ab67a5, 0x1f89f5df,
+ 0x2f08884b, 0x4e8ed270, 0x70f965b2, 0x8c7ca58f,
+ 0x6742b86f, 0x89d6fe1f, 0x03afdfc8, 0x50673d59,
+ 0x39ee965c, 0x6c639901, 0xc2b65f41, 0x5a0cab77,
+ 0x14003d7f, 0x43f81eb5, 0xeb2cc0dc, 0x1a2acf75,
+ 0x7e055e67, 0xe0b8d46f, 0x0a815cc3, 0x28e86302,
+ 0x6a8eb3b3, 0x04196feb, 0xd5e3e038, 0xcb976ce5,
+ 0xfe05abb9, 0xe0aa007d, 0x90f2e2c3, 0x39057bd1,
+ 0x3c0d6bab, 0x899b9401, 0x5ad4e6bd, 0x3485a43e,
+ 0xaeb38525, 0x0aecea20, 0x61511612, 0x239eeb81,
+ 0x427008bf, 0xd3379a76, 0x4b4ee9be, 0x46032dd8,
+ 0x16452895, 0x0b53dd9c, 0xa3880161, 0x841acbe1,
+ 0xe8231020, 0xa11ab5a2, 0xe73d795f, 0xb7f62278,
+ 0x61fd1534, 0xd2dbd080, 0xd0b1a0ea, 0x51a14706,
+ 0x5341a037, 0x5b9bdd64, 0x4939a4be, 0x1d6bfc7f,
+ 0xd971c13e, 0x42983916, 0x5b9e530d, 0xaf728716,
+ 0x248a5250, 0x4869a41b, 0x22761c4d, 0x7bb8ab7e,
+ 0x538ff2e1, 0x509ffeed, 0xf4e68208, 0x8c850e0b,
+ 0x09282053, 0x1c4840dd, 0x8c54f998, 0xf4e705d3,
+ 0x823b3aaa, 0x5abddff5, 0x03013f7f, 0x8ae4d768,
+ 0xece6cbf9, 0xe66caa0a, 0xdb303498, 0xf07334a9,
+ 0xe89f4aab, 0x5faf6759, 0xad1a4a2e, 0xb953b70e,
+ 0x8fc75252, 0x569ecc20, 0xb4067d6d, 0x542ced01,
+ 0x14f05874, 0x3b0872c4, 0x2d4bbc5e, 0x15819311,
+ 0xd3a00956, 0x7cc4cccf, 0x5c21c744, 0xc11174f8,
+ 0x6522a922, 0x0706b0d2, 0x80a63b03, 0xed58edb4,
+ 0x874a8ec5, 0x066e8360, 0xfcf4af9e, 0x788e52a0,
+ 0xd3b020fd, 0x106e3502, 0x04e447a0, 0x933528a9,
+ 0x7dffcd54, 0x3e40b13e, 0x567f4a9f, 0xe4190a67,
+ 0x904c7d49, 0x525b4b7d, 0x4fd40a24, 0x30f7d2a8,
+ 0x47e953ae, 0x3f966c56, 0xa86c9b10, 0x3f1add27,
+ 0xf05e1c2c, 0xe6286279, 0x880a2224, 0xcb2b8e00,
+ 0xa55bd474, 0xfb8404ce, 0x45be6081, 0xb54b3bdc,
+ 0x3d6eccc1, 0x982d691f, 0x6d7a38d4, 0xab2afc6e,
+ 0xeb07addc, 0x6609be95, 0x64c3b658, 0xb51336c2,
+ 0xc4e211e9, 0x2da523d3, 0x37099aba, 0xa6b76d02,
+ 0x3e25b5dc, 0x7658d7c4, 0x82587cfe, 0xaa8fcb70,
+ 0x6f39d48f, 0x8a9bf171, 0x37816d5c, 0xe2553caf,
+ 0xaf5efae4, 0x28bc89b4, 0x209d05e4, 0x276f777f,
+ 0x677e8d41, 0x23dd6005, 0xf2a9c8dd, 0xc9cf245d,
+ 0x7d800e9e, 0x2bbaae1b, 0x295708d4, 0x27446095,
+ 0x012ab8a1, 0xb378bf9e, 0xbba0a97d, 0xcc0badeb,
+ 0xf0c56a87, 0x6de5f550, 0xc51abd35, 0x785ece33,
+ 0x066879d0, 0xb03e5228, 0x4255e2e0, 0x2f9c9ed8,
+ 0x944aaaf6, 0x543f84d9, 0xf0581cde, 0x39743ba4,
+ 0x2a408c43, 0x68849eb2, 0x398b8b2d, 0xc583c53a,
+ 0xa02426ad, 0x2dfd572e, 0xb8d64fbf, 0xada6868f,
+ 0xce107bee, 0x5cffa0d6, 0x16c36c79, 0x972c59e9,
+ 0x4804fb78, 0xa74271eb, 0x30e33dc2, 0xd9810651,
+ 0x904a0334, 0xd7c55c53, 0x8cd3afba, 0x11e6115d,
+ 0x2c9bc958, 0x005fb92e, 0x7620b68d, 0x96839df4,
+ 0x6e906fae, 0xff72c67a, 0x2f6f2fc8, 0xc77140e0,
+ 0x0bb70fc6, 0xb465002d, 0x8e4ddcc7, 0x506438e5,
+ 0x4876de45, 0xd59e9d4d, 0x263ca61e, 0x25c5657e,
+ 0x3da43a5a, 0x03add868, 0x7fdc5e12, 0x2f7144e4,
+ 0x7402f204, 0xe52a898e, 0x41010c79, 0x96a28935,
+ 0x2c471566, 0xe6993392, 0x99db96b7, 0x7603b736,
+ 0x8eef59fa, 0x3fd40e58, 0xc8410c77, 0x46ac6007,
+ 0x0a5f7576, 0x712e2755, 0x448d7764, 0x7a528ecc,
+ 0x48f56308, 0xc5f2422b, 0xcb6b7520, 0x6a3f75f1,
+ 0x8dbcb7aa, 0x5ac6588d, 0xd52e29c2, 0x73f1f592,
+ 0xe6fbf90f, 0x12255f80, 0x905b7a61, 0x77255392,
+ 0x3b0a2d15, 0x3a27c651, 0x12eb67b4, 0xfca53a97,
+ 0x17fed5ff, 0xb48fef9d, 0x6feef9e5, 0x5b215030,
+ 0xc412c5a6, 0x2528fc95, 0x6ac8b956, 0xf7f96f29,
+ 0x6fd1bbd5, 0x8f40d6fd, 0x03ceb0ca, 0x4272a3a3,
+ 0xd845bc6f, 0x444f8f52, 0xa53a5c19, 0xfeddf13d,
+ 0x1a8705d7, 0xdb5f526d, 0x7b17f0f2, 0xf9b556e8,
+ 0x0efb625a, 0x116b0ca1, 0x6adec476, 0xd3290962,
+ 0xcd6544c7, 0x66ebd670, 0xf7cf89c7, 0x8cec409b,
+ 0x904bd4f8, 0x00714689, 0x74e45dbf, 0x76fb3fd9,
+ 0xd60f7ea7, 0xf2ed6d9a, 0xff5b4b7a, 0x95cc5343,
+ 0x4161ad19, 0xc1fc3ee9, 0x58627163, 0xe090cb5d,
+ 0x16d36e21, 0xf753e038, 0x291ad1b2, 0x96b61f40,
+ 0x0aff600f, 0xe36cc959, 0xbf78ae41, 0x02382911,
+ 0x310114e2, 0xedaab306, 0x4d8a5a94, 0xcc51c0bd,
+ 0xf896a312, 0x404cc886, 0x5d469823, 0x19138390,
+ 0x4e478b4d, 0x4af7ed31, 0xfb5f6068, 0xb4aad5db,
+ 0xf40ea203, 0x098357cb, 0xe48dcf55, 0x3ecc63eb,
+ 0x57e6b677, 0x04c26490, 0xa78c507e, 0x07ccf951,
+ 0x7fa83420, 0x63638d9e, 0x8b344723, 0xf81138b3,
+ 0x509c0561, 0x0c044466, 0x6a1847bb, 0xa5b8390b,
+ 0xb05c9a71, 0x509903f6, 0xa5c30d89, 0x09e9c3b2,
+ 0x8aa23b84, 0xc624b8ee, 0xc8d30f0b, 0x585baea0,
+ 0xadfbc05f, 0x430f9e86, 0xcea65781, 0xe2f92f01,
+ 0x8e58a07a, 0x7e0ca7ce, 0xa231ebdb, 0x3c81dc1c,
+ 0x192a7758, 0x398befd6, 0x2b0c1d21, 0xf3361352,
+ 0xd6e04807, 0x540d1831, 0x91e3f217, 0x5108207b,
+ 0xfa6ea712, 0x834a5893, 0x006da259, 0xf8af43f4,
+ 0x641c6c3a, 0xb19f94ab, 0xa506bb54, 0x121d8d81,
+ 0xc88397c6, 0xa8a0ff6e, 0x050c1cd6, 0x7a616dd7,
+ 0x363b9cf8, 0xe4c9f2bb, 0x6ae1d5ef, 0x0be739f2,
+ 0xf9dc24e1, 0x7e5ae30c, 0x98e85d4e, 0x85bb98e8,
+ 0x4395da0e, 0x5eb89b18, 0x1ed53732, 0xa4fb1aa8,
+ 0x7c41e550, 0x1385fead, 0xc3970ad0, 0x9ce74279,
+ 0x5df9a345, 0x7f2dc938, 0x65fab066, 0x2e4bf388,
+ 0xde835e94, 0xfa18d76f, 0xbc8e9809, 0x1afb5a18,
+ 0xab09bca4, 0x95e13e76, 0x62b565d5, 0xcc303d51,
+ 0xdb27ca4e, 0x61cb95ab, 0xa20b7f79, 0x137cd1d1,
+ 0xc0cbbd7f, 0x380568f2, 0x39807d8b, 0xbe925a54,
+ 0x0bdce5f7, 0xcb40ff17, 0xf5aab191, 0xecfa5ca6,
+ 0x598fb8e4, 0x523d4a5d, 0xa7b849f6, 0x0a24d5e2,
+ 0xd890405e, 0x4cb6cee8, 0xa004765e, 0x840be587,
+ 0xb7a4ba78, 0x2845138a, 0x24aa30c1, 0x926bdfba,
+ 0x21d39639, 0x6446d413, 0x8f61306c, 0x58bc4695,
+ 0x802d0b44, 0xaf2bb84a, 0x2c6705e6, 0xc7841eda,
+ 0xe8c43604, 0xd46c72f1, 0xf4f70d38, 0xeaf6cf76,
+ 0x39b452ec, 0xa6cf0abd, 0xc1c6664a, 0xc8b377ee,
+ 0xd15a5e30, 0x5f7adfe3, 0x52a43c6d, 0x6abbf0e2,
+ 0xdca9ac20, 0x85275fff, 0xe8851daf, 0x5356c5d4,
+ 0xe124bb52, 0xac28d954, 0xee70cd07, 0x92442739,
+ 0xc4ebbaf7, 0xbc1b0765, 0x04633ab7, 0x2c40182a,
+ 0x515de804, 0x761cb00e, 0x55e2736f, 0xabe392d3,
+ 0x1606ab31, 0x65bab89a, 0xb92e2aab, 0x784a9334,
+ 0x481356f8, 0xb142662f, 0x321a2630, 0x9ac0a6b2,
+ 0x880e424a, 0x53745533, 0x03a0bd19, 0xba764eaf,
+ 0x85c69ded, 0xa9614c60, 0x72b92597, 0xc2019232,
+ 0x87b0b4a9, 0x4dc7065e, 0xb1fd2896, 0x040ddce6,
+ 0xfa7785b1, 0xccc389a9, 0xb79f295b, 0xcba3aa36,
+ 0x61a7396b, 0x5ff0bd25, 0xba717c7b, 0x16ae6582,
+ 0x56e43f40, 0xf145ec96, 0x70547b08, 0x4d737e21,
+ 0x41955ce6, 0xf3438d68, 0x0fc9ce5b, 0xc071e980,
+ 0x356df762, 0xd030905f, 0x5fa0efac, 0x1098ac64,
+ 0x937766d6, 0x5f56f835, 0xcb7b24f7, 0xeb0f4ec3,
+ 0x220ee6ca, 0xe8ff8f72, 0xce166acf, 0x73ac4f8d,
+ 0xfc30d28a, 0xc0577298, 0xa51d7a8c, 0x8ddadba7,
+ 0x85c3093c, 0x67287f64, 0xdcb5b3f0, 0xe9b01e78,
+ 0x5dd04462, 0xa2d67b33, 0x289edd77, 0x12558cc4,
+ 0xfe4c3e88, 0xfd74ad66, 0x379c651f, 0x11fb5bd6,
+ 0xda9c38b2, 0x4161dddf, 0x3d8c8828, 0x3fac762e,
+ 0xf9a7217b, 0x5b1feb5c, 0x4525f697, 0x0f19feae,
+ 0x7d07fd16, 0x27d158d5, 0xa7a8e81f, 0x71dcb0aa,
+ 0x6c57a48e, 0xefb8a817, 0x4f367674, 0xa90c9b22,
+ 0x561e6b23, 0x52d11b5c, 0x52260020, 0xcd05088c,
+ 0x4d2c124c, 0xdb72bd6c, 0x58d2d9a9, 0x88fa1748,
+ 0xb3ad05c8, 0xdb167422, 0xb5db8ad5, 0x37d0cd11,
+ 0x926c6ec0, 0x2585541c, 0x9fabbf8c, 0x80c1b1a4,
+ 0x242babff, 0xbb686018, 0x3bf68389, 0xb0972998,
+ 0xe610bc5a, 0xc539d1df, 0xe9b6c911, 0x81fccd86,
+ 0xc710804f, 0xb646161e, 0xd2a0669d, 0x9d23c437,
+ 0x7b846680, 0x1ed6daaa, 0xaf7caf3e, 0x5c017e95,
+ 0xc3bf784d, 0x27fec315, 0xc52f2d6c, 0x8b2aaf84,
+ 0x0b6aa659, 0x46f3133e, 0x624a87e9, 0x436844a7,
+ 0x2ce9cfde, 0x98f00c12, 0xb68c181d, 0x5f8e93a4,
+ 0xe1d72390, 0xdbb7bd8b, 0xe82c45af, 0xe8d95468,
+ 0x18f20406, 0x37329cd3, 0xafeb5437, 0x909de54a,
+ 0x67e31339, 0x2a90b199, 0xf66fc078, 0xa5a477c1,
+ 0xad598121, 0xd67cec01, 0x31da6b5a, 0x923f759a,
+ 0xd936adec, 0xdb6c21a2, 0x8e32c84f, 0xbec79a87,
+ 0x07f9f323, 0xd8fa595b, 0x44162a12, 0x0932e616,
+ 0xa127c8cf, 0x762433fe, 0x15bb722b, 0xf1ca78d4,
+ 0xe0b5de21, 0x1e561a3c, 0xe8e49bb5, 0x3ef69845,
+ 0x014b1920, 0xd56ed7b4, 0xd8068eb5, 0x369a21b1,
+ 0x4639fede, 0x8f243107, 0x939fa0cf, 0xe6d620e4,
+ 0xba18058a, 0x808f3d01, 0xed052ad3, 0x09829d7d,
+ 0xd4b18c54, 0x2c7a4569, 0x700a8a66, 0x61b6c28c,
+ 0xd34a2db7, 0xc788b319, 0x6fdd44b8, 0x9394c34d,
+ 0x5c56967e, 0x36929553, 0x49a3d41d, 0xa51409e5,
+ 0xc0449831, 0xbd2abbdd, 0xa46b122f, 0x636d6ca4,
+ 0x4d9c82d6, 0x7786178f, 0x1d29e68a, 0x020766b5,
diff --git a/src/cpu/intel/model_206ax/microcode-M12306A4_00000007.h b/src/cpu/intel/model_206ax/microcode-M12306A4_00000007.h
new file mode 100644
index 0000000..989081c
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12306A4_00000007.h
@@ -0,0 +1,576 @@
+ 0x00000001, 0x00000007, 0x09082011, 0x000306a4,
+ 0x7e23e5af, 0x00000001, 0x00000012, 0x000023d0,
+ 0x00002400, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000a1, 0x00020001, 0x00000007,
+ 0x00000000, 0x00000000, 0x20110907, 0x000008d1,
+ 0x00000001, 0x000306a4, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xb3a03995, 0x1d99bbc7, 0x1a0f8f30, 0x7d07bab1,
+ 0x0b26d78b, 0x0cad10d7, 0x4be62ef8, 0xe11cf1e6,
+ 0x5a3401db, 0x42caecce, 0xb4d8e75e, 0xe6dbaf24,
+ 0x7861b35f, 0x6bd717bc, 0x23b9b731, 0x82ec1ac8,
+ 0x20337b64, 0x5396dbf1, 0x59973bff, 0x724bc7e9,
+ 0x5237193b, 0x0b8647c1, 0x6a0d0e16, 0xbf9ddb5b,
+ 0xace2cc1c, 0xad707638, 0x056f102f, 0xa37e60f8,
+ 0x76255642, 0xfb86e030, 0xb8069a40, 0x367795f1,
+ 0x653fb05e, 0xab7f14ad, 0xb6e8a8e1, 0xd2598d20,
+ 0x2eba3f68, 0x78b372f1, 0xba8d13f8, 0x1f1de861,
+ 0x97f951d5, 0x8097c728, 0x27dbf904, 0xb97906a8,
+ 0xffe7a4ac, 0x4b947668, 0xc1dbd726, 0x2adcf777,
+ 0x63b1bcf0, 0x818e2a1b, 0x49aa907b, 0x2faf5e8d,
+ 0xae842352, 0x82707fae, 0x0aa12b41, 0xa0bae11c,
+ 0xb4298c47, 0xd2b4099c, 0x4ff625f2, 0xcd2630d4,
+ 0x79850981, 0x05dbf57d, 0xb05b81a5, 0x56e73ec7,
+ 0x95cb3897, 0xe262bda5, 0xb2c6e288, 0xcb7f8e77,
+ 0x72b8bdd3, 0x3f400494, 0x63ade65b, 0xbc4adc71,
+ 0x00000011, 0x19abf071, 0x575e6385, 0x36ebcdfe,
+ 0x57f4937c, 0x92fbe313, 0x1d5512a5, 0x0905c16a,
+ 0x8de33f42, 0xb6818477, 0x233c41ff, 0x6c1d4d53,
+ 0x9c1be6ad, 0x623ec48c, 0x91508e0a, 0x79253847,
+ 0x85d8e18e, 0xdc150937, 0xf974828d, 0x81ba11ff,
+ 0x7d9d91b0, 0x214843ac, 0x9434d146, 0x2ec1fce7,
+ 0xc16e8737, 0x027ba667, 0x52b9808d, 0x6eb2bda2,
+ 0x770c9cf1, 0x96521f7b, 0x2fbc4f54, 0xdeb1a3a8,
+ 0xfbfc8582, 0xc3dcb6ca, 0xdef8632a, 0xcfed28ab,
+ 0xcfe1e086, 0x37511ec2, 0x18686104, 0x2ecc7231,
+ 0x102e474a, 0x3d7f8dea, 0x9454227e, 0x43bef27d,
+ 0x1cb1868a, 0x264a89f6, 0x9adfb681, 0x76407c96,
+ 0x477b3e8c, 0xe70917f8, 0xd922c68b, 0xaeaed84e,
+ 0xb596c67c, 0x1d13fb45, 0xfb22f377, 0x3e170148,
+ 0x3db16d05, 0x3afc649a, 0xa7af0815, 0xd37c35bb,
+ 0x72aa63b8, 0x2d937be5, 0x35258930, 0x67e1a556,
+ 0x2f402d84, 0x4cbd1331, 0xe36a0104, 0x83c9817d,
+ 0x6090b7de, 0xe6140e95, 0xc93378ab, 0xbe8a7e29,
+ 0x31282549, 0x6fcc9a48, 0xab3fd69e, 0x6d416631,
+ 0x43933197, 0xd740ad28, 0x529bbb3f, 0x60743c20,
+ 0xa8f63be0, 0x658f28be, 0xd7b58381, 0x4b815237,
+ 0x58594057, 0x8dabb3b4, 0x07a25b23, 0x4032bf20,
+ 0x77daa69e, 0xf67bf7b8, 0x90ced783, 0xded37555,
+ 0x2d6af421, 0x916ea5ab, 0x167465b5, 0xe3bcd36e,
+ 0x508bf21c, 0x73853f7e, 0x2880ed76, 0x225c788c,
+ 0x15ec0f5a, 0x15acc7be, 0xc6a06337, 0xdbfcfcd0,
+ 0xa21b5839, 0x740e6e38, 0xa8b43643, 0x7651cc4b,
+ 0xa12d4b31, 0x386cc72e, 0xe57b512a, 0x786fce17,
+ 0x6b4d127f, 0x6ae88cc6, 0xf3297dac, 0xd0cba77e,
+ 0xe4693105, 0x6c5e0d4c, 0x1aa89ae3, 0xbd393a08,
+ 0x68ce716d, 0x9bcc507c, 0xb972aa10, 0x52c911dd,
+ 0x8da8be43, 0xb6da1d9c, 0xaf13b041, 0x66de981e,
+ 0xa3924b55, 0x33c2ba86, 0xf6e8fa50, 0xc8428735,
+ 0xd9500ca8, 0x2d30e9df, 0x15c7b4c9, 0x661c4bdb,
+ 0x5bd7b778, 0xa88adead, 0x749dc059, 0xd0876ba4,
+ 0xb2c58c54, 0x29b7b8f9, 0xc3e838a7, 0xe1005a1c,
+ 0x9ad5c2d9, 0xdec51c8d, 0xe5e2ba05, 0x2efdcd0e,
+ 0x4e983aab, 0x57db53cf, 0x883cbc3e, 0x77e4606b,
+ 0xb0a312a1, 0xc9007482, 0x95847d9e, 0x488c37ea,
+ 0x60af9eb1, 0x05dae2df, 0xf0706b79, 0x5c5e596c,
+ 0x020c60c0, 0x3685039e, 0x724091ea, 0xb8203ea5,
+ 0x5396ab30, 0xeb4bbbb0, 0x2c843dce, 0x91cca5b2,
+ 0x7f846faa, 0x1414aae2, 0x3182deee, 0xda997d06,
+ 0x218b63a5, 0x321fac27, 0xa1ad3122, 0xe481a05c,
+ 0x78a5308e, 0x3df4f921, 0x88eab5c3, 0x749d1a1f,
+ 0x90bafaf7, 0x01a86381, 0xd6dcb109, 0x5a381934,
+ 0xe1b2ecd4, 0x04dfe933, 0xf79a65d5, 0x2e6eea9e,
+ 0x9e85aef6, 0x8181267c, 0x78ea07aa, 0x421c2c89,
+ 0xe05f6ae6, 0x46547f9e, 0xcb428cf1, 0x6a29c749,
+ 0xa0841467, 0xe231df3b, 0xd1d131ed, 0x0b90e8c2,
+ 0x6c997511, 0x4fc0a070, 0xc4f29403, 0xa39c0d07,
+ 0xd12972c6, 0x28d229cf, 0xc41fd64f, 0xf45daa92,
+ 0x58fb8aa8, 0xc7a283b6, 0xe49f2316, 0x5b68bb84,
+ 0x69dc9cb0, 0x8c54be58, 0x40c9f099, 0x2dae4ba5,
+ 0xcf7c8d10, 0x133f7708, 0xc853a94b, 0x7cc290d2,
+ 0xbef31399, 0x76ab3883, 0x62ca514a, 0x2c8600eb,
+ 0x62093203, 0x25b2bfd9, 0x8ee2907e, 0xaea4867a,
+ 0x9499913a, 0x57ecaf91, 0x80a3f1ae, 0x2c8bee30,
+ 0xa3a7dcb3, 0xb10fbb26, 0xd78ea136, 0xbce5f1e0,
+ 0x7b7b3ccd, 0x46753e6a, 0xefb8fb11, 0x97048045,
+ 0x14278dd1, 0xe105225b, 0x773c9088, 0x713c4cb0,
+ 0x2cca528f, 0x45f41034, 0x39728447, 0x73dc9a51,
+ 0x8c940b5e, 0xf799830d, 0xd01f5d09, 0xd5431a00,
+ 0x35d806e8, 0xd8f39f19, 0x09b85f61, 0x7faad8a6,
+ 0xf1fdf364, 0x338b046d, 0x29769669, 0xf5ea3620,
+ 0x6d4a51d2, 0x1af81917, 0xaac93080, 0xaf23163b,
+ 0x590899c8, 0x875f7dea, 0xd1dd5f92, 0x5ef57034,
+ 0x726a4ccc, 0xa8db944e, 0xfd1b8651, 0x0ea53afc,
+ 0x77095765, 0x67bb5b61, 0x1c8ccdd1, 0x282cc5e8,
+ 0x99b5b1a4, 0x992f09ef, 0x4b7cc638, 0xb01f8ba4,
+ 0xeedfbb34, 0x08032a16, 0x20df1801, 0xdd549c83,
+ 0xc98bc230, 0xb6aa95d1, 0xfacbee14, 0x62e29252,
+ 0x4860d2c4, 0x25f7a7c8, 0x2b92beb5, 0x4a730c54,
+ 0x0736c512, 0xb998a584, 0xf218847c, 0xdc820ce7,
+ 0x19f2f9a5, 0x21a82370, 0xefe72372, 0x8e003cd6,
+ 0xf4f8dd29, 0xeac46a58, 0x0948738f, 0x2dff22bf,
+ 0xef1a9b1c, 0xdbd54942, 0x090c14c4, 0xe3aa27c9,
+ 0x0d7dc1f6, 0x29d72b82, 0xbc6fa51e, 0xf4401294,
+ 0x20e2a293, 0xa8eb9685, 0x5a28dcb9, 0x37323458,
+ 0xb3479f64, 0x8afb14c2, 0x4cb8ce1a, 0x8a1f318a,
+ 0x984b8e40, 0x071a40d0, 0x307afe99, 0x1802a7db,
+ 0xcbceab6e, 0x37493f96, 0xb10a984c, 0xb80c70b1,
+ 0x53c56287, 0x67728ded, 0xbd21ef96, 0xe1521485,
+ 0x8cc8ac0c, 0xf90b32b6, 0x2ee7992c, 0xdfaaac98,
+ 0x7df2c219, 0x583aa4e6, 0xcf6f513b, 0xc1053364,
+ 0xc191a928, 0x6f9c0bcf, 0x30801e06, 0x5caf1fcf,
+ 0xce41b4f5, 0x1e23000d, 0x21cb56ab, 0xa0f4b728,
+ 0x8ce5c84f, 0x7cd86048, 0xdcbb964b, 0x765cf373,
+ 0xf809cb81, 0xf03507d8, 0xf294d43d, 0xe41745ce,
+ 0xe24a314c, 0x18cb3342, 0x4bb837f7, 0x085c741c,
+ 0x415e64e0, 0xb8dd16e7, 0x0f7c3cec, 0xa47d66a3,
+ 0x72315363, 0x06835946, 0x1aef4dd3, 0x423344df,
+ 0x01b07c51, 0xaed97e91, 0xab70300d, 0x1b43d0f3,
+ 0x46b16ac7, 0x3d166779, 0x6258643f, 0x10368aa9,
+ 0xb9c87eb1, 0xa3d70988, 0x84ab98bf, 0xb7f0dd6a,
+ 0xa0a36b4a, 0x627e374d, 0x6dc1135c, 0x82b85706,
+ 0x41c8be24, 0x6d479f63, 0xcbb87d49, 0x43c53a97,
+ 0xa70aca34, 0xa1f43320, 0xacd255f0, 0x05061e4f,
+ 0x0d026da0, 0x257b9d7e, 0x95f5dc24, 0xf3888c08,
+ 0xe5d4a1cd, 0x219f9f2b, 0x38b0eb4c, 0xa5aefb4b,
+ 0x98921ed5, 0x4dd4df26, 0x59229d41, 0x8ba8906b,
+ 0x56b38a69, 0x8d9ce578, 0x607558c9, 0xc64795e8,
+ 0x0e0c2bc9, 0xca64a377, 0x726efba7, 0x9c2f5f9e,
+ 0xb8ed25a8, 0x9dd4d875, 0xd7617c22, 0x77e875be,
+ 0xbf282699, 0x0f575dcb, 0xa0b25cd5, 0xd0d58e6b,
+ 0xbb546f19, 0xff33d417, 0x1a4089b0, 0x8c6c2089,
+ 0xefdac5d2, 0xd307ffaf, 0xf5add107, 0xa97cb249,
+ 0x7a15392e, 0xa314d29b, 0x159140e2, 0x6b1cface,
+ 0x1078b0dc, 0x2e1e2641, 0xf2ff5d66, 0x425731bb,
+ 0x137def65, 0x291cb270, 0xd97d5074, 0xd90e9c12,
+ 0x2a74e10a, 0xce613cd7, 0xda0e191e, 0x063d4ef7,
+ 0x1de08f03, 0x3a516d55, 0xf6aecd3f, 0x4dfa8665,
+ 0xcae6d7d2, 0x3b932e7e, 0x6aa40f12, 0xa4874989,
+ 0xf599574d, 0x63ed7b31, 0xe32b8beb, 0x337692cc,
+ 0x065d65ff, 0x40f43575, 0x701928b3, 0xb62d790f,
+ 0xcfe6cd53, 0x6f9ab30d, 0x5ab29eef, 0x58ff395e,
+ 0x766c6b11, 0xb829aa6f, 0xc1ba3696, 0x6adbb942,
+ 0xf087105e, 0x883ccb50, 0xa80baebe, 0x6a532c5e,
+ 0x0e7f81f7, 0x7d3da268, 0xb0955f4e, 0xbed3c8b0,
+ 0x7a5765e7, 0x384cf1e7, 0xeae2b05c, 0x040e766c,
+ 0x2309f0d4, 0xcaad1d76, 0x52b7b326, 0x5a72ddfd,
+ 0x8f782d7a, 0x455f89d8, 0x89bfe426, 0x0348f165,
+ 0x489b2e0d, 0x990cf7c3, 0xbb61c3f2, 0x36ca2306,
+ 0x4cdca11d, 0xbe6bf45c, 0x51d93659, 0x26f8c7f3,
+ 0xaffbec9f, 0x85ab6174, 0x7444540d, 0x8f0a12e4,
+ 0x3b039d56, 0xe3128b94, 0x53b441db, 0x092a76e9,
+ 0x9fed2d7f, 0x18dc256c, 0xbfdbacd2, 0xa804ed23,
+ 0x43bc563b, 0x68d2c5bf, 0x05c4d52f, 0x06eab2c7,
+ 0x2360545a, 0x0a04e930, 0x2d72c7e3, 0xf4a64ccf,
+ 0x33c3325f, 0x3d7df032, 0xd6d4b945, 0x5faf419c,
+ 0xc8a9e95e, 0xfa80e2c3, 0x135057ee, 0x7a60e004,
+ 0x0f8094dd, 0x3ad99282, 0x69e410ff, 0x186970cb,
+ 0x6a27a9da, 0xd9ad914d, 0x82bb1e8e, 0x08214567,
+ 0x5d2bb249, 0xa610b870, 0xb4d99744, 0x3503cd86,
+ 0x5ed691a6, 0x7db74d82, 0x13d409eb, 0xbc3e729b,
+ 0x36c46d89, 0x10087864, 0xf74ee3c5, 0x188f104f,
+ 0x5e06558b, 0xae22f54e, 0xd01b782c, 0xeb8d0832,
+ 0x0824052e, 0xeccb789b, 0xc31bed4a, 0x3927db31,
+ 0x9566eb89, 0x2736dff3, 0xdf456657, 0x77ff3c12,
+ 0x2215cb1a, 0x9e716e24, 0xcb34aa8b, 0xea3aa46b,
+ 0xc37a05fb, 0xa44070c8, 0x8cb53a3d, 0x382e44e9,
+ 0xcf6ece89, 0xc769a63f, 0x449e9158, 0x582e8aa0,
+ 0x50fad18f, 0x03b087c0, 0xe387e7bf, 0x5ab77856,
+ 0x7bb31f91, 0x75a34299, 0x92acfecf, 0x2b8c3824,
+ 0xd21e48fe, 0xdc22e3f6, 0x5f21cc48, 0x48d9dcaf,
+ 0x2574d9bc, 0xbb945665, 0x105b0a97, 0x8e398cef,
+ 0xbe1b17b8, 0xc639e799, 0x00b169e1, 0x425c6ce5,
+ 0x45cd9081, 0xddb2d2f8, 0xa681e9e1, 0xf0aac2c0,
+ 0xa1bac0c5, 0x379de16c, 0x0a239d83, 0xafb284fb,
+ 0x69902bf5, 0xb2393c90, 0x922dc597, 0xe48bd771,
+ 0xc512bb9b, 0x0d99f3af, 0x6ddc5f57, 0xd717437e,
+ 0x499b1fdd, 0x68319024, 0x4ffa0720, 0x6d4fbe4a,
+ 0xfa393e26, 0x5540e2b7, 0x6c5f2693, 0x82e383e1,
+ 0x6c04192b, 0xe5325618, 0x44df24a0, 0x406a7bdc,
+ 0x5a7bc931, 0xfb7adbd1, 0x3676f27f, 0x9193f7bd,
+ 0xc2a64851, 0xf691cf9f, 0x724f4f81, 0x2ed4605a,
+ 0x1c9a3fed, 0xfbfac0bc, 0xc6fc2f26, 0xa22a1f04,
+ 0xacdfbca9, 0x117789c5, 0x4b159bf3, 0x8726bbe8,
+ 0xaa11c468, 0xc1cbe367, 0x04db4d54, 0x66c848d2,
+ 0x9b7e109b, 0xd88c6bff, 0x6222dd94, 0x5cd17d1a,
+ 0x79e803ea, 0x4f2434f5, 0x54534884, 0x965d2235,
+ 0x198b8cb5, 0xe5f04cc6, 0x1b410573, 0x15077780,
+ 0x001fc7bf, 0xc0cc62b9, 0xe2f0bd21, 0x12da8b04,
+ 0x9eac0221, 0xd589e864, 0x49eb30bc, 0x04b0ea03,
+ 0xa324e1ab, 0xe71aa458, 0x34ba45d9, 0x3b5b487d,
+ 0x7fcf3c01, 0x44f47d48, 0xdeb974ae, 0x2a972848,
+ 0xa21cbd97, 0x584ec628, 0x3f1de1be, 0xc7527634,
+ 0xf44a8137, 0xc4adb799, 0x70abebf6, 0xff21aa07,
+ 0x62481764, 0x31e37d46, 0x8781a8b6, 0xc2b363de,
+ 0xc836ecca, 0xe83d4fbf, 0x150ed79b, 0x7c904bdf,
+ 0x94250f64, 0xf660eefa, 0x81c38094, 0x96094ecb,
+ 0x9104b303, 0x2e515c05, 0x675b2e51, 0x09520c3c,
+ 0xbec0c984, 0xcf079906, 0x71a8d449, 0x8a97fde5,
+ 0x3afb7fbd, 0x3b64f9fa, 0x55d19b11, 0x32c0eb4e,
+ 0xd1fe2cf1, 0x3ddc23ae, 0xdc7294bf, 0x0e249f0c,
+ 0xb3c576a3, 0x618e16bc, 0xc8e95e71, 0x95bfd3f0,
+ 0x8c931f95, 0xf2b2a117, 0x632c8b99, 0x20ef6b5f,
+ 0x8bfb64c3, 0x3f86d990, 0x4f6765bb, 0x6640f99c,
+ 0x1f3ba4f4, 0x130a5f9e, 0x3c6262ae, 0x58c845f4,
+ 0x28ed2140, 0x042756f1, 0x96151c0e, 0xee23cde9,
+ 0xac1e1328, 0xd2ab0654, 0xb89e597f, 0x701f47af,
+ 0xdcf675d2, 0x545af75f, 0xb9132ca8, 0x83a5b0a2,
+ 0x3cfdafbf, 0xf44253ac, 0x3c96e1f0, 0xaeba3d99,
+ 0x11d10c3d, 0xe36ceee9, 0x04505fd8, 0x1a718fec,
+ 0xf2b6cfaf, 0xc1e12669, 0x405e1a0f, 0x74ec02c0,
+ 0x03423483, 0x7fcddaff, 0xc1fc2e1f, 0x8215518b,
+ 0xf8b63c01, 0x77d78177, 0x9fabaa4a, 0xd63f22a2,
+ 0x7e55c207, 0x1b06ca27, 0x43f594be, 0x76ff94fa,
+ 0xb713ab03, 0x848abf69, 0xeb41b6bc, 0x8b20895e,
+ 0x7618e5c4, 0xbed98dd5, 0xacf2bd4e, 0x5497b714,
+ 0x3894c78c, 0x3774d3b6, 0x9730846b, 0xe4bd110d,
+ 0x04fdf02e, 0x07308b78, 0x51a0ec6f, 0x8eb947e1,
+ 0x9c13b9a6, 0x6db24694, 0xabad2049, 0x8049b97c,
+ 0x2b7bf15f, 0xea812ba2, 0x9f995ece, 0xac73417d,
+ 0xfca49ad9, 0xf50beceb, 0x526c0df1, 0x2cf8975d,
+ 0x3b353807, 0xa6438e20, 0xb3ddc8ce, 0xe8479899,
+ 0x4145d910, 0xa2c5d568, 0x23f634ee, 0x80625386,
+ 0xc05b4e4f, 0x0e9e564e, 0x38177d4c, 0xc3427d42,
+ 0x7fa294aa, 0x6bf3ff8b, 0x73106d03, 0xf167be2e,
+ 0xd5e9f885, 0x25547c6b, 0xc22df74e, 0x0d45898b,
+ 0x1f1c0120, 0x711dd9eb, 0x50bac016, 0x190fc1d7,
+ 0x67cac946, 0x88777823, 0x535e17e8, 0x525ee0eb,
+ 0x3faf0333, 0x558a056b, 0xbd0a963f, 0x0724368d,
+ 0x6f5c4133, 0xd054addb, 0x123847fd, 0xc2e49493,
+ 0x3a803cac, 0xcd139148, 0x709074eb, 0x2937814f,
+ 0x2e10831f, 0x4dd439da, 0x9258992f, 0xe4498517,
+ 0x8d8304aa, 0xf2c68bc0, 0x6153968e, 0xfb3e63e5,
+ 0x9f7e9239, 0x14507d5c, 0x48503f78, 0x552f871c,
+ 0x25a61be4, 0x96c2cfea, 0xd902121e, 0xa6a09fde,
+ 0xd66dac1d, 0x5d86aa6e, 0xd90ff409, 0x47968d9c,
+ 0x45668efc, 0x36626277, 0x76121dc6, 0xa38f9459,
+ 0x66fd9602, 0x1f6107cf, 0xbd2270c2, 0xc9a9aa34,
+ 0x1db7d70a, 0x02c63eb1, 0xcc44d2ab, 0xf087333d,
+ 0xbe9f9f5a, 0x1d97e411, 0xb2a9f038, 0x3379bc44,
+ 0xfd5de5ae, 0x37215c9a, 0xe0853a8d, 0x10d948f7,
+ 0x7fb55ee2, 0xe4afdbb3, 0x200f6b38, 0xb5727876,
+ 0x695767fd, 0x1f84ba34, 0x1a4e60f7, 0x47295799,
+ 0xedc0fc72, 0x814e918f, 0xde04d4eb, 0xbd63c229,
+ 0x028d9710, 0x8e3357ea, 0x470daae7, 0x4d124abd,
+ 0x5a18d74f, 0xc2f9f7cb, 0x18437f56, 0x8b85b196,
+ 0x24fc240f, 0xf400c27a, 0xfcd18a68, 0x4db7c38b,
+ 0x5ae45a27, 0x57d9dcd4, 0x1d359848, 0x5312d4ed,
+ 0x093d41ce, 0x9792df11, 0x8a5ae34e, 0xc506e5b3,
+ 0x62f2436f, 0xb46ccff7, 0xc3a2877c, 0xb47c4bcf,
+ 0x042ff7b7, 0xbb351dc2, 0x07a80f57, 0xf00f504a,
+ 0x61fa57d1, 0x6cabe9ac, 0x3f8db966, 0x59c459dd,
+ 0xfe22805a, 0x76231272, 0xbe067850, 0xbeb7e473,
+ 0xebe7884a, 0xfbd672ef, 0xd1d7ea57, 0x21eba2b7,
+ 0xab307832, 0x860b4e87, 0x5e7bc217, 0x4de67fdf,
+ 0x8e157fc0, 0x1c5a6a50, 0xadf02e8e, 0xfbdcedea,
+ 0x8dd4d576, 0xde010af2, 0x954d4562, 0x7b38eec5,
+ 0x9071b1c3, 0xcc6c1300, 0xd8bb8a98, 0x77adc657,
+ 0x35f870de, 0x72c4fb01, 0x2f82b499, 0xbff0fb00,
+ 0x0b9c916e, 0xd51efec5, 0x66aef35f, 0x98c0425d,
+ 0x1257bd59, 0x73c96fb0, 0x143009b6, 0xc8da6154,
+ 0xcedd3931, 0xe639f255, 0x31195455, 0xf8d384f1,
+ 0x7c622711, 0x76461b7e, 0x12d1b13a, 0x49458cad,
+ 0xf70d1701, 0x2258e262, 0xab241855, 0x7e2af8b2,
+ 0x0f4a5415, 0x9fabfb24, 0x025367e3, 0x8ee2dd89,
+ 0x370ace6d, 0x71b1d73d, 0x1be9048d, 0x40268ddd,
+ 0x1bb00dab, 0x08846f16, 0xb1d94d3a, 0x710e6e0f,
+ 0x5c2f324f, 0x41383439, 0x48ca7be0, 0xe55c13aa,
+ 0xf21122b1, 0xf5cdfcab, 0x10f5f7eb, 0x43c07367,
+ 0xcc013676, 0x28fa490a, 0x6c8f7f9a, 0xf68e1b8e,
+ 0xc934f441, 0xd3a873c6, 0x50ca67db, 0xbcc54c78,
+ 0x909d33b4, 0xfb1a331b, 0x4ab01904, 0xcd3c9876,
+ 0xcc564d2f, 0x20091bbd, 0x79755f60, 0x8260b295,
+ 0x53f31a5d, 0x0093a19a, 0x43fdbbac, 0x15e6d171,
+ 0xa77e03f9, 0xf46444a1, 0x897398ac, 0xf6d63a11,
+ 0xfc75a39c, 0xa900fd98, 0xd0dd0777, 0x5cab7856,
+ 0x80d06a1c, 0x9ee8c1d8, 0x1cd7712c, 0x5b1a4f07,
+ 0xb7039a75, 0x62435396, 0x324194bb, 0xae5e5eb5,
+ 0x91cbfc4b, 0x46ef4da2, 0x40571d59, 0x9db9c694,
+ 0xf07420fb, 0x1e6f4e49, 0x7452ae52, 0x1a9cd4e1,
+ 0x3431f092, 0x52bf5917, 0xe2bc92c3, 0x74c7c2e6,
+ 0xc3551052, 0x21993218, 0x988d3083, 0x543f7bba,
+ 0x22684d70, 0xf162e524, 0x92894a49, 0x26e78331,
+ 0xd8b286ef, 0x8cfcb379, 0x00b2ea56, 0x41ae0286,
+ 0x13360a90, 0x84f80051, 0xeba616e2, 0x87a827e2,
+ 0x1bd09ffe, 0x9b70baf3, 0xf3d2a45e, 0x3ceec8fe,
+ 0x696ddfed, 0x70c86b0d, 0xd2b0c194, 0x63606821,
+ 0x2fba5d37, 0x2fab6508, 0x07896201, 0x07b10a17,
+ 0x36ef09e9, 0xdd60c2e9, 0x9c602225, 0xc556599a,
+ 0xec4c491e, 0x6b6c0ebf, 0x178486f8, 0x9ae164d6,
+ 0xdb334752, 0x709b9cfb, 0xb6bb8bb9, 0x383c0808,
+ 0x4703d8e5, 0x2db679ee, 0xac7f3801, 0xc4876dd2,
+ 0xb568e55f, 0xda2fa896, 0x8fe566ca, 0x8c767925,
+ 0x36651163, 0xe7d259e9, 0xf94c850f, 0xb6e9ab4e,
+ 0xd31cce5e, 0xd5794bd1, 0x3130d416, 0x30e2eec3,
+ 0xe9dcf8e5, 0x11d435c4, 0x0d0ec366, 0x845b8178,
+ 0x858a73ae, 0xdd80b6fc, 0x48c85811, 0xe39934f8,
+ 0x1b442724, 0x2515deb5, 0x2efd8f90, 0xab25c3d0,
+ 0x23ce7269, 0x3fde4de1, 0x5a5c6a9d, 0x57e01ac8,
+ 0x9e2375e7, 0x83d0d980, 0xd7ae58b7, 0x0f960a4b,
+ 0xb121d495, 0x00d85784, 0x330fdf7f, 0x72a98d6a,
+ 0xa6431e5a, 0x83b37570, 0xdfe8561a, 0x0def8168,
+ 0x534a7e92, 0x8899222b, 0x6b5c95bf, 0xe968b1dd,
+ 0x1ba4c3f4, 0xb2ae5a7f, 0x12df0337, 0x6dfcfe82,
+ 0x3aa87290, 0xb32e9115, 0xb709b7c3, 0x118968f2,
+ 0x081176ff, 0x9e12bca9, 0x5c18b7a8, 0xbba6183e,
+ 0x222dd29a, 0x612d9cd8, 0xf5f5778a, 0x78e262dc,
+ 0x085022f9, 0x7210f53a, 0xcd39e0cf, 0xea7d3d44,
+ 0xf28012f1, 0x15ef37d5, 0x9b3c568a, 0xa9a67e97,
+ 0x1b79e75a, 0xecd56787, 0x2f4c1cbc, 0x7bd4fab0,
+ 0xee076605, 0x644306e3, 0xb0a4d867, 0xf10ec614,
+ 0xf08158cd, 0x21af5c11, 0x8f52852f, 0x20c602e0,
+ 0x3f06c7b6, 0xfec4ec97, 0x317776f1, 0x88ffe504,
+ 0xdee24a8a, 0x058c9061, 0x5ffbeac5, 0xd5540516,
+ 0x1a89f410, 0x21506f34, 0xf6a5cfbb, 0x6581ef0d,
+ 0x81c5deb2, 0x8059e379, 0xf537286f, 0xc225b03d,
+ 0x6a6912de, 0x59d5f033, 0x116066b7, 0xd870df1d,
+ 0x316e1195, 0x2f7483c2, 0xa990c0f7, 0xcd5ac3d6,
+ 0x95fa591b, 0x40a4d640, 0x8e4a12f5, 0xb52e1b85,
+ 0x9e903fe2, 0x3ed4e751, 0xd28a44e8, 0x3ab4ebec,
+ 0x3f4d21ba, 0xf0ac6886, 0x0f7cf03a, 0xb72c525d,
+ 0x76e7e118, 0x18c1d113, 0x539dae8e, 0x8d25bb9a,
+ 0x484b5d4b, 0x72da9543, 0x20e6b3b8, 0xdbe01baf,
+ 0xba5ec55d, 0x252ed21b, 0xd0727a55, 0xf7003e16,
+ 0x818e1861, 0x1e2c8a25, 0xee76420c, 0xcff6c0d7,
+ 0x8303e9ca, 0x6d229a6b, 0xa9050013, 0xb58d50de,
+ 0x3c4c83aa, 0xbf3875e0, 0x40965c5d, 0xa6e3e509,
+ 0x592f5b92, 0x2c260cfc, 0x8284feb3, 0xd29d5fd5,
+ 0xdd4d8218, 0x0ae2a0cc, 0x1ee9f558, 0x6bfc9bbe,
+ 0x82b48fed, 0x30232706, 0x9c9c0458, 0xc42e6c74,
+ 0x0c56f7b3, 0xfcfaca28, 0xd3957753, 0xa28b1974,
+ 0xf4674ee7, 0xca4f2977, 0x990ef13a, 0x12bc198e,
+ 0x8dd91865, 0x9c1170f7, 0x06eedf30, 0xc1751117,
+ 0xdaca3428, 0x8047dc38, 0x3e87a8b1, 0xf226a647,
+ 0x7c750e79, 0x6b19d571, 0xff42d3de, 0x8797ce4f,
+ 0x8a196cae, 0xe30061b2, 0xa3928975, 0x081e02c9,
+ 0x9a12de54, 0x402e3b79, 0x5ce9d578, 0x463a436f,
+ 0xe94d2649, 0x0ebf55e1, 0x8b78d43b, 0xec91927b,
+ 0x503c0bf8, 0x873bda5a, 0x55b0a7d1, 0x44ebb04c,
+ 0x7823714f, 0xb414bc36, 0xb9b6d07b, 0x54059262,
+ 0x25a50e78, 0x29f6741c, 0x381d43e1, 0x33ffa14e,
+ 0xabd49aba, 0xfe13816b, 0x39a12200, 0xe0035383,
+ 0xf6cf39fa, 0xa51859e4, 0xa2844484, 0x182eb455,
+ 0x64d94cf1, 0xfa5e5cb6, 0xbb9c4ed0, 0xf6eda8cb,
+ 0x6ea7d62d, 0xeca15d1d, 0x8bbd2993, 0x4c6e7d52,
+ 0xfa566995, 0xde1abaea, 0xfddd2591, 0x189af0d6,
+ 0x60b22d4d, 0x8d9e8b8c, 0x0aab95ca, 0x7305be5b,
+ 0x4ba61073, 0x734c5c4d, 0x120b2f0a, 0xc7f69baf,
+ 0xa87a68c9, 0x04a6a2e5, 0xbe3dec54, 0xc16c25f4,
+ 0x17c45f40, 0x99a39ca1, 0xda1b5393, 0xc7985259,
+ 0x52fa8da2, 0x66a28573, 0x6cc37d02, 0x0329b8cd,
+ 0x2cb8e45c, 0x44729798, 0x74f44c0d, 0x65642399,
+ 0x72867ab6, 0x2bee1f1e, 0x7157a738, 0xc37a01fb,
+ 0xd48948c0, 0x94387593, 0x393460a9, 0xa72c7ab3,
+ 0xb3a29184, 0x03ad1cdf, 0x79cc1767, 0xaeac8b9f,
+ 0x1e6453a0, 0x3bfb8383, 0x12b12902, 0xf0a0d2f9,
+ 0x0eff78b5, 0x108fa479, 0x33f1a233, 0xae779a8d,
+ 0x20bc31d9, 0x39f82966, 0xda4a0eeb, 0x90128c2b,
+ 0x9bee3a2c, 0x42ef4e32, 0x020ab513, 0x72a89a05,
+ 0x060fc28a, 0x70ebd8d2, 0x8c2975f5, 0x5b7665ca,
+ 0x0120a9f7, 0xc8deb59b, 0x854fb449, 0x1136f9a3,
+ 0xfd1bd5f2, 0x1826e4f8, 0xdda8d903, 0x3b6d5234,
+ 0x2a11b9a3, 0x61f25f38, 0x2f1c99ae, 0xfb0a99dd,
+ 0xf17104f1, 0xeb7f2b84, 0xa6bb59c9, 0xca24db51,
+ 0x5815f07a, 0x4222bc1a, 0x9aa6de8a, 0xed0c1477,
+ 0x1f45fad7, 0x088fc446, 0xc74595f1, 0xa0c271c5,
+ 0xc28841d2, 0xc2f8a32d, 0x47185b03, 0x6ccfbccf,
+ 0x3e12e6e4, 0xb07b9656, 0x257718b0, 0x1fdd981e,
+ 0x178b5f2c, 0x446cad42, 0xafcdc07d, 0x6277bcbd,
+ 0xfba426f9, 0xa69e0bac, 0x88af0871, 0x854e5f33,
+ 0x19f34f17, 0x30332608, 0x30c8b69a, 0xa563ca2d,
+ 0x30f79b47, 0xd67f18c8, 0xaaf5da97, 0x7c14f966,
+ 0xb1628b44, 0xaadfb39d, 0xecbe0a4c, 0x3be0b53e,
+ 0xd9066672, 0xf8fac3e2, 0x74f1f28b, 0xfbc19563,
+ 0x32bf841e, 0x862545fb, 0x690d55ee, 0xdd8c8540,
+ 0x26cd54f4, 0x501db8ef, 0xfc9c873c, 0x1288a541,
+ 0xea8a3330, 0x928f2842, 0xa680494a, 0x1f6e5540,
+ 0xdbbc143d, 0x139d50d6, 0x138e4d49, 0x9d94ae05,
+ 0xcb28851d, 0xb93cc740, 0xba0be624, 0xe92ad5bd,
+ 0x29fca04a, 0x2b79015f, 0x7538d1d0, 0xdd53357c,
+ 0x5529a541, 0xf0f02503, 0x1c41ba49, 0xd10bd305,
+ 0x4beaf82a, 0x396a1ef9, 0x98480517, 0xf46f5133,
+ 0x5cf72cc6, 0x59041a30, 0xe35788c1, 0x8555f078,
+ 0xdbe4ee07, 0x2d9d4c01, 0x2ea8675e, 0x58f4ab9b,
+ 0xa8a3adb7, 0xea78c9b4, 0x644ec10a, 0x91ff476c,
+ 0xa4ee0099, 0x85c2a71b, 0xe4f0c751, 0x25f7d864,
+ 0x9cdc0c0f, 0x3a6ccd69, 0xc19c5837, 0x33d1bce9,
+ 0x3491b323, 0x64a55b20, 0xfbbf0dc0, 0x80361cf0,
+ 0xc4dfa1ad, 0x47c59434, 0x085bf934, 0xb544fffa,
+ 0x4a6e2b8a, 0x043f9f57, 0x17fced7c, 0x4443ef41,
+ 0x57cd86e7, 0x7bbcdf5d, 0x28c6d5ec, 0x6ea655fe,
+ 0x08cf8ba6, 0xd98493d6, 0x6869fe9c, 0xb1018ba9,
+ 0x00ba69f5, 0x1c1db5db, 0x46a3f43d, 0xfccb13f9,
+ 0x286a158b, 0xbc8456f9, 0xcd70c05b, 0x4875b2f6,
+ 0xaec2f9e7, 0x1d353392, 0x8193baa9, 0x97912c63,
+ 0x2270bd6d, 0xdf48b467, 0x43f862bb, 0x0922716a,
+ 0x59778603, 0xb4eebad7, 0x2ac10451, 0xc8e0f911,
+ 0x8691ae9f, 0xa47cc146, 0x9365b133, 0x78803020,
+ 0x28e4ebdf, 0x33d927ac, 0x48f9cf59, 0x7fe5ea60,
+ 0x358130ec, 0xa33d2b2a, 0x7e4cc747, 0xac1bdd24,
+ 0x9070f611, 0xf57db3d2, 0x0b176723, 0x06ceb308,
+ 0x0d94effe, 0x1965cd46, 0xe3ce8566, 0x76482423,
+ 0x79c72959, 0xb552fdf8, 0x1b252075, 0x34ea64be,
+ 0x2ea74b59, 0x1828528a, 0x5937563a, 0x58fe8d44,
+ 0x3a19b828, 0x6d8a898b, 0x4f86b126, 0x12a5b994,
+ 0x9972c558, 0x963c6b32, 0xc2f07330, 0xf523965c,
+ 0x4dd1e269, 0x279bc606, 0x290ae7ba, 0xff0e1277,
+ 0x35a157bd, 0x24e08231, 0xfce08cc4, 0xf2769488,
+ 0x8e425c9c, 0x483a2418, 0x00e226f2, 0x0abc34a4,
+ 0xba7519c3, 0x8cf47f7a, 0x3b9a456e, 0xcc571017,
+ 0xaeac4c7e, 0x66952d6e, 0x893a254a, 0xab3c6bb2,
+ 0x9ca62b34, 0xa43bc103, 0x637e66ce, 0x840c2532,
+ 0x5a105fb1, 0x665c6c43, 0xb179fddb, 0x74a20c09,
+ 0xe3ecf5a3, 0x50463b4b, 0xb2961aa4, 0x5dbc27e5,
+ 0x6ddea0ad, 0x44a9e587, 0x54e6995d, 0x5cd9c33c,
+ 0xfee1c267, 0x05825ba0, 0xef02e95f, 0x375bf0ce,
+ 0xf5e48110, 0x2c0181e3, 0x823b95d4, 0xb444b3ac,
+ 0x04518b27, 0x536f8f9e, 0xcdc19c53, 0x9960a155,
+ 0xc55a5f23, 0x9c43edca, 0x286738ad, 0xfd56265d,
+ 0x2b62e150, 0x54274276, 0x09a1c288, 0xa8aa5f6c,
+ 0xa4aa3f41, 0xa2ec648e, 0x410d901c, 0x3cb389ab,
+ 0x8a419eec, 0xb84d7dcd, 0xb17aa165, 0x94c652bf,
+ 0x35f7cfee, 0xc3d840a5, 0x30a945aa, 0x020507c0,
+ 0x6ce7f818, 0xbc58090d, 0x4daac2f5, 0x878beb1d,
+ 0xcbdb6eb0, 0x79832250, 0xb3470960, 0xc61bf099,
+ 0xf1ad9092, 0x5ffa5333, 0xefcb5652, 0xfb96c119,
+ 0x487e2b82, 0xc3d00054, 0x0f15fe12, 0x1a54da5a,
+ 0x57ea0e41, 0xc30a4bc3, 0x61a37e3a, 0x15bcfd3d,
+ 0x74e52a3d, 0x5619f4d3, 0xc8ebbc79, 0x60166885,
+ 0xc65d8527, 0xa2d81be6, 0x02e4ee47, 0xc9746e7e,
+ 0xbfd61f0e, 0xb52cf36f, 0x4787da40, 0x6b2ae085,
+ 0x5c9a7d9f, 0xfd2e51aa, 0x193d67c6, 0x18c31882,
+ 0x1287de0f, 0xc8c92e61, 0x5c7440bd, 0xa088af2d,
+ 0xc6446ead, 0x9e7d082e, 0x2a705216, 0xe1afd94f,
+ 0xef30e8ab, 0x1339dd08, 0x5eaf99ce, 0x5892d22a,
+ 0xfcb12b2d, 0x075fd04c, 0x13d3c186, 0x89df21c1,
+ 0xd7b934dc, 0x0ba666cf, 0xc735bef4, 0x0775a6ae,
+ 0xb2d50509, 0x02ec6a6e, 0x1f41eda4, 0xeca4adea,
+ 0x2bfe48f5, 0x7f9a2e4a, 0x8d168488, 0xf9d83c7b,
+ 0x2ec780e3, 0x1d533263, 0x288e2296, 0x7894010d,
+ 0xa7bbb038, 0x12de353b, 0x61f08cbd, 0xdbe00bc4,
+ 0x4f628f30, 0x9cce4d01, 0x1c4c9ddc, 0x4548cfe7,
+ 0x56cbc3d3, 0xa6ec73d2, 0x884a57d4, 0x1f61df47,
+ 0x0eb7a7ee, 0xb8814bdc, 0x2edf3a1f, 0xc6345669,
+ 0x5ff19e24, 0xfa6d2b7b, 0x67739aa3, 0xdc99ccf3,
+ 0x363274e0, 0xefec006e, 0x6b4cc24b, 0x04a87c55,
+ 0x039d75be, 0xc4c5b20e, 0xa46d6a36, 0x07cf0aa4,
+ 0x5279aaca, 0x895bdd63, 0x4df5096f, 0xb8a398c5,
+ 0xa9708281, 0x532b5ee8, 0xed7c436d, 0xffc40133,
+ 0x23ff5089, 0x3d30e388, 0x45c7b7f3, 0x6d9923d8,
+ 0xbcae4c2a, 0x2c7eeba1, 0x85a70f96, 0x2d19d9a5,
+ 0x5fa771b7, 0xa4bd176c, 0x9022c6a4, 0xc459f501,
+ 0x90cb6b5b, 0x60e2f4bd, 0x4641d237, 0x13c1f7e9,
+ 0x1e8d4c22, 0x140d4f94, 0xdb46a4b7, 0xd81b0e47,
+ 0xb153455b, 0x1fed1397, 0x1f62b03b, 0xd2cc135d,
+ 0x762851d1, 0x032e1792, 0x4ef3d480, 0x9ea803fd,
+ 0x7a67de82, 0x3b0a2ee7, 0x02053b59, 0x45be2578,
+ 0xc7c665a7, 0x6993efdd, 0xa6c649d4, 0x030244e4,
+ 0x5c4ae38b, 0x38796122, 0x0bcdaa6e, 0x8371b4d0,
+ 0xf48995d3, 0x97c55931, 0xeca4a076, 0xc5b134f4,
+ 0xe76da2f3, 0x3c9eb6e9, 0xf832b2ce, 0x431cc97b,
+ 0x3afa5c22, 0x66b1abdb, 0x2f78d404, 0x4a8873d5,
+ 0x885f1f35, 0xe6a1cd4a, 0x683bb92c, 0x63064bed,
+ 0xb047d11d, 0x81aa644b, 0xd3ddaa9b, 0x035d30db,
+ 0xaa0344e4, 0xb84021d5, 0x97212e44, 0xa28a8ffb,
+ 0x54b0d2a1, 0x0e7bac30, 0x38f15f53, 0xfb294ca3,
+ 0xe5f8cf4d, 0xf75a4b4d, 0x8b6d8475, 0x75020629,
+ 0xbc0d4f15, 0x96c606f5, 0x086d7018, 0xfedd1cbe,
+ 0xf3ed72c9, 0xae4a0f07, 0x905205e5, 0x6390ff12,
+ 0x091ab8e4, 0x4883ad11, 0xa6ae4f18, 0x74369bfe,
+ 0x8c8ca6d8, 0xa26d3628, 0x979272d0, 0x7be7078c,
+ 0x07b55ce8, 0xd182d554, 0x56aa100e, 0xf3af795f,
+ 0x8cf5c2b5, 0x59ca7609, 0x61ed3bd4, 0x1d95769e,
+ 0x2e54c24b, 0xfc70187a, 0x6612d02c, 0xaa7d71cc,
+ 0x57275e04, 0xc843b9a5, 0x511eb2bb, 0x0c079ba1,
+ 0x583e5e98, 0x2325f2b0, 0x93c6fa1d, 0x461949e2,
+ 0xb6919764, 0xfcf8d454, 0xc0c02029, 0x3c98af45,
+ 0x8f8700d4, 0x47ce94bf, 0x15cbda00, 0xc0af798f,
+ 0xf6d1d496, 0xee4fccda, 0x872aac3e, 0xa308f889,
+ 0xb33e96a8, 0xfcf9fb3b, 0x5b0a9716, 0xcb5e92dc,
+ 0x20495efa, 0xeafb9f21, 0x8f2d44fb, 0x57d6a532,
+ 0x3a48b77d, 0x670133fb, 0x877f5fe7, 0xe1e01dea,
+ 0x0a084b76, 0x80ab1eed, 0x9af5756b, 0x7fbace8d,
+ 0xce7f5a73, 0x37881268, 0x7b054372, 0x27a0a74d,
+ 0xca02c5c1, 0xc4bcf2a5, 0x9c20c6f2, 0x5dc475b6,
+ 0x23f4aea5, 0xf45d2b36, 0x9c604078, 0xea094271,
+ 0x09be1939, 0x0b367cc6, 0x848dfe6f, 0x100ecc3d,
+ 0xddc88e55, 0x7b5d28a2, 0x7860b89e, 0x775e68b4,
+ 0x30ab4038, 0xb1fdc22a, 0xc095b7c6, 0xc0154c83,
+ 0x42f90faa, 0xe3c7fd74, 0x6535ab87, 0x1cf7d3a9,
+ 0x5549ad53, 0xde9151ad, 0x9ea7303e, 0x027722ee,
+ 0xaacb1059, 0xbc6d92ce, 0xd9379962, 0xea981e27,
+ 0x126fac29, 0x69862409, 0xb5fbd874, 0xc3835a43,
+ 0xa339dd93, 0xabb8ca7b, 0xac5868f8, 0xa8233840,
+ 0x6956fbd9, 0xb6c2fddd, 0x1a777e9b, 0x74a5a6f7,
+ 0x6200dc1b, 0xbe21c654, 0xc59aa445, 0x8cc3b5f4,
+ 0x1f6b91e7, 0x21f1a74e, 0x867945d5, 0x6f7ab56b,
+ 0x2bd4c41b, 0x84eeb02a, 0x8e508e5b, 0x600bdf6a,
+ 0x48dc391c, 0xce8fd525, 0x327b3254, 0x03897193,
+ 0x2b451e99, 0xd3c07c62, 0x71382315, 0x9af721f9,
+ 0xd17564ea, 0x4351159b, 0x94ee1459, 0xcf43ebbb,
+ 0x260459bd, 0xc4a0aa8a, 0xa174b150, 0x5519aa51,
+ 0xfc9d34ea, 0xe42d5a00, 0x3aa60346, 0xb8f01a97,
+ 0x179ad8bc, 0x31e6491d, 0x0ca4d363, 0xebf1b063,
+ 0xfe575797, 0x6e086e70, 0xad0c1d16, 0xe04f5f5b,
+ 0xdef4824a, 0x890a8034, 0x96ebfedc, 0xb80b9cae,
+ 0x152c42a6, 0x0db1e18e, 0x0bec54a4, 0xebe7511a,
+ 0x647576d2, 0x26c74185, 0xb88c0a7e, 0xef586fbd,
+ 0xfdc52573, 0x44818b5f, 0xe25388b1, 0x903eacd6,
+ 0xaadfcfec, 0x7887ed8b, 0x20f2657d, 0xdb2d5086,
+ 0xbd7b2d27, 0xb4be4695, 0x71c9db2f, 0x6dc2868f,
+ 0xee317131, 0x4bd8a206, 0x74b2aecf, 0x9644c6bd,
+ 0x16ee2e84, 0x5e6e59c5, 0x3ed8c83f, 0x3d3ece60,
+ 0x6ff23f23, 0x69ea7e8e, 0x628bfb3d, 0x1f27d10b,
+ 0xd3ad7632, 0x22f3e0dc, 0xed2f2f27, 0xb9010b31,
+ 0xffdb13ec, 0x5fefec44, 0xb1956a71, 0x60d72e8e,
+ 0xf3db1cfc, 0x21b03a36, 0x9c749c52, 0x871736b8,
+ 0xddb876b5, 0xbe72ba05, 0xcadd94bd, 0xcd235899,
+ 0x990ef14b, 0x75d45063, 0x5d0dab6f, 0xf07efba3,
+ 0x19d755a7, 0x225cebef, 0x0eb66983, 0xb2b790a1,
+ 0xba5ecaf1, 0x8fbd6f40, 0x598d850b, 0x993a4f9f,
+ 0xc0060760, 0xfd77fb8e, 0xfe23bd8e, 0x934e2ba8,
+ 0x4f0ed544, 0xa1b5a292, 0xa02982de, 0xa48b12a9,
+ 0xbb29c86d, 0xc1ba635d, 0x16d44889, 0xbcee85bb,
+ 0x180f284b, 0x4be25661, 0x6e527152, 0x7009553a,
+ 0x42c91272, 0xba0e0409, 0xe09a190c, 0xf9b3413f,
+ 0x0194438d, 0x2d9b3183, 0xb4ffdef3, 0x2a3e81fd,
+ 0x506aaca8, 0x22808572, 0xeaa65056, 0xa3189e8b,
+ 0x8ed4c27d, 0x5cc3f0ab, 0x5c3fd9e9, 0xd4128422,
+ 0x1670b0a7, 0x1bb0ab0b, 0x24a5fa36, 0x90fe5731,
+ 0x08fdf04c, 0x6aa77212, 0x541e708e, 0x6730edd1,
+ 0xacc62be9, 0x5dcc2fea, 0xc7a6e1da, 0x5f46c34e,
+ 0x41615597, 0x932828da, 0xf377df2b, 0x7bbb8a45,
+ 0x7ed2988c, 0x8edc2d9f, 0x3461f64b, 0x1d3df37e,
+ 0x39efbfe7, 0x3e7db3a9, 0x85b77222, 0xd332bc41,
+ 0x7a0e7916, 0xa972d1fc, 0x4fdbcb4d, 0xa4cec6ad,
+ 0x79ab2ae7, 0xcd30a5d3, 0xea713115, 0x2e12d660,
+ 0xdeeb001b, 0xf2616836, 0x14fc8167, 0x9c18d6e6,
+ 0xbbee9b3b, 0x079e235c, 0x73959951, 0x940c905b,
+ 0xae4fa152, 0xfbbdc0c7, 0x46b6eb5b, 0x2fcaebaa,
+ 0x2f6d0c36, 0x5334b4c8, 0x3d68ae16, 0x2a8d2411,
+ 0x1730fa08, 0x6f63fc2b, 0x91ae6073, 0x3cd23a79,
+ 0xbcc42b7d, 0x6456502d, 0x949c44ee, 0x6aeb0bbd,
+ 0xe718b8a9, 0xca541325, 0xe5259811, 0x2c8d8bae,
+ 0x2f5aa1ee, 0xad473c8b, 0xc74af72a, 0x5681dbae,
+ 0x47ee969b, 0x2f4a0305, 0x22872f75, 0x72e31e0f,
+ 0xb5b455ff, 0xad4e2dd1, 0xc4314c55, 0x9a8467c1,
+ 0x619c8d11, 0xb5a52598, 0x921594d1, 0xd64014a2,
+ 0x74a88f0c, 0x3cf93fd2, 0x5bf792f5, 0x3111176d,
+ 0x8b84cce1, 0xcfe53fe7, 0x4a7f6738, 0x04d0bbdd,
+ 0x5497f76a, 0x8eb366a6, 0x55baaff5, 0x0b1f6b03,
+ 0xf26058d5, 0x6fbefd1e, 0xa457c5af, 0x7dc2243b,
+ 0xef19f368, 0x5e2863f8, 0x6385e880, 0xa4f62abe,
+ 0x09093681, 0x9aacbacf, 0x0575a0a0, 0x3436658c,
+ 0x25bc30f6, 0x0f64a1de, 0x22504451, 0x9421d08b,
+ 0xc9853159, 0xf1983fc2, 0x84d3b606, 0xed782243,
+ 0x1925429c, 0x91dc6406, 0x75703e73, 0xc2a4059e,
+ 0x1041011b, 0x337278c4, 0x8b48ad4a, 0x470d6f75,
+ 0xdfa6299e, 0x5d4bdeab, 0xdb7b7223, 0x5da0e3f1,
+ 0x402cf2a1, 0x9000292d, 0x12b2d362, 0x957124cc,
+ 0xa1845ccd, 0x1fc677f2, 0x3a219f4f, 0x91739ea6,
+ 0x62419ff0, 0x71147744, 0xf902e26b, 0xbd057ef2,
+ 0xc6ff27ef, 0x958b4db9, 0x114e12cc, 0x55e9226d,
+ 0xf02e578c, 0xf02797c5, 0x58a88aa6, 0xf4e54d03,
+ 0xae002724, 0x5a22d4ca, 0xea92e7b5, 0x32ab91f7,
+ 0x63a8758f, 0x02bb78d0, 0x629a88ec, 0xa89fe5ba,
+ 0x376be9d0, 0xa9e32771, 0x7c3a2869, 0xca6fe27f,
+ 0x7ff9333b, 0xd2fa3bef, 0x11c0330a, 0x580e0e06,
+ 0x0214de27, 0xc9b8f055, 0x1ce38df4, 0x7e1cbcac,
+ 0xe6598422, 0x4ca01991, 0xef73e1ea, 0x6c7a3450,
+ 0x72aea16d, 0x6b25a1ce, 0x6afe28c3, 0x538ba485,
+ 0x9bb4bdd8, 0x11d67c85, 0x75a91822, 0xe3fb9348,
+ 0x90750bbd, 0x30b435dc, 0xa4d8370b, 0x778a93c1,
+ 0xe33b4278, 0x91bb14bb, 0xe50f900c, 0x1e7d0382,
+ 0xc5a8c01f, 0x7acd835b, 0x8dffa7f1, 0xe683cb36,
diff --git a/src/cpu/intel/model_206ax/microcode-M12306A5_00000007.h b/src/cpu/intel/model_206ax/microcode-M12306A5_00000007.h
new file mode 100644
index 0000000..7f7e590
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12306A5_00000007.h
@@ -0,0 +1,576 @@
+ 0x00000001, 0x00000007, 0x09092011, 0x000306a5,
+ 0x08e38731, 0x00000001, 0x00000012, 0x000023d0,
+ 0x00002400, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000a1, 0x00020001, 0x00000007,
+ 0x00000000, 0x00000000, 0x20110908, 0x00000871,
+ 0x00000001, 0x000306a5, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xb19d6427, 0x45644b90, 0xe8f7cf6a, 0x3106acc4,
+ 0x45ec3068, 0x8de9ec3a, 0xc840bf97, 0xf0feb883,
+ 0x5a3401db, 0x42caecce, 0xb4d8e75e, 0xe6dbaf24,
+ 0x7861b35f, 0x6bd717bc, 0x23b9b731, 0x82ec1ac8,
+ 0x20337b64, 0x5396dbf1, 0x59973bff, 0x724bc7e9,
+ 0x5237193b, 0x0b8647c1, 0x6a0d0e16, 0xbf9ddb5b,
+ 0xace2cc1c, 0xad707638, 0x056f102f, 0xa37e60f8,
+ 0x76255642, 0xfb86e030, 0xb8069a40, 0x367795f1,
+ 0x653fb05e, 0xab7f14ad, 0xb6e8a8e1, 0xd2598d20,
+ 0x2eba3f68, 0x78b372f1, 0xba8d13f8, 0x1f1de861,
+ 0x97f951d5, 0x8097c728, 0x27dbf904, 0xb97906a8,
+ 0xffe7a4ac, 0x4b947668, 0xc1dbd726, 0x2adcf777,
+ 0x63b1bcf0, 0x818e2a1b, 0x49aa907b, 0x2faf5e8d,
+ 0xae842352, 0x82707fae, 0x0aa12b41, 0xa0bae11c,
+ 0xb4298c47, 0xd2b4099c, 0x4ff625f2, 0xcd2630d4,
+ 0x79850981, 0x05dbf57d, 0xb05b81a5, 0x56e73ec7,
+ 0x95cb3897, 0xe262bda5, 0xb2c6e288, 0xcb7f8e77,
+ 0x72b8bdd3, 0x3f400494, 0x63ade65b, 0xbc4adc71,
+ 0x00000011, 0x8eba90b2, 0x99b07166, 0x60fb3478,
+ 0x9f432ee0, 0x61217155, 0xba20ca5d, 0xdf062cb6,
+ 0x0361d883, 0x38e4cb35, 0xc94178eb, 0x9aadd7de,
+ 0xf2b976da, 0xf53392a3, 0x107a3711, 0xe1a02869,
+ 0xe14b16f6, 0x00b49cab, 0x64e8c50a, 0xdc6c8e97,
+ 0x0c07d951, 0x96d88637, 0xd003b1a6, 0x838c8c28,
+ 0x9940649c, 0xada7a8f9, 0x6665a9d2, 0x7e5d982e,
+ 0xb8b03135, 0x9b900639, 0xc37838ce, 0xa650b930,
+ 0x2c316b53, 0x7374f0b9, 0x166b3629, 0x525f517a,
+ 0xff217dce, 0x73ef5afe, 0x781fb969, 0x86960bd5,
+ 0x5cac84a3, 0x1b98906e, 0xfa2870c3, 0x95c648c4,
+ 0xe075523c, 0xc080a72e, 0xb5aee95f, 0xe1e833a7,
+ 0x22c4042a, 0x2e3f2468, 0x3bd41153, 0xfc7dc293,
+ 0x1f438bc7, 0x4ed57b9a, 0x25f23177, 0x56db710f,
+ 0x8c8f9af8, 0x2a2debc5, 0xec73f945, 0xb33506bb,
+ 0xcf5a825b, 0xefcc4487, 0xcadfb1ce, 0x2f885b5e,
+ 0x00fd6c35, 0x022ce468, 0x976eeaf0, 0x7c32c1a0,
+ 0x3863b05f, 0x93f87d3e, 0xecb03e5c, 0x9fc77cac,
+ 0x4b3bee3d, 0x15293a31, 0x54db0240, 0x046aa9e8,
+ 0x7e369cb7, 0xa8a3536d, 0xc720279b, 0xe4dee7f5,
+ 0xd7c37f35, 0x4eb5c9cf, 0x2e73f972, 0x91e9cb3c,
+ 0x336048e0, 0x49b5eaab, 0xb2892003, 0xb36714eb,
+ 0x3de29838, 0xd4f3254f, 0x9745f6e2, 0xd4ac7f3e,
+ 0xe6145545, 0xe4a4de99, 0x001220c1, 0x8181d672,
+ 0x7e6d0425, 0xa4adb6d3, 0xb258f3d3, 0xf5dca0b6,
+ 0x2636f4fb, 0x7afacad9, 0x4a8dec27, 0x140cd684,
+ 0x7592e735, 0xbe693141, 0xc44798bc, 0x0faddc0d,
+ 0x038c095e, 0x63771803, 0xffab64ed, 0x0cdaaa8e,
+ 0x188037df, 0xfab094f3, 0x64caabd4, 0xb603d23a,
+ 0xf9cd4713, 0x4010afff, 0xaf6b8c07, 0x1fd3e7f2,
+ 0xc534c3df, 0x48231d06, 0x03758785, 0xef6c1b56,
+ 0xeda29afc, 0xb6d05760, 0x9af58d28, 0xf2477cda,
+ 0x84857a72, 0x644df758, 0xdc48fa8a, 0x82350df5,
+ 0xc8ee429f, 0x6a1b6d77, 0x6827f435, 0xbbf7b7bd,
+ 0x05bc39a2, 0xcebc261d, 0xca685502, 0x8981efa2,
+ 0x7e415400, 0xb5f2aff9, 0xbe33cc56, 0x865169ed,
+ 0x0d1db258, 0xc71522ea, 0x24b765a5, 0x22c43129,
+ 0x43200be2, 0x2d085aa8, 0x890776d7, 0xcd17c358,
+ 0x700d508c, 0x7529d2ec, 0x542e5479, 0x8f040b79,
+ 0xfb98bccb, 0xf9815b12, 0x0940e7e3, 0xc8ebf4c6,
+ 0xb7f4221e, 0xc9ca8504, 0xc9c64deb, 0xa37690ab,
+ 0x38cdec9f, 0xdc573e73, 0x5cd250e2, 0x8f5aebf0,
+ 0x3c3cb33d, 0x3b2bc536, 0xfa925ffe, 0xbf38dc0d,
+ 0x42653c00, 0x1dbb4a15, 0x858deb4f, 0xdd78ae6a,
+ 0x122b2859, 0x1cc8fe04, 0xc717f1f6, 0x6eb52371,
+ 0x483dc5d8, 0xc6ea2eff, 0xee6d7109, 0x13cb245d,
+ 0xef777cae, 0x383c21f0, 0x200329d7, 0x27e63cfe,
+ 0x7f600294, 0xc3f5eb42, 0x36a5254b, 0x97f96771,
+ 0x20ed56e4, 0x4cd58e5a, 0x9c4e778f, 0x83bff1a9,
+ 0x10ca2223, 0x1f02d63b, 0xfbafd02a, 0xa87c720a,
+ 0x7ff78c22, 0x704ff519, 0x11c87c2b, 0x613b19a7,
+ 0x887609cc, 0x00875a39, 0x6b2b3e07, 0x18c7908e,
+ 0xc6f85508, 0x2bd6e37d, 0xee2a582f, 0xb76786eb,
+ 0x00f6096a, 0x6a659a11, 0x0c100275, 0xb01cd536,
+ 0xfea298b3, 0xfe111ace, 0x5b725ba7, 0x5a9cd6f8,
+ 0x7fa0b669, 0x2b715e3b, 0xd047d607, 0xafe6bb80,
+ 0xb0efcd80, 0xe917ae03, 0x60a87dda, 0x97096139,
+ 0x64eaaf67, 0x3012142d, 0xe5ef45d8, 0x229c6b34,
+ 0xce453df0, 0xfd6ff9a7, 0xfdd7bb21, 0xc4975203,
+ 0x338bb827, 0x900ff88f, 0xcc6111a4, 0xd1338ae3,
+ 0x3cc7123d, 0x05a71cc8, 0xa979bb55, 0xb23700c8,
+ 0x7d7c1b2b, 0x1ec9cc47, 0xf4700344, 0xe2bf54b7,
+ 0x914b77f9, 0x85fad2a8, 0x313adbb7, 0x31712a10,
+ 0xb000a261, 0xf9f08bea, 0x13a66c82, 0x562884d3,
+ 0x1b5ffa27, 0xa87a6fdc, 0xf11f35c4, 0x6cd5e813,
+ 0xfbf6813b, 0xa0b64b44, 0x26dffab5, 0x81fde0f1,
+ 0x49fa755c, 0x33f5661e, 0xa73df874, 0xf5279374,
+ 0x5dd3411f, 0x2c0cb1ab, 0x3f55ff15, 0x32d75abb,
+ 0xde2b4b90, 0xd7c5b66e, 0x3eef8cc3, 0xc7a4625b,
+ 0x97021d4c, 0xe3880deb, 0xc8c647e1, 0x4dde6b72,
+ 0xca53ce2c, 0x84d70a2e, 0x2e9cceb5, 0x1c3afa04,
+ 0xbac1fd85, 0x0731a787, 0xdb121a3b, 0x86c8f784,
+ 0xd3659cbb, 0x80fa19f3, 0x1aad8486, 0x5457678b,
+ 0xe88bfece, 0x427ffb19, 0xde80bc9f, 0x839c16ea,
+ 0x5a70eb7a, 0xeef425ee, 0x22d2512f, 0x58b553e5,
+ 0x2635bc3b, 0x52ac999b, 0x61fab797, 0xfdf07f99,
+ 0x9d09901d, 0xdf8f1d61, 0x56120e18, 0xd86d4302,
+ 0x8b08c0f5, 0x45e17c97, 0x9a55223e, 0xbc4b43a7,
+ 0x67f70abc, 0xbdadf261, 0xa54a416b, 0x87642523,
+ 0xdea190cd, 0x5fe812a2, 0xdabf8c5a, 0x8de91c90,
+ 0x38457858, 0xb2dd023a, 0xfed888d3, 0x1411e218,
+ 0xac52cec0, 0xb399eb10, 0x0dbf4d43, 0xe85dc29f,
+ 0x7d6b16f4, 0x39d320f5, 0x48978880, 0x2f12c536,
+ 0x623df5b0, 0x2b8cf178, 0xece0b710, 0x6e9215b5,
+ 0x26570670, 0xcb263bd8, 0x1e194b28, 0xf7a3c433,
+ 0x968f9997, 0x728645d7, 0x4ec1235e, 0xf984a578,
+ 0xd1e734a3, 0x9229cf8f, 0xbe48770d, 0x09935e3d,
+ 0x2461a4a4, 0xb4086153, 0x090caf57, 0x0618c17e,
+ 0x3bc0b8d6, 0x0f901886, 0xbb601c6c, 0x3baf5096,
+ 0x09c1b883, 0x2013e9fb, 0x92c71c68, 0x1f44fb76,
+ 0x4aceea69, 0x62385666, 0x09a9a786, 0x865c8159,
+ 0x9f944c60, 0xa4a039ba, 0x2d32a151, 0x50a1f2af,
+ 0x5626a8cb, 0xcb792ac8, 0x8959aa9e, 0x5ba20256,
+ 0x307c9191, 0xb410e646, 0x168669cb, 0xc8ac1c57,
+ 0xfd252c64, 0x965c1ac6, 0x2b7b0d5c, 0x68282eb2,
+ 0xc37a69c5, 0xbe9597f6, 0x4ff2a59a, 0x15084cbd,
+ 0x5739e661, 0x0c3a2c9a, 0x62d62b45, 0xe951ce06,
+ 0xc2699784, 0xe0ecd1e7, 0x9ae9fb53, 0x76398c1f,
+ 0x99f1bb04, 0x8bbe1ea1, 0x062186cf, 0x0f41f975,
+ 0x0f3a574e, 0x22187bd3, 0xb521e845, 0x3e102fa7,
+ 0x9a1bd487, 0x60131c75, 0x04bfd9a3, 0x3b7c8138,
+ 0x923024a1, 0x79a9ffea, 0xea685d31, 0xd44445df,
+ 0xd88ebcd7, 0x4fe10042, 0x5d8dcb46, 0x5a693ee5,
+ 0x05ccfd20, 0xc11fc97b, 0x388ca021, 0x59713770,
+ 0x52b800f0, 0x51200b01, 0xae7df264, 0x9f0cd4a5,
+ 0xdb052d0d, 0xb4265003, 0xc69dfd4d, 0xb651bae1,
+ 0xb3212918, 0x50fd143a, 0x9f2b82fd, 0x7756471c,
+ 0xd4a23ca2, 0x001547a4, 0x5d42a3b0, 0x2e4284c3,
+ 0x5ebb9117, 0x57b00d30, 0x9bdb5c01, 0x824725a9,
+ 0xd26e0a85, 0xa4709293, 0x01f37361, 0xbd78c659,
+ 0x873dc38d, 0xbe4ba28e, 0x07f8fa8f, 0x2a3932d1,
+ 0x6c4b82eb, 0x54e2c06d, 0xea8825ba, 0x5bb6c583,
+ 0x12fa46ed, 0x952293c9, 0x9821eb6f, 0x3cf4ce74,
+ 0x7d1434da, 0xcd8a8e33, 0xe38abcb6, 0x57ebee62,
+ 0xec03d7cf, 0xb71fa50f, 0xc6dfdee6, 0x8950e006,
+ 0xf611d70c, 0x6939f743, 0x5e943bf4, 0x78c8631a,
+ 0x11a96a36, 0xd0066e94, 0xf5d6f08f, 0x28a1e799,
+ 0x828cbf96, 0x77c3ff93, 0xa8657d9e, 0x39f6f26e,
+ 0x722eac57, 0xe243d6d0, 0xcdc48b22, 0xa3d2f876,
+ 0x505f842c, 0x29370d83, 0x5d48d758, 0xa6ca2400,
+ 0x90553aac, 0xa6178ef1, 0x26c54d68, 0x927c726c,
+ 0x66aaba9a, 0xb8b878bd, 0x26345aac, 0x1b11c115,
+ 0xc1a7e10e, 0x31455f66, 0x1f897e61, 0xd5e48532,
+ 0xdd47f34c, 0x4a02667b, 0x06e01d08, 0x0a600510,
+ 0x6a8224f1, 0x2857cb2f, 0xdec0ddc1, 0xd8767cbd,
+ 0xf09e4ded, 0x2a47b0ae, 0xb0a2072b, 0xedff3737,
+ 0x24f10ed4, 0xfc77c5d1, 0x856c0758, 0xc00d8ab8,
+ 0x0d02a587, 0xd0c12d06, 0x0628c6b7, 0xcfc8a29a,
+ 0xe86a89ca, 0xd125ff40, 0x0f167ee9, 0x1b45559f,
+ 0x2374a09b, 0x2fa2936c, 0xcf24f155, 0x5e75ef39,
+ 0x3bc7da04, 0x7cc9e8a8, 0xe27b7df9, 0x180b20d6,
+ 0x799b29f9, 0x89aeab86, 0x345e1f66, 0xdadf1773,
+ 0xe7f8df38, 0xba93ea9c, 0xa0713950, 0x1c693728,
+ 0x09b24ebf, 0x94e80ca2, 0xff4f5c25, 0x050a1874,
+ 0xda15573c, 0x0bc47e01, 0x3406586f, 0xb416b3aa,
+ 0x94fef9ca, 0x5eb6a63c, 0xee5c0174, 0x13a23c4a,
+ 0x4543dba7, 0x0cb92b5a, 0x3e1bc02b, 0xb9fa4989,
+ 0x0dbb8c54, 0x87a3fdf8, 0x3036836e, 0x73b06a78,
+ 0x8757fae6, 0x869d650a, 0xce175be7, 0x9874d0f2,
+ 0x78efb32a, 0xa91bb374, 0xe57e3e62, 0x63acd71d,
+ 0xca1706f3, 0x0c5e3834, 0xddcaff5c, 0xb421bb97,
+ 0xe5caa70a, 0xe2839e67, 0xa7e35bd1, 0x9982a635,
+ 0x30a5b07b, 0x3d79f433, 0x9e4d8b09, 0x643f1210,
+ 0xc1e4df39, 0x0cca26c8, 0x9a95f0c0, 0x8d6ab68a,
+ 0x73427e53, 0xacc3a993, 0x5a4dd0d8, 0x961051ec,
+ 0xca1843e1, 0x3b223329, 0x447a9ef8, 0x0d68e38f,
+ 0x4f6cc40a, 0x2ebcbf87, 0xd76141af, 0x20d0a180,
+ 0x29b7b791, 0x94722b21, 0x7947f16c, 0x4af7fa89,
+ 0xfabb5e7c, 0xa0b4c06d, 0x727c61d3, 0x97505208,
+ 0x60b92b10, 0xcac0c6cf, 0xbd04a665, 0xdbff9ad3,
+ 0x61dfb7ca, 0x0d08b92f, 0x895e1748, 0x92301325,
+ 0xe529024a, 0x3dc58ef8, 0xe7ab24ac, 0xf89845b8,
+ 0xdb71ab1b, 0xcda66f3c, 0x2efd4d2c, 0xefc3db22,
+ 0xcbe6c35a, 0x294a2366, 0xcbaa262c, 0x99bbb4fc,
+ 0x6c224c20, 0xac6105c2, 0xafff5b1e, 0x8cfecaaa,
+ 0x31fa3bf0, 0x9603be0d, 0x7f1d56d7, 0xdc9437b5,
+ 0x5e1d64fe, 0x5384e454, 0xe5001761, 0xcfb53906,
+ 0xefa72870, 0xb7e43b6f, 0x55175bda, 0x9a1988c9,
+ 0x7a7e4948, 0xfef33c4e, 0xe312d299, 0xe6892bbd,
+ 0x8aefb498, 0x02e6f8ee, 0x893f15ef, 0xc2513114,
+ 0x9b7d5590, 0x65efa8e6, 0x6600382e, 0x24c34ae5,
+ 0xdcc68f8e, 0xdd7a3fc2, 0x36b31faf, 0x9ac2603e,
+ 0xa36bd5e1, 0x534c658f, 0x5d750ef3, 0x85a44f3b,
+ 0xd05eabf8, 0xd76b3377, 0x49914856, 0x3e4084c2,
+ 0x981f8086, 0xca30425a, 0x6206f73a, 0x5be88cfd,
+ 0xa8fcadf6, 0x2110cde8, 0xd2bb3b20, 0xc1c8b3db,
+ 0x6a738ae0, 0xfab3a929, 0xa08ac13a, 0x19b609a1,
+ 0x67bcfdc7, 0xb0f51e16, 0xc18dfe6e, 0xdc14923b,
+ 0x4bf12eda, 0xacc8ee4b, 0xa1067858, 0x3ab996e7,
+ 0x91fc1ecd, 0x72e40234, 0x86051577, 0x1e38b4f8,
+ 0xe1fa8b9d, 0xe9a307fb, 0x528f4de8, 0x6eeab097,
+ 0x352a083e, 0x0254b0f4, 0x91489dd2, 0xd2c1a37d,
+ 0x56fba53e, 0x7f5f7878, 0x4ef7096b, 0x3e5e05d4,
+ 0x530ddeee, 0x4b358b5b, 0xfa2d13b5, 0x612468c5,
+ 0xa41d9778, 0xa1690829, 0x60742e97, 0x0affe291,
+ 0xc3110b6c, 0x1c471ae9, 0x24ac0e6e, 0x64700f32,
+ 0xb40d7e01, 0x8fcb8777, 0x9187eeae, 0x4f374518,
+ 0x9dfaaf96, 0x1ea8b126, 0x0634309d, 0xb947ea87,
+ 0x77e091fb, 0x585e6f9b, 0xe2fa3cc0, 0xf8554c49,
+ 0x29c48030, 0x8ab401e0, 0x03f11938, 0x863bcd13,
+ 0x04c3bdc8, 0x1d679416, 0x70722137, 0x2e9915fa,
+ 0xa18f44f3, 0x607b5670, 0xdbb3e675, 0xba1e419e,
+ 0xca50acee, 0x7a065a5d, 0x8e5a551f, 0xefe7daa5,
+ 0x1b550562, 0xd76a881f, 0x7a3380b9, 0x7cf80cb2,
+ 0x2c48edf2, 0x0e6e7c78, 0x9f800a18, 0xb1ef3e72,
+ 0xa942bab4, 0x4b057a61, 0x07d35ced, 0x1484ee3a,
+ 0x2e3adb03, 0xd3b0177b, 0x15cfb615, 0x20c2fd07,
+ 0x4a172f17, 0x6ff62034, 0xc1941273, 0xbd404f2f,
+ 0x597507c5, 0xd0c024e2, 0x14061e48, 0x869afa52,
+ 0xfcebe92d, 0x73da8c56, 0x21e5e330, 0x41db744d,
+ 0xbda3bbe6, 0x05f2dc15, 0xbb954c68, 0x76dc00c7,
+ 0x8abab209, 0xc4b1fa44, 0xb59cc60c, 0x127b6430,
+ 0xe527601d, 0xa5ce413e, 0xc890aceb, 0xb5ceaa0f,
+ 0xa096a30d, 0xb7dba77b, 0xb2f08363, 0x0e9bb72a,
+ 0xc8b00926, 0xdca48394, 0xbd18b515, 0xb34af68e,
+ 0x07575204, 0xa508752e, 0x8cf44563, 0xb5d9914c,
+ 0xeb5bac0c, 0x0efc0826, 0xf256e8f2, 0x8d96cd98,
+ 0xf5913d1d, 0xea046617, 0xfc2d2d0a, 0x9e4c43b3,
+ 0x4c0c3139, 0x46320203, 0x87e05cf3, 0xd9dc8716,
+ 0xb1c9a742, 0xe116b27c, 0x28e5ea42, 0xf72a419f,
+ 0x24724f77, 0x120c8167, 0x18f2a565, 0xb5a7e461,
+ 0x4a5f54e7, 0x97391799, 0xa475c0be, 0xb4392065,
+ 0xb2e70f78, 0xf1dd8409, 0x5768dcba, 0xc86ae8de,
+ 0x1178323d, 0x7251421b, 0xd137d355, 0xb87741b4,
+ 0x37789ef7, 0xf574daf8, 0x6808c1b5, 0x56cbceb9,
+ 0x02621bd6, 0xe1d58259, 0x410594eb, 0xfe1a760b,
+ 0x8fcc5ae6, 0x8eb49454, 0x5914fdc5, 0x4d482918,
+ 0x9bcebc94, 0xf8dfb0a2, 0x708a7faf, 0xeac28b23,
+ 0x94bb4dad, 0xfb543078, 0x36c58c0d, 0x86a10337,
+ 0x2f56c640, 0xe125eeea, 0x099890e2, 0x356784a9,
+ 0x5a89add8, 0x995e6137, 0xe0d6959c, 0x365b7c04,
+ 0x81bb9664, 0xc085d819, 0x92b191e2, 0x3378b1c8,
+ 0x9c535ad5, 0xac7281c6, 0xebc83ec6, 0xcc1524d1,
+ 0xb9222b86, 0xeab14329, 0xb1a4d78e, 0x432a05fe,
+ 0x03a48e25, 0xd78da70c, 0x4760588f, 0xb67ffebb,
+ 0x8a0f38a3, 0x98915610, 0xa6887f59, 0xda9faea0,
+ 0xcb24dd66, 0x5721831c, 0x73199e39, 0x48d59dcf,
+ 0x207fee88, 0x96f50f10, 0x563ebed9, 0xc136f2de,
+ 0xaf990e2f, 0xd952a732, 0x128766c9, 0x80546c7f,
+ 0xf2445ac1, 0xd4d8f998, 0xbcbcadaf, 0x4da44337,
+ 0x884b3df0, 0x186aca55, 0xe6c9dbb0, 0x482e2171,
+ 0x6371bed3, 0x9f54d44f, 0xe99d6661, 0xbcd49a8d,
+ 0x63b586f6, 0x430d36fa, 0x21d0ad53, 0x906f32be,
+ 0x83848189, 0xd711a5a7, 0xe1a2462d, 0xf1f80181,
+ 0x0af3d2b2, 0x4a3a5e2c, 0xa2392474, 0x305d006a,
+ 0x46785678, 0xf54eb005, 0x4a2c189a, 0x6e441e22,
+ 0x8dda18d0, 0x6c2e9e11, 0xf9a75cad, 0x698bd350,
+ 0x87bbdb99, 0xd656e312, 0x921579c3, 0x50a50d30,
+ 0x816c8aad, 0xf019dba0, 0x6144b38c, 0xa97e7083,
+ 0x77d5dcbc, 0xdb753e67, 0x61ac35bc, 0x67eee916,
+ 0x93cfdcd9, 0xe2f1ca57, 0x9954cfec, 0x0f2dc1fd,
+ 0x3700da97, 0xb9851596, 0xe872c6cc, 0xf59221d6,
+ 0x9aa19c43, 0xd3c518d9, 0xbff5c0d2, 0x53a0dbf8,
+ 0xaa8a4b43, 0x7f7f9e5e, 0x64d6a2db, 0x9d780f09,
+ 0x2a4e70da, 0x6b9bf43b, 0x88e6569a, 0x036c4a46,
+ 0xb3502407, 0x5a95f09b, 0x97ad6ba5, 0xcb9d99ba,
+ 0x227d8004, 0xa7b76d48, 0x141431e6, 0x6cbf8e06,
+ 0xbefa69bb, 0x2ac7bf1a, 0x6098834b, 0xdbb6fe67,
+ 0x8f5196e9, 0x217fb6f6, 0x7f915b8b, 0xf6903013,
+ 0xed24352e, 0x3dbbfda6, 0x2d1c7f6e, 0x5a769449,
+ 0xf5fb4435, 0xd4e6667e, 0xb65f6d6d, 0xcae2e91c,
+ 0x015998ff, 0xf4be0d8e, 0x2d8a387b, 0xc59d14e9,
+ 0x6843c8a3, 0xb3c78d8d, 0x9f65a7da, 0xc2918a86,
+ 0xd0236b2c, 0xdcc4dece, 0xcb2231e0, 0x1f9443ba,
+ 0x9c3e887b, 0xe878416c, 0x3e3f6bda, 0x09ac5540,
+ 0x4415c5e7, 0x244776e5, 0xc2f9a797, 0x064b9578,
+ 0x0199e4c6, 0xcdabd3b7, 0x45f30d15, 0x3ad21f49,
+ 0x3864670e, 0xe1dcd5e6, 0x5c27b602, 0x80887553,
+ 0x4db58644, 0x7025bbfc, 0xe5f27d4b, 0x81f12d53,
+ 0x98b4f58d, 0x59f24cf8, 0xad6930ce, 0x64d83c3c,
+ 0x465f846c, 0x88baefc1, 0x819a6a9d, 0x2f315e06,
+ 0x70b4c6c8, 0xbba3c425, 0xc5753e27, 0x74eac5a1,
+ 0xe9b8ec61, 0xd3536052, 0x24ce33da, 0x7a24ade4,
+ 0x2e24fa6e, 0x4f02551b, 0x47e4c103, 0x1d33c34b,
+ 0x20483b9b, 0xc8317f9b, 0x65a8faed, 0xd5c07a48,
+ 0xa1643073, 0x5ddb5d3a, 0xc2135afd, 0x9d800ad0,
+ 0xafaf0168, 0xd6067383, 0xddeb3052, 0x1002fc07,
+ 0xda51b249, 0x2504ca4a, 0x5dff4899, 0xa5e8ebce,
+ 0xbab8909c, 0x5ca2971b, 0xb0af040e, 0x2f9dff7f,
+ 0xe58f53a0, 0x22a8ba4f, 0x22b66a7c, 0x9a51d9a3,
+ 0x4edecd09, 0x7e6d6402, 0x7cf06d67, 0xca2faa15,
+ 0x5727e450, 0xbb8dfbfd, 0xef13b160, 0x541731a5,
+ 0xa176b699, 0x337ad6b5, 0xafe718e7, 0x31ea4773,
+ 0x1859cd94, 0x504c70c4, 0xd0f5da5a, 0xe0bab277,
+ 0x75a92a95, 0xcb232237, 0x0b149a4a, 0x4931a161,
+ 0x8176d7ff, 0xa8e73d6f, 0xe6763fb0, 0x9a509b92,
+ 0x71543ebf, 0xaf2afbb6, 0xfa8f2e98, 0xd6b299e1,
+ 0x42a9edd3, 0xe9c970db, 0xb52b7668, 0x0df769cc,
+ 0xf5fdce17, 0x4117919f, 0x10abe7db, 0xff0f27b7,
+ 0x4d241470, 0x89ee8762, 0xacbc4618, 0xd8136844,
+ 0xf0e36131, 0xaac6de18, 0xe0ebb8fc, 0x122aab9e,
+ 0x825a9a49, 0x16fa2e3e, 0xe73a7ca0, 0x810c8f07,
+ 0xe116ad18, 0x213a034c, 0x7c9a9f0b, 0xea5e5ac2,
+ 0x75212ee5, 0x9155f794, 0x414f642e, 0xccc41808,
+ 0x2159d497, 0x5d0426e1, 0x13bc77d0, 0x786b666d,
+ 0x8dea44bc, 0xcf5485c6, 0xc66baa60, 0x1859c1a7,
+ 0xc4abc762, 0xa80be227, 0x87b2e69e, 0x2f0af08c,
+ 0x0ad4e0de, 0x62197a58, 0x94c03262, 0xdad43b71,
+ 0x2d63d69f, 0x81af9e07, 0xf0653b05, 0x5427be4e,
+ 0xa3c6d4cb, 0x31793877, 0x6b870325, 0x21ed52c1,
+ 0xdde3d817, 0xd43c5a16, 0x1df2ea8f, 0x43f59dcd,
+ 0xa3363c8d, 0x42aedb7f, 0x9aa014cc, 0x05d63699,
+ 0xfc35577e, 0x9034b5f3, 0xb5bef0c1, 0x0bdfdd96,
+ 0x6a3ababf, 0x4ff499f5, 0x51988400, 0xfcdc956c,
+ 0x8cad4f49, 0x00e34d8e, 0x88d54613, 0x74fd6f41,
+ 0x2d50a76a, 0x6ff5593d, 0x455a008e, 0x54d299d5,
+ 0xe156182e, 0x790c7fad, 0xab5cb66d, 0xf5bb192c,
+ 0x91efb2ae, 0xa58bdeff, 0x983f2596, 0x61c92fd2,
+ 0xcb04a9c6, 0x1c5869ac, 0x054b690c, 0xd75f853a,
+ 0x38291bbf, 0x01974bff, 0x731e8674, 0x5ecf03db,
+ 0xfd8e064b, 0x33dee27c, 0xf4514376, 0x9694e016,
+ 0x96f4c916, 0xabed9ea6, 0x23341d38, 0xb248222b,
+ 0x9785d01b, 0xfea938b4, 0x5dd07e44, 0x102f0aaf,
+ 0x93e932d4, 0x94efbfe1, 0x6be51f97, 0xe94cd91a,
+ 0x6164ea96, 0xaa6bc520, 0x48092613, 0xcc475e66,
+ 0x5bae345b, 0xc5ecf8a7, 0x86a432b1, 0x176749bf,
+ 0x18aeff8a, 0xbedc0266, 0xff1164c7, 0x7da72f42,
+ 0x033ff853, 0x0ee392c2, 0x78426196, 0xff6c5bd7,
+ 0x761fc7e0, 0xcc0818ec, 0x4688a1ac, 0xe5d10549,
+ 0x398c6420, 0xd6171b4b, 0x64b6c776, 0x3cd2dffb,
+ 0x94006e50, 0x6d609469, 0x7593312f, 0xae93bf2f,
+ 0x86401bff, 0x4803f688, 0x8133107a, 0x42c27314,
+ 0x73128b38, 0x0bbea19d, 0x817bbc13, 0xa35b592b,
+ 0xf3f7435e, 0x3d2d4506, 0xa2a2a123, 0x6299fc29,
+ 0xc8d0b6f4, 0x3e074310, 0x5a3ffe01, 0xa3f48f59,
+ 0xc6e1afdd, 0x5e2bfa3f, 0x4dd49e68, 0x016658d9,
+ 0x48cd4509, 0x72e502a9, 0xc708d696, 0xff96db51,
+ 0xa03f4710, 0x2b6bc06d, 0xa12ed2b1, 0xf5f2fece,
+ 0x0d3d44e3, 0xd8375553, 0xd56b5b22, 0x66f2aa06,
+ 0x576f76eb, 0x5a3c8604, 0xc624c43b, 0x3df16065,
+ 0x7e62abf7, 0xbf4d015b, 0xf564e063, 0x4ee519cc,
+ 0x34938aac, 0x60c035fc, 0x0a726280, 0xe81f1516,
+ 0xd6eacf56, 0x84dbdff8, 0x0ceb2641, 0x5ab07c3d,
+ 0xe9c7ffe8, 0x012ae0e0, 0xb9a20bfb, 0x6ef2aa82,
+ 0x87c34b2f, 0xb0405904, 0x0be39045, 0x7ed550b9,
+ 0x5a099efc, 0x7e1094ac, 0x0c9ae5bd, 0x8b80843a,
+ 0xe040325d, 0x7b861c95, 0x325e699e, 0xcee68f99,
+ 0x1da23e51, 0x8b2c2ea5, 0xb911e819, 0x4f40b8f7,
+ 0x2b97709e, 0xba6b3a91, 0x9a0be148, 0xd31e017e,
+ 0xf4764c73, 0x579759e1, 0x7b93aeaa, 0x470d1051,
+ 0x4e12177d, 0x95fdec35, 0x1533952e, 0x8b68fff5,
+ 0x1e9016ed, 0x37894290, 0xaf70209e, 0x9788efe4,
+ 0x3f3343c4, 0xffc3c2ee, 0x1d0394d1, 0x940546ff,
+ 0x6acde9d1, 0xf30ed7b1, 0xc0001534, 0xcbb9909e,
+ 0x73479a46, 0x7c47e28d, 0x66c67f11, 0xff54904f,
+ 0xeddb27c9, 0x3749c767, 0xea30af3b, 0x146d9340,
+ 0x39c79a0c, 0xe0371104, 0x0990053d, 0x1a42f5b7,
+ 0xaf2601bb, 0x107517ce, 0xc921def6, 0x76c0f3b5,
+ 0x63ff2f0f, 0x85fdea86, 0xeb882180, 0x4dbf7b0f,
+ 0x9ec8d9cb, 0xf3229afd, 0x50c2d2ed, 0x49a7586c,
+ 0x771a4fa1, 0xee0e534d, 0x2f12f5ac, 0xa73ac75e,
+ 0x60b9af6f, 0xf7ff83a1, 0xe2bb703c, 0x64306302,
+ 0x14568be5, 0x9dd33411, 0xd281f8f8, 0x4099d569,
+ 0xe9858186, 0xfa90089d, 0x65f19b7d, 0x70dbb85b,
+ 0x395b94a8, 0xeffed9a7, 0x3f350714, 0x7e61d143,
+ 0xfe0a0d12, 0x9541c3aa, 0xdf6871a5, 0xd51f96cb,
+ 0x074022c3, 0x67999ef5, 0x6ad1158f, 0xc96d31a1,
+ 0x7ff426cb, 0x60ea27c5, 0x46336d92, 0xde686b2c,
+ 0xfb06301b, 0x186375b2, 0xaf73a4ac, 0xcb572b27,
+ 0x462c0dd6, 0x51e4954e, 0xf194f3a2, 0xd2143268,
+ 0xdc5b60b9, 0xe4d615a1, 0x9c3a08a6, 0x473ddc68,
+ 0xce508f5a, 0x88249b16, 0x8e8e2027, 0x0bd98ae5,
+ 0xe801d745, 0x2f921241, 0x3f2baab9, 0x2a20e2ed,
+ 0x47f792a3, 0xada7bfb4, 0x6fd81fce, 0x4287ef70,
+ 0x5b3b9520, 0xeed4eb13, 0x6b9395f5, 0xdddee8c9,
+ 0xfde20095, 0xf5d910b3, 0xdebda085, 0x2058c161,
+ 0xd3f81511, 0xbef78587, 0x9148c141, 0xc2df3379,
+ 0xbab4d171, 0x02813ba2, 0x85b2ae5f, 0x62ea578e,
+ 0x930785cc, 0xd23979c8, 0x980fe259, 0x983b1aca,
+ 0x3469b033, 0x31335aee, 0xf362d1bd, 0xbb3befae,
+ 0x6423a378, 0x58e05f60, 0xdc6fb246, 0x72788312,
+ 0x349e0916, 0x8c185f08, 0xc84c5efe, 0xa1d83cd9,
+ 0x0590c56d, 0x2e6a3128, 0x18e49591, 0x254d210e,
+ 0x535b0efe, 0xfe769c6e, 0x923acb1d, 0x86d01399,
+ 0xe4235164, 0x2ba908c9, 0x41bf884b, 0x41f69720,
+ 0xb844e280, 0x3037005e, 0xd3580f5a, 0x61870816,
+ 0xcf9185d2, 0x36e90fce, 0xa1535504, 0x0504c026,
+ 0xf0f34b6e, 0xe60d2964, 0xff9aa1e9, 0x84f67bd8,
+ 0x00af4ded, 0xdbc01028, 0xe0fe8c12, 0x6d8c501e,
+ 0x29794649, 0x1d2bfbbb, 0x5720c3d9, 0x608ace6e,
+ 0xbcd5e222, 0x52c4abd1, 0x99d96a1d, 0x52d7558a,
+ 0xd3051dbb, 0x1d23ddfd, 0x735901d4, 0x3bec2256,
+ 0xf164dd09, 0x430fd7a9, 0x7e29e768, 0x30709d33,
+ 0xff5d894e, 0x210d67f4, 0x26a43609, 0xdfa922d1,
+ 0x4f1816d2, 0xa0a47b38, 0x333d24c8, 0xd0976685,
+ 0xefcaabf6, 0xa4a4d784, 0x15e5be4d, 0xe5e8c993,
+ 0xa69391b2, 0x607d1f4f, 0x555a1576, 0x703aacdc,
+ 0x0dbcfa8b, 0xf4e9a3f9, 0x0eae9403, 0xcb19f1f6,
+ 0x7716adab, 0x69d3ac10, 0xa05d8d97, 0x552600cf,
+ 0x31b62fe8, 0xc14ba90a, 0xd42c2d72, 0x22a919d7,
+ 0x81ba57a7, 0x96d0fb81, 0xe251a5f9, 0x2d9e1476,
+ 0x0a02dc1d, 0xdbec72d3, 0x1a8c63d9, 0x8a8be8a1,
+ 0x918c0750, 0xfe504821, 0x07b0d625, 0x3ee97d72,
+ 0x09c43cf0, 0xdc953705, 0xd41bf31e, 0xc9105c2f,
+ 0xd1bccefc, 0xe99eac44, 0x02834280, 0x59f7ce4a,
+ 0x95741bd9, 0xe152f131, 0xff8eed72, 0x4e118500,
+ 0x96afbb81, 0xffedec84, 0x0cbbf7be, 0xdb48c8b5,
+ 0xea45b323, 0x258f38ab, 0x7c930fd3, 0x6898f771,
+ 0x325e520f, 0x7b76fadb, 0xb8e00dcf, 0x0359f17a,
+ 0x62ee1ea1, 0xd563cf70, 0x62af5844, 0x0809d556,
+ 0x3f40a89d, 0xcca31d22, 0xe5ad0abd, 0x7e263d18,
+ 0x2061153e, 0x329a509b, 0xe8dc5d3b, 0xfd6916c1,
+ 0x1a9817a9, 0xc8cda37d, 0xe8ab3b78, 0x8800bf51,
+ 0x98c4009c, 0x174f871e, 0x49b8de46, 0x8e98bf0f,
+ 0x286f44a5, 0x22086f7e, 0x2515f46c, 0xfcbf726c,
+ 0x3d720c72, 0x0cfe552b, 0xef6887f1, 0xf931ab5a,
+ 0x3aed9c78, 0x660d3196, 0xc813fcef, 0x4beb76f8,
+ 0x6331873d, 0x6d94fc13, 0xf0ddd8e8, 0x699b0b21,
+ 0x353430fc, 0x725e44c0, 0x7ffd3708, 0xf1dde8ba,
+ 0xbcc2e9c0, 0xdc805299, 0xda5f6846, 0xd475aff3,
+ 0xbed1dee7, 0x5ad0afdc, 0xd7e66e20, 0xbe33608f,
+ 0xce795b21, 0x167e90ed, 0x38af0156, 0x88ac7309,
+ 0xd25033d5, 0xdcab169d, 0x820a374d, 0x39d34b84,
+ 0x28dd94f7, 0x834bd392, 0xda139605, 0xc053d8aa,
+ 0x2cb9580b, 0x80d230e9, 0x5467e33a, 0x2fd7b149,
+ 0x3a6186a8, 0x884dd788, 0x1d70568f, 0xee18e8f1,
+ 0x315979b2, 0xe261b648, 0x10d221a2, 0x7815b83b,
+ 0xff808b41, 0xb9c6863e, 0x806fd3ae, 0x3e344141,
+ 0xa3ea1cad, 0xdfcb2933, 0x30a77d85, 0xa6a9d431,
+ 0x785e7c27, 0xda942cb3, 0xb0034267, 0x1594440c,
+ 0x79ae7746, 0x96f8ab25, 0xab1a09a1, 0x5b832528,
+ 0xe2b679e6, 0xa78d5d20, 0xc8aae1e4, 0x55078395,
+ 0xbbe4e640, 0xdffb0c61, 0x441c1bca, 0x8d30e73f,
+ 0xfa30e9b3, 0xd8f06b07, 0x7f1b4e35, 0x4d6ef0ad,
+ 0x3a64b06d, 0x97bcd436, 0x3ed822eb, 0x6f969930,
+ 0x103c07ac, 0xe537e4d5, 0xa309b9bb, 0x838beb4f,
+ 0x64f2d7ed, 0xf1decabd, 0x906908f3, 0x7450e4ec,
+ 0x8dde52f9, 0x8b599262, 0xbfab80bc, 0x7bcb9373,
+ 0xcdf4a2b5, 0xc2c4a81c, 0x17b105af, 0x3f797206,
+ 0xc075d0d0, 0x31854148, 0x011a018d, 0x9b1ec515,
+ 0x517e1ec5, 0xb5ba74a9, 0x8c9a1095, 0xa13ceb06,
+ 0xf097a087, 0xd0a414ad, 0xb1914131, 0x5e952756,
+ 0x34618c45, 0x920a0fb1, 0xf3aeac96, 0xf15704d9,
+ 0xae19e04d, 0x705ca2eb, 0x4bc1e5eb, 0x98388d15,
+ 0x201869f0, 0xbbf41d16, 0x580c6e13, 0x4560f83a,
+ 0x24e7c61b, 0x771c1023, 0xd4313415, 0xc0b209d6,
+ 0x19e51aaa, 0x4ba1e72b, 0x6cc1bce7, 0x7980dcc2,
+ 0xfb0599b4, 0x333f5ed9, 0xf4632eb9, 0x982ccdd3,
+ 0xd7540319, 0x06ce2da6, 0x310060fa, 0xd3efc6ef,
+ 0x4c653b1d, 0xd0cc39b6, 0x83097b2b, 0xb9e4ea63,
+ 0x330d4bd5, 0xea5eaa08, 0x0249be99, 0xa17810cc,
+ 0x41030c1c, 0xe12027c8, 0x7b41d9dc, 0xc37aa89f,
+ 0xa35673a7, 0x5ee7359f, 0x48426bdc, 0x1b6d141a,
+ 0xd9b7fba7, 0x0a49211e, 0x3014b927, 0xc1754959,
+ 0x1c3ad354, 0x61640912, 0xf5f12724, 0x24070d11,
+ 0x3d6e2ca7, 0x29f6096e, 0x98adacbc, 0x6a273297,
+ 0xe5079174, 0x707df4eb, 0x634c6c6b, 0x3ecb22fb,
+ 0x3d458436, 0x8191fc3d, 0xebe7bbc5, 0xf364347d,
+ 0x12dbb37d, 0x4ad5f869, 0xe957cbc3, 0x64c3a6a3,
+ 0xfbad0854, 0x84230f26, 0x436faf5b, 0x261079d3,
+ 0x8f231927, 0xcdf3d468, 0xbbcd7bc6, 0xaa473eb2,
+ 0xece8c033, 0x26edb28e, 0x53055db4, 0xdf1ea5a0,
+ 0xbe4bd963, 0xe297793b, 0xf27a24a8, 0xff60af66,
+ 0xd596cfa5, 0x57fd7b35, 0x813057ea, 0x3a9453d9,
+ 0x1a80704b, 0x9ca1185b, 0x447b5483, 0x315a22d1,
+ 0x1ddcecaa, 0xc52dbcd9, 0x9746abdb, 0x4bc737e8,
+ 0xb4deaff3, 0x277baea4, 0xd514f567, 0x7f8d5d13,
+ 0x61c98c71, 0x9746a13f, 0x284e6bd7, 0x9ff47773,
+ 0xb223170e, 0xa24cb3b2, 0xaf13a7e5, 0xf9eef2d0,
+ 0x42d825d4, 0xde85f61b, 0x848068fc, 0xb40d1de0,
+ 0x87af332b, 0x2e543f52, 0xfb493958, 0xcf5d6d71,
+ 0xb216b5f2, 0xb10cb4bb, 0xaf95a328, 0x47806d41,
+ 0x9e46dd3a, 0xd5a5dd2b, 0x2fab0b4a, 0x5abb26bb,
+ 0x8f45c4a5, 0x8da3ae87, 0xbcfb840d, 0xee5d1cc9,
+ 0x3f406d22, 0xb10398a8, 0x61642f36, 0xc3cc27d3,
+ 0xfe72310d, 0x7af5e85e, 0x4e2a86ed, 0xca2fe7c9,
+ 0xbba737af, 0x623c820e, 0x85d1f1c1, 0x8120e232,
+ 0x257d4272, 0xadc79294, 0x7197d2ae, 0xdf5ef3df,
+ 0x5e0aefbd, 0x182f9d5d, 0xe91ebca0, 0x657a390c,
+ 0x30d511c9, 0x4c291d48, 0x5dce841a, 0x4b50a5f5,
+ 0x7ecacf22, 0xe9e8f7af, 0xb1d99403, 0x5b303278,
+ 0x44d353f8, 0x4e1b5789, 0xddbfe2d2, 0x67e4720c,
+ 0xa0ae36b2, 0xceab6cde, 0xd515e5fc, 0x79478c0f,
+ 0x71d9743c, 0xe3b3b081, 0xcc4e4c2d, 0xe00adaf4,
+ 0x827a94a0, 0xd39c6047, 0x8fad816f, 0x0c5bf72b,
+ 0xb840cf46, 0xdf9e4f34, 0xafa5d2ba, 0x84f8139e,
+ 0x13a05e20, 0x5dcb4fd5, 0x5866a820, 0x67fb9c73,
+ 0x26ea7179, 0x5b374178, 0xe7819b64, 0x7901ab31,
+ 0x870473b0, 0x6314a2db, 0x07cbf6a5, 0x8726f9d4,
+ 0xdabc5fca, 0x4e46dec8, 0x7b3f26c7, 0xdb7836b9,
+ 0xdda83c1b, 0x01a93646, 0x1466a1d4, 0xe1266cf9,
+ 0xa68d8cc5, 0x4ac76529, 0xcd32ff59, 0x8ee8774d,
+ 0xd33a8423, 0x46925ba8, 0xef5b2dfd, 0x58bf5712,
+ 0x62a70a9c, 0x35acc89e, 0x0abcd977, 0xe5debba2,
+ 0xcf90d656, 0x6144dc5c, 0xedaff63e, 0x801fb5ae,
+ 0xc96f2d49, 0xb1f44dfe, 0x6f6023ce, 0x2df8ef40,
+ 0x41aa5e71, 0xadb2e8a4, 0x2fe7c319, 0xf2d43393,
+ 0xf02c909b, 0xd4bbc970, 0x89f80199, 0x6dab42c3,
+ 0xae9264d3, 0x9c73dc38, 0xceff2809, 0x2b4b728d,
+ 0xbc9bb2d5, 0x2d99cea0, 0x8b175688, 0xbf486902,
+ 0x049e8008, 0x0d961c54, 0xe0710b21, 0x74e4b9f1,
+ 0xcca8bc85, 0xb742ce90, 0xd8b78266, 0x480cc5e0,
+ 0x5e07a825, 0xb11adc33, 0x2716fff0, 0xe9d8d689,
+ 0xbbeb9047, 0xb5cfa57b, 0xbb2773e9, 0xd6a06fb0,
+ 0x484bb37d, 0x15d196df, 0x71b83fce, 0x7c55b103,
+ 0x3cd4b67e, 0x2638afce, 0x51087e24, 0xd2370684,
+ 0x5599979f, 0x6a7af608, 0x95825d52, 0xc947e4de,
+ 0xbc75ed91, 0x190496e4, 0x510070b9, 0x6eb44403,
+ 0x27686bbd, 0x19b28aa3, 0xa08b7e81, 0x0fd26de8,
+ 0x810124b9, 0x8cdd6547, 0x25839dc5, 0x61fb8c9b,
+ 0x6ed83266, 0x112a8caf, 0xfbdc47bc, 0x74435426,
+ 0x9dcabee2, 0x635835f6, 0x11bd9142, 0x1c9a4894,
+ 0xf97624c5, 0xda6ffb05, 0xdb5e314d, 0xd085e2a8,
+ 0xe324d60c, 0x809d9b59, 0x46871dd2, 0x28359f4d,
+ 0x7642633a, 0x81141f9a, 0xee15a0a5, 0xbdf73966,
+ 0x140ed2d5, 0xf1520de9, 0x0da41833, 0xdbf5f4f3,
+ 0xb57e2ab9, 0x4408732d, 0x9dae8282, 0xed9c362f,
+ 0x3dd65553, 0x1b654d98, 0x381c0447, 0x5b225dd6,
+ 0xa5772cfc, 0xe6ef2288, 0x74790849, 0xf0043cff,
+ 0x0105a8cb, 0x681c6e7e, 0x1d42b7a7, 0x7167906b,
+ 0x5e3b2b4b, 0xe5213423, 0xd8d0d078, 0x37ad2d22,
+ 0x4f565b87, 0xfa626633, 0x45e3fa2b, 0x919fff47,
+ 0xeebee7b3, 0x71e07a3a, 0x9ef2d03b, 0x97afe9ae,
+ 0xfd580d6f, 0x037814b5, 0x49eaa632, 0x45a2a070,
+ 0xe0acb025, 0x18441e28, 0x3f55b5fc, 0x8f515111,
+ 0x6077e650, 0x228b8c06, 0x4a23d7be, 0xd6c52041,
+ 0xd5b622ec, 0xf1be00c6, 0xa2d49bfd, 0xb65194a2,
+ 0xc2ba51cd, 0x260ebdc1, 0x252d43e8, 0xa006eb2d,
+ 0x7a4ae59a, 0xe4996753, 0x62ab4fef, 0x5d3e9f4c,
+ 0xfb19a2ed, 0xbdee4759, 0xae73ec2d, 0xcf15da11,
+ 0x4cc2dd94, 0x10b7282c, 0x0c62c3a5, 0x36dd2207,
+ 0x6484d9ed, 0x3ce2a8af, 0x040c75fd, 0xd6c69d82,
+ 0x9766e56e, 0x0f38f22c, 0xd68cfa3c, 0x1f9742fa,
+ 0x36d95a41, 0x9aea1f0b, 0xd2b5c865, 0xa628581a,
+ 0x2a099542, 0x126d5954, 0xefac19a4, 0xf9dbedef,
+ 0x15a9bdca, 0x3cbb3a05, 0x108db3e4, 0xbc9e1d14,
+ 0x753eebcc, 0xcfd9fda4, 0x18f75094, 0xe0e7a7e2,
+ 0xa0f698bf, 0xd5a78548, 0xb371f853, 0xcfe4570a,
+ 0x986bb322, 0x11d605d7, 0x110fdb12, 0xe1866154,
+ 0x7f252926, 0x52745874, 0x6c525926, 0x70ca1329,
+ 0x7eb2d5b3, 0x27c84010, 0xd192a118, 0x8aba3127,
+ 0x5da16558, 0xe7dcb912, 0xea5fb0d0, 0xe22d5de3,
+ 0x09c31f0f, 0x0d23df28, 0x8a33c0ca, 0x250b4f72,
+ 0xebbf360a, 0x4364194c, 0xee682039, 0xd9a2c18c,
+ 0x71084fbc, 0x6e9833ea, 0xa10ae922, 0xe3d9432a,
+ 0x48432181, 0x69f44537, 0x1240d2ae, 0x8f722a09,
+ 0x59b65b6b, 0x0d816db4, 0xa5cf46c1, 0x54693edd,
+ 0x3c28d620, 0xeeba470a, 0x7338aa45, 0x5b79c0e2,
+ 0x1935cbf1, 0x1f956f56, 0x4d31345e, 0xf1c431ab,
+ 0x05b3e010, 0x3c0a7dfa, 0xfc26dc9a, 0xf58afc55,
+ 0x7d4c3190, 0xf95449a5, 0x210fcc27, 0x42da30be,
+ 0xb03244a0, 0x6c170e67, 0xf44d4a90, 0x8d614243,
+ 0xf8d3438b, 0x28bc6f08, 0x7a4d9554, 0x232d5073,
+ 0x2eaabb2e, 0x53f54925, 0xf56e9406, 0xd421b661,
+ 0x4c5ddeaf, 0xbeaa0fbc, 0x040c110e, 0x52dadd44,
+ 0xba8338ad, 0x95c56414, 0x289f5d3c, 0x65315795,
+ 0x93db923e, 0x039bf141, 0x714c0ab6, 0x23a619f5,
+ 0x62b5c25d, 0x5de222a8, 0x9367ba09, 0x58593f5e,
+ 0x2ae30ab8, 0x20812a3f, 0x16b9ca50, 0xc764268a,
+ 0x0e73a0e9, 0x029cef74, 0x1b891bbe, 0xcbb1de8c,
+ 0x7ef8058f, 0xe8aeebf4, 0xddb9fa12, 0x3cabc8fb,
+ 0xb843d4e6, 0x5392afba, 0x5683b2a4, 0x025c103a,
+ 0x34b6ceb3, 0x31d2c226, 0x459d501e, 0x16dc10b0,
+ 0xe693edba, 0xa595d9ff, 0x79c57422, 0xf5201c08,
+ 0x4505890e, 0x670af29b, 0x68164d53, 0x9e8a0dbe,
+ 0xa6b6a3e6, 0xe82698a1, 0x0096368c, 0x71d1009b,
+ 0xf72fc2de, 0x440be50d, 0x35d7a24c, 0x072314e9,
+ 0x8f5ed7b2, 0x51860174, 0xdcb3938a, 0x26899f67,
+ 0xdcf616f2, 0xe558bcae, 0x60670b82, 0xb6fe496e,
+ 0x8f8ad53a, 0x6e57ab62, 0x469e8231, 0x35bda2b1,
+ 0x3597dbd3, 0x9a8e8c24, 0xa62fb58d, 0xdeb2658b,
+ 0x8ee0feeb, 0xa1da2b0d, 0x82a2d9b3, 0x301f36de,
+ 0x5cc421c1, 0x27cbcd12, 0x75b87a8d, 0xdcc8face,
+ 0x24843f57, 0x63b23f78, 0x2f8f2dbc, 0x9157f004,
+ 0x2a9180a8, 0x63210422, 0x1d1d89b7, 0x2ab8a327,
+ 0xe95ee370, 0xc84db7b0, 0xf41eb572, 0x1c9474c0,
+ 0x695576eb, 0x5b1fba8f, 0xfaae4a04, 0xd048dbc0,
+ 0x2ad7be31, 0x20d25a7f, 0xa01d2e13, 0xb5e7c74c,
+ 0xc6805a14, 0x73713639, 0x63d18906, 0x9a2f8296,
diff --git a/src/cpu/intel/model_206ax/microcode-M12306A6_00000002.h b/src/cpu/intel/model_206ax/microcode-M12306A6_00000002.h
new file mode 100644
index 0000000..3c6ba76
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12306A6_00000002.h
@@ -0,0 +1,384 @@
+ 0x00000001, 0x00000002, 0x08312011, 0x000306a6,
+ 0xe9ce4ee5, 0x00000001, 0x00000012, 0x000017d0,
+ 0x00001800, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000a1, 0x00020001, 0x00000002,
+ 0x00000000, 0x00000000, 0x20110830, 0x000005f1,
+ 0x00000001, 0x000306a6, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0xeaa96815, 0xbf0016eb, 0x16d2125d, 0x3ed0f544,
+ 0xd82192eb, 0xd4963752, 0xa4a5f9f7, 0xad490c3c,
+ 0x5a3401db, 0x42caecce, 0xb4d8e75e, 0xe6dbaf24,
+ 0x7861b35f, 0x6bd717bc, 0x23b9b731, 0x82ec1ac8,
+ 0x20337b64, 0x5396dbf1, 0x59973bff, 0x724bc7e9,
+ 0x5237193b, 0x0b8647c1, 0x6a0d0e16, 0xbf9ddb5b,
+ 0xace2cc1c, 0xad707638, 0x056f102f, 0xa37e60f8,
+ 0x76255642, 0xfb86e030, 0xb8069a40, 0x367795f1,
+ 0x653fb05e, 0xab7f14ad, 0xb6e8a8e1, 0xd2598d20,
+ 0x2eba3f68, 0x78b372f1, 0xba8d13f8, 0x1f1de861,
+ 0x97f951d5, 0x8097c728, 0x27dbf904, 0xb97906a8,
+ 0xffe7a4ac, 0x4b947668, 0xc1dbd726, 0x2adcf777,
+ 0x63b1bcf0, 0x818e2a1b, 0x49aa907b, 0x2faf5e8d,
+ 0xae842352, 0x82707fae, 0x0aa12b41, 0xa0bae11c,
+ 0xb4298c47, 0xd2b4099c, 0x4ff625f2, 0xcd2630d4,
+ 0x79850981, 0x05dbf57d, 0xb05b81a5, 0x56e73ec7,
+ 0x95cb3897, 0xe262bda5, 0xb2c6e288, 0xcb7f8e77,
+ 0x72b8bdd3, 0x3f400494, 0x63ade65b, 0xbc4adc71,
+ 0x00000011, 0x38ac9f0f, 0xb4156ce3, 0x5dc4da3f,
+ 0x53eb7c7b, 0x0079dd4f, 0xaa3df28f, 0xce6fdcc9,
+ 0x074a5ae8, 0x67b50ca6, 0x5b24a2c7, 0x8a2b7c07,
+ 0x677ee532, 0x7051267a, 0xfefcafc5, 0x6ef28a14,
+ 0xb87e54e6, 0xac6522da, 0xdc689c8c, 0x94c73235,
+ 0xbb421b4b, 0x63c30d81, 0x966f29e4, 0xc2cac70e,
+ 0x18da0d29, 0x24a7e1fb, 0x4214c1cc, 0x6064b927,
+ 0x55a1889d, 0xefdea3e4, 0xde89d159, 0xbddbae9e,
+ 0xbca4b888, 0x1fad580a, 0x1ee6f78d, 0x75c5f074,
+ 0x21b90fd7, 0xa257e08c, 0x5e83b04e, 0xe5ac0763,
+ 0xe7073db6, 0xa9a313ca, 0xd0b03786, 0x7b02d7f7,
+ 0xcae1c146, 0xc365fc96, 0x0fa15115, 0xb336207b,
+ 0xe59703c8, 0x8f48b65c, 0xcf458fab, 0xc4a1d377,
+ 0xee0b0f7d, 0xf8e75028, 0x102af212, 0xcef8363d,
+ 0x022842da, 0x8ed4bf21, 0xb29d35ad, 0x94e37988,
+ 0xc1fe410d, 0x561f5885, 0x0dacb91c, 0xcc3cd641,
+ 0x9de4f875, 0xf3bdea1e, 0x372a102d, 0xfd42391c,
+ 0xff2e9fbe, 0x58805096, 0x2d39e235, 0xe7cc4864,
+ 0x11343168, 0x968b9ceb, 0x24ed599a, 0xc7a55e50,
+ 0x24c70ff5, 0xa0697d66, 0x02c7a31e, 0x04017ae6,
+ 0xb27ad9b3, 0x9c2487c6, 0xd3347029, 0x1dac49fb,
+ 0x21acf089, 0x06382af3, 0x7aa6e972, 0xb749e98c,
+ 0x4d55714e, 0xc10cd419, 0x85416ad9, 0x0c0e2407,
+ 0xcc71cca2, 0x70a69969, 0x6c953e87, 0xe66be904,
+ 0xf69fab02, 0x7259d978, 0x90e2daca, 0xe6f6ecfd,
+ 0xe1c36d4a, 0xded87dc4, 0x2aa35e4b, 0xb9d8d1ac,
+ 0xd2d0f621, 0x10894447, 0x725086e8, 0x4c3f37f2,
+ 0x6beca92d, 0x6a4b1d5b, 0xffc8b550, 0x5733694b,
+ 0xf6162227, 0x3f748554, 0x261c9891, 0x0efbec4d,
+ 0xcb0758db, 0xee819d84, 0x1b9f30ed, 0xcdfb096e,
+ 0x7a8a26ba, 0xd1dbcfd5, 0x50ec8c13, 0x8197cff5,
+ 0x3a0ddf9a, 0xc33e268a, 0x80ff474d, 0x0fa70985,
+ 0xaa8e0eb5, 0x6ba07e75, 0xc49a118c, 0xdbba7064,
+ 0x60e66252, 0x3d6efb61, 0xc8ec2eab, 0xec4ec2e9,
+ 0x64e6b27d, 0x861c7b8f, 0x04e4e01e, 0xba9800ed,
+ 0x607056a9, 0x5c076ab3, 0xe4ac7092, 0x4ad67f26,
+ 0x03394408, 0xc922fd95, 0x231ed10f, 0x01c6821e,
+ 0xd3d4022d, 0x50d69c90, 0x355c96e2, 0x0b7e2df6,
+ 0xba8476de, 0x20fa0033, 0xc2391bff, 0x1cf3dded,
+ 0x2b15eb1e, 0xd3d79c61, 0xe8791aee, 0x596182bf,
+ 0x08ae5405, 0x2c21bede, 0x67201199, 0x04a637e0,
+ 0x3dd39f30, 0x7149b326, 0x98731a76, 0x5ca773e2,
+ 0xaa42585a, 0xf66b28e6, 0xa1be70ba, 0x914d5f3e,
+ 0x7fc56635, 0x985cd1b4, 0x0abd5590, 0x2032d2fa,
+ 0x42052ce9, 0x9dff6fda, 0xd358630b, 0xca6fd0db,
+ 0xa16fe2ff, 0xf75fe9c4, 0x37fcfef2, 0xf9ed9368,
+ 0x93594de4, 0x389a32d3, 0xc4ec7a4c, 0xaf92e40c,
+ 0xb876be6e, 0xa03b4f5a, 0x520efd67, 0xe7024eaa,
+ 0x847577d8, 0x53c065f2, 0xcd3d6215, 0xc4628ba4,
+ 0xea05a759, 0xe5f54593, 0xa94a5f9d, 0x51c8acc6,
+ 0xb415164a, 0xa1a94b2c, 0xfb16a62a, 0x3b9a8b86,
+ 0x2c15e4c3, 0xbe17f0b4, 0x8bdeda08, 0x8dc040de,
+ 0x85173ff8, 0xa93526fb, 0x82a14d2c, 0x6b77fdfe,
+ 0x0ffefc0d, 0xf9d60197, 0xef228860, 0x4907df59,
+ 0xf0067253, 0x7b642650, 0x2a2393a8, 0x745609b2,
+ 0x2cb652ce, 0xa8f15683, 0x71f3a1ff, 0xe737983c,
+ 0x7231e659, 0xf3ae658c, 0x66ab51be, 0x545b1d2a,
+ 0xc0ff3437, 0x1b47397d, 0xd2d35a19, 0x04badbdd,
+ 0x0f2bcc0d, 0xe7aee4ef, 0xca09614b, 0x0217101e,
+ 0x9d7b6cc7, 0xcc347bcf, 0xa08e33be, 0x22d8e5d7,
+ 0x11155f1d, 0x141c6886, 0x5a51f28c, 0x6c24f4f6,
+ 0x16a82fc1, 0x8b451f91, 0x769e8906, 0x1847c4e5,
+ 0x762b06b4, 0x3c41a6b4, 0x5368060b, 0x887e0654,
+ 0xfc47b486, 0x60a0d279, 0x05896959, 0xd4f9ec57,
+ 0x34d88a6b, 0x2ea299af, 0x5383e6e8, 0xd99590e4,
+ 0xbbbd7ce8, 0x67d781ce, 0x29662b72, 0x10e919eb,
+ 0xb9e7d23c, 0x64503030, 0x02890e86, 0x4edea478,
+ 0x13c6e0f0, 0x08fe7c81, 0x9341eb6a, 0xd842f9fd,
+ 0x3199d533, 0x220d7d0d, 0x37cf33f0, 0x992b0333,
+ 0x93cb3b74, 0x544dd8f8, 0x7633881c, 0x93a6fd49,
+ 0x0ed83723, 0xe2a85a87, 0xe336dbf8, 0x839e7d3b,
+ 0xd0e6815a, 0xc88bb70e, 0x2b1d8552, 0xa84e999f,
+ 0xf9bf094d, 0xd35bd5bd, 0x1f7b2873, 0x3f079540,
+ 0x823951d5, 0x4d989993, 0x91c1dcfa, 0xc935a629,
+ 0x22ca55df, 0x6fb04a93, 0x41bfb297, 0xe80a493c,
+ 0x059c2d2f, 0x1824b40f, 0xc7b5b891, 0x1a344e47,
+ 0x635191f4, 0x44f4b87f, 0xbd9a5d61, 0xa9eec49d,
+ 0xb2b26209, 0x05fab66c, 0xf74b4dcf, 0x927c41f5,
+ 0x2c06e8f0, 0x7c02c993, 0xeca47568, 0xa0dbd313,
+ 0xe50d7c89, 0x3aae0da2, 0x6045fa68, 0x334403ca,
+ 0xe9fac688, 0x288b3c3f, 0xc148ee64, 0x7c1f4e20,
+ 0x5800dc60, 0xe7ce5fa5, 0xcd833c1a, 0x28f035d7,
+ 0xe397fb4d, 0xc4011f25, 0x119cc6c4, 0x9f9e07b4,
+ 0x04283b5d, 0xee1b4c20, 0x5f57842a, 0x97749294,
+ 0xc80d31e6, 0xcf639a39, 0xc52ef00d, 0x97c8a3bf,
+ 0xf49260c6, 0x4773eb81, 0xb1aeb5af, 0xcd641b80,
+ 0x9931fd15, 0xd9ece255, 0xc13d3104, 0xa8fa5745,
+ 0x6c718c54, 0xeb8f64c8, 0xaa7d0037, 0x79b0154d,
+ 0x3f98f1c8, 0x884528f3, 0xbadef46d, 0xdabec09e,
+ 0x75e249aa, 0x01fffa2b, 0xa5d5b9f1, 0x3f40bb16,
+ 0x0ab461ab, 0x83342953, 0xa2978bf2, 0x0f98f86e,
+ 0xecfb066b, 0xbb486e27, 0xe0c6d03f, 0x84445088,
+ 0x3bb688dc, 0x508c4338, 0x803a32f3, 0xdf955c80,
+ 0x6b84e4d8, 0x2d590a90, 0xb5b0e0fd, 0x0c79af18,
+ 0x09918548, 0xc9aa474e, 0x26bcbccf, 0xd70c5c18,
+ 0xd0b6b42e, 0xd4a8c97b, 0xb8bf3877, 0x1cf6b7ae,
+ 0x991e7fd6, 0x965e5d35, 0x06b33509, 0xba5b0e05,
+ 0x2d2f4820, 0x26e278c5, 0x1f516c10, 0xc670a2a6,
+ 0xeb10ae27, 0x36307698, 0x01523c03, 0x06417c57,
+ 0x2901e3a5, 0xa1f61ee5, 0x454c61c9, 0xd51f4cff,
+ 0x5450c647, 0x156ab06e, 0x13e4d416, 0x43b2e55d,
+ 0x01b9b2f4, 0xa3a0b87e, 0x83b91344, 0xbba16bfe,
+ 0x6a889ebb, 0x5f97942b, 0x610c3a6a, 0x85dbc617,
+ 0xc5ae2b2d, 0xa1f320cb, 0x35a5cf5e, 0xec0af4c5,
+ 0x4a4780cc, 0xbda150a6, 0x26a91e0b, 0x89e02118,
+ 0xa13ae1ef, 0x72aec6a9, 0xf978bdab, 0x7bf5557a,
+ 0x28eac9da, 0x93d1259d, 0x6a7a1262, 0x4c54fd91,
+ 0x6189e29e, 0x8f3c1f14, 0x85417a4a, 0x31efe683,
+ 0x9cc5ef64, 0x4b65fdf6, 0xdd5a66bb, 0xd6cd06d4,
+ 0x9ed09d41, 0xe56704f6, 0xf0942c8a, 0x6cb0ab33,
+ 0xbcbb4648, 0x5c0cf32b, 0x13c294a0, 0x22e6134c,
+ 0x16020bfa, 0x7a34d63e, 0xbb9ff793, 0x60020f2d,
+ 0x52715f71, 0x85b278be, 0x06d9c6e4, 0x9ea397ce,
+ 0x0af08069, 0x6e4281e9, 0x7304f7ab, 0xbb241137,
+ 0x8ed10cac, 0x04736847, 0x8dae29e1, 0x168f1aa3,
+ 0x6e2aba1f, 0x47ab0ebd, 0x62187535, 0xe276b5a7,
+ 0x77879654, 0x262a0d48, 0x846bc810, 0x44ab1be4,
+ 0xf945289f, 0xeaea018e, 0x9b8bdbc9, 0x990e7f6c,
+ 0x713fc43b, 0x4c02802b, 0x64d3bc7d, 0x9a217516,
+ 0xb727ab52, 0x6cdc56a8, 0xebb8d351, 0x905cede3,
+ 0xff58d536, 0x1a1ba1fb, 0x9bad80a8, 0x61842623,
+ 0x56032aba, 0xa778a686, 0xb1a8fcba, 0x7a053440,
+ 0x1caba507, 0xafd2ed87, 0x1592a689, 0x5916be55,
+ 0x82614e21, 0x0f85a939, 0x48c4c6cb, 0x6d1ab12f,
+ 0x16091fc0, 0x97dcbac1, 0xc9c2acd7, 0x43b796d9,
+ 0xe95d2022, 0x585b20a4, 0x34eac923, 0x3b60dbb4,
+ 0x41ad361d, 0x448eef1c, 0x58011794, 0x664d8775,
+ 0x32adbedc, 0x81db1825, 0x796161f4, 0x04d4efc3,
+ 0x89f29fed, 0x44c929ea, 0x22a258ee, 0x2f379a8a,
+ 0xab6fa455, 0xa4c357ee, 0xfdede306, 0x1eea21a6,
+ 0xb2dada43, 0x53b8126b, 0x7a1d93ea, 0x6e320d26,
+ 0x81df4c72, 0x6bcf3d1a, 0x53d97407, 0xb93da96f,
+ 0x4ca83508, 0x152d39f6, 0x139b211d, 0x0c60ec25,
+ 0x78fc6997, 0xea232eca, 0x2bf69997, 0x9799dba7,
+ 0xbfa64e15, 0x5385edb8, 0xeae9a72e, 0x7b04646c,
+ 0x1524210c, 0x700296b9, 0xfa9efa76, 0xdb1ec967,
+ 0xd9559a88, 0xe1cef762, 0xb3bdac80, 0xc1a085a6,
+ 0xa6645021, 0xb4d39a1c, 0xbf866682, 0x14188e1b,
+ 0x5477797e, 0xd4888548, 0x707d0d12, 0xc87b1693,
+ 0xeb0d9e22, 0x227d5ef1, 0x658dc627, 0xb8a4fedb,
+ 0x8186ca84, 0xed54db37, 0x611ade6b, 0x9a95fa10,
+ 0x0bfe233b, 0x42676905, 0x6f00d1c7, 0xc6db9823,
+ 0xe385fd97, 0xd7f43f60, 0xde693ed2, 0xfc5f6753,
+ 0x672e3232, 0x0c051e6f, 0xfe6c7a31, 0x13305b5d,
+ 0x3f42f2fd, 0xdc217f86, 0x8484af50, 0xb4ab372c,
+ 0x8df7e31b, 0x3e8edb85, 0x6f746731, 0xbad73a1b,
+ 0x50b5c6a9, 0x6673ca19, 0x6d1efe4e, 0xa9f22f6d,
+ 0x12a85175, 0xb8dce570, 0x01c4dfca, 0x32738ba1,
+ 0x1e8faaad, 0xdcb58a2b, 0xd28ca3a6, 0xd836dec7,
+ 0x245bbd41, 0xb7ae396c, 0x8aa97452, 0x9eac9899,
+ 0x5856a849, 0xed668405, 0xc6eb79d3, 0x2bc6d735,
+ 0xd866a5f6, 0xcb4eb649, 0x4c2bb992, 0x63bcf3c3,
+ 0x0a3c2b25, 0x1b0fa3fe, 0x55bdd9cb, 0x91c0a44b,
+ 0x36debaf4, 0x0fc3fa30, 0x135f05ce, 0x7486c06f,
+ 0xab814f50, 0x7245b169, 0x0d588979, 0x3955156b,
+ 0x6ae3fac8, 0x9e3142dc, 0xff6b5558, 0x6d0bbdb7,
+ 0x5eae4fcd, 0x506d05e8, 0x4fc08e61, 0xf3318ee7,
+ 0x5129b256, 0x26fccfc8, 0xf3799a23, 0x65429a3e,
+ 0xb84035e6, 0x2ca651eb, 0x2a6d4a7c, 0x2cc2b89f,
+ 0x5211893d, 0xf9fb2a86, 0xeb6fe6c3, 0xfc184d2d,
+ 0x5439b889, 0x4f43a3cd, 0x890e8bb3, 0x5ca34837,
+ 0xb0a2aebb, 0xb125b056, 0x815eb93a, 0xe41f19a8,
+ 0x0bcea835, 0x033fc017, 0x6ede6d41, 0xa123bdbb,
+ 0x7ca43851, 0x74f272f4, 0x7ebc956c, 0x6f7b4c30,
+ 0xbee92a5c, 0x68e1530d, 0x532553d1, 0xd1b88b16,
+ 0x82c15e64, 0x0beb18ac, 0x74348efd, 0xea7242fc,
+ 0x90b7658f, 0x5f4aa652, 0xa4c89968, 0xd13ffee2,
+ 0x31a185de, 0xea95476e, 0x74f2e4fb, 0xc1bfb0d2,
+ 0xc8d9dc22, 0xc8ed0f3b, 0x9257519d, 0x951699cc,
+ 0x65ceeeb1, 0xada75da2, 0x203f05c0, 0x82e3aed8,
+ 0x0046e8f3, 0xf51092c1, 0x2f97a780, 0xb9f49d70,
+ 0xc548ccc6, 0x71b17d57, 0x06d60c08, 0xba1266e4,
+ 0xac00b3c5, 0x6ecd17bf, 0xafe69e47, 0x2cf15183,
+ 0x170df923, 0x9965db00, 0xddd0975d, 0xfc97318e,
+ 0xb823145f, 0xc9148971, 0x451a60d1, 0x142dc417,
+ 0xb821eaac, 0x8a226b83, 0x7f3a42fd, 0x46bdc002,
+ 0x63d30c50, 0x33bf607b, 0x1622d1ab, 0x84406663,
+ 0x05fa508a, 0x99e4a7ce, 0x85b74d2e, 0x06e757e8,
+ 0xcf31f2e8, 0xa2d96da5, 0xa9609871, 0x66c174da,
+ 0x25c0beb2, 0x2f431c4b, 0x5c84ed22, 0x5a32725d,
+ 0x830ffc70, 0x740965db, 0x1209289b, 0xed00d801,
+ 0x548c1be8, 0x3fe17d39, 0xd064f60b, 0x1daeb1c1,
+ 0xe7700c0f, 0x6f921a2f, 0x817c79e7, 0x309317d8,
+ 0x0a8e54d7, 0x7de8f19f, 0xfeaa6d93, 0x0f9b2e2d,
+ 0x6ca506d7, 0x78a8a02d, 0x09308118, 0x29f0c3dd,
+ 0x93b68bd8, 0x38e50107, 0x9e7455b6, 0x76d45134,
+ 0x98fabf9c, 0x6655e512, 0x66a64b4b, 0x59cad0ac,
+ 0x348493b9, 0xd7f0cdac, 0xd3e8b666, 0x73bef86c,
+ 0xa0cd8753, 0x688a19e3, 0x62d76794, 0x9190fd83,
+ 0xffbff536, 0xbc1e8fe5, 0xde0790de, 0xa977326e,
+ 0xbdeb2bc3, 0x991e3548, 0xd30c4867, 0xd878747a,
+ 0xe9ac9864, 0xfc481d14, 0x150a17dc, 0x74d119fb,
+ 0x2e90c950, 0xb50608d9, 0xc0793460, 0x8dc70895,
+ 0x046975eb, 0x209e5f44, 0x20512ecb, 0x6dbc6a4e,
+ 0xc616bf46, 0xde922fcb, 0x8cde7cb2, 0xe469e1ae,
+ 0x5c34da1a, 0x41cdb147, 0x9ea48b58, 0x058d1560,
+ 0x1760ade6, 0xe4641418, 0x1a75a0be, 0x80a19c95,
+ 0xf8de79d8, 0x9bc8a253, 0x7bcf96c5, 0x29d75f45,
+ 0x0b881e46, 0xdbedcce1, 0xcbca8678, 0x487fc6fb,
+ 0x22e423dd, 0xeee86593, 0x00c0d4a2, 0xa97a9dc2,
+ 0x936f09b3, 0xf46221ba, 0x88ba82c9, 0x981e806c,
+ 0xc242a920, 0x647d9a1c, 0x5afba7ee, 0x9250b299,
+ 0x287473fc, 0xe0a958d6, 0x45abe4c3, 0xf530dbda,
+ 0x23901326, 0xf2abef55, 0xc00b15a5, 0xb5560695,
+ 0xac324464, 0xeaedff30, 0x2fb72613, 0x7f80ceb8,
+ 0xd92e61ad, 0xa3922d8f, 0xdb0c649e, 0xb2bd43b5,
+ 0xff6de336, 0xa37580c2, 0x1a76d318, 0xfc6a2eaa,
+ 0xba663743, 0xe0e9c85c, 0xc9e7c52f, 0x2451eb8f,
+ 0x1dc47d35, 0x1eae01b0, 0x8a4f0872, 0x748faf7d,
+ 0xe1c06cf6, 0xa5dddb88, 0xbfe7e0fa, 0xb696f377,
+ 0xc8d622f4, 0x256ebdae, 0xd0e30ce8, 0xed1222c4,
+ 0xe56c0c13, 0xfe59e2b0, 0x493a329d, 0xf803fba7,
+ 0x734b7982, 0x115c76be, 0xb69c8cac, 0x5f172599,
+ 0xe56b1a64, 0xa7472163, 0x5d2e7eb5, 0xc425e08e,
+ 0x24e63c5a, 0x7ba0b8aa, 0x3b29597f, 0x9dd86ba2,
+ 0x5cada62a, 0x2c54c829, 0xf7a94555, 0x244728be,
+ 0x9e85c26f, 0x2a433437, 0x43b471a0, 0xfe0f1cf5,
+ 0xe2befd62, 0x7e0a3cfe, 0x853af42c, 0xe8ba9b10,
+ 0x30f844f6, 0x1faab458, 0x818de104, 0xbf265ce4,
+ 0x34af9651, 0xe71a8b35, 0x5fc96bd1, 0x5d625c4c,
+ 0xf35b9216, 0x75a36ab7, 0x025759f5, 0x47f2f62c,
+ 0x1c5d4213, 0xcbbfa087, 0x9539604d, 0x4da0af8d,
+ 0x2ff219ce, 0xc3f76c29, 0xef089d74, 0x60ca4b6f,
+ 0x82bd32af, 0x1d5424ff, 0x46d4f77b, 0xf70bbcc7,
+ 0xe758c403, 0x47df7637, 0x175bf34a, 0x33a0241e,
+ 0x9cf24ccd, 0xab4fc44f, 0xe798328f, 0x407bf3dd,
+ 0x84a7d158, 0xcc152534, 0xef51a4a8, 0xb7450836,
+ 0x1972ed3f, 0xae8be937, 0xa6c4dc3d, 0xd793fea6,
+ 0xfb409d42, 0xcf83ac4b, 0xf468e31f, 0xf915180b,
+ 0x53ad27d6, 0x98c4d239, 0x5af4e4be, 0x28be952f,
+ 0xbf09115b, 0x92eed6f9, 0x45f64b4e, 0x33e42757,
+ 0x6f1d23ce, 0x226db3df, 0xf1286ab1, 0x4f9e4dea,
+ 0x20486bcd, 0xdf8419bc, 0xf9dadaa2, 0x118a5517,
+ 0x652bd97c, 0x01f83569, 0x7aa4dbd1, 0x7aaf2f69,
+ 0x444c6b89, 0x679bbc56, 0x05d752ac, 0x18eb8462,
+ 0x1fed6072, 0x21d7484c, 0x5da02ac1, 0x1f416be5,
+ 0xccc1618f, 0x8f4c0e76, 0x5f56c103, 0xb404f46c,
+ 0x57079839, 0xc7165e79, 0xb14a3d71, 0x463af1e9,
+ 0x4348c4ba, 0x522fd29e, 0xa660346b, 0x6683ccba,
+ 0x02ec59bc, 0xe1514013, 0x55d9631b, 0xceddab96,
+ 0x64ce3004, 0xf01e9c36, 0x377f85be, 0x47217cea,
+ 0x7002c461, 0x20369470, 0x145f162e, 0xe941d828,
+ 0xcbd8517f, 0x14e8e489, 0x6b2b06bc, 0xdc004075,
+ 0x723014c8, 0x640a537f, 0xc831e89e, 0xd82df3ae,
+ 0xa5ca8c97, 0x83f99215, 0x202f7c21, 0x0e7c6962,
+ 0xadcaa3a2, 0xde77a73b, 0x0f0beb7d, 0x6ade3ea7,
+ 0x520734e7, 0x017159ea, 0x133cdddb, 0x79651221,
+ 0xe5af92c7, 0x4d3abed4, 0x92b2b2de, 0x6e68386f,
+ 0x885d07a7, 0x185cbb66, 0xcc7f2080, 0xdaedd636,
+ 0xeacf4a3d, 0x6c17ad90, 0xb8474d66, 0x377d8588,
+ 0x5f2af28e, 0xd272e4db, 0x8a727a31, 0x623cd060,
+ 0xbd17142a, 0x39f43230, 0x5385856e, 0xbaa19999,
+ 0x8c29b382, 0xc5e8bca9, 0xb0766a2f, 0x72de1ea7,
+ 0x82db58d7, 0xcd686d45, 0x55b8a187, 0xe3fe770b,
+ 0x3fd01567, 0x9daf6042, 0x4330ba5e, 0x25f8ca25,
+ 0x7feb8b8c, 0xe2a49567, 0xd19902a6, 0xbca3f61f,
+ 0xbc55dfdd, 0x4adccac8, 0x948b7bdf, 0xeeb2257e,
+ 0x61790c85, 0x4deb3663, 0x537eb6f3, 0xa984d8cb,
+ 0x5e3ccd7f, 0x1076cc3b, 0x9993b755, 0xe55ac802,
+ 0x597daf68, 0xc0aeaf5c, 0x05fa176d, 0x873c6b98,
+ 0x73f55379, 0xdac484b2, 0x71d83be7, 0xc11eccd6,
+ 0xad21100c, 0x902e517e, 0xc2dfc41f, 0x91aa4f5a,
+ 0x3c1aea4b, 0x2b70e6f1, 0x9f89d3d8, 0xba5e6fb0,
+ 0x42148819, 0x3c5f837b, 0x926ac3ba, 0x03447e81,
+ 0xd7a666dd, 0x09bca9f9, 0x33f360fe, 0x8fb072d1,
+ 0x3ea3d789, 0x249a7b62, 0x887c85e2, 0xd773d347,
+ 0x4d509729, 0x8e70cd83, 0x40e206b7, 0xca15d5e2,
+ 0x4fbc41cc, 0x0dffe7f9, 0x6f423942, 0xbf66de01,
+ 0x61adb429, 0x0c25d19a, 0x8f0c4af2, 0x245b3640,
+ 0x71a93e9a, 0x3064f7b5, 0x8fcc7ce8, 0x3c72fd22,
+ 0xa8d506fb, 0x5b57670f, 0x6cc3da45, 0x0f51a6a3,
+ 0xb0494ab3, 0x4516ce3d, 0x95965825, 0xabced34a,
+ 0x8bc9789e, 0xa93d81e0, 0xe0db2466, 0x1919134b,
+ 0x4c00d4e5, 0x2b9ab4ce, 0x4ffea6aa, 0x1240070b,
+ 0xee1ddd9c, 0xd927cb4c, 0x39d9b3b9, 0xfd79d79c,
+ 0x80ff4d52, 0xb2d12f16, 0x43690044, 0xa0c64fbc,
+ 0xbdf7ed27, 0x74be0dfb, 0x1cbac9f8, 0x87c51b24,
+ 0x13f60cfb, 0xafe77b05, 0x5b17986c, 0x334b6e14,
+ 0xf5303945, 0x1dec53e6, 0x94b31630, 0xb6677e38,
+ 0x4036ee99, 0x0279aa47, 0x7b877890, 0x5f6af223,
+ 0x270e8414, 0x980f3ea1, 0x4d072b3d, 0x9782822e,
+ 0x0f81b474, 0x14a74b39, 0x70c996f8, 0x254f9ddf,
+ 0x285cf710, 0x728e3003, 0xe910d915, 0x1e0dc365,
+ 0x46e3f9b5, 0x186e4a2c, 0x53a47fe9, 0x30031402,
+ 0xeedb25f6, 0xf47a0564, 0xc741ea25, 0x43830a2f,
+ 0x1079ee84, 0x790e49b1, 0xd73b66b8, 0xbca6fb27,
+ 0x573a5e83, 0xa0964bd9, 0xd4f65a5d, 0x399914b4,
+ 0xf87a6f20, 0xd6251b6c, 0x04aec019, 0xe0056f0b,
+ 0xfbc51f69, 0x8ed78136, 0xc8eedf0d, 0x969bcafc,
+ 0x664dc3ec, 0xc22e0074, 0x8d695eae, 0x85eb07ed,
+ 0x0b1a3c48, 0x06ad64ce, 0xf3f742ff, 0xc84356e1,
+ 0x642a55ed, 0x97f94824, 0x988ed85e, 0xe90e2aaa,
+ 0x91e3325d, 0xaf1a13c3, 0x59dccee0, 0xac947fda,
+ 0xe2000f40, 0xb0f49ab7, 0x7ce3292f, 0x79bcdb1b,
+ 0x3d1efcae, 0x08ad67fd, 0xdc3d9dc2, 0x58b6a9f9,
+ 0x616e9986, 0x4c414f34, 0xaae23616, 0xaf980b07,
+ 0x925b08b1, 0x58712776, 0x39d14331, 0xf0991d83,
+ 0x9d2afd7a, 0x6895d6be, 0x8509da31, 0xb669643c,
+ 0xbdf301d5, 0x230ab7ef, 0xb5be4ce7, 0x32faee37,
+ 0x79eb836a, 0x2de038b4, 0x2a5edb92, 0xe0d41400,
+ 0x0fd463c1, 0x38619ed4, 0x052b60c4, 0x4ac45a2a,
+ 0xcd992782, 0x66a42505, 0x948b3dcc, 0x4890ed9f,
+ 0x3f0944df, 0xa5031959, 0xbaef9cbd, 0xc9fd58e4,
+ 0x6b01540b, 0x1553420c, 0xf3bf279a, 0xb2647028,
+ 0xab22933b, 0xefa0e657, 0xa6ba2a3c, 0xd2eec6cd,
+ 0x2647f2b3, 0x00e5a483, 0xfbe910f0, 0xfd92fb11,
+ 0xb5366a32, 0xbfbe393e, 0x01f511e9, 0xfd3fddf1,
+ 0x26b634a1, 0x6f5b92e5, 0x94dbf536, 0xceab9d5d,
+ 0x607ff06c, 0x8955a5e3, 0xf71f24e7, 0x30df8e14,
+ 0x1429761b, 0xe94df1cc, 0x9a1f821f, 0x21e15d73,
+ 0x86f2960d, 0x6f4ee7f1, 0x86ec25f3, 0xf6f0f0f5,
+ 0x03606361, 0x3b90c2e7, 0x2302dd2f, 0x5753a789,
+ 0x2e3a0c07, 0x2327269f, 0x41051953, 0xc2be42c3,
+ 0xb27f1956, 0x2f36176f, 0xc24b662e, 0x541875d2,
+ 0x435cbc65, 0x8c6928fe, 0x1f282682, 0x1f2da9d1,
+ 0xa9f93ee2, 0x04227aa0, 0xfb3951e4, 0xae72dc77,
+ 0x330e3b18, 0x34fdc918, 0x317dffe2, 0x7c7631bd,
+ 0x5ed76305, 0x581b5979, 0x94c15074, 0x9e610748,
+ 0xe10cb169, 0x490c1baa, 0x9a0a6775, 0x5550ee45,
+ 0x582ae8af, 0xd5ccc66a, 0xc7331fb5, 0xcaaaa739,
+ 0xff03332f, 0x496799b1, 0x5e1f80c4, 0xe0175b6d,
+ 0x852d709f, 0xcbdd5250, 0x133484a3, 0xb71fde2b,
+ 0xfb2e77a0, 0xba2f26a3, 0x02f50324, 0x634f7a59,
+ 0x20d04d76, 0x67db3fec, 0xa45c88dc, 0x9217183a,
+ 0xe861f7a8, 0xb1c9baa7, 0x29ec4e3d, 0x78e806e0,
+ 0x5ce0e9af, 0x88d6cb15, 0x396ef45c, 0xb7429997,
+ 0x6ca35b40, 0xcd04ef55, 0xe27fac1a, 0x21b0eaf6,
+ 0x8d844678, 0x8954090d, 0xb6b85c1e, 0x2b244dbe,
+ 0x45547dc6, 0xa436b970, 0x4ce19b18, 0x36fc3457,
+ 0xcfb1a35c, 0x15302cef, 0xb59e3515, 0x141097dc,
+ 0xd6fbd844, 0x3aaf6931, 0xb0b5401f, 0x05469bfe,
+ 0x466c6b32, 0x85505bf5, 0xc8ca5a73, 0x77054c9f,
+ 0x143e80c4, 0xc64885c6, 0xd700c060, 0x2b86831e,
+ 0xcc4190ec, 0x19b614ad, 0x62314429, 0x1900a299,
+ 0x757a7e5f, 0x733329aa, 0x679eb7ef, 0xbb2a7f89,
+ 0x047047b8, 0x0955a5d4, 0x62a59106, 0xce9de78b,
+ 0x82182e03, 0x97e75a6f, 0x4a62f5c1, 0x3bd2df51,
+ 0x2c9edb8c, 0x0c457bc3, 0xb9eedd66, 0xdadb756d,
+ 0x5e9e33ea, 0xcd532541, 0x296dd564, 0xd67e7450,
+ 0xcea6df03, 0xab8798b8, 0x272ac204, 0x5f43f31b,
+ 0xe84fe559, 0xfe26bf7a, 0xfe00504b, 0x17e849aa,
+ 0x8fae7d57, 0x3b5d0580, 0x5e0f11ca, 0x03d66007,
+ 0x3eb21080, 0x125196f3, 0x65c24637, 0x1b986ad5,
+ 0x628309d9, 0x83971881, 0xaeeea5e9, 0x552893db,
+ 0x7cbe399d, 0xe4fd478e, 0x3db795f8, 0x092aa958,
+ 0x523fb2e1, 0xa47f99c0, 0x0e3516c5, 0x42dfacc2,
+ 0x5619e0b4, 0x46738297, 0xa9245fad, 0x5fffd06e,
+ 0xafb5ab01, 0xf08fdf29, 0x9abdff9e, 0xeadf7f0e,
+ 0xb5f57798, 0x1cd128da, 0xe6d64296, 0x15f16c59,
+ 0xd7ba399f, 0xf113ff8d, 0x3547b881, 0x74d4236e,
+ 0x679e4f48, 0xcad6fb29, 0x4c54a82d, 0xd19c5b11,
+ 0x7fedbe91, 0x6dbc0a20, 0xf18e9da7, 0xcbee3417,
+ 0xa5611e5d, 0xc4e5cf62, 0x918a88da, 0x12cfdf03,
+ 0xc7d84404, 0x6f80d41b, 0x8b352752, 0xc1af0120,
+ 0xdea03916, 0x597dd900, 0x7ba04f97, 0x4c0e7e49,
+ 0x11c4a446, 0xf4fbb8aa, 0x07bc87cf, 0x264b0e53,
+ 0xf3760292, 0x471b31dd, 0xf36e1742, 0xfbaddcb6,
diff --git a/src/cpu/intel/model_206ax/microcode-M12306A8_00000010.h b/src/cpu/intel/model_206ax/microcode-M12306A8_00000010.h
new file mode 100644
index 0000000..ce80526
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12306A8_00000010.h
@@ -0,0 +1,640 @@
+ 0x00000001, 0x00000010, 0x02202012, 0x000306a8,
+ 0xe44a4ef2, 0x00000001, 0x00000012, 0x000027d0,
+ 0x00002800, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000a1, 0x00020001, 0x00000010,
+ 0x00000000, 0x00000000, 0x20120217, 0x000009e1,
+ 0x00000001, 0x000306a8, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x1b403d49, 0xf16c1064, 0x0f7ffc0f, 0xf6974b9b,
+ 0xc2b9fab8, 0x16333546, 0x1bd94702, 0x61c3363c,
+ 0x5a3401db, 0x42caecce, 0xb4d8e75e, 0xe6dbaf24,
+ 0x7861b35f, 0x6bd717bc, 0x23b9b731, 0x82ec1ac8,
+ 0x20337b64, 0x5396dbf1, 0x59973bff, 0x724bc7e9,
+ 0x5237193b, 0x0b8647c1, 0x6a0d0e16, 0xbf9ddb5b,
+ 0xace2cc1c, 0xad707638, 0x056f102f, 0xa37e60f8,
+ 0x76255642, 0xfb86e030, 0xb8069a40, 0x367795f1,
+ 0x653fb05e, 0xab7f14ad, 0xb6e8a8e1, 0xd2598d20,
+ 0x2eba3f68, 0x78b372f1, 0xba8d13f8, 0x1f1de861,
+ 0x97f951d5, 0x8097c728, 0x27dbf904, 0xb97906a8,
+ 0xffe7a4ac, 0x4b947668, 0xc1dbd726, 0x2adcf777,
+ 0x63b1bcf0, 0x818e2a1b, 0x49aa907b, 0x2faf5e8d,
+ 0xae842352, 0x82707fae, 0x0aa12b41, 0xa0bae11c,
+ 0xb4298c47, 0xd2b4099c, 0x4ff625f2, 0xcd2630d4,
+ 0x79850981, 0x05dbf57d, 0xb05b81a5, 0x56e73ec7,
+ 0x95cb3897, 0xe262bda5, 0xb2c6e288, 0xcb7f8e77,
+ 0x72b8bdd3, 0x3f400494, 0x63ade65b, 0xbc4adc71,
+ 0x00000011, 0x8ed1ffe5, 0x32c0109c, 0x587709ef,
+ 0x3bfb445b, 0x7369bcab, 0x2f3140b0, 0x0aab6762,
+ 0x5536ef35, 0xa70d4c69, 0xdb94af6e, 0x5feb3f29,
+ 0xbf625a22, 0x27dd0e55, 0x70a64d8e, 0x9bd2fc9a,
+ 0xf152ad62, 0xfbc6cddd, 0x6b159e05, 0x91a47294,
+ 0xfbe6d820, 0x2d824170, 0x18c5f95a, 0x2f346c7e,
+ 0x11a313b1, 0x5066c4de, 0x1ca9c891, 0x4dde7c15,
+ 0x5d3d56ec, 0x0e0d4792, 0x8c483c37, 0x848f8af1,
+ 0xada87f75, 0xe79c95f8, 0xc9e3e195, 0x307f3447,
+ 0xa3e4d6fb, 0xe2f2c218, 0x68ebc6b6, 0x3818a8d2,
+ 0xbb6449a4, 0x553d8936, 0x471d410b, 0x15cfdd5a,
+ 0x69425847, 0xb3082c97, 0x00b33509, 0xa7367dec,
+ 0x2338371c, 0xbe267648, 0x64cdfeac, 0x3cc88866,
+ 0xf9016fb9, 0x19976c2b, 0xda55e997, 0x5ab2f3c4,
+ 0x5020f1fc, 0xbec51b96, 0xe4b1eb53, 0xa3ea7ddc,
+ 0x9a81863b, 0x218a497c, 0xb6c19b12, 0x24c3a52a,
+ 0x2080b56f, 0xa8248e0c, 0xcff0c1b7, 0x81752837,
+ 0x11e317f4, 0xcbb8d75f, 0x6ac515e6, 0xa76a6c6a,
+ 0x637dc946, 0xeead71cc, 0x83749b23, 0xf75067ea,
+ 0xc2e7ba17, 0xe1e54dbf, 0xe0a1376c, 0x62c74f31,
+ 0x94fcbf68, 0x5c876940, 0x93a5d360, 0x9534923a,
+ 0x99a8f770, 0x6fdb59c9, 0x740344fd, 0x68f6e40b,
+ 0xe9745bc1, 0xc75fb19e, 0x3959dc04, 0xaf0f2d1c,
+ 0xc978a38c, 0x90aeaa15, 0x71e4532c, 0x7739da2a,
+ 0x3b6d0d75, 0xdd7ce2d3, 0x4cce3ef6, 0x6394bfcb,
+ 0xad6ab2f0, 0x7edcc9ac, 0xeb3121cb, 0xbc14dac2,
+ 0x1977b501, 0xe9191390, 0x256db186, 0x275efe89,
+ 0xcd3531fa, 0x8ecfeb51, 0x0768b391, 0xa187fb6e,
+ 0x9f4805be, 0xc7f66104, 0x59db1d4f, 0x357e7a00,
+ 0x60c3e5dd, 0x20a537f1, 0x12953d15, 0x4099e4eb,
+ 0xb32717b8, 0xda4af0df, 0xd5114850, 0xa1a29261,
+ 0x87d28a41, 0x0f8f2744, 0xcc0fd7c8, 0xca53595d,
+ 0x03aea4ec, 0x86f807b5, 0x6b72a690, 0xb6602cec,
+ 0x233900fe, 0xb22bd58c, 0xbb7b3987, 0x14c598ec,
+ 0x52135028, 0x708d51d5, 0x198a25f3, 0xf4e0e415,
+ 0x182627ae, 0x6fce4e16, 0x9c44b519, 0x2acf1727,
+ 0xcf98eeff, 0x046c8df1, 0x44f7b6ff, 0x50cbd25e,
+ 0x5aa62194, 0xe70b1576, 0xebd98996, 0x5b39cee6,
+ 0x377785a5, 0x0f5a1be5, 0x6657c95c, 0x046f5a36,
+ 0x1b6d8aee, 0xe7a39d21, 0x46490081, 0xf9004fce,
+ 0xd0eb2e85, 0x64b1393a, 0xdd3d8696, 0x696db443,
+ 0x8b134e06, 0xa312c32a, 0x82c0eae7, 0x3f8058b9,
+ 0x0e943831, 0x995d1d4c, 0x02ede949, 0x4e903aeb,
+ 0x82cec214, 0x3e494984, 0xbf6ddd3c, 0x2e59dbdd,
+ 0xca9fe3aa, 0x656e3c16, 0x520e5aee, 0x8c2f8cae,
+ 0x1614fd07, 0xdcd06b40, 0x061c8152, 0x63633118,
+ 0xebd254f9, 0xdc83eca8, 0xe99649e2, 0x5ff42ac9,
+ 0xd0f1735a, 0x8f94b9f5, 0x5f0f96a6, 0x66123def,
+ 0x432bac97, 0xfe72ce20, 0x964f770d, 0x67396529,
+ 0xe65f76ca, 0x7fed0d47, 0x7eb8a942, 0x36fb9c3c,
+ 0xdb5493cd, 0x89a82f0f, 0x715c5eb3, 0x0d1edac3,
+ 0xd0bff985, 0xa194fc1a, 0xd42455f0, 0xef38212b,
+ 0x05b9773c, 0x066ad255, 0x5d043acc, 0x56a505ad,
+ 0xb7f580ef, 0xdee8a63c, 0xe4f90dc4, 0x8add5bdc,
+ 0x9d34e9de, 0xc9cb8e25, 0x0eaf9fa2, 0xb4aa1df4,
+ 0x8b93af47, 0xf11c6a6a, 0x4a2f3d7a, 0x96e7ed11,
+ 0x2257f261, 0x5ea36468, 0xae6fd9b4, 0x22a7c6cd,
+ 0x5d6164ce, 0x52b256ef, 0x0b02890b, 0x4cc21a2a,
+ 0x83322c58, 0x4e274f12, 0xdc8fa5f6, 0x2d267c84,
+ 0x9b7f5131, 0x8449d38c, 0x04720fc6, 0xc17548a9,
+ 0xe6f4ab12, 0x292bddfb, 0xc1a151db, 0xc99e0fb1,
+ 0x3c5d2bc5, 0xc4755ffa, 0xef6f3cb6, 0xe04fcd8c,
+ 0x11ccb674, 0xd9ab3b01, 0x0902c30b, 0xcf7d59b1,
+ 0x76aca5bd, 0x3ad17103, 0x05252567, 0x691308f3,
+ 0x534e7a0d, 0x9f9af825, 0x3fe5d9d0, 0x7d895da2,
+ 0xe0832f82, 0xe6ea0830, 0x20338d42, 0x35d29098,
+ 0x1089c3fe, 0x217ec856, 0x4b597f7f, 0x6a8646df,
+ 0x404ba334, 0x7e268709, 0xd13370b4, 0x405d1f33,
+ 0xc54e5a93, 0x950f48ab, 0xe7d80318, 0x93e6e200,
+ 0x53b018ab, 0xdd06f71c, 0x4958da7d, 0xe3e222b4,
+ 0xf3d05fba, 0xe12cee3a, 0x4711b233, 0xd7c0de5f,
+ 0x89d209d5, 0xf47b1861, 0x847668f7, 0x90bced48,
+ 0x0bcd9d51, 0xeb26f077, 0x70b42ec5, 0x97d44d1d,
+ 0x9c9ca62f, 0x0defcf8f, 0xb3a0d81e, 0x99d11293,
+ 0xbe556b59, 0x568ec6c8, 0x28dca86a, 0x70ec0031,
+ 0xf7ff7b73, 0x141fe540, 0x1faf5b69, 0x406778ad,
+ 0x08b17862, 0xb06f06cd, 0x2cd2f974, 0xf6d6d79d,
+ 0x81d0d8c9, 0xae322fb8, 0xedee7b79, 0xdde84ca3,
+ 0x6ed57ad5, 0x9fc1bea4, 0x6872cce2, 0x645fb8d2,
+ 0x5d83af4f, 0x33396fda, 0xd37c3928, 0x175a0b01,
+ 0xfb4b906d, 0x262bfc26, 0x0c447bdc, 0x165f984e,
+ 0xbe8afb92, 0x777b8dab, 0x4f0006b9, 0x98acbdb0,
+ 0x0b2364ee, 0xf6eb68e7, 0x34a5963c, 0x84a02a4e,
+ 0x4a5c4c5f, 0x4e96ff7b, 0xe3dd4f4b, 0x0b5536fc,
+ 0xbe2002e9, 0xd4c35600, 0x51975965, 0x6512c700,
+ 0xa41e0183, 0x3f11d85b, 0xabc46b61, 0xabfdbbcd,
+ 0xe6bd7a18, 0x59200bcb, 0x944c2424, 0x8bac5ca0,
+ 0xebe4e015, 0x1e7e3de9, 0x086e01d4, 0xe9e14481,
+ 0x2566251c, 0x79431f84, 0x54db2e78, 0x4d67706a,
+ 0xf974e85d, 0x3b425b07, 0xc4ada871, 0xd15e7c3f,
+ 0xb0ff45c0, 0xbf8b4ed9, 0xdc3efff7, 0xb5aad3b1,
+ 0xb5f4787e, 0x640c9f2e, 0x5ae4ef17, 0x4bd12d2a,
+ 0x594eda9e, 0xc789362c, 0xfc5e5ee1, 0x2f1af1f4,
+ 0x0000db0e, 0x69a1aff7, 0x038b5505, 0x69aad61e,
+ 0x62d37481, 0xcc142892, 0x1cc3b1cf, 0xa6abcbe7,
+ 0x7a7da76a, 0x7ba348ea, 0xafa2b723, 0xda02b6c2,
+ 0xeb6a0703, 0xb59e65ef, 0xe633283c, 0x1b52d87d,
+ 0xf38f0ae8, 0xd224afe3, 0x67f0156d, 0x0bb9051c,
+ 0xea106e30, 0x991a5bd4, 0xac855ac6, 0x13daddb4,
+ 0xbe0b2b1f, 0xc1216471, 0x99f5c233, 0x88a6eb0d,
+ 0xc2e14da4, 0x3e83331d, 0x0046453d, 0x55b8cd07,
+ 0x1429b457, 0xd815302b, 0x193189f7, 0x11aa54a7,
+ 0x1cab8bfc, 0xffb3ab6a, 0xba359aeb, 0x24e23394,
+ 0x565f2288, 0x466d37b3, 0x5d220392, 0xf891d5fd,
+ 0x632f45b4, 0x9ccfcbec, 0x287ad060, 0x697b1f02,
+ 0xf5e155c3, 0x4b3fbcda, 0xe825393a, 0x965ec1ff,
+ 0x17f77cd3, 0x300858bd, 0x6cf92795, 0x9b11b191,
+ 0x62af7b52, 0x14cbd8dc, 0xf86effce, 0x7db2647a,
+ 0x42edbcc2, 0x67386962, 0x69781d17, 0xaf02a582,
+ 0x3e4cc898, 0x7ed70d8a, 0xbbc701cb, 0x92393791,
+ 0x81728ed2, 0x36207d48, 0x8cd4981e, 0x746bf560,
+ 0x9d129931, 0xca0562ab, 0xb611c895, 0xbbfb78ce,
+ 0x6ab7f092, 0x7682442a, 0x1a895d97, 0x1754945c,
+ 0x0326ffc2, 0x048a5c04, 0x0c1eb4c8, 0xd6231646,
+ 0xbdb50b64, 0x24eb6f38, 0xdc0bcc5e, 0x05fd561c,
+ 0xa1326b3c, 0x8a2b2dde, 0x3eb2761f, 0x08918cc7,
+ 0x99f8eb5f, 0x72d7553c, 0x03a96a22, 0x1d231649,
+ 0x528c9244, 0x2a93fe7d, 0x680942b4, 0xaafa9719,
+ 0xb1daa3b9, 0x705dec5b, 0x0dba5dcb, 0xbb5240cc,
+ 0x57b526fc, 0x4a044af0, 0x1b1bad83, 0xb0351978,
+ 0x0271fed3, 0x157f0b21, 0x7fe40200, 0xe39d7095,
+ 0x76abcb7c, 0xb1281f70, 0x801815c2, 0xeb7887b8,
+ 0xb0eebf33, 0x2fb59814, 0xbbb59426, 0x532e3385,
+ 0xdf6d3b10, 0x99d910b4, 0xfed28736, 0xd7ecfd92,
+ 0x79417d6c, 0x40fca289, 0xb0a4a2c8, 0xa6a640c1,
+ 0x9805b236, 0xb6056e3c, 0x7bb8672d, 0x1c659bc0,
+ 0xf028d52c, 0xb7382f2e, 0xfba27fee, 0xca5f0784,
+ 0x32cfba98, 0x1554962b, 0x29df19d0, 0x80e9a583,
+ 0xb62283de, 0x9def92f5, 0x4b4abe22, 0x83e86855,
+ 0x3b3995af, 0x28f8b243, 0x94084fe4, 0x1aa9170c,
+ 0x4c1d2746, 0xba08a33e, 0x5fb97a75, 0xfb1e84eb,
+ 0x48f4de86, 0x0a7e6b80, 0xce254170, 0x8d1303b1,
+ 0x0fdc0bc7, 0x6409029b, 0xc326538d, 0xf15c2622,
+ 0x8e15e907, 0xe7f0771b, 0x779a24c4, 0x1797c90e,
+ 0x0f86f991, 0xbf2725a2, 0x0119351c, 0x2377d08d,
+ 0x2a06101b, 0x1b2adb75, 0xc7480f30, 0xc57db4e2,
+ 0x3e87bef9, 0xa6cb78eb, 0x6220a048, 0x344d7ae5,
+ 0x93606d8d, 0xaf48370f, 0x6ad80fea, 0xc5ca57bb,
+ 0xa231ae1a, 0x32678fc6, 0xa2096dfe, 0x5576eca8,
+ 0xe482fb15, 0x022ad60f, 0xc62c71de, 0x8d3f98a6,
+ 0x2316510a, 0x0c140218, 0x61d18288, 0xbef73906,
+ 0xb1c88fca, 0xb07ecc87, 0x4b81d2aa, 0x76697353,
+ 0xd2aac2d6, 0xd678d02a, 0x3785098d, 0x651f9e0d,
+ 0x92d40e06, 0xbd55fe47, 0xd9f9e256, 0xd5c9af7d,
+ 0xfb213b1f, 0xeee981b7, 0x99d86138, 0x9823535e,
+ 0x73348159, 0xc3e8baf0, 0x481c627b, 0x382fe4c6,
+ 0x5ae779a7, 0x1f06fb44, 0xdc994d8e, 0x85981396,
+ 0xc4f10d52, 0x5a3b6a16, 0xc5535f55, 0x65e7f841,
+ 0x2b012276, 0x0cb8266d, 0xee9242ec, 0x01e79281,
+ 0x36ad3368, 0x5a76aca0, 0xb6c69a47, 0xb0de9732,
+ 0x86031993, 0xd8a949f3, 0x818d13ff, 0x30b618ba,
+ 0x0b41f5e8, 0x220ce2bf, 0x5c5033c2, 0x5eb2be40,
+ 0x6d86e9ca, 0xd9cab26e, 0x6e6a83c2, 0xfe20df66,
+ 0xb56eaa8f, 0xdeb4dfb8, 0x1e39e229, 0x37fa254e,
+ 0xea4d899b, 0x0d201062, 0x1ffcbc7e, 0x7950e245,
+ 0x11aa5c3a, 0xb040a745, 0xb8ebaf3b, 0x4c29509e,
+ 0x073250a2, 0x1da9f622, 0x6a4bda04, 0xd35893e8,
+ 0xcccfc85a, 0x21086f8b, 0x1c3e7485, 0x89534bf8,
+ 0x7be16a45, 0xca0715a5, 0x4302cf50, 0x51b80127,
+ 0xd60a0621, 0x34d2b035, 0xc030f24e, 0x088f8a8e,
+ 0xc0491916, 0x990334ff, 0x6ca3afda, 0x22ae33e3,
+ 0xab25beee, 0x2267dbd8, 0x4493a840, 0xecd18496,
+ 0xc5817a35, 0xd4d92168, 0xfb91c7fa, 0x85cb2d4f,
+ 0xa61770b6, 0x884e23d3, 0xa45c9d27, 0x99ba633f,
+ 0xbf2b6221, 0xebf2ca07, 0xab76708b, 0xbdbc4e8e,
+ 0xfb0b0ad1, 0xf95259f5, 0x7a8388f4, 0xfbe6fa8f,
+ 0x1565d771, 0x3037fb44, 0xb7617c7a, 0xdee2d11b,
+ 0xafea928a, 0x51771eb2, 0xe52285b2, 0x73b1d3ed,
+ 0xfd2a8803, 0x71fdb1fa, 0x89d3b8f5, 0x5bba7300,
+ 0xdebdc483, 0x3c30e40a, 0xb9a85c44, 0x777b756b,
+ 0xe903b1fe, 0xbc85d4cc, 0xc210d30a, 0x5c2e19e2,
+ 0x821cec4d, 0xb78619ee, 0xc8802a35, 0x751515a8,
+ 0x8fd2e06f, 0x8f3d1c77, 0xe1871e87, 0x59bcceda,
+ 0xf649cae8, 0x28a026b9, 0x15e5b3a6, 0xa523a2ef,
+ 0x54e3548a, 0x4d5a7e89, 0x4d22b821, 0xecf216d4,
+ 0xbdf0e7cb, 0xea7f44b2, 0x693f799e, 0xad54ef0f,
+ 0x3397b5e8, 0x4a601fcf, 0x90cafcb6, 0x37b68a82,
+ 0x6a1f4d54, 0x08bbf9d3, 0x02503ed3, 0x0209bbf2,
+ 0x9374cbba, 0x50ee498f, 0xfd26b0c8, 0x6a5f8c54,
+ 0x6cc59aa6, 0xfec94830, 0xbe99402f, 0x58b82d5e,
+ 0x4004af86, 0x0c79ad63, 0x6a59212f, 0x0e7778a6,
+ 0x6b02356d, 0xd7ffe560, 0x84eec5d8, 0x5f4a8f0e,
+ 0xab6823b3, 0x776dce06, 0xa7a8f9af, 0x08fe7b9b,
+ 0xd91bc4f1, 0x5ae6975d, 0xd08531ae, 0xe01ca804,
+ 0xf2fa5a51, 0x19ed0bcc, 0x19eda07f, 0xda47d729,
+ 0x426dbeb3, 0xfc91a8ae, 0xf6276359, 0xd7859616,
+ 0xc327c5ae, 0xa5f4d758, 0xfbf0c81e, 0x73ab2151,
+ 0x342d4877, 0x234037b9, 0xb72f3f59, 0x3cd06b80,
+ 0xf92d3d0c, 0x6a6adb48, 0xf03b4e8d, 0x14b6c0f7,
+ 0x2e697742, 0xe8a7d28b, 0x7894ed2c, 0x8f95d0d6,
+ 0x90c5111f, 0x4ea6ee64, 0x81910dfd, 0x317733fe,
+ 0x8bd6e4f2, 0x225e5c5f, 0x16e11bba, 0xd27b9401,
+ 0xf05c6f6e, 0x0b61ed99, 0x91659c1c, 0x32e9b9b5,
+ 0x45f08118, 0x2cd2074a, 0x1a673425, 0xe6b08df9,
+ 0xccedec3e, 0x388ad803, 0x03883f47, 0x294e960e,
+ 0x095186e7, 0xa2e37c06, 0x47a57eb6, 0x118d47c9,
+ 0x80468277, 0x0b874ee4, 0x769f4026, 0xe42563f5,
+ 0x250a8583, 0xe0bd7857, 0xbe9cccec, 0x0c512a2b,
+ 0xe54ffb00, 0x884de4b1, 0x6f7b0125, 0x8ad2076a,
+ 0xdf5932c6, 0x4e533861, 0x8e0965b3, 0xe5c56390,
+ 0x21764545, 0x606da180, 0xa1e6acd8, 0x12568eaf,
+ 0x5a03595a, 0x35ce7e4a, 0xa7ed542b, 0xb6bec35b,
+ 0xfb9db787, 0x56591449, 0xc673abec, 0xc529199d,
+ 0x3e409a8d, 0x620b6762, 0xe1121630, 0x641d6655,
+ 0xcf4246fa, 0x48b695e9, 0x40fc8d67, 0xc970eed4,
+ 0x4a8b149b, 0x0febfe26, 0xa4c1e834, 0xf7abee0e,
+ 0x83cd8531, 0xe85dfd17, 0x607ab40e, 0x1402398b,
+ 0x06263d81, 0xcf8086a9, 0x2c0b32e1, 0x98f2cfb1,
+ 0x204a9555, 0x6f303228, 0x5a5c2e02, 0x30ce8a24,
+ 0xefb8fd12, 0x83d4cca1, 0xa62b7246, 0xa3573938,
+ 0xabdad789, 0x375cea5b, 0x70e6fdef, 0x5c75b51b,
+ 0x5142b3dd, 0x45d9ed97, 0x62c53875, 0xa4d319d2,
+ 0xff0fd17d, 0xca5f75cd, 0x084eb7b6, 0x4b093a95,
+ 0xcc8a5c6d, 0x77a5d617, 0xfacff95c, 0x8f25ef6b,
+ 0x1c167f25, 0x6d59a3ef, 0x1dd0552e, 0x49cecc8a,
+ 0x12766378, 0x40a709b7, 0x6da4409d, 0x9365b7f1,
+ 0x2fb51b94, 0x34e3e872, 0xa9551d73, 0x2611eb28,
+ 0x688b4864, 0x9c60c81b, 0xd331e77a, 0xd8e9d96c,
+ 0xb193f1e3, 0xdc024170, 0xef17c2c9, 0xc6e93473,
+ 0x2cf37b07, 0x51861e11, 0x811bdd0a, 0xe64caa50,
+ 0x651d9358, 0x8d2fc170, 0x6c1458f9, 0x86c23e31,
+ 0x84e96ab6, 0xedc1dfee, 0x26b9f5df, 0x7a76d67c,
+ 0x2a1f9e90, 0x4ace672e, 0xa9170d21, 0xd6a70724,
+ 0x464c45a9, 0x23afb74a, 0x244a4e67, 0x9f49f35d,
+ 0x859dfe87, 0x23b638d5, 0x0a7915d7, 0x24693b5a,
+ 0x89642898, 0xfa54e0d0, 0x4827d5e0, 0x283bbd2c,
+ 0x2b1d24ed, 0x352f52f1, 0x3f6b3f2d, 0xbac4ad18,
+ 0xe47ad8ae, 0x7920e58f, 0x84126fde, 0x70c9e2bc,
+ 0x432e56c3, 0x05727033, 0x7c0baf74, 0xb65b0da9,
+ 0x5c0b85ae, 0x6ebba8bb, 0x0b510538, 0x17d5cc78,
+ 0xfa9a1328, 0x21a3a39a, 0x397c5702, 0x379b33d1,
+ 0x6ab13ac7, 0x6898216d, 0xd10e7fc4, 0x1993673d,
+ 0x8d51a0a6, 0x44f88ebd, 0x76a6706c, 0x5c745e9f,
+ 0xc838ecbb, 0x7e1e5b08, 0x4800c838, 0x9f17eb73,
+ 0xa6dd8e15, 0x0f986b08, 0x5012f5ae, 0x22fb1345,
+ 0x497eb5ab, 0xdeccd541, 0x6e18d847, 0xbafb05c4,
+ 0xc8815898, 0x5c55204c, 0x4e9f71d4, 0x63d824eb,
+ 0x3dce3f16, 0x203208c4, 0x2774d25c, 0xbc3d1bd2,
+ 0xf78afd97, 0x6ab636e9, 0x7f594e02, 0xaa5cd483,
+ 0x8a666ca1, 0xf5cf69d8, 0x57d7b663, 0x1a9480b7,
+ 0xd9f296aa, 0xa86106bc, 0x6b3324e9, 0x17017a58,
+ 0xa3ebd90d, 0x28b90859, 0x6f386d33, 0x36c09d11,
+ 0x61d51e5e, 0x19f3d44a, 0xc11d90cf, 0x78584b15,
+ 0x60c9ae16, 0x43563af1, 0x01e255a7, 0xffb45991,
+ 0x50f83e98, 0x29e9d365, 0xeda210e3, 0x35f08bd5,
+ 0x133655a2, 0x9b581fc5, 0x1c37f368, 0x10ec99ca,
+ 0xc978fcdb, 0xddc5c480, 0xd70fac0f, 0xaf4ba338,
+ 0xb762a6b5, 0x259ae10b, 0xedd7e5fa, 0xb7cebff1,
+ 0x62e161c2, 0xc39049be, 0x6b1d91b8, 0x01877387,
+ 0x04438b9e, 0x551dec6c, 0xe12e3e27, 0x0e2f5a34,
+ 0x0f41fcd5, 0x4408dc25, 0x9a7454ff, 0x64530a2a,
+ 0x151779c8, 0x97fc86e0, 0x1376755f, 0x762be945,
+ 0xa62e8987, 0x3ae4b0e3, 0xb08a647c, 0x4ec5a8a3,
+ 0xeea0e55f, 0x61427aca, 0x79db5d55, 0x632a4f9d,
+ 0x7868f074, 0x980720de, 0xf2e57ad3, 0xc0a6d755,
+ 0x4edcb25f, 0x26d33a5b, 0xf56557b6, 0x70764263,
+ 0xd4c7f546, 0x357e3012, 0x178aa2e8, 0xa62fb39d,
+ 0xddcbdc9a, 0xae4c18c6, 0x2b1978fd, 0x91576d92,
+ 0xe8b403e7, 0x459ee6a5, 0x083b2288, 0x288a3b9e,
+ 0x63a85704, 0x05db372a, 0x0a405391, 0xac148b3b,
+ 0x69e2bf69, 0xbfe4f506, 0xa5af64d4, 0xf3829a2d,
+ 0xdb922a60, 0x918f3387, 0xdd09f267, 0xe6b3e45c,
+ 0x229580e2, 0x1740f9b7, 0x63e8ecc9, 0x89edaeb6,
+ 0x1f898f37, 0x73a9d6ca, 0xf16c6cb9, 0x010ac646,
+ 0xd85984b8, 0x79373efe, 0xcea11305, 0xddf200f4,
+ 0xeccb238f, 0xe511b52f, 0x4fe080ec, 0x878420db,
+ 0x81d314d3, 0x848b5ded, 0xb757a66d, 0xbdd01bcb,
+ 0x1efce9c4, 0x6527ae2d, 0xa0b0d3a6, 0x6ba2faa1,
+ 0x61f5f27c, 0x32e0524d, 0x52f1ee1b, 0x41059595,
+ 0xbe3d8cf1, 0x18085d49, 0x2ca2c542, 0x358e8859,
+ 0xee5cdded, 0x9e6bd8af, 0x027ee4ae, 0xedeabe23,
+ 0xecced6b9, 0x29ecedbe, 0x1ce532ac, 0xe397c104,
+ 0xd135a120, 0xa54814b1, 0x14ae8434, 0x59b33404,
+ 0xc8c23eef, 0x9002e9cc, 0x89b795c6, 0x1fb7a8d3,
+ 0x21d67258, 0x96612b72, 0x79d416b6, 0xd8668aab,
+ 0x12e1e7d2, 0x31953412, 0xd34a3efc, 0x87ddccb2,
+ 0x51bda328, 0xede2163b, 0xe878cef8, 0x861a7320,
+ 0xfc9b715e, 0x9aa47c2d, 0x3f2d99a3, 0x17f351e5,
+ 0x4c633268, 0x224deb7d, 0xf4c80b7c, 0x82575a27,
+ 0x0f33dd3f, 0x4d4c8d13, 0x8d7e15a4, 0xbeb9f234,
+ 0xac2bf51b, 0x283b81b9, 0x35fa9d51, 0xa58ce501,
+ 0xd87736bc, 0xd5c99c93, 0xddcf1559, 0xfade7cb9,
+ 0x7f65151d, 0x16f0721e, 0x77462cfd, 0x5f1497bc,
+ 0x7d9f07ab, 0x72595eed, 0x780e191e, 0xae31129a,
+ 0x0b09d91e, 0xe4cd5c89, 0xe6b037a9, 0x7158ff60,
+ 0x2b394758, 0xb2175e78, 0xfd129bd8, 0xeac7b5a0,
+ 0x6312d772, 0x7ea2119f, 0xae09544e, 0xfaedf2b5,
+ 0x8a949887, 0xe3742e45, 0x075fc968, 0x0d43f6c4,
+ 0xc4c2466c, 0x4ba7af2f, 0x3cc5446a, 0xc2e87cdf,
+ 0x3568c951, 0x22059762, 0x27fe9c91, 0x4ec94958,
+ 0x0948b4bf, 0x2ee1ddb7, 0xcd669f99, 0x5447070c,
+ 0xbcc04a8f, 0xd59f2f65, 0x3c61b752, 0xc53548e0,
+ 0xa5347af1, 0xfd8e21e2, 0x6ea18c85, 0x6bc0ea47,
+ 0x406af654, 0x6680a87e, 0x4594eb83, 0x3736d113,
+ 0xff75ebfa, 0xc283a0c9, 0x30fdc02c, 0x4ad413f5,
+ 0x1168b9f6, 0xa6a74149, 0x109a81c1, 0x0a203996,
+ 0xad96b12c, 0x2c351783, 0x31290cf1, 0x26a313e7,
+ 0x2d79aa22, 0xccb4efa1, 0xd3536b7c, 0x927dc8b6,
+ 0x81642186, 0x63715a7f, 0x31a1462e, 0xf88df170,
+ 0xfd4e9618, 0xe8f76cb5, 0x601934e7, 0xe703c7ee,
+ 0xb3121c92, 0xd7ab4739, 0x3a5a8781, 0xa1e2cc74,
+ 0x1b4664a1, 0xa3bf6d4c, 0xa38a918d, 0x333af7fe,
+ 0x8796e366, 0xb4d964b4, 0x36862242, 0xfb03e488,
+ 0x57ae22ac, 0x1b2917e0, 0x095ba4f3, 0x77225ce3,
+ 0x95a615e3, 0x3a405d3f, 0x540344ed, 0xcf0fb4f7,
+ 0x7dd639f5, 0x54920f80, 0x1f974d25, 0x5a2b925a,
+ 0x96d1040b, 0xc4c86188, 0x326406f1, 0xa9cc6593,
+ 0x7c3acdca, 0xdc0dc158, 0x03a211d4, 0xb6a8cd3a,
+ 0xd396387c, 0x8041c158, 0x0abb174f, 0x3d5d53cb,
+ 0x6ae0ae00, 0xe4e814a0, 0xbeae7023, 0x0d89b28d,
+ 0x941f1032, 0x4e36e593, 0x1b7d9420, 0xba4641d1,
+ 0x1ce691c4, 0x425a0353, 0x79e8358d, 0x6b308b9a,
+ 0xbc82e1ee, 0xfddc2391, 0x9772070e, 0xa55de228,
+ 0x75f35f16, 0x9a7f5ac9, 0xc74328c3, 0x15f624d2,
+ 0x3b8bad64, 0x9603a99d, 0x0e6331a2, 0x0d6a8071,
+ 0xd6452f4e, 0xbe4b4421, 0x6af26b98, 0x2f0d09d9,
+ 0x5857e60e, 0x61568954, 0x233f2e07, 0xaf50e307,
+ 0x703295e3, 0xb9cfc0a7, 0x83cbce02, 0x384ff1c3,
+ 0x0bcbd690, 0xd36f3716, 0x261d9c35, 0xe746d986,
+ 0x4df8db91, 0x49b3a981, 0x26f83690, 0x03d63279,
+ 0x94df7e92, 0x038dbc18, 0x4185674d, 0x35e6ad17,
+ 0xf981bb19, 0xf345f071, 0xad25bdf4, 0x380676a5,
+ 0x8e6856e7, 0x3c9db238, 0x0c4630fb, 0xd6c48ac6,
+ 0x94723706, 0x7672325a, 0x684a8b77, 0x7274fa4f,
+ 0xe6569c06, 0x8a4933e9, 0x9b0804ef, 0x03330a78,
+ 0xb3e1b166, 0x2337391c, 0x11346ba8, 0x687276ec,
+ 0x538d7fb9, 0x10d9b0cc, 0x4dbd11b0, 0xaabf12ee,
+ 0x0bf8ee48, 0x362e140a, 0x109f8f7f, 0xde2986c7,
+ 0x02f2fb3e, 0xe3160753, 0x25a50bd1, 0x807e9654,
+ 0x057c6b4c, 0x7a6eb29f, 0xc5d9a9a4, 0x3ecba6bb,
+ 0x9cb18e85, 0x0344940d, 0x708c7b90, 0xd8375fcb,
+ 0x36151be9, 0xf1e34368, 0xb4abafc8, 0xe9d90485,
+ 0xc2f61317, 0xc2eb0f53, 0x2a8620b6, 0x50ede275,
+ 0x07371694, 0x8204ea66, 0xb78b70f1, 0x757067f0,
+ 0x1ffeafee, 0xa2306368, 0xe5eadfb8, 0xc28ee5c6,
+ 0xb5620fcb, 0x6fd00771, 0xaf36ce1b, 0x9fbf999d,
+ 0xa20999e7, 0x0a5ea119, 0xf563a582, 0x06fb985c,
+ 0x29534d59, 0xe7fb575e, 0x06bb9bff, 0x40bed6ab,
+ 0x5c22ef4e, 0xb662605f, 0x56c6612b, 0x7709f0b2,
+ 0x3d99f203, 0xc9954f0b, 0x0177d29a, 0x787d232e,
+ 0x210c0a3d, 0xfd4ee781, 0x00da0579, 0x61df5388,
+ 0x29156932, 0x4ad5141e, 0x69a504cc, 0xdbde5849,
+ 0xaa2b4836, 0x838aabc1, 0x678c3aca, 0xd05f37fc,
+ 0x079c38c4, 0x6a673153, 0x252d7bdd, 0xaf4e523e,
+ 0x442cd80e, 0x4ee8da68, 0x6b0341d1, 0x065e1da2,
+ 0x25fe25f5, 0xbf3241b7, 0x3f014040, 0x4f88928e,
+ 0xfeb7fd97, 0xc953054c, 0xf5758a32, 0xa3d45bce,
+ 0x0f450249, 0x77954633, 0xcd3a074e, 0x913cd9d6,
+ 0x4d24b7fd, 0x9c426986, 0x90164c9b, 0x1aecccaa,
+ 0xe2e81ccd, 0x1db0b130, 0x08ff97de, 0x5cbe5455,
+ 0x2ce36ab7, 0x1ee784e9, 0x899fb86f, 0x9b89511d,
+ 0x053e1673, 0xff210754, 0x033d2639, 0x5c361df5,
+ 0x337a95d9, 0xd135bb80, 0xe5a2f8f3, 0xd35239d4,
+ 0xcfbb987c, 0xddfb29db, 0x42efff26, 0x0ce3fb52,
+ 0xafcbc601, 0xa85fb67b, 0x50540153, 0x470a92ae,
+ 0x5720bb24, 0xa93e677c, 0x7dbd2d60, 0x4b9992eb,
+ 0xc0c81b82, 0x188bec4f, 0xf01c36f1, 0x4294e9b5,
+ 0x2cb9a37e, 0xc8b03e84, 0xa5c63116, 0x7c4fbe38,
+ 0x0525cbae, 0x99577296, 0xd6b16604, 0x3d6cc3db,
+ 0x1d98f615, 0xc5c8522e, 0x3aeb8134, 0x7d628433,
+ 0x95cf53ea, 0x97ec7df7, 0xc77b8966, 0xd1a15401,
+ 0x4664c21e, 0xeded479a, 0x4822da2c, 0xc198bb96,
+ 0x8ad2d4e3, 0x0c3c5311, 0x3d58ea9b, 0xf58051fe,
+ 0xdb0c1886, 0xb2b167f0, 0xde971158, 0x1dbfc236,
+ 0x3802142d, 0x893f6d64, 0xcb1a4a4b, 0xcd0c5335,
+ 0xd48773e8, 0x9093f2b2, 0x59f4cdf9, 0x02182dae,
+ 0x1d78d610, 0x030a689a, 0x5c5ff561, 0xdecd1261,
+ 0x3aa1ae39, 0x7dc58609, 0x81ee7412, 0xb00229fc,
+ 0x415d0312, 0xdfbd3c4d, 0x36611f2f, 0x37e91411,
+ 0x2085572b, 0x11589fdf, 0xf9e04555, 0x5b020432,
+ 0x5aef16d9, 0x368c5efb, 0x3eb9a776, 0xcc81a840,
+ 0x744531ed, 0xcae9fe81, 0x2741665e, 0xdcfe6725,
+ 0x4545c2cc, 0x333cd69b, 0x2a5d87dc, 0xcbaf91a9,
+ 0x4c48fbcf, 0x1b206188, 0x7cfe676a, 0xba7cdafc,
+ 0x8e824a1f, 0x5bde2471, 0x1fe8b793, 0xb616b31f,
+ 0x0b42b7b3, 0xdededee8, 0x0a3a2a5f, 0xba4093f8,
+ 0x525d154c, 0x4dd07872, 0xa3f445a2, 0xfbf0fc5d,
+ 0x1347dc1a, 0xfe7753b8, 0x968a1335, 0x0056ac5f,
+ 0x388dcfde, 0xfb1f4cdb, 0x9e4607db, 0x0820af26,
+ 0x051c5371, 0x1095264f, 0x60002a33, 0xf2df08cb,
+ 0xdbb1ea48, 0x0765a888, 0x01056ddf, 0xca2c2036,
+ 0x0ff34cef, 0x2d66bb9a, 0xedf0d73e, 0x6bf2bc43,
+ 0xaf889ffd, 0xffabb752, 0x0204d224, 0x6d24bc8d,
+ 0xa4520453, 0xe214374b, 0x629ed991, 0x836ce84b,
+ 0x7636a7cf, 0xf1c94c81, 0xc75ea049, 0x53e875ea,
+ 0x59e4fab2, 0x6dbf49e0, 0x8fd7f995, 0x6fa712b5,
+ 0x77b53f76, 0xc3554d12, 0x280e0877, 0x72246789,
+ 0x378257ce, 0x73d359cf, 0x2d5ea417, 0x82c4d3aa,
+ 0x24101650, 0xe7adc8bd, 0xe074e4e9, 0x081fdb30,
+ 0xba5f593e, 0x43e3da0b, 0x82befd35, 0x12261903,
+ 0xcc73ba61, 0x3316f440, 0xcad9e1a9, 0x9922b74a,
+ 0xa8ca9b4e, 0x3b9dc087, 0x24e6a2d5, 0x04b031fe,
+ 0xafac80e0, 0x9fb52cf5, 0x8997d60e, 0x50ae7abc,
+ 0xc90d7d09, 0x5a8350b2, 0x622b4dac, 0xab75d772,
+ 0xad99ed29, 0x1f1594da, 0x71aa2ad1, 0x8511c0d5,
+ 0x880b1db5, 0x2d6f9d0c, 0xc59483a4, 0x7ed5b2db,
+ 0x0ad7e43a, 0xd7d3add6, 0x51c23d4b, 0x1fbed1af,
+ 0x0a7d6890, 0x857da084, 0x6bca8ee7, 0xa86af668,
+ 0xeea3646b, 0x34e3a044, 0x1b798580, 0x93988bcc,
+ 0x3cf50e60, 0xa769cba4, 0x12e3309d, 0x16eb2811,
+ 0x44ce514d, 0x36072ddc, 0x7f5b60df, 0xb3834b85,
+ 0xe78ee22e, 0xb389c816, 0x0fce5025, 0xa34eff4c,
+ 0x23a1b542, 0x1c3c7736, 0x328d35de, 0xa5643a06,
+ 0x503107ca, 0x6dad558e, 0x44e08e35, 0x2107fb1a,
+ 0x62103e9a, 0xafa6ba2b, 0x349c6729, 0x7d3a077e,
+ 0x61648e3d, 0xbefc4681, 0x45aec9bf, 0x8c8e3e89,
+ 0x8c50f506, 0x7ac24dad, 0xc124b58e, 0x8a6e9d08,
+ 0x20448106, 0xa0e695f1, 0xb151965b, 0x7a73557f,
+ 0xb1b33ff2, 0xc0100a27, 0xf6add1c6, 0xd17eef16,
+ 0xb7923446, 0x36771aa7, 0xf25f68c8, 0xadbcee46,
+ 0x99c28944, 0xcda56ec4, 0x887ca30b, 0xe14b748e,
+ 0x5f312beb, 0xee80c1b3, 0x403e83ab, 0xa2d82322,
+ 0x02ba184e, 0x59550b83, 0xe5c300c1, 0xcda4bc89,
+ 0x896b6443, 0x310f4da9, 0x8faa7d51, 0x023863f0,
+ 0x86982d5f, 0x913e6f47, 0xc90ea280, 0x97960365,
+ 0xc021c058, 0x86c0ad06, 0xdc6d7a9a, 0xe98bd4ed,
+ 0xec3d3885, 0xf4a0deb5, 0xa338b4d3, 0x8867ef20,
+ 0x29f43403, 0x55be8fc9, 0x248fa311, 0x380f0f02,
+ 0x0f4e6b1d, 0x26af994a, 0xcad8f11a, 0x92b4610f,
+ 0xb839f02d, 0xd99ddbc8, 0x42148c97, 0x5af73ad4,
+ 0x1a10a9ab, 0x7d8b7747, 0xad6ca358, 0x6725062b,
+ 0x2e83681b, 0xd3af30e7, 0xdfac83d0, 0x18c8ee4b,
+ 0x38135ee1, 0x6c9a4b13, 0x745fa6e5, 0xed4dd682,
+ 0xe0c92e55, 0xde5aff36, 0xce84ec0e, 0x217bf7df,
+ 0xb47b33c2, 0x93c338b0, 0x87a46186, 0x8ebd471c,
+ 0x0e336416, 0x4edf9347, 0x7b359cba, 0xa9f2ecbc,
+ 0x424a48f8, 0x4163e289, 0x2042a8de, 0x02ff7371,
+ 0x1be091f0, 0x059178d1, 0xa3a77688, 0xc1989324,
+ 0x2865a935, 0x55d59c2c, 0xbb26908f, 0xe7df8346,
+ 0x0e2c320d, 0xc2addecf, 0x7a656d2e, 0xad7f4f21,
+ 0x96eb6f1a, 0x8449f270, 0x9b912e1e, 0x2c419a70,
+ 0xe020087c, 0xe0a27243, 0x7bca5f3a, 0x9286097e,
+ 0x6adbdadc, 0xceaebb83, 0xe74e7bcf, 0x5ceb5da1,
+ 0x50d85c0a, 0x92264376, 0x7ae833d6, 0x756b103b,
+ 0x5d671ffb, 0x535dd7e2, 0x9e8125e5, 0x94c79e63,
+ 0x1ece3faf, 0xfac2f731, 0x9aed2ef6, 0xe4cb81a5,
+ 0x0939fddc, 0x0a243b68, 0x5291605e, 0x2ce511c0,
+ 0x9609b4e2, 0x82c5a9d4, 0x6eb1f134, 0x19c2fc67,
+ 0x654b5558, 0xeeff82ee, 0x26234d57, 0xf12df7b3,
+ 0x0b745fe7, 0x1b278120, 0xca9c0321, 0xd95e4f27,
+ 0xf1160ead, 0xa88c9592, 0x6ff39abc, 0xc0810dde,
+ 0x6990548e, 0xf95f677b, 0x4acd69c4, 0xfe86927e,
+ 0x745995ad, 0x9ff5da5d, 0xc3e344b4, 0x41dac048,
+ 0x91604908, 0x2e3e0813, 0xe7c069d7, 0xacc1c912,
+ 0x72af0ead, 0x0edcb49f, 0x9fec8dba, 0xb1b8eb92,
+ 0x53b9cf17, 0x08a61abd, 0xe08b48a7, 0x99020207,
+ 0xed400e68, 0x84b31e8a, 0x7e047e33, 0x88618ea6,
+ 0x28eb6380, 0x335341c3, 0x9948744f, 0xd1f1555c,
+ 0xe3d1718f, 0x1121a006, 0xc0ce8e25, 0xc5abd11f,
+ 0x66ddc911, 0xd5d7daa4, 0xfcecaeed, 0x782d171b,
+ 0xf33c430f, 0x8ea1c843, 0x5a2faf64, 0x14423708,
+ 0x1e21d21b, 0x3441d442, 0xb77b5bd4, 0x8e1a987f,
+ 0xbb8ca78c, 0xd6e4f1e2, 0x9a235eb7, 0x4706be43,
+ 0x0e4e4a37, 0x2559bbd9, 0x828515cf, 0x3f2029f2,
+ 0x27fbb870, 0x77b645a2, 0x26d5d8d2, 0x10952a19,
+ 0xed4fa283, 0x4b6e80db, 0x62de67d6, 0x259c1179,
+ 0x8464a228, 0x47569f25, 0x37386538, 0x63420827,
+ 0xada11d29, 0x2d9d6208, 0x6f2545c6, 0xbcfe5b5f,
+ 0x540a2c1c, 0xd53491d2, 0x1c445feb, 0x22b9ca4d,
+ 0x7502bd96, 0xf4c4e79c, 0xcf3e4ce7, 0x4abf7e4d,
+ 0x878cb9cc, 0x3d538740, 0x51d5c94b, 0x9fb4d91d,
+ 0xf8820147, 0x664376e5, 0xf4bbbc5c, 0x20cde3a6,
+ 0xb1faee0b, 0x2997e271, 0xad9d3e02, 0x306f81c2,
+ 0x9c20178c, 0xf79e57db, 0x828af3c2, 0x229d2181,
+ 0x3aaceaa7, 0x32e6b551, 0xfa3cd28c, 0x51a7141c,
+ 0x652e944e, 0xa03bc7a8, 0xd7b649f9, 0xf1c28fe7,
+ 0x854a9789, 0x57b05eed, 0xb69be3de, 0xab0c8ced,
+ 0x096c522a, 0x4009e6cf, 0x5e0c610d, 0xee994848,
+ 0x09c5d492, 0x5029823d, 0xfc1bc29c, 0x03bf3586,
+ 0x1d72a9ac, 0x87db4a65, 0x22ee4296, 0xfd682d29,
+ 0x25235455, 0xddb31b51, 0xc3d7b30d, 0x34fd9c21,
+ 0xee44b970, 0xbfb3969a, 0x32bd7d7c, 0x377e2347,
+ 0x05642393, 0xa06768c1, 0x59907071, 0x3c2b606a,
+ 0x0442c4e0, 0xac10c021, 0xb2b71411, 0xdc944099,
+ 0x66fae366, 0xfa8abb6a, 0x46c2d13d, 0xc9d1351f,
+ 0xbd6a38d6, 0xef921e5a, 0x92e71482, 0x7b724217,
+ 0xb82457ea, 0x6c8717d1, 0x36e6ea8a, 0x0b9639c3,
+ 0x1d1591b4, 0xa317dc1c, 0x56b583e5, 0x6b552739,
+ 0x9e2cb656, 0xd3ad90da, 0x8fa0402c, 0x8a9262b0,
+ 0x6efbb731, 0x7ef631a0, 0x6405c99a, 0x1e79a409,
+ 0x8ca97586, 0x71dad014, 0xa7130e9c, 0x0d41d7fa,
+ 0xb3b9eadf, 0x758c798f, 0x5ae65923, 0x4e076c66,
+ 0xb959a579, 0xfc6c7a29, 0x25d7809b, 0xdf801923,
+ 0x8241ba5a, 0xed30896b, 0xbfb3d6fa, 0x9393b903,
+ 0x9bb1e72c, 0xf47120d1, 0x04022d4c, 0xe93f8354,
+ 0x33048d1c, 0x24972eb3, 0xbf73a202, 0x5a9d2ac5,
+ 0xa61faa62, 0xad34ca68, 0x914cc91a, 0x8de59417,
+ 0xef9146a7, 0xd3c1220e, 0x3f92be66, 0x452c6f6f,
+ 0xa479ce15, 0x409c8c3b, 0xf9f21fa1, 0x8a0e8fb1,
+ 0xe863071e, 0x972e47ab, 0xc7b911d0, 0x7ed74c7f,
+ 0x081b2960, 0xdb4647fc, 0x2fcb0111, 0x3ee02771,
+ 0x5484dd39, 0x9be0189e, 0xba719c44, 0x226510c1,
+ 0x3bc538ee, 0xa1f2308e, 0x98c3a530, 0x23c6e9bd,
+ 0x7810ff49, 0x91003636, 0x997c792b, 0x5af23f55,
+ 0xe2743106, 0x64b05fcd, 0x03c0f1ba, 0x60a0bbbb,
+ 0x4ad57b9e, 0x4c94bbe3, 0xa46c58a7, 0x06a78645,
+ 0x123ed45b, 0x58b23991, 0x3eb26259, 0xb89907b2,
+ 0x219aef23, 0x56a105b5, 0xaed151ed, 0x20eddc82,
+ 0x1540d1fe, 0x53e10de5, 0x01e21dcb, 0x56714020,
+ 0x9f8c6c6e, 0xf7f0334e, 0xea0610b6, 0x2dcabc81,
+ 0x9546d98f, 0xc7e56f57, 0xdbf24f07, 0xf4cc07d7,
+ 0xca031558, 0x1bc7c1fc, 0x0518c2cf, 0xa85182cb,
+ 0x9a1b3669, 0xbe2bec14, 0xf6d3f32d, 0x8160e6a5,
+ 0x230bc7c5, 0x8b02fa5d, 0xfa8f3322, 0x8a163219,
+ 0x71eda011, 0x17d776f6, 0xd7483b82, 0x7ec32be0,
+ 0xac4c62fc, 0xde5a7903, 0x49f15f84, 0xd47e655b,
+ 0x2e4a43be, 0xdeaf778a, 0x9db31536, 0xd90072ba,
+ 0x41454e67, 0x651cf912, 0xabb64c69, 0x4681e722,
+ 0x6141578f, 0x6850f358, 0x436f5bce, 0x1ef2f0d1,
+ 0x353de71b, 0x3fd02d7b, 0x8749bf39, 0x8b0aa0d9,
+ 0x045028a1, 0x1e87b664, 0xaf7773ee, 0xc839d251,
+ 0x4e1a5254, 0x191f66cb, 0xa8c36df2, 0xa3cd7287,
+ 0xa97f822c, 0x6ff7f816, 0x897ae21d, 0x70a0b4f8,
+ 0xb44342ab, 0x0302912c, 0xad63c61f, 0xa3c210e3,
+ 0x0d007694, 0x1369e611, 0xa8426d34, 0x81fd13a5,
+ 0x0f0d26fc, 0x5a99c754, 0xbc858522, 0xb0dbc0ef,
+ 0xa49c99b9, 0xc29efc7d, 0xe4bd5615, 0x3fb84927,
+ 0x31a83d75, 0x405b415d, 0xe4eb3d76, 0xdfd4a294,
+ 0x070756cc, 0x8ddea308, 0x97099f7d, 0x5e55ffe3,
+ 0x3151d0a8, 0x9c1e5ac7, 0x91df96d6, 0xa7513563,
+ 0x8029ad7e, 0xb9108b6c, 0x58f7972b, 0x8f0485a7,
+ 0xdca04b74, 0x2d3450d3, 0xaaccbd6d, 0x24e2a510,
+ 0x6d176309, 0x5c32a471, 0xa5ecbfa9, 0x160bc973,
+ 0x7762485f, 0x5a5297c8, 0x4d23a857, 0xeb3ea778,
+ 0x4e604026, 0xd9ef9815, 0x08b45c13, 0xd3d66b48,
+ 0x1bab98ef, 0x4c74e20c, 0x5d0e696a, 0xf13a5ea6,
+ 0x9df66352, 0x4eb1fe10, 0x3ad957d8, 0x4629d594,
+ 0x562f1652, 0x7d0b2ae7, 0x237b7d3e, 0x63b6f4df,
+ 0x0501adcb, 0x29da8648, 0xd021557d, 0xb6d77aa3,
+ 0x689ae7e4, 0x15c76c4c, 0x876a74bb, 0xa22a220a,
+ 0x5164f2cf, 0x1a1db5e5, 0x8d6586d7, 0xdc8ddc0e,
+ 0x591ba995, 0xd70d7b2b, 0xa83c00c4, 0x4b570ea9,
+ 0xc5b6d1f6, 0xaafc8008, 0x31fd31da, 0x99302c5e,
+ 0x01f89c9e, 0xb4479306, 0xcc5b2166, 0xccd99886,
+ 0xceb7535d, 0x25300a3b, 0x98a56517, 0x294f1fba,
+ 0x4a7b01a6, 0x22bbb61d, 0xaf3cb6d9, 0x01261e53,
+ 0x9b81fa24, 0xa291b08a, 0x6ab9c3bb, 0x1d064e6d,
+ 0x3a1d7b5f, 0x2529fc13, 0x069a4b56, 0x907a0d2b,
+ 0xc7103a93, 0x8ae3a58a, 0x54b2799b, 0xc2c34494,
+ 0x2d2137d7, 0xdf743fb1, 0xc1f89371, 0xde425fa9,
+ 0xde395a6c, 0xb03e26f1, 0xea22c357, 0xe7f79c82,
+ 0x2e8ac5f8, 0x3aad0824, 0xb7a25fe0, 0x32211cf6,
+ 0x02b1bc47, 0xb34e7f16, 0x9aa49c6a, 0x3964c703,
+ 0xcc64fa69, 0xb1ea15d7, 0x58ffb926, 0x62d3a065,
+ 0x7ed38e16, 0x52374f1c, 0xded4e7d4, 0x5d86e726,
+ 0x8657d2fb, 0xc6e57b34, 0x32ff10b6, 0x0f72e6da,
+ 0x08f61fa0, 0x6634094a, 0x2b18ce7d, 0x1eccb35e,
+ 0xb442d5ad, 0xb208f3ff, 0xfbf2ea9d, 0xac9bfad6,
+ 0xb929177f, 0x2c19ae54, 0x37e3e885, 0xfc4b0f84,
+ 0xd1936956, 0x63aff22c, 0x7bbf6cf8, 0xa14a8ea7,
+ 0xdc6a8011, 0x3d0f0706, 0x24c733a8, 0x88f0fe3f,
+ 0x93bffe78, 0x38aef62c, 0x67884d8c, 0x45285a48,
+ 0xef5d3a00, 0x55b1d1e8, 0xa85c67cb, 0x75ec4fcf,
+ 0x9831feb7, 0x9008daf5, 0xb499159f, 0x4ea352b9,
+ 0x51c11b7f, 0xbb7b2e36, 0xa0073506, 0xe45dc699,
+ 0xb30e13d5, 0x0bee1386, 0x87896afd, 0x325ac801,
+ 0xcea825ed, 0x4d11813e, 0xbed0963f, 0x122989fa,
+ 0x943dabb8, 0x09a9107f, 0x7ebd0ee2, 0xb700e930,
+ 0x17d1b005, 0x99e53e42, 0xd3ac9dd0, 0x38eb85d3,
+ 0xee9e83a0, 0x0cf8294f, 0x6e3d257f, 0x727a75bc,
+ 0x5c616c32, 0xe2c8e043, 0x93157721, 0x72601ea7,
+ 0x09b155f3, 0x192285f2, 0xb6b76a9a, 0xad391c9b,
+ 0x2f94db2e, 0x784e2351, 0x024be4bb, 0x6a447890,
+ 0x317bf91f, 0x977296b2, 0xac67125f, 0x29d0ccf8,
+ 0xa2cb6c84, 0x97822a3a, 0xae1e0cf6, 0x67a4b7d8,
+ 0x1f2f7e51, 0x657808e0, 0xa42f952a, 0x8d3d9675,
+ 0x8847b11b, 0xb3ed7513, 0xf7031394, 0xc9a93867,
+ 0x0295c9e3, 0xecb5425f, 0xd33933b5, 0xac6c8965,
+ 0x2326998d, 0xc1fd098b, 0x6414e747, 0xfb3397c0,
+ 0xfefb8cfa, 0x7da58b89, 0x47a24ce7, 0x9f1fc24f,
+ 0x9ae380c8, 0xb7b53a97, 0xd68a6278, 0xa0e26f8a,
+ 0x89a1a592, 0x75f46f7a, 0x101db87d, 0x09eade81,
+ 0xfd44ffa4, 0x3e386e05, 0x4c7bd47c, 0x01a48221,
+ 0x01cec4d0, 0x653631eb, 0x074ebb8b, 0x644a4dbb,
+ 0xcb41fe15, 0xce67a253, 0x7caee48e, 0x30866701,
+ 0xaf7d47da, 0xb44de77e, 0x8b22e9f6, 0xef7ac506,
+ 0x808e9c5b, 0x1b61051e, 0x07276826, 0x1a591171,
+ 0x3bcb4676, 0x17d1f220, 0xa944ae4d, 0xda715839,
+ 0x2c17e654, 0x710fb94a, 0x36952065, 0x857cb5b3,
+ 0x0b0bd111, 0x5602e5c9, 0x5a1f5247, 0x2f011644,
+ 0xb642806d, 0xfa424545, 0xa3fef077, 0x273a98ce,
+ 0x4e4af740, 0x76d4c2ab, 0x7d646acd, 0x363363ca,
+ 0x67a47feb, 0x5f42144b, 0x15aeabd7, 0x062365b9,
+ 0x983a0b99, 0x3af5e603, 0x3cecf3a5, 0x3f950cb4,
+ 0x0a47d85c, 0x01da93bf, 0x282ea589, 0x42bd8459,
+ 0x953ed9e9, 0xbf7bb6a3, 0xcff79f09, 0x8600b807,
+ 0xcbf1cd20, 0x2edbbbcf, 0x3da50deb, 0x362fb833,
+ 0xca9afb28, 0xb7b53b01, 0xeaefbfcf, 0xd100447f,
+ 0x8f10add3, 0xf35625e3, 0x417ee7a9, 0x38539592,
+ 0x6326103d, 0x3fe9bd63, 0xc464b4bb, 0x7ff21fcc,
+ 0x3bd86879, 0x2db532ca, 0xff02411d, 0x95d6cf84,
+ 0xd3a60383, 0x69baf8c6, 0xefd478dd, 0xaf95b198,
+ 0x152af950, 0x03c56620, 0x97152861, 0xb797015d,
+ 0xbef0e659, 0xd63d4202, 0xaf274d9b, 0x5d75a0b2,
+ 0x4eebf272, 0x19a85adb, 0x822eb4dd, 0x2a718896,
+ 0x84e330b4, 0x39e48464, 0x178df644, 0x82635c19,
+ 0xb12deedd, 0x182eafd9, 0xd630bd7f, 0xdb23c22a,
+ 0x09d83b0d, 0x302598ec, 0x3fd1411a, 0xa84928ef,
+ 0x2130239c, 0x9ca274c0, 0x8ff2b8e7, 0x7ff4add0,
+ 0x0df7cd23, 0x5de89567, 0xead66811, 0xc7b48b3c,
+ 0xc9001dad, 0xd0b5eef3, 0x8209952f, 0x57debb9f,
+ 0x933a73dc, 0xeb2b3eb2, 0xaf34bb7d, 0xff3c32f1,
+ 0xbca9c9f6, 0xa60099f6, 0x0bab4794, 0xfa553ef0,
+ 0x9b471628, 0x7e507e48, 0xfb874049, 0xefd10106,
+ 0x1065c827, 0x1a69146a, 0xde8688b7, 0x848c9ee8,
+ 0x3c07cdf2, 0x704b1409, 0xa52722a8, 0x2888f882,
+ 0x0ae1f771, 0xb6462b6c, 0x7dfe13f8, 0x02266df7,
+ 0x43554d04, 0x766a1b9e, 0xb5d77a96, 0xa7b003e8,
+ 0xd93de001, 0xd8945c6d, 0xc8572311, 0x12fe0b8e,
+ 0x61748ccc, 0x62c5c1fb, 0x6c883898, 0xa7466ca1,
+ 0xad310602, 0xff29fb70, 0x95175f5f, 0xe862a707,
+ 0x2baa6734, 0xd7d196d3, 0x4caf2aa1, 0x6b3bc1d3,
+ 0xddd758f1, 0x7a31b117, 0x1da947d8, 0x8eab1276,
diff --git a/src/cpu/intel/model_206ax/microcode-M12306A9_00000012.h b/src/cpu/intel/model_206ax/microcode-M12306A9_00000012.h
new file mode 100644
index 0000000..c03f635
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12306A9_00000012.h
@@ -0,0 +1,704 @@
+ 0x00000001, 0x00000012, 0x04122012, 0x000306a9,
+ 0x44bb9c4a, 0x00000001, 0x00000012, 0x00002bd0,
+ 0x00002c00, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x000000a1, 0x00020001, 0x00000012,
+ 0x00000000, 0x00000000, 0x20120411, 0x00000a11,
+ 0x00000001, 0x000306a9, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x00000000, 0x00000000, 0x00000000, 0x00000000,
+ 0x376a6cad, 0x65a75b66, 0x5fc3b647, 0xc6279cff,
+ 0x2234c08f, 0x1c0eb40a, 0x2790520e, 0x76ae0f41,
+ 0x5a3401db, 0x42caecce, 0xb4d8e75e, 0xe6dbaf24,
+ 0x7861b35f, 0x6bd717bc, 0x23b9b731, 0x82ec1ac8,
+ 0x20337b64, 0x5396dbf1, 0x59973bff, 0x724bc7e9,
+ 0x5237193b, 0x0b8647c1, 0x6a0d0e16, 0xbf9ddb5b,
+ 0xace2cc1c, 0xad707638, 0x056f102f, 0xa37e60f8,
+ 0x76255642, 0xfb86e030, 0xb8069a40, 0x367795f1,
+ 0x653fb05e, 0xab7f14ad, 0xb6e8a8e1, 0xd2598d20,
+ 0x2eba3f68, 0x78b372f1, 0xba8d13f8, 0x1f1de861,
+ 0x97f951d5, 0x8097c728, 0x27dbf904, 0xb97906a8,
+ 0xffe7a4ac, 0x4b947668, 0xc1dbd726, 0x2adcf777,
+ 0x63b1bcf0, 0x818e2a1b, 0x49aa907b, 0x2faf5e8d,
+ 0xae842352, 0x82707fae, 0x0aa12b41, 0xa0bae11c,
+ 0xb4298c47, 0xd2b4099c, 0x4ff625f2, 0xcd2630d4,
+ 0x79850981, 0x05dbf57d, 0xb05b81a5, 0x56e73ec7,
+ 0x95cb3897, 0xe262bda5, 0xb2c6e288, 0xcb7f8e77,
+ 0x72b8bdd3, 0x3f400494, 0x63ade65b, 0xbc4adc71,
+ 0x00000011, 0x7fa102b6, 0xc91cab56, 0x23eb9aa6,
+ 0x9d9d232a, 0x4ac75dca, 0xd138c770, 0x186a46d4,
+ 0x06dbe057, 0x7d0f33ab, 0x05981bd8, 0xd54df27b,
+ 0x8149f6bb, 0x1d96a6a8, 0xe5ed4fd6, 0x2ffe7a44,
+ 0xfaad7abb, 0x87e6d090, 0x1bfea898, 0x44068e3e,
+ 0xbd1bebc6, 0x5c0b1733, 0xa10e082e, 0xaf8f1122,
+ 0xd0df1506, 0x1604b64d, 0xe61bcdd6, 0xa056c761,
+ 0xbfb4496c, 0x73eb9af4, 0x291fc74d, 0x52075a17,
+ 0x48c3faec, 0x194221e9, 0xc433f1a2, 0x66f07734,
+ 0xdf4369cc, 0x524e33e2, 0xef5a52bf, 0xc18d7365,
+ 0x836d3c5b, 0x0c78998c, 0x60733bd6, 0x278e95dd,
+ 0xbb1bd0ef, 0x469f9078, 0x0f8fa449, 0xb64bfd57,
+ 0x699afc90, 0xba666136, 0xd4d920df, 0xb3a41882,
+ 0x904446a5, 0x975fb33e, 0x71ce1284, 0xe7fa7539,
+ 0xa935ab16, 0xbb6ac136, 0x3ce3dc79, 0x545041e1,
+ 0xf575561b, 0xbb7ad8cf, 0x830ac3de, 0x6315b6cb,
+ 0x29d3a868, 0x7496ad47, 0x4fbb5d41, 0x57f0d4e8,
+ 0x0a004772, 0x223b5ae0, 0xda830465, 0xd57cf87a,
+ 0x90d555a3, 0x4b0379b3, 0xb0c287d8, 0x84b4dfc2,
+ 0xbcb65fde, 0x4a9558ae, 0xa45e75f3, 0x38b1b85f,
+ 0x7adeda9c, 0x614b9d52, 0x7491f075, 0x9b45319c,
+ 0xc7959ccf, 0xb7bd723f, 0xdb547a44, 0x870e1f0c,
+ 0xcd7926e7, 0xe2ab8661, 0x9f8b670f, 0x962f5ba7,
+ 0xf47e3237, 0x56ddf93f, 0xd9b210a5, 0x44112421,
+ 0x70b8fd51, 0xd6394597, 0x5ce67cd0, 0x5595530f,
+ 0xa02ef417, 0xfd7a5010, 0x64b0613c, 0xca4557ad,
+ 0xdcffcce5, 0x4d4657d4, 0x05ee7875, 0xe48be667,
+ 0x00bedc08, 0xf9f15f51, 0xe8268e3b, 0x6c6a41e5,
+ 0x9342c06a, 0xd0a30366, 0x1288ed9a, 0xe18a9a53,
+ 0x5c1d7af6, 0x59c20bc4, 0x3dc46a9f, 0x9afc6f4d,
+ 0xd8dda526, 0xe81e2db3, 0x3224c084, 0x2802ccd1,
+ 0x6d9cc1bb, 0x1919ab90, 0x098dc87f, 0x1fc6cd2f,
+ 0xeff71ec6, 0x9c9234a6, 0x0bf1af18, 0x655fde08,
+ 0xb8398ca9, 0x5bd75919, 0x71768080, 0x0744ab3e,
+ 0x4a4e581c, 0x703e5099, 0xb3485db8, 0xbd225fa7,
+ 0xc16f0fd3, 0x5fddef1b, 0x15e8be36, 0x8b932628,
+ 0xad67afdf, 0x4b325b74, 0x956816b4, 0x9dd9120c,
+ 0xfd8f1d7f, 0x0a6a49af, 0x37a29ccf, 0x1b30be88,
+ 0x6f72ca10, 0x9303412c, 0xc18d5844, 0x2ff80f78,
+ 0x47e9b8a2, 0xedefb296, 0xc1fb50c4, 0xdd182197,
+ 0xa0f911de, 0x3be87c47, 0x5f8715bd, 0xa1d1da0f,
+ 0x8cc57e3f, 0xad0ad135, 0x3e879872, 0x7ccf1b8b,
+ 0xe052ca00, 0x3f53d81b, 0x78138f54, 0x9be86c04,
+ 0xd389d537, 0x6edd6ec7, 0xf51edd3c, 0xd267f58d,
+ 0x50224b2a, 0xe012464c, 0x04d5a03e, 0x68d28d9e,
+ 0xbb52f2ae, 0x1a199005, 0xabceaee7, 0x32f27b83,
+ 0xd58ff5bd, 0x3aaa7af5, 0xc7da0f04, 0x6cf7212c,
+ 0xdc561f7e, 0xeffdd163, 0xe5c582c8, 0x97f9f6ba,
+ 0xb2aa92ec, 0x2cafcbf3, 0x274e641b, 0x61a20c6a,
+ 0xc5f06eac, 0x398d44a9, 0x847bc87f, 0xb46f44bf,
+ 0xd1bd89c7, 0xf0e38616, 0xe210f80c, 0x15967416,
+ 0x823fade6, 0xb4e0be82, 0x43b8e63a, 0x5f18798e,
+ 0x317b87b9, 0x1ecc17e3, 0x525d9e9d, 0x95165598,
+ 0x35e678ea, 0xee752e86, 0x9f766235, 0x531a5e78,
+ 0xa40479ed, 0xf146bfac, 0xfa0fd826, 0x740f8552,
+ 0x04f01766, 0xd76eb511, 0x995babc8, 0x7006ff71,
+ 0x0121d05e, 0x7bd6d3e4, 0x77294b25, 0x2b6fc3b7,
+ 0x9c824d3e, 0x93979003, 0xf31b50dc, 0x86f099e3,
+ 0x5422a2d5, 0x3e8ce3b6, 0x3724c4b7, 0xfbb8dca9,
+ 0xc6ccc4e1, 0xc96e7f83, 0x3ff82600, 0x15f86edd,
+ 0x65a58021, 0x202875c4, 0x4f80ce15, 0x8b56c948,
+ 0xb06dd19c, 0x4ddeb24e, 0x201964b1, 0xfa4d9a6c,
+ 0xc6025d00, 0x16b04a03, 0x7fbf1d4f, 0xb6d44535,
+ 0x0984e426, 0xd41d2b04, 0xe25ddfa9, 0xd6ed0b4c,
+ 0x524fe86b, 0xa412e8fa, 0xd27eb815, 0x6ef3e802,
+ 0x541517a6, 0x77a9582f, 0x77d144b8, 0x544e7ebd,
+ 0xd4e67ae5, 0x38d40db4, 0xc4487933, 0x927625d2,
+ 0x33879419, 0xaf47b12b, 0x5d67b83a, 0x51a481b0,
+ 0x22101172, 0x9cf37511, 0xd73ada83, 0x89bfc7ce,
+ 0x7fe0008e, 0xbd83fe09, 0x1e99290a, 0x2f8f368d,
+ 0x7d6a2af1, 0x5ec3ce05, 0x715453dc, 0x2f10fa91,
+ 0x7f4cb2c8, 0xb39f4473, 0x5a2d91eb, 0x46899430,
+ 0x79fb2144, 0xdbf4e241, 0x969b6012, 0xd1fe3692,
+ 0xf02808ce, 0x34fb38cc, 0xf7108077, 0xf6f1de6b,
+ 0x5a4977fe, 0xb3808e51, 0xff24c56f, 0x4da2d767,
+ 0x5425c2d8, 0xb9056323, 0xf755d828, 0x9aa1f568,
+ 0xe756e110, 0xafd22273, 0x8f0e5260, 0xcc509750,
+ 0xc0170e96, 0xf4c1ddbf, 0x79fe6e51, 0x4759c229,
+ 0xc8db585c, 0x518a6b29, 0xef73a5e1, 0xb9663fe5,
+ 0x334f937f, 0x344227f4, 0x17e9c28f, 0x25dbe20f,
+ 0x43712b35, 0xd22b23f6, 0xf1f28e17, 0x0d2b7b30,
+ 0x14f1860b, 0xce03128f, 0x6f0aeba8, 0x08997f0a,
+ 0x1d66c6d5, 0x62e98372, 0x1c9adaae, 0x6b27a95e,
+ 0xe08b3101, 0x53e4ff64, 0x3eb0d25d, 0x0210f8da,
+ 0x8a21dfd1, 0x1e3df218, 0x7c8e477b, 0xa1daa59b,
+ 0xc2c08228, 0x93d35cc7, 0x1620e400, 0x79b7cf10,
+ 0x496b75ae, 0x4b2da284, 0x16e76b09, 0x8d20130e,
+ 0x945008c7, 0x957f154d, 0xa45ed1aa, 0x144c8d1e,
+ 0x6acdeb36, 0x12a7543a, 0x50cc0089, 0xbd68a6ae,
+ 0x7dc4ef1d, 0xf63dd709, 0x5bed5466, 0xcc5c95a2,
+ 0x92c08dbe, 0x8c044cf1, 0x1a335a87, 0x15fa428f,
+ 0x22a006b0, 0xc1a814c1, 0x1e23a377, 0x91fece37,
+ 0x59eda9fe, 0xd8466e07, 0xbbca7bf6, 0xe839cbb7,
+ 0xfe91ab77, 0x10484962, 0x8cc60391, 0xf93ba3ed,
+ 0x71df9ef9, 0x24a71ae7, 0x41da52eb, 0xbcdd8d7f,
+ 0xbabb0d85, 0x3470c86d, 0xb492093f, 0x7cbed682,
+ 0xbbd16265, 0xff9652c5, 0x898fcb16, 0x2362dc4b,
+ 0x46e60c80, 0xecc56ab4, 0x778f80ec, 0xebca4049,
+ 0x838faaf9, 0x0695514a, 0x70886e5e, 0x6dce2b9c,
+ 0x55da4b2c, 0x123a673f, 0xd4581c54, 0xaf997989,
+ 0x62c718e9, 0x0a66a88e, 0x15d96af2, 0x148ddccf,
+ 0x857a8bb7, 0x9d593d3d, 0x57d3c2a9, 0xa88f9306,
+ 0x881de261, 0x5538072c, 0x7c764e6b, 0x2b2cda75,
+ 0xefd2dcbc, 0x823511a9, 0xe3d3c158, 0x016138ff,
+ 0x74604543, 0xb3d37442, 0x044c6c1f, 0xadfd5ffe,
+ 0x3ed72fa1, 0x41b3ec65, 0x362f2e36, 0x2129ea66,
+ 0x6eae1382, 0x86422b41, 0x308f1926, 0x8d5e538c,
+ 0x668d8ed4, 0xf937295c, 0x201c5b9d, 0x21a5dc85,
+ 0x827f8831, 0x3c78dd04, 0xf0510eb3, 0x7762494e,
+ 0x3182c2c1, 0x1774c617, 0x56dc5254, 0xc780cbb3,
+ 0x6b1ae58a, 0xbf5ab9f6, 0x243cdb05, 0xfbd33f09,
+ 0x1a2cc337, 0xc4423713, 0x4c3d7dc3, 0x5ea3e547,
+ 0x5cc9e7b8, 0xe74447bc, 0x03f8abf3, 0xd5742151,
+ 0xcf1cb3ce, 0x52fd2ed6, 0xc9e2d3a4, 0x51a21ed8,
+ 0x954407be, 0x2c2513b6, 0x26d7a536, 0xc2c40602,
+ 0xee672feb, 0x3ae82f8c, 0x5c5333a5, 0x99ddcaae,
+ 0x39736454, 0xe8372723, 0xa961b826, 0x7e87da53,
+ 0x4dbe8063, 0xaf2caf84, 0xe3d791fc, 0xed92cade,
+ 0x1b98ad30, 0x9ea1a340, 0xf6b81fa4, 0xdbf047ec,
+ 0xdb8d3347, 0xdce81195, 0x255216e7, 0x55f9f4a6,
+ 0xd20da40a, 0x535b8f27, 0x8ad4137f, 0x245332aa,
+ 0xb160b148, 0x58bebb7e, 0x70866999, 0x13223854,
+ 0xde1f4fda, 0x67d15e5a, 0xd3afd2bf, 0xaced1f7a,
+ 0xbddca0fb, 0xc71eef90, 0x70dc0ec2, 0xe30c2596,
+ 0x11bef5d4, 0x1f6377c8, 0x3090864b, 0x346ca15e,
+ 0xccb5e392, 0x17b47b75, 0x6275f2a4, 0x5809aad6,
+ 0xeeb12cfd, 0xbee577fb, 0x1f1a96bb, 0x6437be74,
+ 0xc67d5d5d, 0xa7c55f04, 0xa22cc49f, 0xbbf0dc66,
+ 0x82eef859, 0x735b11d0, 0x1d229c39, 0xecc06c69,
+ 0xfd18481c, 0xaeeded12, 0x8161d09a, 0xfa7d3c66,
+ 0xfd33060d, 0x7d0ef812, 0x8e0ba0d2, 0x988137d6,
+ 0x4f69850a, 0x003fcd89, 0x19eccc4e, 0x65b943a3,
+ 0x34640d13, 0xb00db20d, 0xf48bb92f, 0xaf78f369,
+ 0xe94d33a9, 0x79e71aef, 0x3ac7a74e, 0xc6d78553,
+ 0x2784a061, 0x4145842f, 0x52cda09e, 0x303c6092,
+ 0x93eb56d1, 0xf8616fef, 0x726c131c, 0x8f96c9e9,
+ 0x02da9219, 0xb9fb33b7, 0xd524c23a, 0x2e486736,
+ 0x312dc601, 0xfab7516b, 0xb18af872, 0x5e3c69ab,
+ 0x4b23bc50, 0xec63d91a, 0x950d9aa6, 0xa9d4b625,
+ 0x61cbb82f, 0x1d6e7ead, 0xb658aed6, 0xa255676a,
+ 0x928b6489, 0x54ed6bc3, 0x9c43a4f2, 0x8655c7a3,
+ 0x362b778d, 0x5c8feab2, 0xd4049660, 0x78cde231,
+ 0xa64fd60a, 0xb92b1757, 0x2a3f0805, 0x765067bd,
+ 0x73119cc6, 0x4a8a3033, 0xad68d1ee, 0x4f07a51e,
+ 0x196aa656, 0x06ff8c21, 0x3176150e, 0x733918b9,
+ 0x77647673, 0xe3e501db, 0xe613f631, 0x74cf7236,
+ 0x7a2bf75a, 0x3bbaf8e8, 0xc66638b9, 0xb16defeb,
+ 0xe87b54fa, 0x66a37f39, 0x5e0db5e8, 0x1b171fe6,
+ 0x8ec3c550, 0x247da09c, 0x4f334df4, 0x034fda83,
+ 0x5f5bd54f, 0x3acd0ff3, 0x610ca316, 0xc4630da3,
+ 0xaab1f5cf, 0x90b4f46e, 0x7eac344a, 0xf9b84b9f,
+ 0x21839ca6, 0x21c03b85, 0x75637f2f, 0xac05a6fc,
+ 0x183aa6d4, 0x67b2e4f8, 0x8589a08a, 0xb600a1f6,
+ 0xc287f1bb, 0xf6340107, 0xeadb431f, 0xb8900b33,
+ 0x5ceb59b9, 0x807dcd10, 0xeb58256a, 0x9d5281d3,
+ 0x4e4eab0e, 0x81bd9eca, 0x8c225464, 0xfb558da6,
+ 0xed24697d, 0x74ef0e70, 0x9c22936c, 0x393fd425,
+ 0x94f61d74, 0xfa7ea064, 0x622123b4, 0x9dc6eee1,
+ 0xafc55059, 0xf72cdbed, 0xbbf9f598, 0xcc02b1d4,
+ 0x6aab9401, 0x825c4ed8, 0x951d5210, 0xbd0cfa1e,
+ 0x079a14ad, 0x3d185940, 0x15d8277a, 0x5955d243,
+ 0x20889938, 0x5b822087, 0xc87bcbfe, 0xf77896e2,
+ 0x7eef0b71, 0x0746fa08, 0xf25e6ce4, 0x62efb2bf,
+ 0x44ef7e5d, 0x5f2e7304, 0x41e92d35, 0xdb098eb2,
+ 0x34c80bff, 0x36e38910, 0xa089681c, 0x599c0334,
+ 0x96a1da39, 0x501a5f7f, 0x5144e81f, 0x628c860a,
+ 0xe05779cb, 0xd521480b, 0x6f0e956d, 0xa5f5738e,
+ 0x2db458fa, 0x5f38d672, 0xefcfaafe, 0x98c2f228,
+ 0x71dbaed3, 0xc16b2a68, 0x16410edb, 0x144c1c2c,
+ 0x6aac8d87, 0x50901ea0, 0xb3a9a6ba, 0x6459be8a,
+ 0x1eba827f, 0x2ab8eddc, 0xd973a8c3, 0x1d752eea,
+ 0x378316e7, 0x5ed4959e, 0x00f78e95, 0xcd8b9524,
+ 0x5f1b921f, 0xb361c594, 0x1eeb1d0f, 0xaaee4d87,
+ 0xfce616b9, 0xe706a0cf, 0xbdfcdbff, 0x64cc42d2,
+ 0xf5961f68, 0x56c13c4d, 0xe89587a2, 0xf8d233f8,
+ 0x4a379cb9, 0xaff4e372, 0x8df2b641, 0x5d3d497b,
+ 0x79fbd48a, 0x4507730e, 0xd0ed2485, 0x3d764205,
+ 0x3b3cf955, 0xd8f586f2, 0xc815f8a8, 0x5f880aeb,
+ 0x53ee2e32, 0x39920f27, 0x2dc2fb21, 0xb1a3eee3,
+ 0x3d9f9b5d, 0xe33fd48e, 0xfd04878c, 0x49fc6760,
+ 0x77c4400e, 0x63d1290a, 0x6bebe7e7, 0x9131b2aa,
+ 0x0623c135, 0x8d82a973, 0x74cf08d7, 0x5e93da7f,
+ 0xa2de5ba5, 0x84f98a4e, 0xd063cc96, 0xd7133799,
+ 0xd14776ce, 0xa753be87, 0xfddd16bd, 0x78cacfe6,
+ 0xb60d754c, 0xe5c54d16, 0xd2bdc91f, 0xd20c711b,
+ 0x824b12cf, 0x466b0657, 0x750b87d2, 0x85c2790e,
+ 0xbef7abca, 0xded73224, 0x46e7736c, 0x1f256553,
+ 0x680a4cb8, 0xacc123e5, 0x3a51b5fe, 0xb054c144,
+ 0x38826071, 0x08e103e1, 0x3f1f8995, 0xda5d1c8d,
+ 0x424f6bfe, 0x0842142c, 0xe94eb2ab, 0xc9b7acc4,
+ 0x1720cab7, 0xb8aa8142, 0x2d918c9a, 0x4c82d76c,
+ 0x92ba3b20, 0xd88435a7, 0xddeef25c, 0xf7c49287,
+ 0x855a16f6, 0x1eb4dfc3, 0x872b2d14, 0xc2811553,
+ 0xb84047c1, 0x606dc8cf, 0xe9f1d5a7, 0x11b1e0c1,
+ 0x2da24d55, 0xe5bcb59b, 0x5eef069b, 0xd4e7dd90,
+ 0xc0531a60, 0x2adb1dad, 0x043eec5a, 0xccc41f87,
+ 0x8973cc5f, 0xfbe7fb69, 0xd83b69f5, 0x25b8c590,
+ 0x284a43b0, 0x2dbdfd0b, 0xe3fefcea, 0xe2609c09,
+ 0xc2672d76, 0xafb15488, 0x3e192825, 0xee9dc9a9,
+ 0xe21849e1, 0xbf688de1, 0xb463fe75, 0x93677325,
+ 0x1ee2501d, 0x8ad80593, 0x7e78ca27, 0x96dc435a,
+ 0x7a9547a1, 0x26b0adf6, 0x78317ec1, 0x00a4de2d,
+ 0x29772622, 0x84943459, 0x9c201270, 0x933c62fa,
+ 0xfdb997c7, 0x02fe7f59, 0xa99a5e76, 0x2d261e97,
+ 0x4ce8ffe5, 0xa63bc1eb, 0x3378e659, 0x05d4d331,
+ 0xa0ced568, 0x1966e547, 0x3ff36158, 0xda48f693,
+ 0x298be56a, 0x0147b9dd, 0xc46503e0, 0x45a96741,
+ 0x524ff2fc, 0x274d66e6, 0xced6e027, 0x25b6756a,
+ 0x5825dc05, 0x88385c3d, 0x685115cf, 0x735dec4f,
+ 0x2a00b72b, 0x30bef86d, 0x4e42c078, 0x39ff294d,
+ 0xab10bdb1, 0x495fd301, 0x6e4b445a, 0x860a2eda,
+ 0xff6873d8, 0xc7ad4b0a, 0xd2298f65, 0xc81a0577,
+ 0xd5d022a4, 0x397c2c5a, 0x3c25ab26, 0x40eeb0cb,
+ 0x6ddb3d38, 0x1a7389fc, 0x1bcd06ca, 0xbe0265f7,
+ 0xc8535026, 0x0f431bd5, 0x7f9ac4b9, 0x8824f45b,
+ 0x098c05b0, 0x46810fdc, 0x090deeb3, 0xd76c81d0,
+ 0x9baba141, 0x23b0a088, 0x55674e1b, 0x045c03d6,
+ 0x387bd692, 0xea020228, 0xcf3fae4c, 0xf0d901ad,
+ 0xe21f9071, 0xddc49fc3, 0xfd892267, 0xe888e9c0,
+ 0x92c7b549, 0x4a9d820e, 0xd695c26b, 0x2d6a08df,
+ 0xdc5fee42, 0xe9a7c3c4, 0x11efba97, 0xff2355ba,
+ 0xca4f6ebe, 0xf4e7d62c, 0x4c0e38e5, 0xace24ea5,
+ 0x4e30977f, 0xed5ded8c, 0x924beadc, 0x4a1bd491,
+ 0xad5b54aa, 0xb377ca45, 0xb51d17ff, 0x07908ed1,
+ 0xcae79921, 0x694339f1, 0x9deb6478, 0xa5d8a222,
+ 0x6b1779b0, 0xd895922a, 0x45822c71, 0xaa735127,
+ 0xce49b53f, 0xfa40bc8c, 0x6bf62491, 0xdf2be759,
+ 0xd640190c, 0x85f7b600, 0x40ddfeee, 0x992df97b,
+ 0xa25b6a7f, 0xb8a5f3be, 0x87e3d218, 0x0decfcb3,
+ 0x8ad2333f, 0xb424fb2d, 0x5a33542a, 0x4740d643,
+ 0x4c345169, 0x664f4d7e, 0xd618babe, 0x5d1f2138,
+ 0x8c454b65, 0x8c8bc29d, 0x414ca6bd, 0x42d6f7e6,
+ 0xd6acec03, 0xb407bd35, 0x38425c86, 0x3d6c79e7,
+ 0xc536760a, 0xe689ded0, 0xbb484220, 0xcdb72b92,
+ 0x0c2ca27e, 0x09bbdeb7, 0x030e5baf, 0x49150d23,
+ 0xc44c06d9, 0xcce68c5b, 0x10cfdf25, 0x9f9a2fbd,
+ 0xede676c3, 0xa6cf4d52, 0xa56f4e1b, 0x0b17245c,
+ 0x97c19e7a, 0xecbcda54, 0x2864b716, 0x530ff4e8,
+ 0xa26c07ed, 0x29768760, 0x59dd456d, 0xf7630f33,
+ 0x105fef07, 0xfb0b1864, 0xe0f8f808, 0x75b6eab6,
+ 0x8d8b30f9, 0x94d10996, 0x34b98a1c, 0xc889e1b9,
+ 0x87eb653f, 0x8bf01f6c, 0xd2a6785a, 0x89953f72,
+ 0x637c8ce6, 0xfe941147, 0x15433bf2, 0x8df646d2,
+ 0x031eb5d5, 0x5f54cc7c, 0x12150530, 0x51008732,
+ 0x9faadea1, 0x1db96c83, 0xff1f5f4c, 0xe6f787b6,
+ 0x2e95c62a, 0x86fe783a, 0x330ad843, 0xb55478b9,
+ 0x1258a62d, 0x1263eaca, 0xef1ff0c3, 0x81cc9cbe,
+ 0x98bc65ad, 0x5940971c, 0x6dc6690c, 0x2e105d97,
+ 0xd76a990d, 0xeb5bec34, 0x7915d109, 0x6d7b4fb1,
+ 0x978107ce, 0x32787ae2, 0x465f38e1, 0xbb6fdf86,
+ 0x88a941c2, 0xd9ab2e4e, 0xd55b343d, 0xf23472f0,
+ 0xa268b2d1, 0xb195b41f, 0x6a212a83, 0xbaafb80f,
+ 0xef9697e4, 0xc8c4e79a, 0x0028b78a, 0x484be563,
+ 0xf8f54ad2, 0x9e657f34, 0x0eb3ee75, 0x458fe551,
+ 0xc3b123a4, 0x79e7c679, 0xb6e98b33, 0xc5e69bdf,
+ 0xeeaa2283, 0x846bdd38, 0x2e1f75b7, 0x1991aa04,
+ 0xd14280f8, 0x429c5252, 0x14db4cd6, 0x11e8de51,
+ 0x60339185, 0xd1df3d31, 0xe2f63b80, 0x8f4eb01b,
+ 0x56aa65fc, 0xe4117c2d, 0xbbc76e69, 0x6c023982,
+ 0x1779c6d2, 0xabd961e2, 0x342537fc, 0xac225e0d,
+ 0x92b9487e, 0x9e231512, 0xfebb74e6, 0xfc8bfa58,
+ 0x9c16e973, 0xe1fa9d9d, 0x0cc2af76, 0x6265eaca,
+ 0x2b0cc7a4, 0x6563fb12, 0x3906e2b0, 0x951b567c,
+ 0x48652089, 0xa1687666, 0xc4b9b74f, 0xe7979ba8,
+ 0x5dbd109b, 0x6a34ba61, 0x459361a8, 0x1f7a062f,
+ 0x549fb0f0, 0x19f68bbe, 0xfe0c4305, 0xc8461d07,
+ 0xe82c76ff, 0x74323e24, 0x8ec4cbdb, 0x10c7b0fd,
+ 0x6de0c51c, 0x4befe684, 0xd55f3924, 0x43b528bb,
+ 0x142b1764, 0x49cbdb43, 0xaf83d1c0, 0x3de12b87,
+ 0x74f5815d, 0x27f4d384, 0x3dff664f, 0x039a022c,
+ 0xac25aee8, 0x158aa373, 0xbb0aa5b0, 0xc5fb33bf,
+ 0x86b47034, 0x69080a48, 0xf2ceb6ae, 0xa2b10691,
+ 0x5f9d5e14, 0xba9dcaca, 0xf1ca6c51, 0x5d88b26f,
+ 0x0e648678, 0x86382f1f, 0x86e8d54b, 0x99c4e2d3,
+ 0x90e37776, 0xb8f50611, 0x6890ab80, 0x559e7b47,
+ 0xe4e9060d, 0x48cd96c1, 0xc904154d, 0xe1837104,
+ 0xdba0c8a1, 0x696df0d6, 0x002fdae2, 0xecc1c124,
+ 0x3f152f06, 0x0984f6d3, 0xba48a36a, 0xfd27093a,
+ 0x019799e1, 0x0518ffc7, 0x5c4ad28d, 0xd48a95f8,
+ 0x83524003, 0x35d82788, 0x514155ae, 0x07911e43,
+ 0x11f785cf, 0x14cbe0f0, 0xc10a02dd, 0xb439bb11,
+ 0xfe5b26aa, 0x648c7d7b, 0xd8a63cf1, 0x5db53004,
+ 0x4211a6e8, 0x7305e4e2, 0x373ae52b, 0x8209354c,
+ 0x30eeeb51, 0x9bd8cc34, 0x4478e072, 0x9e18fa8e,
+ 0x396b99b8, 0x531b7b2d, 0xe2e86168, 0x54e61277,
+ 0x4cff278d, 0x47c409fb, 0x78615fd6, 0x5098838f,
+ 0xa1241900, 0x76b613dd, 0xf20b8348, 0x9f30620a,
+ 0x6e92e97f, 0x7b52f411, 0xdc00f446, 0x1b85ca28,
+ 0xa654f3cd, 0x54c27ea2, 0xc7a38438, 0x93f23d3d,
+ 0x48858500, 0x9220ee3e, 0x8484b4b7, 0x57e1b31c,
+ 0xf3f05365, 0x4b9b2bc0, 0x17793193, 0x88023aea,
+ 0x68f80e6c, 0xbd5941c1, 0x9228b71a, 0xf0d322d2,
+ 0x32b2f437, 0xdc172b24, 0x8dabf728, 0xa84c3a62,
+ 0x092e0770, 0xca154ceb, 0xac8a39e1, 0xf6bade6e,
+ 0x5edb6711, 0x8e980ac4, 0x6806ab75, 0x58955dff,
+ 0x2c545a28, 0xdf464a32, 0x3e405d17, 0x12b27ed1,
+ 0x826657c7, 0xc9f83718, 0x6ae2a4a7, 0x31ca153e,
+ 0x16251fcd, 0x66230d87, 0x61b4612c, 0x66138e04,
+ 0xd6155d2a, 0x73bf5cf2, 0x7085cb3f, 0xe770e8ba,
+ 0x091b0cbd, 0xc85130b5, 0x234d24bf, 0xc0ef659b,
+ 0x8de7786c, 0x914ce325, 0x38f2cda5, 0x562e9e23,
+ 0x0f35417d, 0x43224196, 0xc9e9a948, 0x43be79a3,
+ 0x9bd763c8, 0x42f7f47a, 0x7a96f0bd, 0xe3104cac,
+ 0x5c4532eb, 0x3d11c850, 0xa3cbc6e8, 0x43287cc5,
+ 0xb0f93fb8, 0xf37d5874, 0x429c61da, 0x2137275d,
+ 0xa5cde30f, 0x55940366, 0xcfb22184, 0xdb5da5cc,
+ 0x5826dac1, 0x65f393c7, 0xa68c56dd, 0x4c57656c,
+ 0xc1b001a1, 0xc7f4cc67, 0x083fdeb8, 0xe11404aa,
+ 0x007f603f, 0x87415796, 0xbb71a3b7, 0xc737f982,
+ 0x0b628253, 0x7206695c, 0x2895a77a, 0x8b7d1cc4,
+ 0x56937843, 0xc239ee82, 0x44b8135e, 0xba3894d3,
+ 0xddaa7f15, 0x7ef8ef2c, 0xb3aee7b6, 0xe29e5186,
+ 0x29de8aac, 0x1391c862, 0xd85bf021, 0xfa72261a,
+ 0xe419445e, 0x20353fcb, 0x5b43a220, 0xe85496a5,
+ 0xed4c082c, 0x428cfd7e, 0x3ba72a85, 0xb00c1c2a,
+ 0xa5229831, 0x0b4e4a7e, 0x9d6673e6, 0x9b8cfcf0,
+ 0x16d49ec8, 0x3ffbf6f4, 0x5944d611, 0xe1896882,
+ 0xbd841768, 0x21bf4588, 0xd8edaad9, 0x9973cfa0,
+ 0xdd5259a8, 0xd0acb04e, 0x9151d0e1, 0x3b341114,
+ 0x90040d2a, 0xa7dc7f98, 0x6f7d3ade, 0xa98d88be,
+ 0xd9889a9e, 0x754dde83, 0x14ba2782, 0xbd9ed127,
+ 0x0efb858a, 0x9988fff5, 0x012f765f, 0x76f0d057,
+ 0xf7ae811d, 0x21e161b1, 0x981dc33e, 0x723007ea,
+ 0x8293a254, 0x6446ac7c, 0xaabee282, 0x2347d63e,
+ 0x3ceae675, 0x87411551, 0xee277ca5, 0xb0e7257c,
+ 0xb90fc54d, 0x4ccb36dd, 0xb6af53cb, 0x0e310750,
+ 0xdd767ca7, 0x67b9a956, 0xbdad1a80, 0x052fd9e4,
+ 0x125d7ae8, 0x0d981c8e, 0x8018e149, 0xa7536963,
+ 0xd8478bd9, 0x3c0f7350, 0x07c410c5, 0x3f983bde,
+ 0xd77b5801, 0x19aab3c1, 0xd14fe45d, 0x6af1aece,
+ 0x972706e5, 0xc9f1f6c6, 0x8098a66a, 0x634eca92,
+ 0xe2daee04, 0x314dc392, 0xb75c50a9, 0x44149b41,
+ 0x4b108875, 0x0c3ae804, 0x35612f12, 0xeb84f9ae,
+ 0x5c4da280, 0x0147f8ca, 0x756a7942, 0x44fe4c28,
+ 0xe6db44f7, 0x9bd6e80a, 0xb4c088a0, 0x592433e2,
+ 0xdf0639f1, 0xa0ca476a, 0x31fe1ccc, 0x790759a7,
+ 0x98267f73, 0xfa774f2e, 0x77051d37, 0xb68dc0b7,
+ 0x7f401f6b, 0x0c84c7c9, 0xe760f16a, 0x613941d3,
+ 0xad30f319, 0xf707e61e, 0x6e855fde, 0x99146d9c,
+ 0x1755ac8b, 0x0fac8195, 0x2cb2900d, 0x5c9f8667,
+ 0x58fc7ee9, 0xc522c2a8, 0x63ab90a2, 0x4d98d938,
+ 0xe2c67a60, 0xc37bba81, 0x9fb54079, 0xbc4b38e9,
+ 0x97ca5bf0, 0xf9def791, 0x5b3e6f57, 0xe5691607,
+ 0x5ec77467, 0xfc54a53d, 0x6c1258a9, 0x3836ba14,
+ 0xebb58b55, 0x242fef03, 0x63f5e508, 0x0586eb18,
+ 0x1556ba05, 0x839faf54, 0x9558434c, 0xa16efc07,
+ 0xeca82b4a, 0xc55e4afe, 0x585ae7e9, 0x86c5803f,
+ 0xc3fcec20, 0x53cec1bd, 0x4dde3942, 0xe3961657,
+ 0xf6242d95, 0xc73381d0, 0xa1d70e8c, 0x022c5690,
+ 0xd395d193, 0x50f9702e, 0xd20a939a, 0x1dde2e04,
+ 0x8356d479, 0xad22c49e, 0x0332faa7, 0x39b46a35,
+ 0x0370fc76, 0xdfce3b0c, 0xb1526e82, 0x10e8ad4b,
+ 0x1721313e, 0x7d6b2443, 0x50104caf, 0x3efa4991,
+ 0x9268b8b1, 0x30bedb93, 0xb8ae786c, 0x1df1f3d8,
+ 0x2bc35c5c, 0x6abdfa8c, 0x5925b778, 0x479bea71,
+ 0x1ffea9e0, 0x08e89a58, 0x2530ae13, 0xfce8dec4,
+ 0x9470e031, 0x9074cf05, 0x619f299c, 0x6dfa39a6,
+ 0xed7ac0d4, 0x66c070de, 0x6db6a10e, 0xf731ff22,
+ 0xcfdaf242, 0x60b181f9, 0xab034a5e, 0x769defc8,
+ 0x674066ae, 0x3703b5ce, 0x40f4eeed, 0x2f892068,
+ 0xf04be4d4, 0x2edfa6c4, 0x59febb76, 0x808742b6,
+ 0x89727940, 0xb089ec70, 0x82ab146e, 0x700a9401,
+ 0x61da426e, 0xa045412d, 0x3eb719d9, 0x661b1ad8,
+ 0xf75005d9, 0x66f8eaf1, 0xbc173fea, 0x5ff5392b,
+ 0xacda8f53, 0x5d7ea13b, 0x862d4ec3, 0xe4ee946f,
+ 0x630518b2, 0x290fd79f, 0x477a0c55, 0x5b2fc14f,
+ 0x2443746f, 0x9c4a8974, 0xba85c1cb, 0xa350b7dd,
+ 0x9ebbc988, 0x4dda06b0, 0x651eeffc, 0x06d53acb,
+ 0x79831946, 0x48153860, 0x09468320, 0xd06defad,
+ 0x7340d21a, 0x8a9676ff, 0x3089f960, 0x29662958,
+ 0xec5ae8b8, 0x2a296293, 0xd7b6e71f, 0x43553c99,
+ 0xa6b3ac45, 0x3628d14b, 0xbb5d4914, 0xcc7f9cbb,
+ 0x19669f34, 0xff148748, 0xeeb0aee5, 0xc5a987c9,
+ 0xbecacdd5, 0xff0b648a, 0xe0ca4274, 0x697d8a11,
+ 0xbb1e67b5, 0x599321f2, 0xb68d74f6, 0xf49ec12b,
+ 0xcaae6a16, 0x0469e957, 0x0a2bbf1a, 0x5188d354,
+ 0x61bbc042, 0xad15960a, 0xec46a2c0, 0xfedf1e46,
+ 0x61b52300, 0x4f4600a6, 0x752a5c04, 0x480a2494,
+ 0xd40bf5c2, 0xa494fadc, 0xedc98d34, 0x3c2de939,
+ 0x4b0bcff0, 0xbde996c4, 0x694ffc37, 0x4df8d7dd,
+ 0x363859a6, 0xf4398400, 0xb4b3a2cb, 0xe7954f12,
+ 0x05fb14fc, 0x82eeb39a, 0x5e9db70a, 0x4ff0f249,
+ 0xe8c48494, 0x44480219, 0x008fcea3, 0xb5545801,
+ 0x8c550bc9, 0x77bf46b8, 0xeef729b8, 0x56a9a1e7,
+ 0xd9ddc7ea, 0x869ba6ae, 0xae0b0513, 0xa3284e38,
+ 0x57390ff5, 0x94d3c886, 0x05b44f30, 0x29e7986e,
+ 0xe57f7a43, 0x13ce02e7, 0xdbbf7d9c, 0xd825a71a,
+ 0xf1c9a57d, 0x1d52d76a, 0x75093610, 0xcc01d147,
+ 0xc47be394, 0xbf84cba5, 0x02fd0d8b, 0x3eba3ff7,
+ 0x1ad19934, 0x14ba7101, 0x600fa13a, 0x7c620095,
+ 0x6420c5ce, 0xc0c04a01, 0xe3808df2, 0x83973113,
+ 0xa3d65a2a, 0x08d5401e, 0x0c2c158c, 0x8c856ef5,
+ 0x453977c4, 0x8c8e26e1, 0x5bc777a0, 0x19c3a1e4,
+ 0x1c31d142, 0x8f6587f8, 0x8c5ed782, 0x67926438,
+ 0xe3a3e285, 0xd54415e2, 0x72491774, 0x8bdc8dc2,
+ 0xfbf88ba4, 0xdf7c656f, 0xd534a477, 0xa8e014f7,
+ 0x459f84e9, 0xcf802d2a, 0x08245b16, 0x6a028919,
+ 0xae264bf1, 0xdf2174c1, 0x1aa78d57, 0xff430bd9,
+ 0xa17c0146, 0x2baa1b4e, 0xf503fccf, 0x1d17e73e,
+ 0x06e44ba9, 0x596942f5, 0x01bd41b3, 0x2c34e4eb,
+ 0xea3949d5, 0xa5b9033d, 0x3a3700b6, 0xf19f8adb,
+ 0xf46faced, 0x1fa7f8ba, 0x0e4f24ea, 0xb10e2ba3,
+ 0xd8f31da7, 0x222afe94, 0xbd5226be, 0x4ff8b1a5,
+ 0x0e658024, 0x80b43837, 0xb532fda1, 0x5675d524,
+ 0xe057c4c2, 0xf4496676, 0xc74735c4, 0x342483e6,
+ 0xd558288f, 0xc0d8600c, 0xd60dbf45, 0x4ccb7690,
+ 0xe0ba185d, 0x15f63d1b, 0xeefc9a4f, 0x6619ae43,
+ 0xba8bf103, 0xc186ff34, 0xbb895b0e, 0xe898fe32,
+ 0xb7d444ee, 0x7bb8fc1b, 0xd0aca081, 0x175131c6,
+ 0x189b69a9, 0xbea6ebfa, 0x812d6ea0, 0x229a1500,
+ 0xd7579361, 0x0d7fa620, 0x2ba17909, 0x06d4281d,
+ 0xcdc92c2a, 0x4249f155, 0x0920663c, 0xe7d7ff00,
+ 0x3d24ac94, 0x17adb552, 0x21750de9, 0x8d13028f,
+ 0xc2362278, 0xebcfc4a0, 0x786cfbdd, 0x14228fb8,
+ 0x6f1f47e8, 0xe76918a1, 0xd8cffd7c, 0xde9e6c11,
+ 0x90942c6f, 0x40ca335d, 0xaef42016, 0x665297ae,
+ 0x3f1852ad, 0x5ac0e67a, 0x65c5194f, 0x8670e74c,
+ 0x40ef7539, 0xe2e9638d, 0xf435a6fd, 0xce3ef42c,
+ 0x15d78405, 0x720d9055, 0xf29b775d, 0x5eb3287e,
+ 0x553c9843, 0x850e6b26, 0x2029b67b, 0x6fc82a97,
+ 0x73dec8e0, 0xfef96a4c, 0x0e5fe517, 0x4d8a9649,
+ 0x27657ffd, 0xb1486785, 0x0bd2ffbd, 0xedf60ae0,
+ 0x72786e5b, 0x0d68bdc2, 0x1a503903, 0x3da57d17,
+ 0x68e61e99, 0x81a67bb5, 0xb8e3444d, 0x0205d442,
+ 0x7d04427c, 0xe7b11bfd, 0x3c25818c, 0x7d30e440,
+ 0xd4099162, 0x2c5ddf57, 0xf6308981, 0x717c6630,
+ 0xb2fb5a26, 0x8525eeab, 0x18a2b831, 0xee330ed1,
+ 0x4331bb74, 0xd3c2789b, 0xdfceedf1, 0xb2ded69a,
+ 0x1992480e, 0x5d96af46, 0x00c62666, 0x56b29993,
+ 0x9d995062, 0x79060912, 0x3330b346, 0xd59fa9eb,
+ 0x96c0911a, 0xf031021f, 0x73132ad7, 0x15cb198e,
+ 0xb4711b92, 0x19904ca7, 0xc3760e6a, 0x40ef97ba,
+ 0x66820299, 0x321c9ec5, 0x8f0d720f, 0x34a4040c,
+ 0x29c8116e, 0xab55b709, 0x4cf58f36, 0x90b42de2,
+ 0xca7db382, 0xef08909c, 0x7609e013, 0x142efb41,
+ 0x746e30bd, 0x665c63f8, 0x4bc664ed, 0xc2474d27,
+ 0xcc94641e, 0x8062069c, 0x77f11c65, 0x2a450788,
+ 0x0f88f518, 0xd805567c, 0x2aa9a7a1, 0xcb849831,
+ 0xe2ddb6ed, 0x0639ead0, 0x060fb532, 0xd80106a2,
+ 0x268cc919, 0xa33c52a4, 0xa767baef, 0x40d45fdf,
+ 0x0762bc85, 0xaf50bcb7, 0x9876a53a, 0x0898ffd5,
+ 0x2cbc6104, 0xc3d88763, 0x9dc5f99e, 0x4ba5fcc0,
+ 0xb2433106, 0x94755b2e, 0xd3b77837, 0xa54ddf40,
+ 0x91c53192, 0x4f08a77e, 0x8e74d1da, 0xe562b28f,
+ 0x2bfeaa16, 0x24334325, 0x70a22523, 0x6cf8b83b,
+ 0x57c656dd, 0x4dd0e192, 0x7e31a55e, 0x2090a3fb,
+ 0xb7709b48, 0xf8c80d44, 0xe5c6e20c, 0xef6c1a06,
+ 0x70c9ad1d, 0x9c2e93b6, 0x94a254b2, 0x1a209fa1,
+ 0x9b4365ea, 0x0879d3f7, 0xc4dbaf4d, 0x83f80f9c,
+ 0x6560527d, 0xff7e272c, 0xaa7d2205, 0xdd27d9e9,
+ 0xa4e90703, 0x6acfd890, 0x70edb353, 0x95a2ed59,
+ 0xa0c85a2e, 0x54c683d4, 0xf34347c7, 0x8e11c72a,
+ 0xeb943942, 0x37f9bf7b, 0x31981ce0, 0xc7d764f7,
+ 0xda0873c6, 0xc2713940, 0x58ab6bc8, 0x935a694e,
+ 0x3f915b14, 0x28a9225f, 0xe04ad797, 0x60675c36,
+ 0xc3b1c9c4, 0x9511600e, 0x02fe83b8, 0x5986b677,
+ 0x083e3e97, 0xbdb8d2cc, 0x0f9503bf, 0x561b66bc,
+ 0xb1863ed7, 0x78f88f32, 0x8c7aebc8, 0x5c8e5bb8,
+ 0x9e32e0b6, 0x9d28c3e6, 0xe8b75d45, 0x314ac759,
+ 0xafaae9d2, 0xb87d4eef, 0x5479cbd5, 0x0d9cd83a,
+ 0xffc46c21, 0x63dfdcd6, 0x248a4d57, 0xe051bafe,
+ 0x1a4e13cf, 0x3d5974ac, 0xdd032701, 0xd8fa48d5,
+ 0xd7f83db9, 0xdd5a7e1e, 0xb1976914, 0x7e88be65,
+ 0xcb50963e, 0x8aa1d4b0, 0xb2e18e0c, 0x9ad42023,
+ 0xa9182a79, 0xe34b34eb, 0x09a63e19, 0x9b0ac88f,
+ 0xb77c3e87, 0xe66ccaf2, 0x936e3e2f, 0xf10681cd,
+ 0x93bba8f7, 0x1b5d515a, 0xf179118d, 0x2b3e30ba,
+ 0x5738fa2c, 0x0e3593ea, 0xfe4497e7, 0xb18b620e,
+ 0x41f5c0d0, 0x46037444, 0xfa6c97a7, 0x1f2eb791,
+ 0x5352d0f0, 0x2930b33b, 0xbbb8cc8c, 0xf1e5dae1,
+ 0xcddb5700, 0xccd412fa, 0xb5fa4517, 0x6a8aae03,
+ 0x1c0dc13a, 0x47013e43, 0x88fc6f8f, 0x17ffbf41,
+ 0x30f2e867, 0x147cfbbe, 0xfc45945c, 0x23e0e348,
+ 0xe2a99750, 0x033df77d, 0xa6f05555, 0x1aae25ec,
+ 0xda717415, 0xf4610818, 0xbe2bddae, 0x386a92eb,
+ 0x88b66825, 0xb50fcb42, 0xd2d8e63f, 0x57de7da2,
+ 0x9a6d7c1f, 0x0c505cda, 0x1956a144, 0x6fec0d85,
+ 0x7a53fa60, 0x87e352fc, 0x55bf363e, 0xfef43874,
+ 0x7a77924a, 0xd860f651, 0xc61517ad, 0x8c7efd7a,
+ 0x775cc7c3, 0x25865c04, 0xce86e00c, 0xf150203a,
+ 0x9c47e0f5, 0x37f68167, 0x7178f521, 0x4dbe0583,
+ 0x1a1beda1, 0xe7a80a53, 0x81d23a72, 0x3f6bb0bd,
+ 0xac766413, 0x969fbf69, 0x960c2d7a, 0xca981acb,
+ 0x5501a119, 0x133a8478, 0xc7d31778, 0x5b1d80c4,
+ 0xe3330803, 0xa1ba5969, 0x63386ba2, 0x9e6020b1,
+ 0x65a0ace1, 0xfb6e20f6, 0x25803027, 0xb8a149d4,
+ 0x1de36284, 0xa465ce6a, 0xf85a7159, 0xf33e2ff7,
+ 0xf92ef8da, 0x82815696, 0x36967915, 0xbbc78858,
+ 0xd2072258, 0x7e5ad61f, 0xa7200062, 0xb313da54,
+ 0x958e14e8, 0xe1e70460, 0xd932dbf0, 0x6e568248,
+ 0x8d5c0db4, 0xaedafdba, 0x7a9be745, 0xffce9a12,
+ 0x36f5ee32, 0x60282b4e, 0x5c82bbc8, 0x36fb1b5c,
+ 0x48de3883, 0x4e0d8941, 0x1e490452, 0xa175c35c,
+ 0xee693682, 0xf4fd8639, 0x10c7e09f, 0x0f0a0d30,
+ 0x17c7aeef, 0xa7b6202a, 0x9d9e0fd2, 0xe8f9c542,
+ 0x6c522adc, 0x30577e3e, 0x3f16ff6c, 0x985b1132,
+ 0x5ac3f934, 0xeb6cd3ff, 0x29be3fca, 0xb4429116,
+ 0x874b5519, 0xc70f2390, 0xe0882b21, 0xad040d19,
+ 0x326e8fcd, 0x14df0a3a, 0x159690d6, 0x24d7cd28,
+ 0xc7b219f4, 0x0dadd9d8, 0xe84c0ce2, 0xb3060d61,
+ 0x2a87497b, 0xa9a1856d, 0x806c4ae9, 0x1b721858,
+ 0xf4c86a45, 0xf66f194e, 0x6f39344b, 0x94c056f6,
+ 0xfce9555e, 0xd91adeca, 0xa0fed61f, 0x8c7edd45,
+ 0xf0000fe8, 0x70430870, 0x4188e944, 0xf9cd9b0f,
+ 0x74c8459a, 0xb2a20d0a, 0x3057bb1a, 0x8ca55245,
+ 0x448585eb, 0x852f52d9, 0x45e4ecdd, 0xeb482b25,
+ 0xdbdfa424, 0xdc69756b, 0xdb29c296, 0x09b8251c,
+ 0x693091df, 0x0c499ebc, 0xc4f7b4fe, 0xd8a5e949,
+ 0xb45f8f6c, 0x159c37ef, 0x4ff5c2a1, 0x6b7d6a10,
+ 0xa42ab8bc, 0xda20daa9, 0x6e43599a, 0xb44d3869,
+ 0xe710509a, 0xe2170999, 0xd83b3cda, 0x4c707a08,
+ 0x7255e8cb, 0x6ce73a0f, 0x5e88cad6, 0x02011aa4,
+ 0xdaa189bd, 0x4090c386, 0xc098086b, 0x0072efa3,
+ 0x1358ebe0, 0x32d66aca, 0x9d486694, 0xcb4945ee,
+ 0x483e72b0, 0xf6b87a80, 0x4b00c1e1, 0x05799f39,
+ 0x5f01370c, 0x6c9e46ca, 0x9277a928, 0x602d7c0b,
+ 0x5bc1ea24, 0x7a07c7ff, 0xa4aff8d6, 0xb1ccf1f8,
+ 0x509766a6, 0x07f9ff58, 0x80761ff8, 0xdf1ed8fe,
+ 0xefba6e4a, 0x46fcbacd, 0x5f35d71b, 0x6791bd55,
+ 0xafcd2d67, 0x0d581d24, 0x9994e456, 0xa6bde985,
+ 0xa1f408e8, 0x7407be94, 0xe6932458, 0x7fbd728c,
+ 0x3368e2b9, 0xb40557ed, 0x04745d32, 0x73312cbd,
+ 0xf96e2d9a, 0xfff24346, 0xb61372f5, 0xb287067c,
+ 0x247b9066, 0xdcce1fee, 0xbb0ea1f0, 0xa9a6a04b,
+ 0x2e7a8051, 0xd5f68661, 0x5cf5c462, 0x64567594,
+ 0xf32f533a, 0x9e896060, 0x9b3a1025, 0x81fb18e5,
+ 0xa34aaf4b, 0xdbfa8c30, 0x2f44af0c, 0x36404163,
+ 0x48bf986b, 0x5e39d98a, 0xb622b634, 0xc8c24190,
+ 0xdc8317a3, 0xdd833be3, 0xc25deb9a, 0x5e57e750,
+ 0x2dfeb7eb, 0x456ec1d8, 0x794188f3, 0xad861c01,
+ 0x3a37ef46, 0xab261c62, 0x1b7ab6ba, 0xb69fd41c,
+ 0x62cd7a8c, 0xfb065f17, 0xc51ac58a, 0x54bb6f7a,
+ 0xae9d323d, 0x95e45d96, 0x97168ff2, 0x62c4ac10,
+ 0x6e812251, 0x16d42973, 0x39a818a7, 0xa637d97b,
+ 0x50bc243b, 0xe2726406, 0xec5e8f30, 0xa245a2c2,
+ 0x98117f0b, 0x3be7d442, 0xb5ec6189, 0x13aa32d7,
+ 0xdab0f04e, 0xe4a200ec, 0xcad5af19, 0xcac3f8ee,
+ 0xf3aaeaa7, 0xc77bdb3f, 0x4543d0f7, 0x75f55057,
+ 0x0597c71b, 0xed80f57d, 0x3d5c5d64, 0xda33f71e,
+ 0xa89dbfec, 0x1db6e477, 0x7cac1a64, 0x242058b2,
+ 0x55cce2d9, 0xf022bc4d, 0x4fffa80a, 0x6fe5163e,
+ 0xd1024a09, 0xa64884b2, 0xc0c30f2b, 0x80ce10ba,
+ 0x7f756f72, 0xbb98620b, 0x8d02b97a, 0xb425462b,
+ 0xe70bed1f, 0x6e650358, 0xbb19a2ba, 0x12c47d9f,
+ 0x7be7bdb8, 0x157990fc, 0x7d466fc1, 0x7fe0e37e,
+ 0x81397bea, 0xbfd76cf3, 0xf5a9ed52, 0x4d6a707b,
+ 0xaf0a0e45, 0xb2dc36cb, 0x710b30d3, 0xee5b5f66,
+ 0x817546ed, 0x46997e89, 0xfbb9dc86, 0xeb092845,
+ 0xfe2fc4dd, 0xecc63e74, 0x501a8d5e, 0x66d71a2d,
+ 0x57ada923, 0x00e8c4e7, 0xab8f26ef, 0x9619e2c5,
+ 0x5879912a, 0xd8473a43, 0x5555e22c, 0xda9d4569,
+ 0x2243b8f9, 0x59583c81, 0x3e7739f4, 0x66c4e980,
+ 0x5dd574ee, 0x1aeeeb02, 0x4914c7f4, 0x8ea5339d,
+ 0x31104b0e, 0x3e9f341b, 0x069f93ac, 0x0ecb1a4b,
+ 0x0588278c, 0x8d7c2217, 0x1cc63ead, 0x13bcc4e8,
+ 0x684f566f, 0x54352461, 0x680287dd, 0x326fc71a,
+ 0x51eafc0f, 0xe39b8ef0, 0xada7199a, 0xc37be74f,
+ 0x1da19eff, 0x149a0f0c, 0x7fad40ce, 0xa4564c8f,
+ 0x4afdfa0e, 0xccc906a1, 0x6add7f59, 0x6ba06cc1,
+ 0x026e75a4, 0x3a5e9db6, 0x3875050a, 0xebef67a3,
+ 0x2455265f, 0x573bb9f4, 0xb9e4d2ee, 0x4223a560,
+ 0xed5260ed, 0x1a6c41cc, 0x222593ae, 0x10587391,
+ 0x10abf725, 0x04afc601, 0xc4a61b87, 0x35326c6c,
+ 0xca8a77d7, 0x6f4cdb44, 0xe6c8b2be, 0x06dcd66f,
+ 0xfe7bc8e8, 0xb2ff0521, 0xe6dff962, 0xe3b198b1,
+ 0xe51c6236, 0xd2cbcce0, 0x0f310acd, 0x72002cf1,
+ 0x762239e2, 0xc2fe47f6, 0x7fd4b079, 0x5ec612e7,
+ 0xc4a0be43, 0x9244f345, 0x33fc0014, 0x9bf84814,
+ 0xfcc56b71, 0xa61361cd, 0x89d09190, 0x5428d359,
+ 0xd978cfa8, 0x41169ebf, 0x73affbee, 0x97ce8d8e,
+ 0x766ead85, 0x2cd36fae, 0x5666d7ac, 0xe07dc373,
+ 0xce683608, 0x3e6650af, 0xc19366e9, 0xa52b757e,
+ 0xe67110a6, 0x41c7cc0a, 0xde426ec2, 0x8849a22d,
+ 0xcca8fd2a, 0xfaf9ffb9, 0xa3b422cb, 0xcf759bd5,
+ 0xbc10f9c0, 0xeca1563c, 0x6e40abf8, 0xbee2ac9e,
+ 0x4732c988, 0xe75bd265, 0x0bcc26c6, 0xc9d30cfc,
+ 0x1fd28683, 0x92f8be08, 0xfa5ffef1, 0x57942d33,
+ 0x4c9cf9b3, 0xe8b06003, 0x611d07d1, 0xba098978,
+ 0xc8459efe, 0xdb085aa4, 0x43f6202d, 0x0db3902c,
+ 0x63a1d9c7, 0x9ca64899, 0x1bcd45da, 0xf097e707,
+ 0xda4c001e, 0x96a530d6, 0x4578cb18, 0x37354784,
+ 0x5f627f39, 0x36c9e91e, 0x96ab1a60, 0x20f8248e,
+ 0xe58387f8, 0xf56e29bf, 0x5d13dbc8, 0x7b0afbcd,
+ 0xe688c0a5, 0x6c3fa74b, 0x2e40d5c7, 0x0f34c659,
+ 0xcdd8ffd9, 0x11e84d6a, 0x1d061f34, 0x7815b27f,
+ 0x69183d33, 0x656a33ef, 0x26038c98, 0x1fdf581d,
+ 0xdca6582b, 0x82b021b6, 0xd2cb7721, 0x39ac0233,
+ 0x50fa5905, 0xe4b1d104, 0x97b9326e, 0xf9efa816,
+ 0xde4b96e1, 0x7393fb15, 0x5ffc51db, 0xe0fe5c22,
+ 0x896262df, 0xe211528b, 0xe76f1585, 0x4a922bf0,
+ 0xd3ed057e, 0xe4162a77, 0xd413a9c2, 0xa3c7573f,
+ 0x7d112bc2, 0xf14a587a, 0x36b40df2, 0x4df43767,
+ 0x98cb1c9b, 0x82f535d6, 0x4a4f249d, 0xe9e361ba,
+ 0x51cf2fae, 0x279dcc30, 0xda36c38c, 0xab6ff70b,
+ 0xe728fad8, 0xe6633ae8, 0x0f3374b5, 0x9e688e00,
+ 0x7d006aba, 0x461c43fd, 0xb59a4764, 0xdc9a3e57,
+ 0x6e7d805b, 0xd96320ce, 0x5d5acf7a, 0x896908d0,
+ 0xa139ccfd, 0x31d85d99, 0x59463f3d, 0xcbf0edb4,
+ 0x05d0e20e, 0x880e2851, 0x380bb19d, 0x83dc5d26,
+ 0xdb26eb5c, 0x85727442, 0x42d83770, 0x4a292406,
+ 0x5ef19014, 0x6689219b, 0x45d854e7, 0x309dab92,
+ 0xa8ea4da1, 0x25a2a0dd, 0xeb32d32a, 0x2a8c21b8,
+ 0x2dff1c4a, 0x35bbdca4, 0x9109cac2, 0xc279dc89,
+ 0xa330ca60, 0xe7bdf1b8, 0x70ad6a46, 0x3f5b8ef0,
+ 0x2e73d00e, 0xedfd0c29, 0x35b42f6e, 0x0d3ca84e,
+ 0x7053e352, 0x4ac6077b, 0x59035795, 0xc7ed284a,
+ 0x890d4c0e, 0x9d47be22, 0x392cec3c, 0xd135a442,
+ 0xc8d06471, 0x91ec8d81, 0x3ea96c49, 0xe7a525ec,
+ 0x603d443d, 0xe0fa8878, 0x55da15d6, 0xaf4cceb2,
+ 0x1c446ac5, 0x8104c9df, 0xeb8d9436, 0x3cdff4c9,
+ 0x28579aac, 0x42b46085, 0xdbaaa5dd, 0xe13b4bd5,
+ 0xe0f5b5d7, 0xef01f0c6, 0x8ed65f24, 0x9cf267dc,
+ 0x15d3160e, 0x7e96f58f, 0xbf87bcdf, 0x3fe40e68,
+ 0x8427400a, 0x1457eb63, 0xdcd5c725, 0xf24d1409,
+ 0x0a656eea, 0x0019cc8d, 0xa396abd7, 0x09597ae6,
+ 0xf7fece68, 0xb8dcce22, 0xc3657e24, 0x58e90b9a,
+ 0x5c1bf05a, 0x252fdd34, 0x81e6730d, 0xfe7d5a35,
+ 0xbe5d6fa0, 0xa6dee26f, 0x211a80c7, 0x9a4ce8a6,
+ 0xeafcb0b7, 0x5101d296, 0x4920ef07, 0xa2facdee,
+ 0x5f534b8a, 0x41d32300, 0xa369e054, 0xa8f4b0ab,
+ 0x85ffa925, 0x0825793d, 0xdabc953b, 0x82af6b22,
+ 0x4ddd1dce, 0x322dc73d, 0x15609797, 0xdcc060b8,
+ 0x3e11b85d, 0x808d4418, 0xb6407ac6, 0x473a0a6a,
+ 0xf4fdd540, 0xa912e4df, 0x70258ded, 0x627ebb16,
+ 0x01782bb2, 0x006c8314, 0xdd054bf4, 0x0c65417c,
+ 0xff80542b, 0xd45486b6, 0x70dd6c40, 0x8dfd6af8,
+ 0x81f16d60, 0x1fe8eb9e, 0x62565e48, 0x325a903d,
+ 0x5953bcb7, 0xb02e999c, 0x50ae21b8, 0x8205e89c,
+ 0xadf855fe, 0xd405c2fd, 0x15bd2331, 0x77dfa0ae,
+ 0x3ec6b09e, 0x1feb017b, 0x821803db, 0x05a7b96e,
+ 0x1966f294, 0xa36935b9, 0xb8a1f857, 0x2762851d,
+ 0x4bb8a3e8, 0x2b0bc1cd, 0x7e0ab9ca, 0x96542f77,
+ 0x61b96f6d, 0xcf2d9380, 0x1818da07, 0xe55c1f16,
+ 0xfe449007, 0x1d09972f, 0x47afaa1c, 0x71c9260e,
+ 0x805a8bbf, 0x9ccc9899, 0x7feec8c0, 0x1d0b6817,
+ 0x71dae85a, 0x54aa4aea, 0xbbecdc64, 0x34d394d6,
+ 0x6fd09745, 0x2e1e2dd2, 0x3bdcf2eb, 0x487c9512,
+ 0x57cdf10e, 0xcfe7498a, 0x019a7f50, 0xebe011f6,
+ 0xc8e93ab0, 0x946847f9, 0x1bfdf3af, 0x90e64da1,
+ 0x725ad96d, 0xc16a4577, 0xaf67847c, 0xb26b9c9e,
+ 0x3cd88c06, 0x0b86cfd1, 0x3169b7ef, 0x84617014,
+ 0x171c3a84, 0xbc9bee8d, 0x7c7902d9, 0x3e3748c7,
+ 0x11462fe0, 0x8a23bb93, 0x3811da6c, 0xddec1b2e,
+ 0x7df8db3b, 0x454607bc, 0x90ba50c1, 0xf360a53f,
+ 0x035a888a, 0x1405c2ed, 0x62c78807, 0x9cc6f6b6,
+ 0xe17cdac5, 0xcfd263b0, 0xc9dd06b1, 0x5e41f4f3,
+ 0x36ab3411, 0x7b72568a, 0x7e7a3d26, 0xe81ef3c0,
+ 0xb5b5a27b, 0x7f0b9172, 0x8a185b9d, 0x302b9482,
+ 0x15375a28, 0x7ea3c41c, 0xa1aced48, 0x7c17fdc5,
+ 0x7a73401a, 0x2c874219, 0xe58f8bf2, 0x1bf22510,
+ 0x453d8af7, 0x6e51afe6, 0xdd1865ad, 0x9d1d5577,
+ 0xee060961, 0x8893b076, 0x43763c36, 0x2f51555f,
+ 0x1a152fd3, 0xca4e4cd1, 0xa28bfc2e, 0xce908e5b,
+ 0xa56daa1b, 0x5ec093cb, 0xc7e0084f, 0x861a622b,
+ 0x24faced2, 0x813cfbff, 0xd6f0db36, 0xc9c36829,
+ 0x4ef9fd81, 0x4bfe667e, 0x1b50b06f, 0x7442a6cb,
+ 0xcac5a243, 0xc04f3ce7, 0xc4977bdb, 0x7251fced,
+ 0x24665410, 0x734a09d9, 0x64ed949d, 0x83bdd716,
+ 0x03a14515, 0x802916f1, 0x62aa1f20, 0xc4c0fcef,
+ 0x516106b3, 0xfdf20fc7, 0x8c786fed, 0xe330bb8d,
+ 0xa9ae7510, 0x3bc96599, 0xa6d4575a, 0xfc7df15d,
+ 0x53917858, 0x746d3398, 0x18ec8451, 0x227288c2,
+ 0xfb9d2c06, 0x7e86b010, 0xd624f2b4, 0x6e2fbeb8,
+ 0x98fee6ef, 0x3ccacaca, 0x40daa817, 0x59ea2b0f,
+ 0x383990d7, 0x3630756e, 0x0a1dd7e0, 0xd353e00b,
+ 0xe205acc3, 0xcbab36d0, 0x0175e604, 0x19b71f87,
+ 0x77ef8163, 0xf62d1657, 0x5efba5e5, 0x043713dc,
+ 0x2ba9d339, 0x54dca0ea, 0x514ea118, 0xbdb4b32f,
+ 0x293ab65b, 0x98c3c531, 0x802f2811, 0x5d4473eb,
+ 0x276817f9, 0x087888f0, 0xc3cd6cf4, 0x034dc17d,
+ 0xd517c1fe, 0xeb6225da, 0x880eef15, 0x4c9e30ae,
+ 0x857dc578, 0x29a9f02d, 0x32590be3, 0xfe254b15,
+ 0x10596aaa, 0x530a85df, 0x67b2a03e, 0xc5136994,
+ 0x9695ffde, 0x8bf4293d, 0x40304387, 0xc8947dce,
+ 0xbf002265, 0x95cad63c, 0x4c11cbd7, 0x9367db0c,
+ 0x0a00675f, 0x441f95e7, 0xcdfe7930, 0x8cfc06ff,
+ 0x0e7c9c39, 0x3649cf9b, 0xb5465baa, 0xd2eb5b51,
diff --git a/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h b/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h
deleted file mode 100644
index 229fba2..0000000
--- a/src/cpu/intel/model_206ax/microcode-m12206a7_00000025.h
+++ /dev/null
@@ -1,611 +0,0 @@
-//+++
-// Copyright (c) <1995-2011>, Intel Corporation.
-// All rights reserved.
-//
-// Redistribution. Redistribution and use in binary form, without modification, are
-// permitted provided that the following conditions are met:
-// .Redistributions must reproduce the above copyright notice and the following
-// disclaimer in the documentation and/or other materials provided with the
-// distribution.
-// .Neither the name of Intel Corporation nor the names of its suppliers may be used
-// to endorse or promote products derived from this software without specific prior
-// written permission.
-// .No reverse engineering, decompilation, or disassembly of this software is
-// permitted.
-// ."Binary form" includes any format commonly used for electronic conveyance
-// which is a reversible, bit-exact translation of binary representation to ASCII or
-// ISO text, for example, "uuencode."
-//
-// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
-// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
-// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER
-// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
-// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//---
-/* Thu Nov 10 10:30:59 CST 2011 */
-/* m12206a7_00000025.inc */
-0x00000001, 0x00000025, 0x10112011, 0x000206a7,
-0x6aa14554, 0x00000001, 0x00000012, 0x000023d0,
-0x00002400, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x000000a1, 0x00020001, 0x00000025,
-0x00000000, 0x00000000, 0x20111011, 0x000008d1,
-0x00000001, 0x000206a7, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x00000000, 0x000008d1, 0x00000000, 0x00000000,
-0x00000000, 0x00000000, 0x00000000, 0x00000000,
-0x9d225b45, 0x6ab4c3b0, 0xebba1c32, 0x469a230a,
-0x8a7d6315, 0x2fc24d3e, 0x82506f79, 0x18dbb9d6,
-0x1a7bbeb1, 0x355a1d62, 0x2e7eb594, 0x09f8dea9,
-0x432a49e4, 0xbf520253, 0xdafa4010, 0x893a858a,
-0x766e0efb, 0xd91e196d, 0x838bd2ef, 0xe5146494,
-0xd515f413, 0x29704828, 0xe85598b6, 0xdcbe6c51,
-0x88eabbfa, 0xa1e8909f, 0xd8931721, 0x35386554,
-0x089a78a7, 0xd9914775, 0xd4644748, 0x1556a4dc,
-0xf44448f6, 0xd054d7db, 0xf30f2b7d, 0x5ae223d0,
-0xcbbb48b0, 0x5c8b0383, 0x177de157, 0x9c1e5f73,
-0x2ec28289, 0xd72a7b6c, 0x823b6eb2, 0x35e02171,
-0xba8deae4, 0x06f4d468, 0x13dbafaa, 0x72b419f1,
-0x033385b5, 0x05806920, 0x4c6034cf, 0x9bd117dc,
-0x976e2d04, 0x250330f0, 0x7250b5e1, 0x184980c2,
-0x12a9d7d6, 0x1bc808f9, 0xae79994f, 0xc6f87901,
-0xc0e3132f, 0x671491c5, 0x236cad39, 0x37889d9c,
-0x67f7c3f3, 0x964a6be5, 0xbcced7da, 0x57eeaa6e,
-0x7bca1522, 0x654fee4c, 0x2a1ca5d9, 0xa1803cf3,
-0x00000011, 0x3f96e33b, 0xbcc97e7d, 0xfecb5781,
-0x24a87ac3, 0x281fad3d, 0x6c5d0169, 0x406f3d4b,
-0x1bedf9bf, 0x514f3332, 0xb33e1926, 0x539139d4,
-0x0b5a03bb, 0x7948224c, 0x403919aa, 0xd30c64b2,
-0xb1df420a, 0xbc62cb65, 0x8b036cd8, 0x662064a0,
-0x7381ae61, 0xfb070274, 0x9a3978d9, 0x051c1cbd,
-0x7bcfb857, 0x2c94fcc0, 0x25f643f1, 0xda3d4463,
-0x8aad6318, 0xabd2966c, 0x663d015a, 0x9fe4c504,
-0x43786fce, 0xa1b3dfdc, 0x435783a4, 0x1e44e90a,
-0x85ae6018, 0x9402a6c9, 0x709f4d13, 0x1bdec841,
-0x4840a539, 0xaa446221, 0x27401d2d, 0x1e0d39c6,
-0x6ae8973f, 0xc8b603b8, 0x8044340d, 0x9a4846e1,
-0xf7e68ad9, 0xd2a0cbd1, 0xc64bf2bf, 0x51286697,
-0xf3110b6f, 0x1562e9dc, 0xc682712e, 0x5cfbda8f,
-0x0d575c4f, 0x929f8530, 0x69abd158, 0x41c783e1,
-0xbfe313de, 0x33cbec29, 0xbcbddb8a, 0xe0861b12,
-0x866f3884, 0xf3b79ad6, 0x3415ad37, 0x3a17893c,
-0xb29694df, 0xecd242ce, 0x5d8231ef, 0x5b208f8f,
-0xc781cb94, 0xeb8dc8b8, 0x9d04fd73, 0x4639b3f9,
-0x543fbc28, 0x3957879c, 0xc7f0d4a1, 0x29ac4965,
-0x10f47a96, 0xf7d5b5ce, 0x8ed0c39f, 0x5a36d20f,
-0xff5bd157, 0xf4a3152e, 0xfa9087b4, 0xe4021354,
-0x2b394395, 0x118d8abd, 0xa6ef26da, 0xe47688e5,
-0x15352ccd, 0xa2a1120c, 0xf86a3b13, 0x3453d233,
-0x74d464e9, 0x28cb0910, 0x1c0d9908, 0xf7a672c4,
-0xa725013d, 0xfd618f4a, 0x2035f826, 0x2544d00b,
-0xe6bd2f30, 0xd6e3992f, 0xf7f39f5e, 0x282a3593,
-0x00de27bf, 0x5d0470c2, 0x14473c88, 0xc763ad23,
-0x2ccd5c60, 0x71f0d333, 0x09e8b8cd, 0x716fd1e1,
-0x2dfd1003, 0x006b819f, 0x7b157ad2, 0xa6305470,
-0xcde50f1a, 0x955bc9c8, 0xbe464835, 0xf67f9b33,
-0x21ab56ea, 0xc133d4c6, 0x77d754bf, 0x130877e0,
-0xbd1b247a, 0x7840690d, 0xe6174dd0, 0x61d13bfd,
-0x675ae943, 0x9149e21b, 0xce8ddf65, 0xe06ca163,
-0x33ee3750, 0xa89318e4, 0xa5476a0f, 0x72d15429,
-0x1442d6e5, 0x13f70d65, 0x81923d22, 0x4eefbbc5,
-0x1af2cbf1, 0x052ae881, 0x2fcb621a, 0x44e6c1f6,
-0x10c0c127, 0x6132dbfc, 0x0b3e5d38, 0x18379c7c,
-0x24848ccf, 0xb929cddf, 0xbd0c9549, 0x68d44ac1,
-0xf1a4967b, 0x60d466f9, 0x60a12700, 0x6bdf875f,
-0x2d8255a9, 0x464c149d, 0x32c047ee, 0x5d744d6c,
-0xdf44c2b2, 0xda41f152, 0xb83bd853, 0x3f612ed9,
-0xcecd3f95, 0xde938fc5, 0x2120712d, 0x6e895650,
-0xa5d34947, 0xb5d7459d, 0x13df64d9, 0xf8d40e55,
-0x7f590e01, 0x1724e7cf, 0x5843ee08, 0xdce43dd9,
-0x574cae1c, 0x5ec349e6, 0x56ab1066, 0x7d518ee9,
-0x1f83b1fe, 0xac633b58, 0xcef8a5fd, 0xacf35357,
-0xa93932b1, 0x64e73ca0, 0xb824e2b0, 0xb6c68da4,
-0x287ee847, 0xec1dbf97, 0xd313d2fa, 0x9fe37eec,
-0x281d8559, 0x2fd0c6c7, 0x15e9a89a, 0x273e9932,
-0xf081dec8, 0xa04d5e16, 0x8a3ac66a, 0xe5b25b5c,
-0x4138b7b3, 0xace013c4, 0xe5bee1c8, 0xd9daafd4,
-0x952af837, 0xf28c36bf, 0xcdff2a71, 0xa1cf3b94,
-0x8821440c, 0x3693fab8, 0xd6d2d0d0, 0xa2ccd66d,
-0xe8736467, 0x8a8952f8, 0xe32db4d9, 0x47b71bdf,
-0x620f3c22, 0xdb2922a7, 0x98e5cc6b, 0x905be886,
-0x822feb82, 0xf722cf0c, 0x7a356d80, 0x9c6b3ab6,
-0x19a3cc17, 0x08dfaf09, 0x4c99a23d, 0x0926d99e,
-0xa81577e5, 0xc684495a, 0x359aa743, 0xbc7aa166,
-0xaac2e24d, 0x16110785, 0x8ccc6fbc, 0xfd90cf70,
-0xb34be19c, 0xf57fef0d, 0x9c29c8a7, 0x022c249d,
-0x946cef68, 0xe07b7779, 0x4f6ea6b4, 0xe3a4eef4,
-0xfed31061, 0x96e78ae9, 0x220c0f91, 0x30aca707,
-0xa081c7b9, 0x159dc936, 0x4cbaa290, 0x447910e2,
-0x6ec95f93, 0x3cc3fde8, 0xce2c17a1, 0x4f18c4cb,
-0x025605b1, 0xbce02471, 0x21656693, 0x9368f6cd,
-0x0c19760f, 0xcc35da81, 0x4c5edab1, 0x85a0890e,
-0xbc5b861e, 0x203a23a6, 0xddc7d7ed, 0x0b585825,
-0xec9e7ab2, 0x1f1ad49a, 0xa7444b1f, 0xe77976b4,
-0x99e8c05e, 0x8b04c7c2, 0xb1aeb88b, 0x416d07ac,
-0x5a5689be, 0xe4094686, 0xe048c8e6, 0x2e0259dd,
-0xd2fe1113, 0x6190504b, 0xa0352318, 0x6f0cae7c,
-0x040da641, 0x29fab483, 0x2e354a07, 0xab62c485,
-0xbd787e0a, 0xc345308c, 0xc8ab8568, 0xf75adc1d,
-0x82b55654, 0x6cf29bbf, 0x8786a46e, 0x433c20d2,
-0x9229c1ee, 0x5e8eedf5, 0xab9bb981, 0x1a1a5419,
-0x97994816, 0x010eef10, 0x0172fd65, 0x975b8297,
-0xff6c4377, 0x6fca39f8, 0x13accf88, 0x94f05a02,
-0x5a772f20, 0xfbf97bca, 0x60801139, 0x64cbd0a6,
-0x72512821, 0x0830cb9a, 0x402f033c, 0xd0e2a50d,
-0x7ac45ee3, 0xbae23515, 0xd213695d, 0x72016572,
-0x20651143, 0x3552bc4d, 0xf014ebb1, 0x9aeebedf,
-0xee65d90f, 0x53abd424, 0x841f5383, 0xa43a2e44,
-0xee379480, 0x1638e568, 0x2573aad0, 0x2e935090,
-0xb9dcbe13, 0x9cdc4e30, 0xce8d170c, 0xbc546d14,
-0x18b77a7b, 0x3b652642, 0x79ae26c2, 0x5ab240c2,
-0xf74cfe35, 0x30be64cf, 0x3b5e7456, 0x81be84d1,
-0x12bb10db, 0x573da6b3, 0x83e28efe, 0x395c1512,
-0xf11928ee, 0xe64d50b5, 0x6f714c8b, 0xb3393f61,
-0x13b6b2f4, 0x0ab3b2aa, 0x5cada4c7, 0x19dfb423,
-0xe7b1c195, 0x47ee32d7, 0x03ab86bd, 0x08b8a8c6,
-0xdc7a6cdf, 0x3e5b4f68, 0x9ea0e297, 0x13193f7e,
-0x8fe31f30, 0x6118a11c, 0xc0762196, 0x9fd26fc0,
-0x9f515662, 0x5a1abb55, 0x5e434855, 0x4c6af26a,
-0x163cf95d, 0xa54ee076, 0xb41a0c1a, 0xf8a8affb,
-0x69db8391, 0xa7204db3, 0x86dc9909, 0x25ba82c5,
-0x04154f7a, 0xa191c23a, 0x6f3ee8ed, 0x55162d2b,
-0x14f9478d, 0xc717fb1c, 0x91408cdd, 0x7a87a50d,
-0x44d10ceb, 0xd04b5347, 0x82a3b3ce, 0x07e3998e,
-0x1dafee6f, 0x77c24219, 0x4ff885ef, 0xd994194a,
-0xfeff078a, 0x20f4b18a, 0x529676bd, 0x17738de7,
-0x01f8491b, 0xe31d2728, 0x34e5155b, 0x87120d79,
-0xb96f615c, 0xd6d15cd2, 0x4a1f66a8, 0xa0b37474,
-0x0713a36e, 0x70df574c, 0xe6015de6, 0x5f50f282,
-0xbd828397, 0xda75bb9f, 0x13e35581, 0x5bb84a7f,
-0xf66216ca, 0xac35d098, 0xff3a8f78, 0xb43a2d55,
-0xcb820994, 0x74f97ab1, 0x0ebb37aa, 0x5457d670,
-0xc7617908, 0x5f0ad21e, 0xeb8a4b9f, 0x0c678bc7,
-0x705cb6ce, 0xc2b3ef2a, 0x89c0c723, 0xab4399a9,
-0xc2216b3e, 0x9adda9ee, 0x82c7bfa0, 0x9d56f661,
-0x0f715ee5, 0x627d8182, 0x306a00b9, 0x2d9c259c,
-0x251b933c, 0x67fbe9e7, 0x103e2322, 0x29d1c68a,
-0x8f019d2f, 0x077e80b4, 0xbbbd9c2a, 0x266f4f74,
-0x96b32213, 0x5019c61d, 0x4a59782c, 0x8810efb7,
-0xfa55eaae, 0xbabe0b82, 0x956cae7f, 0xf016453c,
-0x255e2b2a, 0x1b805b17, 0x9c9b51cb, 0x0eaafa33,
-0x45fb3835, 0x2c2070d2, 0x70005da8, 0xf39c43b4,
-0x78c372ac, 0xa6fe8b80, 0x473ab824, 0x758cf1c0,
-0x8d012210, 0x8e26dc51, 0xf8f88450, 0xd1ffe2b8,
-0xa36a40ff, 0xbed11609, 0xaaa32039, 0xbc6ee3b5,
-0x36f84b62, 0xbacf3880, 0x26af8917, 0x9c6cb47f,
-0xa2a70b0b, 0x4b003af3, 0x83d9d354, 0x7aa355ce,
-0x75ec5db9, 0xa4384855, 0x0e8ac979, 0xa55a370e,
-0xbb3af0dd, 0x42153802, 0x32531de8, 0xe57570a8,
-0xe490a98c, 0xa9a910ee, 0x453953a6, 0x1348535e,
-0xb73595c5, 0x89bcd5dd, 0x0c68cc61, 0x5e880831,
-0x65cf0e50, 0xa4ccd3ac, 0xe61f9f5f, 0x01b610b0,
-0x7387c5aa, 0x6458654f, 0x35bbb16c, 0x90e9e91c,
-0xc56957f2, 0xaadb7f70, 0x07732d08, 0xce4ad932,
-0x7fa3e135, 0x31a83cad, 0x43271bcf, 0xa74b4eab,
-0x4f483674, 0x9cc84d3c, 0x7562feb5, 0x0b445b18,
-0xc1b1b769, 0xcfd31f23, 0xdf6f0843, 0x56789e7b,
-0x0ed7daf8, 0xe28e3610, 0x0b516cac, 0x5d805128,
-0xe430861d, 0x993bc596, 0xd85434cb, 0x740f7d13,
-0xe91e0d47, 0xe518a80f, 0xf729e13a, 0xd7fde910,
-0x838697c0, 0xf25c49b6, 0x7b9a6956, 0x70c8cb88,
-0xe5befc43, 0x84e0cd72, 0x2799a866, 0x62f8241e,
-0xa13dd267, 0x675404c0, 0x107995e6, 0xd5a44abb,
-0xe8b14bc2, 0x299705c4, 0xe691d679, 0x2a72edfa,
-0x353adfa6, 0x89aa4a58, 0x22247d90, 0x5a97fc14,
-0x09843de7, 0x4537f188, 0x7cd7cb9c, 0x7395900f,
-0xa178c352, 0x96fff660, 0x3b1d36a9, 0x7872cd2c,
-0x4e8e86ac, 0x6d0d129e, 0x366d1810, 0x84e4869f,
-0x9d73317d, 0xfc92685c, 0x6b3ba9cf, 0x573d9a1f,
-0xa5e5a1bd, 0x29620cbd, 0xd7a53209, 0x156f5151,
-0x58a48a3b, 0x91e00b57, 0xf68f1270, 0xb0911b95,
-0xf33c953b, 0x7402498a, 0x7cd9d9b5, 0x7f306060,
-0x08de3b88, 0x4e1b3dfa, 0xb7f0044f, 0x1e215ef7,
-0xaa6a9016, 0xdc45a3f7, 0x6a5266f9, 0x44f25fa1,
-0x64d10347, 0xf518fca6, 0x0043e846, 0x9f768875,
-0x2338de08, 0xecb485e7, 0xe53abf19, 0xdb887ab5,
-0xb61c7a2e, 0x33ff900b, 0xf8323567, 0x34eaf959,
-0x861b3ee3, 0xb416d9a8, 0x38073e63, 0x2f05c10f,
-0x84159c49, 0xaeb0462f, 0x82c74fd4, 0x471c5d20,
-0x6c6b77b9, 0xd9e07c77, 0xe49a020b, 0x9b15469b,
-0x53a1dd1d, 0xf372f68c, 0xc42b3729, 0xee64f017,
-0x06969bc7, 0xbc538ee3, 0xec79f4dd, 0xa948e000,
-0x77e45852, 0xeba3a61e, 0x21d74dc6, 0x62c47642,
-0xa12854b5, 0x10359530, 0x181703f1, 0xae4b7bf7,
-0x567633f7, 0x585012e9, 0x74e8837e, 0xf6750d5c,
-0x31edb0be, 0xa1fbe771, 0x1414bb70, 0x5f451222,
-0x56b71fa1, 0x42fe4e54, 0xaafb543f, 0x8e861547,
-0x8281a64c, 0x9f316107, 0x156bd5db, 0xd6b8e0e9,
-0x419fe658, 0x6897a516, 0x98d60208, 0xbbf31e8a,
-0x82e78e6f, 0xbb08b49a, 0x5b5fdeb5, 0xb3a9e8da,
-0xbfc6b353, 0xfbcdcf56, 0x20732e73, 0x8026f595,
-0x99cabead, 0xa831e2aa, 0x6a70356d, 0xa1566f0c,
-0x2340d50a, 0xd9e99b6f, 0xddd31fec, 0x79479c00,
-0x66c993e9, 0x3e5a6bbb, 0xc973c063, 0xcaf97f9a,
-0x94726d54, 0x367a657d, 0x084244e0, 0xea281246,
-0x8deca641, 0xca9812de, 0x9e6c0227, 0x6572f207,
-0x3d9282ad, 0x9a5888f8, 0x437fb2f2, 0xa59fd791,
-0xf46fad2f, 0x91b04878, 0xdbe527b9, 0xddf11081,
-0xfe7aab5d, 0x535d00d2, 0x6281997a, 0xbdf3a7fb,
-0x2b00033a, 0xfa6eee8c, 0xdf2ddf1c, 0x67a47291,
-0x5fcc2258, 0x9718099f, 0xb667495e, 0x154f12da,
-0xcade895c, 0x3c5a8529, 0x06727bf8, 0x28ece4f9,
-0x881481f3, 0xa5299ac6, 0x7602f0ed, 0x9cc90020,
-0x0e6e42bc, 0x749c85a6, 0x8fff0e9f, 0x75e4e9a4,
-0xd7d1b424, 0xec83f7d6, 0x229a883e, 0x35790b38,
-0x7f973e98, 0x1198edd9, 0x15349ffa, 0x3a5224ad,
-0x135f46e2, 0xa62b3da4, 0x3924c952, 0xcf193aed,
-0x1de1ce38, 0x57d72478, 0x605c1961, 0x45f76230,
-0x55f8d7b8, 0xe26499d8, 0xd214b4b8, 0xa9939f45,
-0x36610bd1, 0x65a3d400, 0xce82c54b, 0x2e4d3e01,
-0x07fdb9ec, 0xda246930, 0x6dcf119a, 0x80904d6c,
-0xe4950422, 0xe5e8bee8, 0x19e9d0d5, 0xacecf91b,
-0x0f4edefe, 0xc1d98382, 0x7e22975d, 0x3cc17318,
-0x036df2e6, 0x8811ba2d, 0xf9a75154, 0xeb65faa4,
-0xad7b4294, 0xae8be741, 0x23009705, 0xc3ec4131,
-0xf1257f3a, 0x7472f715, 0x6e6a9a61, 0x4f54f585,
-0xdc200841, 0x05164b24, 0x633b0c72, 0x7abd83a7,
-0xc32b4865, 0x7fafd317, 0x835395a1, 0xa1989b58,
-0x3638fae8, 0xcfcb3e12, 0x8370e894, 0x39ff005a,
-0xb61a1923, 0x047e0336, 0x5a7e61bb, 0x79bf462e,
-0xb978d8e2, 0x61036c49, 0xc4590141, 0x6a1b3cc8,
-0xef911d1f, 0x037c8e5e, 0x5e03ff55, 0x1d987d84,
-0x577afd01, 0xca680678, 0xef93d41f, 0x7eb7a00d,
-0x24b96544, 0xcae6dc5c, 0x13880a0c, 0x1931eb40,
-0x120bb052, 0x9d29c0d5, 0xe8508f3e, 0x48f79aa3,
-0x620c6e62, 0xe8a32b41, 0x9ef5f0cd, 0x734ccfe1,
-0xe373ddfd, 0xa58f816a, 0xbf0a8320, 0xdc9eb021,
-0x8d111767, 0xb63f07af, 0x34a49062, 0xc766e22e,
-0x7b858a87, 0xe30429f2, 0xb9d6e6d2, 0x2a5a0a5c,
-0xa69fcc61, 0xeabc878b, 0xa1bd76a3, 0xc1e7ad18,
-0xcdbb6778, 0x26f9f4cb, 0x5c5eb98e, 0x68595618,
-0x18980a09, 0x3f2fd59f, 0xc190c9e6, 0xbf9feb9b,
-0x82904bda, 0xd8caf976, 0x17759190, 0x0e3584d7,
-0xaae29da2, 0x5af72bb9, 0x10032dfb, 0x78fb8c42,
-0xb883ecb2, 0x023b5f8a, 0x29c8fac5, 0x6c0fd4dc,
-0x566ad781, 0x7c467064, 0x40b04bd0, 0x17483069,
-0x4edb6951, 0x722e9b73, 0x6b3aa8fa, 0x6102de88,
-0xf329cc45, 0xb9d9e5c6, 0xfdd1b48a, 0x7bee844f,
-0xdaa5ba6e, 0x1a77be4e, 0xf3fff7e4, 0x77f23560,
-0x52ec1835, 0x5a3309e6, 0x66e57a4f, 0x2e09d3f9,
-0x06c8dc63, 0x41cdbae8, 0x0471a391, 0x08f42ae2,
-0xd210e0d5, 0xffb0605d, 0x2bbc723b, 0x9bb7ebac,
-0xc8b1514e, 0x988de7d9, 0x3fe2681f, 0x25d50d87,
-0x75ef655e, 0xe4b6ee36, 0x534d0ed7, 0x09bbabc5,
-0x8c98d8c1, 0xda844b84, 0xe4cc19c5, 0xa337404b,
-0x2a0274f1, 0xbd2efe16, 0x7da6a62e, 0x2ac77399,
-0xb3354115, 0x147f564d, 0x53e0081c, 0x5879feab,
-0x6677eb78, 0x7a092b8d, 0xe4767106, 0x2522d836,
-0xe41a4856, 0x44375433, 0x03e50549, 0x82a25e07,
-0x600fc53a, 0xe9df6e40, 0x270a0e39, 0x99f3c993,
-0xdf81fa72, 0x4ebfc21d, 0xca53b339, 0x774df819,
-0xa91d2d62, 0xfeb422a7, 0x5441fa53, 0x5b233223,
-0xa804fafb, 0xbd45f42a, 0x4c5e0f6b, 0xe24ef499,
-0x4910fcd6, 0xadd7dafb, 0x2fd61693, 0x4472656d,
-0xa2764e29, 0x7d599640, 0xeb70907c, 0x4a649bcc,
-0xdfc05c3f, 0xeaef2ec4, 0xf6e1145e, 0x37bcc4e4,
-0xa53dba9e, 0xf03cc163, 0xc13c6931, 0x2edc20df,
-0x078d54b7, 0xee035c4b, 0x76101348, 0x72f252c9,
-0x98f1e252, 0x14daa04f, 0xed8ffea5, 0x3d2dab6b,
-0x44e76b29, 0xcdcd35ea, 0xfdb49b6c, 0x03f54f94,
-0x2b45bc9b, 0x1f13d589, 0x6695eb7f, 0xba389af8,
-0x9d3a77e6, 0x85b5d65f, 0x8bb17ab8, 0xdb6c6029,
-0xbec995d1, 0xbee54aa1, 0x5ea9416c, 0x8ef97a5e,
-0x704b8d5c, 0xcdc04d02, 0x9c6c5475, 0x4b296402,
-0x47387a84, 0x75d7d716, 0x7fabb8c9, 0xfe635111,
-0xb87ba47b, 0xe1c1fd1b, 0x5318691c, 0x0f4ea1d0,
-0xbc473b01, 0x0fa27fb4, 0x87dfe823, 0xc0b25fc7,
-0xef102726, 0x85246ca6, 0x82530da1, 0x6e520f56,
-0x6dad6256, 0x6d085c80, 0x06d4db1a, 0x9b346bf6,
-0x0de7db35, 0x7f20a08b, 0xbc587ca1, 0xb87be5ce,
-0x792d1d77, 0xd170de23, 0xa84917cd, 0xa508a09f,
-0x80c3fb3d, 0xdce4c70c, 0xd8803517, 0xb29e7dfb,
-0x922b4c99, 0xbcac718b, 0x2c3c2933, 0x21286fbe,
-0xf323b403, 0xc4d0fde9, 0xca754bcf, 0x4f87cb96,
-0xef6ef20d, 0xfdcc7cc1, 0x25c910ed, 0x3cc3835e,
-0xbf490f6c, 0x5c38abf6, 0x1ed9ac16, 0x06d77efd,
-0xf36d3abf, 0x812c8c7e, 0xa6adf73d, 0xcfcb345a,
-0xedb6a82f, 0x47132156, 0x810b50c1, 0xd75fa9e8,
-0xa11e5166, 0x25ca93a2, 0x3f5c3d5c, 0xc35f5289,
-0x32b5a15b, 0x5a5c99b2, 0xe8a5efb9, 0x6a764bc5,
-0xc841c2b3, 0xfcbcacfc, 0x8bb897f8, 0xa3651805,
-0x9bb91956, 0xc0262cbb, 0x693c8072, 0xcb6bd69f,
-0xcf9ff920, 0xd550b6e0, 0x95602c8f, 0x444f40c7,
-0x894d4cd0, 0x0010e65d, 0x6705fd32, 0x9b9c1c49,
-0x89447cd9, 0x791d1c5e, 0x3545f4eb, 0xbd708c36,
-0x54d4ec1f, 0x8e8c7541, 0x0befc0bb, 0x604b32b1,
-0x472242d0, 0xee64a895, 0x1aa38ffb, 0x58129ee0,
-0xca4f73f8, 0x402508a0, 0x9e47bdc7, 0x68f66e41,
-0xd21fc596, 0x22c6ad97, 0x895b94dd, 0xa2504849,
-0xa2e93280, 0xdb8b1017, 0x3d5c2f41, 0xa1141892,
-0x1bc6761f, 0xddd38e05, 0x6765e5fc, 0xdaf73d22,
-0xefea8b26, 0x072db03e, 0x206395f6, 0xd1f157cc,
-0x48076326, 0x96cc1c9e, 0x5d22a18e, 0xe09876c9,
-0x49735852, 0x2d22596d, 0x83fbd660, 0xad07c37b,
-0xa7eb7c8f, 0x8749415b, 0x4e2fb8ad, 0xfd14301e,
-0x2f34bf4c, 0x0897e405, 0xdd1674fb, 0x3fbbcb6c,
-0xce64eb32, 0x635f92ee, 0x0703710a, 0x8f5bbb08,
-0x44d53fea, 0x4031aeaa, 0x6c8e46b0, 0x3ef83794,
-0xf1a53b71, 0xf9fa63ac, 0x7eee8f50, 0x372a2115,
-0xbf5778e4, 0x9a0fa641, 0x7ce02977, 0x543b876e,
-0xcdc95e5e, 0xc2b9bbe0, 0x1ce9b510, 0x53e6085a,
-0xf5a1687c, 0x5a081846, 0x2e75f4e8, 0x59435753,
-0x3b1b421a, 0x181d1935, 0x80d07eeb, 0xbbf10c83,
-0x7dab3f14, 0xb00d2bf6, 0x0f118041, 0xc36373ce,
-0x8a9727da, 0x0694ab19, 0x406262c9, 0x7d03dc82,
-0xd381fc9d, 0x8b0a38a0, 0xd02ca17b, 0xd5f1b2e4,
-0xa3073d25, 0xf7bc4bb9, 0x71d3bcfd, 0x4b581f61,
-0x8b73ebcc, 0x59e0c26a, 0xdb93fe79, 0x3cbd90ba,
-0x69914b97, 0xd3165a59, 0xd56f756e, 0xa73ecf33,
-0xb1e27146, 0xb6869cdb, 0xd1535149, 0x1abbd8cf,
-0xafab3059, 0x75802fb5, 0x9e306c2d, 0x70775bb3,
-0xeb61fefb, 0x06417435, 0x3b0677c9, 0x2052b076,
-0x3ddafb36, 0x768e1e6c, 0x9fcb0e24, 0x8c48bbb0,
-0x325b3d6e, 0x71d22a1c, 0x82a4b55f, 0x9991b978,
-0xf6395a90, 0xcef98150, 0x34bf6ba8, 0x025faf6c,
-0x16e1532f, 0x0bcbb9be, 0xb538e854, 0x50a44c93,
-0xf3bb28e8, 0xc7a58580, 0x1d0c37bc, 0x537e7a40,
-0x87ae36f9, 0xefe50765, 0x91d4e689, 0x9feea767,
-0x40633598, 0xd73d5f27, 0xb9b3dfb6, 0x871e45d5,
-0xf14b7246, 0x7e30ec5f, 0xcca72651, 0x5bf4bec9,
-0x1febf9b2, 0xd3c0cc4d, 0x7011372c, 0xe43c14c4,
-0x383a72c5, 0x0d0ad12d, 0x10351ed2, 0xed4d4eed,
-0xf6ce5995, 0xf8013eb7, 0x797e2a3a, 0x50bfb3eb,
-0x21a827f9, 0xe57f0f1c, 0x5ad1f4f7, 0x94c96972,
-0x31fd2341, 0x5c3fdc9f, 0xc9977254, 0x4ff165c9,
-0x3f2fe417, 0x6ea43e26, 0x3ebb9fb6, 0x1bc55753,
-0x70c99c08, 0xc39c0026, 0x537681b9, 0x208c21cd,
-0x0c7a5403, 0x597efcef, 0x6be988ec, 0x218165ee,
-0x844795ec, 0x7628644a, 0xdca723b8, 0xece99c20,
-0xf0cf60a0, 0x530f93a6, 0x09d5e5b7, 0xb7374d5a,
-0x6c48408f, 0x1f538e31, 0x60992c0a, 0xaf459405,
-0xcc41703b, 0x60e58f6d, 0x9490284a, 0xf17ae982,
-0x3d95264d, 0xc8392eb8, 0xab992abc, 0x1e7895e4,
-0xe8488196, 0x332ecbb8, 0x218fc7f6, 0xe98dfb71,
-0x77d7e6e5, 0xfe1fba07, 0x2542bb6f, 0x934e60ff,
-0xe0e829e9, 0x1c00b6b9, 0x85395a25, 0x69daf035,
-0x30abc36a, 0x66dd22b7, 0x6245306a, 0xaddde5c0,
-0x4e04dbd0, 0xbb5a030c, 0xa5cca2d3, 0xa2e74827,
-0x5895a5d5, 0xa469ec03, 0x952dbea9, 0x10945bfc,
-0xadded5ea, 0x0819a75f, 0x98b50299, 0x6db9ac1f,
-0x8ec51f0f, 0x9876b3e0, 0xa604a743, 0xc4daa955,
-0x0ce72bbe, 0x3d45ccdb, 0x266e63c3, 0x9a6e65ef,
-0xad49601a, 0xaefbba48, 0x684ae417, 0x7eb5d504,
-0xdb3b476d, 0x935a21cd, 0xca75a938, 0xc9b5db9f,
-0xbff1d079, 0x672f54b5, 0xb06203d6, 0x5a8c1c73,
-0xc7baad2a, 0x241cdc99, 0xacba90b9, 0x9ebf8815,
-0x00bc590e, 0xd0ca284f, 0x6ef95529, 0xa3f8fade,
-0xa8730db1, 0xa8daf232, 0xf83dbbc1, 0xe92365fd,
-0x7de3f217, 0xd8fcfe30, 0x5477e0ae, 0x113c2c12,
-0x42670906, 0x6e1c5e37, 0x53704757, 0x212a922a,
-0x80446b4b, 0xac1e5158, 0x3d5138f7, 0x531ea8ad,
-0x9c750cca, 0x72aa6f97, 0x0c25e215, 0x852d7a37,
-0xd0d8f8ff, 0x3ace7b86, 0x1535e3bb, 0x216a5a59,
-0xb5cd6f41, 0x734d63a8, 0x9454799c, 0xd4fad0e2,
-0x73669742, 0xfe67a49d, 0xc55c7355, 0x08c4e57e,
-0xef962f80, 0x9664274e, 0xd349ab2e, 0x67961ba0,
-0x63dc0bc9, 0x46a1ae19, 0x08e1627e, 0x7d6ca569,
-0x101c5ea2, 0xdab84bbb, 0x2dc55a75, 0xcd49a33a,
-0x848200de, 0xa9d13dd1, 0xbeb93d9e, 0xb11aaa1c,
-0xb8d2d50c, 0xb56a384a, 0x62913304, 0x273503f6,
-0xce3b70e9, 0x2d792155, 0x395f4fa4, 0xd285d394,
-0x04119784, 0xd311691d, 0x176a6f10, 0x1f2e7a50,
-0x51efaa32, 0xc5ee3906, 0x79125b79, 0x1d2af495,
-0xd7358d56, 0xff8e5367, 0xc4234368, 0x3c461649,
-0x197af5ba, 0xd22701f7, 0x19ccadbc, 0x808da622,
-0x0d5a41b9, 0x34292985, 0x6d57221f, 0x952150b5,
-0xf5e39633, 0x65aa7a0c, 0x238fe4ec, 0x692c6d01,
-0x0587bd92, 0x298154c5, 0xceb23846, 0xbb18653d,
-0x0e081538, 0xd4b81118, 0xb3788dbf, 0x9384e224,
-0x126ebd30, 0x6cad6a3f, 0x0915426c, 0x1547b564,
-0x22d204ce, 0xfead5812, 0x513c91dd, 0x307cf6ba,
-0x1971d8a0, 0x045f93c7, 0x27c96ae2, 0x625a1a6e,
-0x940fa029, 0x1cb12b97, 0xc00e41bb, 0x8c6a032b,
-0x469108da, 0x4505b8ab, 0x5010b78f, 0x390e0be8,
-0xf4bf5a37, 0xf3494ab2, 0x5c9084f5, 0x2a197c7a,
-0x5611276e, 0x40b8a450, 0xba4f6321, 0xc772e5cd,
-0x0ea7070e, 0xbd4afff0, 0x6a9715ec, 0x21b2e161,
-0xfac2ae9b, 0x00e5ff50, 0xceba2003, 0xcd9bf99f,
-0xa5dcc3a2, 0xeccb134d, 0x213224c5, 0x37426c43,
-0x34af1b6c, 0xe7743de6, 0xc8dd2a26, 0xee5ab984,
-0xe09ab493, 0xde0066c7, 0x37529565, 0xbd3dfe53,
-0x27202b4e, 0xbcc7a208, 0xed6f4c45, 0x82cab65e,
-0x2afc80a9, 0xd063c3c2, 0xf41d48f4, 0xdc5fefee,
-0x4111aa68, 0xb20bef31, 0xf8004c44, 0x1c632882,
-0xd2530ec9, 0x4e956f3b, 0x240d5d12, 0x3dac3b36,
-0x2970d02a, 0xefa4c0eb, 0x950537cf, 0xcdc9d1b9,
-0x25449a3d, 0x1e76f046, 0x708114f9, 0x02a9ad00,
-0x5186ab9f, 0x8a301145, 0x8175f0f4, 0xacdff2ab,
-0xbaca756d, 0x65d33620, 0xe35a5db7, 0x69bb75cb,
-0x2f5c123d, 0x841f9c77, 0xffcf384e, 0x3aa6d707,
-0x3207be98, 0x83784052, 0x4eb0c27d, 0x6def8ca4,
-0x427910cf, 0x28bfceb8, 0x0ebda330, 0x9850fd1e,
-0x81e639f4, 0xa838aa33, 0x0174e6e7, 0xd768e4a2,
-0x2abe1041, 0x9cc6ecd8, 0x58c20300, 0x5824ebfa,
-0xadb81dfc, 0x3770a8b2, 0x473d8f26, 0x1e775e35,
-0x259f5ad7, 0x13fef5c5, 0x3aa92640, 0x5a76c79b,
-0xdfa3ff6b, 0x43d6bba4, 0xae2a900e, 0x8c698a3e,
-0x51ce5a96, 0x66908c24, 0x0911f46e, 0x70d619f7,
-0x972efb65, 0xb5c23792, 0x1b3ee153, 0x909746c1,
-0x8370fa25, 0xbcde8c5c, 0x1aa4f41d, 0x373a398a,
-0x3c8559a2, 0x4b528ba2, 0x54019afe, 0xe409c632,
-0x160581e2, 0x7e30d7d4, 0xf841f0a0, 0xdc1d200a,
-0x46ed47de, 0x0f77093c, 0xac835c24, 0x2ce29974,
-0xc031bfe9, 0xe879d971, 0xa67200ee, 0x3fe62089,
-0x90a38599, 0xcf7107d2, 0x45b49b01, 0xebb5ad89,
-0x8f42d795, 0x77b19427, 0x800e71fa, 0x6bc93b64,
-0xc0cdf4d6, 0x97dc9d9f, 0x7cf2edd3, 0xcb482372,
-0x6221fd9e, 0x84492515, 0xbd2b7283, 0xfc15f19e,
-0x547a79ae, 0x73337e65, 0xec64a1de, 0x822bf271,
-0x65c6b44a, 0x6d3246ea, 0x464aa85a, 0xd5110102,
-0x2578e4ef, 0xb5c4273f, 0xef03fde4, 0x1c5358fd,
-0x9b30fb66, 0x214b5514, 0xc7c50eb5, 0x76372928,
-0x5ec235f3, 0x20df4fbc, 0x12c684c5, 0x141308c1,
-0x1ffda6ae, 0x1a64f972, 0xad2f29b8, 0x4de7315a,
-0xd0fa953d, 0x8c55fe93, 0xa375129d, 0xd120f9b8,
-0xbb20cb19, 0x535d873d, 0x1fa8e047, 0x6dd4c1f5,
-0xd456632c, 0xa388867b, 0x762656d5, 0x00812012,
-0x1225a049, 0xf7900f05, 0x5b50f75d, 0xf720a919,
-0xbb8dcb70, 0xa6d48d13, 0xf750522c, 0x8ad277b3,
-0x334daf09, 0x5f882b42, 0x38a53713, 0xe9bbeef7,
-0xcc7fd1d6, 0xda484573, 0x4b3e2894, 0xbc0ef5ab,
-0xb2be1128, 0x88f27a64, 0x84ccdf55, 0x93aca22b,
-0x80b9641e, 0xa2bc2354, 0x5d78ca97, 0xb36ab105,
-0xdeb4d233, 0xe7e653bc, 0x7a29de17, 0x950c7ece,
-0xca5e997c, 0x5b8d4b6c, 0xaa5b0c7f, 0x2048cacf,
-0x71bd96bf, 0x580520f9, 0xc4da2129, 0xa3f0d78e,
-0x5235e085, 0x30c220c3, 0x2edbb5eb, 0xd12227ed,
-0x67f8faf5, 0x0d5f8ef1, 0xd8176ac6, 0x1ee955f7,
-0x13b75133, 0xb935ee9d, 0xdfe2d54f, 0x43ff1de9,
-0x6e848017, 0x4011e255, 0x5180f71b, 0x72ed0330,
-0xc737adbd, 0x7f6839a6, 0x142bd2d2, 0x66d6143b,
-0x69cf3cd0, 0x9b492cb9, 0x3266f995, 0x8ce763fe,
-0xdf8493e0, 0x8a981e31, 0xe6351c8e, 0xb0fd34fe,
-0xdc236978, 0x385f0118, 0x1c44fcdb, 0xcf70bb77,
-0x6046d066, 0x2d9475af, 0x3799ac4b, 0xe9efc39c,
-0x90d0450c, 0xa40a5fc6, 0xcfb5ef83, 0x049854c0,
-0x7215e231, 0x0424cc7e, 0x56ad0075, 0xff0a28a0,
-0x7488be97, 0xe1f82798, 0xc445794d, 0xeb7dd129,
-0x631403b5, 0xfcfd85de, 0xbf795cac, 0x00aafac9,
-0x6a2fe3ec, 0x294c2bde, 0x12861212, 0xddff6bfb,
-0xb0b29b5a, 0x46387e2d, 0x4a5a42a2, 0x4549f462,
-0x4f20df9b, 0xd189a190, 0x0ef70bb7, 0xa544ce4b,
-0x44a69377, 0x5e8c0f35, 0x2ecf5b5c, 0x0c1b08be,
-0x7f054c31, 0x73ed91a2, 0x82cd81c4, 0xf693111c,
-0x1ce7be10, 0x55d7acf8, 0x015c32a7, 0x5a3d7795,
-0x1372ac6d, 0x038755f6, 0xd1ed8be2, 0xe1b2bd04,
-0x20f3c81c, 0x326ffd81, 0x658c1e11, 0x37f74017,
-0x0a8388b2, 0xa8e74512, 0xcb9f97ab, 0x3588376e,
-0x483048d2, 0xe3ee2145, 0x029eba71, 0x2a6efdb8,
-0x7e629d7c, 0xe7458f31, 0xd2edd71b, 0xa265588c,
-0xee3a7a3d, 0xc3f6a74d, 0xb55fbbb2, 0xac3dc469,
-0x350e24ac, 0xfdfb094c, 0xc6760d93, 0x014aad92,
-0x4bf74e51, 0x9ab932af, 0xc600d00f, 0x5dd0c96d,
-0x6b081fbe, 0xecba3e1c, 0x19abcf55, 0x46905ea0,
-0x41ff2a8f, 0x9305e1c0, 0xdbfa1df1, 0x8100370e,
-0x0df9b3df, 0x09763efc, 0x60447b79, 0xb64eb88a,
-0xe4c706de, 0x2dadc973, 0xf6bc6357, 0x7395486a,
-0xf15aae31, 0x1daca268, 0xa5b8395f, 0x127bcb11,
-0xe84c9715, 0xe0417152, 0xc3d8520e, 0x0bdcbb00,
-0xf3daba82, 0xe1925ffb, 0x3526a2e8, 0xda189c78,
-0xa32bf2fc, 0xe7de02ab, 0x2f344593, 0x07b916dd,
-0xe2d46b57, 0x83921885, 0x6f066626, 0x7ce5ab67,
-0xebcaf5de, 0xbb0f6b00, 0x6d1faffb, 0x1eff0018,
-0x2debe6bc, 0x57d003b3, 0x3a3f5f80, 0xec6b7c0e,
-0x9f1dd663, 0xbebdbf56, 0x98e5774e, 0xb7a29504,
-0x5166a8c5, 0xaf7ce332, 0xca5e70c5, 0xfe235309,
-0x9c23f707, 0x99b08cc4, 0x2fe1edd1, 0xba36918f,
-0x262dd395, 0x423edc8c, 0x801e8f1f, 0x5b4cc6c5,
-0x3fcdf7f4, 0x5a490992, 0xd4006978, 0x977e2f86,
-0x6311af7b, 0x06bb2412, 0x2be72eb1, 0x5706b252,
-0xa000c75b, 0xe3ea5cff, 0xc9208730, 0xd9e369fb,
-0x1aed50e2, 0x8916d70d, 0x87f01eb6, 0x663b8f67,
-0x3dc68ee3, 0x5197b72b, 0xddb19fb8, 0x6839be2a,
-0x99fcfc25, 0x5542f267, 0xa922eea9, 0xc9ae9d93,
-0xcf8a9d64, 0x76bfeec4, 0xacbcd4c6, 0x81960ab0,
-0x7b24eb81, 0x8e8cad81, 0xfb2c1362, 0x9ccf1224,
-0x16d2c962, 0x18f7d553, 0x2a7f9c1e, 0x3678f775,
-0x1210588a, 0xe1644769, 0x3dd29db7, 0xbe9daa2c,
-0xe9c4e13a, 0x8d9de528, 0x19c3075e, 0x68a336d4,
-0x0ba157f3, 0xe3780ca6, 0x69c54c28, 0x9f96bb00,
-0xa78204e9, 0x1c8627cf, 0x2fd52aa9, 0x957b15ed,
-0xd3d61e03, 0x658cea71, 0x42d77750, 0x0c0755bc,
-0xde372a0d, 0x0d3687d7, 0xc04c56f6, 0xc3882257,
-0x98fd462c, 0xb65fac1e, 0x01b5ecab, 0xd554413d,
-0xb4beec40, 0xb4caab5e, 0xdeee4085, 0xd1b0500c,
-0x6845de70, 0x5a06e889, 0xfc89a4a7, 0xedbfd435,
-0xac039058, 0x9c1acd2f, 0x876fbfac, 0x9d8b83f3,
-0x8aa71c5f, 0x2e0f12ef, 0x87ff0c68, 0x53a9d19a,
-0x0ee62d27, 0x5d93a3f4, 0x7f13dc77, 0xd4ec7c79,
-0xd72a35c8, 0xb84ba058, 0x21e1d1ad, 0xbcf9c0fe,
-0x106fb166, 0x84ff4a86, 0x3b2d960f, 0x4cf3ab0e,
-0x65d25f76, 0xdcda7e29, 0xc444ddc8, 0xe97096dc,
-0xbfe1815c, 0x25b9dec5, 0x7aed80de, 0x6cbb6f7a,
-0x2daf76b7, 0x249ee47f, 0xdc6e770d, 0xa5a02e7d,
-0xd019d0d7, 0x17feead1, 0xbf80c1f6, 0x83644ac0,
-0x412f1ce4, 0x59c1de41, 0x1a47db26, 0x8848ab89,
-0xc2c17745, 0x31183c80, 0x9bb13cc3, 0x6da9c349,
-0x414b378d, 0xd58df4ba, 0x41f5ca37, 0x02a5162f,
-0x2843bb24, 0xbd2bb85a, 0x0b2c6e81, 0x2d50fe1d,
-0xc67b2c07, 0x630ce2b3, 0x73274d84, 0x3b4ba900,
-0x5e672d3c, 0x7ef23846, 0x81036625, 0x380b3d3b,
-0x391470b1, 0x5b3dcbed, 0x63038751, 0xa0c7aed8,
-0xc185b677, 0x516b8170, 0xbf79f025, 0x2b4c9edb,
-0x29354139, 0x9deabe33, 0x2838f581, 0x0574281f,
-0xc1267da2, 0x0c070755, 0x6832a8b9, 0x57436eed,
-0xe604c645, 0x4f13172a, 0x3227ac12, 0xf6b78267,
-0xbbd5d003, 0x5f8ae7ed, 0x74b6682c, 0x356b9e81,
-0x82703c20, 0x8ccf1f78, 0xa6b79197, 0x434d5316,
-0x1ba0853a, 0xe6ae4829, 0x1193ed0a, 0xa2d171f0,
-0x4f565a15, 0xf78ea4af, 0xa9a27e39, 0x30a45316,
-0xc005a8f6, 0x79a23d86, 0x07edcbe3, 0x3b76806b,
-0x3df6268a, 0xb0f33186, 0x2fd51855, 0xb34efefe,
-0xa24ce423, 0x6c62d711, 0x335c7252, 0x0d2ddcff,
-0x64485539, 0x00c8a89e, 0x4827ad2d, 0x01de50f4,
-0x593a9a38, 0xee90b919, 0xf523cd40, 0x97ed7009,
-0x1038e6b0, 0x95931966, 0xaaac22b9, 0xef1b9915,
-0x23f6d33c, 0xe417a460, 0x4e9b59c2, 0x3fd38b75,
-0x7ceabd08, 0x8279d672, 0xf24936e8, 0x668630f8,
-0x3cb0ddc0, 0x56c56418, 0x91221ef8, 0xc8926c65,
-0x4d7436b6, 0xc06b5b1e, 0xdea496b1, 0x4fa4c971,
-0xeea15028, 0x7aead456, 0x1329b826, 0xcf9a4d4f,
-0xabd69aba, 0x9dd78c2e, 0x5e9782ff, 0x563f3cb0,
-0xfc2db55c, 0xb2d5f64b, 0x9478caeb, 0x7409ae76,
-0xc4690516, 0xb12bb352, 0xad5283c7, 0x608e7a23,
-0xc8b4b59a, 0x0da06391, 0x9a6ccd78, 0xe4af91ad,
-0xb156f74a, 0x790b21dd, 0x6ce9970b, 0x46e89ac1,
-0x07815d28, 0x1f2fc3ac, 0x690cd168, 0x6ae48bb4,
-0x1ed48c84, 0xe5f121a3, 0x49a762cf, 0xc5e8fd6a,
-0x75d45162, 0xf49c2c5e, 0xd161eb4a, 0xb6351b73,
-0xc2605562, 0xb097aa9d, 0x114421ee, 0xf93baf78,
-0x82b9b2ab, 0x0374be4d, 0xd715656b, 0x3524549f,
-0xb37dc283, 0xfa8308d0, 0x3f69f2be, 0x238bc31e,
-0x839f3f68, 0x0639b8d7, 0xa8cdbe8e, 0xd15c7cb3,
-0x0a31ec87, 0x39a57286, 0x7c3ffef5, 0x461d70b2,
-0x7d1e8a90, 0x629b803f, 0x351b6cb8, 0x255391c2,
-0x07215420, 0x5e1aef8c, 0xa3b48e74, 0x8fa78c73,
-0xb6fab65c, 0xb13cb77f, 0x5bd44236, 0x31cbeab2,
-0x9f68d29a, 0x207a2b05, 0x668ac8a7, 0xb6de6033,
-0x3d2a4173, 0x04a2543a, 0x559b1b7c, 0x5e9116d4,
-0x5cb3ee57, 0x4a47f644, 0x90be9381, 0xbccc9cd2,
-0x3160e0d5, 0xed791f87, 0xdd9da7a8, 0x3e6d398b,
-0x6a68ad78, 0x418974ef, 0xfd010940, 0x8bed7055,
-0xf21e4d13, 0xac8160b9, 0x85f10ecb, 0xd637b0e2,
-0x987dd54e, 0x9835f225, 0xdbee940c, 0x9a34e16d,
-0x15fcfb54, 0x6720e48c, 0x9a42e266, 0x31eb0270,
-0x714dee04, 0xbcd417d8, 0xedf7757e, 0x099c4e89,
-0xee3e6c2e, 0x6246d530, 0xfbdad1d6, 0xbbe301a3,
-0xe08f829c, 0xa3c7d9c4, 0xe753a1dd, 0xf1466da1,
-0xa1e353a7, 0x33828150, 0x267d4059, 0x458bd806,
-0xac0ed307, 0x2079bf7c, 0xb25200db, 0x9dfd338c,
-0x0b94573e, 0x8188fa16, 0x9e641b63, 0xafa2a60c,
-0x61e5f820, 0x63a38983, 0x172d3a6f, 0xc98a34b2,
-0x532b56f5, 0x1883cb1a, 0x93ba9692, 0x7d85d109,
-0xd20ffd1a, 0xcc6e9937, 0xb3813eb1, 0xea7e1b45,
-0xf1e09c71, 0x35aa1ab9, 0xbd2d43d7, 0xc53a07ef,
-0xf3fa3fd6, 0xf3cd1e20, 0x5e620481, 0xd7bec1b0,
-0xc7d3caf6, 0xe9eae29f, 0x19c5b2c1, 0x940e3186,
-0x200f0a30, 0xbaf511b1, 0x103cb39c, 0x3f46b067,
-0xba6c5e9a, 0xc32b5592, 0x393e8503, 0x7ea29847,
-0x04d4a493, 0x18fc67d5, 0xea4ff94e, 0xc0281d5e,
-0xaeeaae85, 0x13be6b70, 0xa1bc8be4, 0xa1edbe06,
-0x572b8b35, 0x3baca7c5, 0x06ac9591, 0x8309b11d,
-0x7f381b05, 0xb16dd9b2, 0xf9b5d898, 0xb2e04c3a,
-0xed89b7dd, 0xd30e7e33, 0x4ac6cb61, 0xd2c50800,
-0x6554ae61, 0xa263efe2, 0x666244c3, 0xb6aaa480,
-0xcb4344ee, 0x31cf3efa, 0x14a4a476, 0xf6804765,
-0xaca47c23, 0x7e15ae69, 0xaffade7d, 0x693a6ff9,
-0x3f0f22c0, 0xe6135bcb, 0xf0632009, 0x06fa2abb,
-0xad0c1085, 0x3ce130b3, 0x70001594, 0xd80c452b,
-0x486c9d1f, 0x93b94966, 0x81612f95, 0x7573faea,
-0x1568ddb9, 0x3c1d26e5, 0x0a5d7b45, 0x5ea78077,
-0x1c5491f9, 0x24363c4b, 0x54b8e62a, 0xb86697e6,
-0x18750c76, 0xa355cee8, 0x9c09de46, 0xb022ec2b,
-0xfa142272, 0xd1e1dcce, 0xc7c2f6c9, 0xd8e72fc1,
diff --git a/src/cpu/intel/model_206ax/x06_microcode.h b/src/cpu/intel/model_206ax/microcode_blob.h
similarity index 72%
rename from src/cpu/intel/model_206ax/x06_microcode.h
rename to src/cpu/intel/model_206ax/microcode_blob.h
index d055b2e..fc3d202 100644
--- a/src/cpu/intel/model_206ax/x06_microcode.h
+++ b/src/cpu/intel/model_206ax/microcode_blob.h
@@ -18,11 +18,14 @@
*/
-#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
- #include "microcode-m12206a7_00000025.h"
-#elif CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
-#else
-#error "Which microcode to use?"
+ #include "microcode-M12206A7_00000028.h"
+#if CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
+ #include "microcode-M12306A2_00000008.h"
+ #include "microcode-M12306A4_00000007.h"
+ #include "microcode-M12306A5_00000007.h"
+ #include "microcode-M12306A6_00000002.h"
+ #include "microcode-M12306A8_00000010.h"
+ #include "microcode-M12306A9_00000012.h"
#endif
/* Dummy terminator */
0x0, 0x0, 0x0, 0x0,
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 3343d11..a7ca04a 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -22,15 +22,19 @@
#ifndef _CPU_INTEL_MODEL_206AX_H
#define _CPU_INTEL_MODEL_206AX_H
-/* SandyBridge bus clock is fixed at 100MHz */
+/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100
#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
+#define MSR_FLEX_RATIO 0x194
+#define FLEX_RATIO_LOCK (1 << 20)
+#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
#define IA32_MISC_ENABLE 0x1a0
+#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
@@ -75,24 +79,35 @@
#define MSR_PP0_CURRENT_CONFIG 0x601
#define PP0_CURRENT_LIMIT (112 << 3) /* 112 A */
#define MSR_PP1_CURRENT_CONFIG 0x602
-#define PP1_CURRENT_LIMIT (35 << 3) /* 35 A */
+#define PP1_CURRENT_LIMIT_SNB (35 << 3) /* 35 A */
+#define PP1_CURRENT_LIMIT_IVB (50 << 3) /* 50 A */
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_SKU 0x614
#define MSR_PP0_POWER_LIMIT 0x638
#define MSR_PP1_POWER_LIMIT 0x640
+#define IVB_CONFIG_TDP_MIN_CPUID 0x306a2
+#define MSR_CONFIG_TDP_NOMINAL 0x648
+#define MSR_CONFIG_TDP_LEVEL1 0x649
+#define MSR_CONFIG_TDP_LEVEL2 0x64a
+#define MSR_CONFIG_TDP_CONTROL 0x64b
+#define MSR_TURBO_ACTIVATION_RATIO 0x64c
+
/* P-state configuration */
#define PSS_MAX_ENTRIES 8
#define PSS_RATIO_STEP 2
#define PSS_LATENCY_TRANSITION 10
#define PSS_LATENCY_BUSMASTER 10
+#ifndef __ROMCC__
#ifdef __SMM__
/* Lock MSRs */
void intel_model_206ax_finalize_smm(void);
#else
/* Configure power limits for turbo mode */
void set_power_limits(u8 power_limit_1_time);
+int cpu_config_tdp_levels(void);
+#endif
#endif
#endif
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
index 874ce4d..0f4a99a 100644
--- a/src/cpu/intel/model_206ax/model_206ax_init.c
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -37,6 +37,7 @@
#include <pc80/mc146818rtc.h>
#include <usbdebug.h>
#include "model_206ax.h"
+#include "chip.h"
/*
* List of suported C-states in this processor
@@ -115,45 +116,6 @@
{ 0 }
};
-static const uint32_t microcode_updates[] = {
- #include "x06_microcode.h"
-};
-
-static void enable_vmx(void)
-{
- struct cpuid_result regs;
- msr_t msr;
- int enable = CONFIG_ENABLE_VMX;
-
- msr = rdmsr(IA32_FEATURE_CONTROL);
-
- if (msr.lo & (1 << 0)) {
- printk(BIOS_ERR, "VMX is locked, so enable_vmx will do nothing\n");
- /* VMX locked. If we set it again we get an illegal
- * instruction
- */
- return;
- }
-
- regs = cpuid(1);
- printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling");
- if (regs.ecx & CPUID_VMX) {
- if (enable)
- msr.lo |= (1 << 2);
- else
- msr.lo &= ~(1 << 2);
-
- if (regs.ecx & CPUID_SMX) {
- if (enable)
- msr.lo |= (1 << 1);
- else
- msr.lo &= ~(1 << 1);
- }
- }
-
- wrmsr(IA32_FEATURE_CONTROL, msr);
-}
-
/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
static const u8 power_limit_time_sec_to_msr[] = {
[0] = 0x00,
@@ -212,6 +174,19 @@
[0x11] = 128,
};
+int cpu_config_tdp_levels(void)
+{
+ msr_t platform_info;
+
+ /* Minimum CPU revision */
+ if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID)
+ return 0;
+
+ /* Bits 34:33 indicate how many levels supported */
+ platform_info = rdmsr(MSR_PLATFORM_INFO);
+ return (platform_info.hi >> 1) & 3;
+}
+
/*
* Configure processor power limits if possible
* This must be done AFTER set of BIOS_RESET_CPL
@@ -268,6 +243,14 @@
/* Power limit 2 time is only programmable on SNB EP/EX */
wrmsr(MSR_PKG_POWER_LIMIT, limit);
+
+ /* Use nominal TDP values for CPUs with configurable TDP */
+ if (cpu_config_tdp_levels()) {
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ limit.hi = 0;
+ limit.lo = msr.lo & 0xff;
+ wrmsr(MSR_TURBO_ACTIVATION_RATIO, limit);
+ }
}
static void configure_c_states(void)
@@ -323,10 +306,35 @@
/* Secondary Plane Current Limit */
msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
msr.lo &= ~0x1fff;
- msr.lo |= PP1_CURRENT_LIMIT;
+ if (cpuid_eax(1) >= 0x30600)
+ msr.lo |= PP1_CURRENT_LIMIT_IVB;
+ else
+ msr.lo |= PP1_CURRENT_LIMIT_SNB;
wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
}
+static void configure_thermal_target(void)
+{
+ struct cpu_intel_model_206ax_config *conf;
+ device_t lapic;
+ msr_t msr;
+
+ /* Find pointer to CPU configuration */
+ lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+ if (!lapic || !lapic->chip_info)
+ return;
+ conf = lapic->chip_info;
+
+ /* Set TCC activaiton offset if supported */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+ msr = rdmsr(MSR_TEMPERATURE_TARGET);
+ msr.lo &= ~(0xf << 24); /* Bits 27:24 */
+ msr.lo |= (conf->tcc_offset & 0xf) << 24;
+ wrmsr(MSR_TEMPERATURE_TARGET, msr);
+ }
+}
+
static void configure_misc(void)
{
msr_t msr;
@@ -373,16 +381,24 @@
static void set_max_ratio(void)
{
- msr_t msr;
+ msr_t msr, perf_ctl;
- /* Platform Info bits 15:8 give max ratio */
- msr = rdmsr(MSR_PLATFORM_INFO);
- msr.hi = 0;
- msr.lo &= 0xff00;
- wrmsr(IA32_PERF_CTL, msr);
+ perf_ctl.hi = 0;
+
+ /* Check for configurable TDP option */
+ if (cpu_config_tdp_levels()) {
+ /* Set to nominal TDP ratio */
+ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL);
+ perf_ctl.lo = (msr.lo & 0xff) << 8;
+ } else {
+ /* Platform Info bits 15:8 give max ratio */
+ msr = rdmsr(MSR_PLATFORM_INFO);
+ perf_ctl.lo = msr.lo & 0xff00;
+ }
+ wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
- ((msr.lo >> 8) & 0xff) * 100);
+ ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
}
static void set_energy_perf_bias(u8 policy)
@@ -457,12 +473,14 @@
cpu->path.apic.apic_id,
new->path.apic.apic_id);
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
/* Start the new cpu */
if (!start_cpu(new)) {
/* Record the error in cpu? */
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
+#endif
}
}
@@ -474,8 +492,7 @@
/* Turn on caching if we haven't already */
x86_enable_cache();
- /* Update the microcode */
- intel_update_microcode(microcode_updates);
+ intel_update_microcode_from_cbfs();
/* Clear out pending MCEs */
configure_mca();
@@ -508,15 +525,15 @@
enable_lapic_tpr();
setup_lapic();
- /* Enable virtualization if enabled in CMOS */
- enable_vmx();
-
/* Configure C States */
configure_c_states();
/* Configure Enhanced SpeedStep and Thermal Sensors */
configure_misc();
+ /* Thermal throttle activation offset */
+ configure_thermal_target();
+
/* Enable Direct Cache Access */
configure_dca_cap();
diff --git a/src/cpu/intel/model_6ex/Kconfig b/src/cpu/intel/model_6ex/Kconfig
index 31d24bd..e2b1986 100644
--- a/src/cpu/intel/model_6ex/Kconfig
+++ b/src/cpu/intel/model_6ex/Kconfig
@@ -4,3 +4,4 @@
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
+ select TSC_SYNC_MFENCE
diff --git a/src/cpu/intel/model_6fx/Kconfig b/src/cpu/intel/model_6fx/Kconfig
index 851685c..4517f17 100644
--- a/src/cpu/intel/model_6fx/Kconfig
+++ b/src/cpu/intel/model_6fx/Kconfig
@@ -4,3 +4,4 @@
select SSE2
select UDELAY_LAPIC
select AP_IN_SIPI_WAIT
+ select TSC_SYNC_MFENCE
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index 0eaee2e..e85a76b 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -27,6 +27,22 @@
bool
default n
+config TSC_SYNC_LFENCE
+ bool
+ default n
+ help
+ The CPU driver should select this if the CPU needs
+ to execute an lfence instruction in order to synchronize
+ rdtsc. This is true for all modern AMD CPUs.
+
+config TSC_SYNC_MFENCE
+ bool
+ default n
+ help
+ The CPU driver should select this if the CPU needs
+ to execute an mfence instruction in order to synchronize
+ rdtsc. This is true for all modern Intel CPUs.
+
config XIP_ROM_SIZE
hex
default ROM_SIZE if ROMCC
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index bb6cca7..c7b0aa7 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -50,6 +50,7 @@
timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
break;
case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+ case 0x3a: /* IvyBridge BCLK fixed at 100MHz*/
timer_fsb = 100;
break;
default:
@@ -79,7 +80,9 @@
{
u32 start, value, ticks;
- if (!timer_fsb)
+ if (!timer_fsb || (lapic_read(LAPIC_LVTT) &
+ (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED)) !=
+ (LAPIC_LVT_TIMER_PERIODIC | LAPIC_LVT_MASKED))
init_timer();
/* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index e491d46..540791c 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -1,8 +1,24 @@
/*
- 2005.12 yhlu add coreboot_ram cross the vga font buffer handling
- 2005.12 yhlu add CONFIG_RAMBASE above 1M support for SMP
- 2008.05 stepan add support for going back to sipi wait state
-*/
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2001 Eric Biederman
+ * Copyright (C) 2001 Ronald G. Minnich
+ * Copyright (C) 2005 Yinghai Lu
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
#include <cpu/x86/lapic.h>
#include <delay.h>
@@ -16,7 +32,15 @@
#include <cpu/cpu.h>
#include <cpu/intel/speedstep.h>
-#if CONFIG_SMP
+#if CONFIG_HAVE_ACPI_RESUME
+char *lowmem_backup;
+char *lowmem_backup_ptr;
+int lowmem_backup_size;
+#endif
+
+extern char _secondary_start[];
+
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
/* This is a lot more paranoid now, since Linux can NOT handle
* being told there is a CPU when none exists. So any errors
* will return 0, meaning no CPU.
@@ -26,28 +50,23 @@
*/
static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
{
- return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
+ // 16 bit to avoid 0xa0000
+ return (unsigned long)orig_start_eip & 0xffff;
}
-#if CONFIG_HAVE_ACPI_RESUME
-char *lowmem_backup;
-char *lowmem_backup_ptr;
-int lowmem_backup_size;
-#endif
-
-extern char _secondary_start[];
-
-static void copy_secondary_start_to_1m_below(void)
+static void copy_secondary_start_to_lowest_1M(void)
{
extern char _secondary_start_end[];
unsigned long code_size;
unsigned long start_eip;
- /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
- Also We need to copy the _secondary_start to the below 1M region
- */
+ /* _secondary_start need to be masked 20 above bit, because 16 bit
+ * code in secondary.S. Also we need to copy the _secondary_start
+ * to the below 1M region.
+ */
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
- code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
+ code_size = (unsigned long)_secondary_start_end -
+ (unsigned long)_secondary_start;
#if CONFIG_HAVE_ACPI_RESUME
/* need to save it for RAM resume */
@@ -61,9 +80,12 @@
memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
#endif
/* copy the _secondary_start to the ram below 1M*/
- memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
+ memcpy((unsigned char *)start_eip,
+ (unsigned char *)_secondary_start, code_size);
- printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
+ printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, "
+ "code_size=0x%08lx\n", start_eip,
+ ((unsigned long)_secondary_start - start_eip), code_size);
}
static int lapic_start_cpu(unsigned long apicid)
@@ -98,14 +120,15 @@
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n",
- apicid);
+ printk(BIOS_ERR, "CPU %ld: First APIC write timed out. "
+ "Disabling\n", apicid);
// too bad.
printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
printk(BIOS_ERR, "Try to reset ESR\n");
lapic_write_around(LAPIC_ESR, 0);
- printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+ printk(BIOS_ERR, "ESR is 0x%lx\n",
+ lapic_read(LAPIC_ESR));
}
return 0;
}
@@ -129,8 +152,8 @@
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n",
- apicid);
+ printk(BIOS_ERR, "CPU %ld: Second apic write timed out. "
+ "Disabling\n", apicid);
// too bad.
return 0;
}
@@ -203,7 +226,8 @@
if (send_status)
printk(BIOS_WARNING, "APIC never delivered???\n");
if (accept_status)
- printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status);
+ printk(BIOS_WARNING, "APIC delivery error (%lx).\n",
+ accept_status);
if (send_status || accept_status)
return 0;
return 1;
@@ -217,44 +241,58 @@
* for select the stack from assembly language.
*
* In addition communicating by variables to the cpu I
- * am starting allows me to veryify it has started before
+ * am starting allows me to verify it has started before
* start_cpu returns.
*/
static spinlock_t start_cpu_lock = SPIN_LOCK_UNLOCKED;
-static unsigned last_cpu_index = 0;
+static unsigned int last_cpu_index = 0;
+static void *stacks[CONFIG_MAX_CPUS];
volatile unsigned long secondary_stack;
+volatile unsigned int secondary_cpu_index;
int start_cpu(device_t cpu)
{
extern unsigned char _estack[];
struct cpu_info *info;
unsigned long stack_end;
+ unsigned long stack_base;
+ unsigned long *stack;
unsigned long apicid;
- unsigned long index;
+ unsigned int index;
unsigned long count;
+ int i;
int result;
spin_lock(&start_cpu_lock);
- /* Get the cpu's apicid */
+ /* Get the CPU's apicid */
apicid = cpu->path.apic.apic_id;
/* Get an index for the new processor */
index = ++last_cpu_index;
- /* Find end of the new processors stack */
- stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
+ /* Find end of the new processor's stack */
+ stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) -
+ sizeof(struct cpu_info);
- /* Record the index and which cpu structure we are using */
+ stack_base = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*(index+1));
+ printk(BIOS_SPEW, "CPU%d: stack_base %p, stack_end %p\n", index,
+ (void *)stack_base, (void *)stack_end);
+ /* poison the stack */
+ for(stack = (void *)stack_base, i = 0; i < CONFIG_STACK_SIZE; i++)
+ stack[i/sizeof(*stack)] = 0xDEADBEEF;
+ stacks[index] = stack;
+ /* Record the index and which CPU structure we are using */
info = (struct cpu_info *)stack_end;
info->index = index;
info->cpu = cpu;
- /* Advertise the new stack to start_cpu */
+ /* Advertise the new stack and index to start_cpu */
secondary_stack = stack_end;
+ secondary_cpu_index = index;
- /* Until the cpu starts up report the cpu is not enabled */
+ /* Until the CPU starts up report the CPU is not enabled */
cpu->enabled = 0;
cpu->initialized = 0;
@@ -280,7 +318,8 @@
#if CONFIG_AP_IN_SIPI_WAIT
/**
- * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of delay.
+ * Sending INIT IPI to self is equivalent of asserting #INIT with a bit of
+ * delay.
* An undefined number of instruction cycles will complete. All global locks
* must be released before INIT IPI and no printk is allowed after this.
* De-asserting INIT IPI is a no-op on later Intel CPUs.
@@ -309,7 +348,8 @@
/* send an LAPIC INIT to myself */
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
- lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT | LAPIC_DM_INIT);
+ lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG |
+ LAPIC_INT_ASSERT | LAPIC_DM_INIT);
/* wait for the ipi send to finish */
#if DEBUG_HALT_SELF
@@ -381,7 +421,7 @@
#endif
/* C entry point of secondary cpus */
-void secondary_cpu_init(void)
+void secondary_cpu_init(unsigned int index)
{
atomic_inc(&active_cpus);
#if CONFIG_SERIAL_CPU_INIT
@@ -398,7 +438,7 @@
cr4_val |= (1 << 9 | 1 << 10);
writecr4(cr4_val);
#endif
- cpu_initialize();
+ cpu_initialize(index);
#if CONFIG_SERIAL_CPU_INIT
spin_unlock(&start_cpu_lock);
#endif
@@ -448,13 +488,15 @@
device_t cpu;
int old_active_count, active_count;
long loopcount = 0;
+ int i;
/* Now loop until the other cpus have finished initializing */
old_active_count = 1;
active_count = atomic_read(&active_cpus);
while(active_count > 1) {
if (active_count != old_active_count) {
- printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1);
+ printk(BIOS_INFO, "Waiting for %d CPUS to stop\n",
+ active_count - 1);
old_active_count = active_count;
}
udelay(10);
@@ -474,6 +516,21 @@
}
}
printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
+ for(i = 1; i <= last_cpu_index; i++){
+ unsigned long *stack = stacks[i];
+ int lowest;
+ int maxstack = (CONFIG_STACK_SIZE - sizeof(struct cpu_info))
+ /sizeof(*stack) - 1;
+ if (stack[0] != 0xDEADBEEF)
+ printk(BIOS_ERR, "CPU%d overran its stack\n", i);
+ for(lowest = 0; lowest < maxstack; lowest++)
+ if (stack[lowest] != 0xDEADBEEF)
+ break;
+ printk(BIOS_SPEW, "CPU%d: stack allocated from %p to %p:", i,
+ stack, &stack[maxstack]);
+ printk(BIOS_SPEW, "lowest stack address was %p\n",
+ &stack[lowest]);
+ }
}
#endif /* CONFIG_SMP */
@@ -502,8 +559,9 @@
/* Find the device structure for the boot cpu */
info->cpu = alloc_find_dev(cpu_bus, &cpu_path);
-#if CONFIG_SMP
- copy_secondary_start_to_1m_below(); // why here? In case some day we can start core1 in amd_sibling_init
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
+ // why here? In case some day we can start core1 in amd_sibling_init
+ copy_secondary_start_to_lowest_1M();
#endif
#if CONFIG_HAVE_SMI_HANDLER
@@ -512,7 +570,7 @@
cpus_ready_for_init();
-#if CONFIG_SMP
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
#if !CONFIG_SERIAL_CPU_INIT
/* start all aps at first, so we can init ECC all together */
start_other_cpus(cpu_bus, info->cpu);
@@ -520,9 +578,9 @@
#endif
/* Initialize the bootstrap processor */
- cpu_initialize();
+ cpu_initialize(0);
-#if CONFIG_SMP
+#if CONFIG_SMP && CONFIG_MAX_CPUS > 1
#if CONFIG_SERIAL_CPU_INIT
start_other_cpus(cpu_bus, info->cpu);
#endif
@@ -531,4 +589,3 @@
wait_other_cpus_stop(cpu_bus);
#endif
}
-
diff --git a/src/cpu/x86/lapic/secondary.S b/src/cpu/x86/lapic/secondary.S
index dc00b08..bc6e5bc 100644
--- a/src/cpu/x86/lapic/secondary.S
+++ b/src/cpu/x86/lapic/secondary.S
@@ -41,6 +41,8 @@
/* Set the stack pointer, and flag that we are done */
xorl %eax, %eax
movl secondary_stack, %esp
+ movl secondary_cpu_index, %edi
+ pushl %edi
movl %eax, secondary_stack
call secondary_cpu_init
diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c
index 7a1f51d..593f066 100644
--- a/src/cpu/x86/mtrr/earlymtrr.c
+++ b/src/cpu/x86/mtrr/earlymtrr.c
@@ -21,11 +21,11 @@
}
#if !defined(CONFIG_CACHE_AS_RAM) || !CONFIG_CACHE_AS_RAM
-static void cache_lbmem(int type)
+static void cache_ramstage(void)
{
- /* Enable caching for 0 - 1MB using variable mtrr */
+ /* Enable caching for lower 1MB and ram stage using variable mtrr */
disable_cache();
- set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, type);
+ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
enable_cache();
}
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index cce526a..e645f8d 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -118,8 +118,6 @@
base.hi = basek >> 22;
base.lo = basek << 10;
- printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
-
if (sizek < 4*1024*1024) {
mask.hi = address_mask_high;
mask.lo = ~((sizek << 10) -1);
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index bbed0f1..83ebaf9 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -117,8 +117,14 @@
{
unsigned int node;
smm_state_save_area_t state_save;
+ u32 smm_base = 0xa8000; /* ASEG */
-#if !CONFIG_SMM_TSEG
+#if CONFIG_SMM_TSEG
+ /* Update global variable TSEG base */
+ if (!smi_get_tseg_base())
+ return;
+ smm_base = smi_get_tseg_base() + 0x8000;
+#else
/* Are we ok to execute the handler? */
if (!smi_obtain_lock()) {
/* For security reasons we don't release the other CPUs
@@ -146,18 +152,22 @@
case 0x00030007:
state_save.type = LEGACY;
state_save.legacy_state_save = (legacy_smm_state_save_area_t *)
- (0xa8000 + 0x7e00 - (node * 0x400));
+ (smm_base + 0x7e00 - (node * 0x400));
break;
case 0x00030100:
- case 0x00030101: /* SandyBridge */
state_save.type = EM64T;
state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
- (0xa8000 + 0x7d00 - (node * 0x400));
+ (smm_base + 0x7d00 - (node * 0x400));
+ case 0x00030101: /* SandyBridge/IvyBridge */
+ state_save.type = EM64T101;
+ state_save.em64t101_state_save =
+ (em64t101_smm_state_save_area_t *)
+ (smm_base + 0x7d00 - (node * 0x400));
break;
case 0x00030064:
state_save.type = AMD64;
state_save.amd64_state_save = (amd64_smm_state_save_area_t *)
- (0xa8000 + 0x7e00 - (node * 0x400));
+ (smm_base + 0x7e00 - (node * 0x400));
break;
default:
printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld
index 016b5a0..6def972 100644
--- a/src/cpu/x86/smm/smm_tseg.ld
+++ b/src/cpu/x86/smm/smm_tseg.ld
@@ -10,6 +10,34 @@
.handler (.): {
/* Assembler stub */
*(.handler)
+ }
+
+ /* We are using the TSEG interleaved to stuff the SMM handlers
+ * for all CPU cores in there. The jump table redirects the execution
+ * to the actual SMM handler
+ */
+ . = 0x8000 - (( CPUS - 1) * 0x400);
+ .jumptable : {
+ *(.jumptable)
+ }
+
+ /* Data used in early SMM TSEG handler. */
+ . = 0x8400;
+ .earlydata : {
+ *(.earlydata)
+ }
+
+ /* 16KB for the heap at 64KB */
+ . = 0x10000;
+ .heap : {
+ _heap = .;
+ . = 0x4000;
+ _eheap = .;
+ }
+
+ . = ALIGN(0x4000);
+ .smm_c_handler : {
+ _smm_c_handler_start = .;
/* C code of the SMM handler */
*(.text);
@@ -29,25 +57,10 @@
. = ALIGN(4);
*(.bss)
*(.sbss)
-
- /* What is this? */
*(COMMON)
. = ALIGN(4);
- }
- /* We are using the TSEG interleaved to stuff the SMM handlers
- * for all CPU cores in there. The jump table redirects the execution
- * to the actual SMM handler
- */
- . = 0x8000 - (( CPUS - 1) * 0x400);
- .jumptable : {
- *(.jumptable)
- }
-
- /* Data used in early SMM TSEG handler. */
- . = 0x8400;
- .earlydata : {
- *(.earlydata)
+ _smm_c_handler_end = .;
}
/DISCARD/ : {
diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S
index 8fdd75f..c61a611 100644
--- a/src/cpu/x86/smm/smmhandler_tseg.S
+++ b/src/cpu/x86/smm/smmhandler_tseg.S
@@ -20,7 +20,11 @@
*/
/*
- * +--------------------------------+ 0xffff
+ * +--------------------------------+
+ * | SMM Handler C Code |
+ * +--------------------------------+ 0x14000
+ * | SMM Handler Heap |
+ * +--------------------------------+ 0x10000
* | Save State Map Node 0 |
* | Save State Map Node 1 |
* | Save State Map Node 2 |
@@ -39,7 +43,7 @@
* | ... |
* +--------------------------------+ 0x7400
* | |
- * | SMM Handler |
+ * | SMM Handler Assembly Stub |
* | |
* +--------------------------------+ TSEG
*
@@ -91,6 +95,7 @@
/* If we did not get the lock, wait for release */
wait_for_unlock:
+ pause
addr32 movw (%ebx), %ax
cmpw $SMI_LOCKED, %ax
je wait_for_unlock
diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc
index 9ffc0bb..9a2f71e 100644
--- a/src/devices/Makefile.inc
+++ b/src/devices/Makefile.inc
@@ -11,6 +11,8 @@
ramstage-y += pci_ops.c
ramstage-y += smbus_ops.c
+romstage-y+= device_romstage.c
+
subdirs-y += oprom
ifeq ($(CONFIG_PCI_ROM_RUN),y)
diff --git a/src/devices/device_romstage.c b/src/devices/device_romstage.c
new file mode 100644
index 0000000..475f94a
--- /dev/null
+++ b/src/devices/device_romstage.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2003-2004 Linux Networx
+ * (Written by Eric Biederman <ebiederman@lnxi.com> for Linux Networx)
+ * Copyright (C) 2003 Greg Watson <jarrah@users.sourceforge.net>
+ * Copyright (C) 2004 Li-Ta Lo <ollie@lanl.gov>
+ * Copyright (C) 2005-2006 Tyan
+ * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/path.h>
+#include <device/pci.h>
+#include <device/resource.h>
+
+/** Linked list of ALL devices */
+ROMSTAGE_CONST struct device * ROMSTAGE_CONST all_devices = &dev_root;
+
+/**
+ * Given a PCI bus and a devfn number, find the device structure.
+ *
+ * @param bus The bus number.
+ * @param devfn A device/function number.
+ * @return Pointer to the device structure (if found), 0 otherwise.
+ */
+ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus,
+ unsigned int devfn)
+{
+ ROMSTAGE_CONST struct device *dev, *result;
+
+ result = 0;
+ for (dev = all_devices; dev; dev = dev->next) {
+ if ((dev->path.type == DEVICE_PATH_PCI) &&
+ (dev->bus->secondary == bus) &&
+ (dev->path.pci.devfn == devfn)) {
+ result = dev;
+ break;
+ }
+ }
+ return result;
+}
+
+/**
+ * Given an SMBus bus and a device number, find the device structure.
+ *
+ * @param bus The bus number.
+ * @param addr A device number.
+ * @return Pointer to the device structure (if found), 0 otherwise.
+ */
+ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
+ unsigned int addr)
+{
+ ROMSTAGE_CONST struct device *dev, *result;
+
+ result = 0;
+ for (dev = all_devices; dev; dev = dev->next) {
+ if ((dev->path.type == DEVICE_PATH_I2C) &&
+ (dev->bus->secondary == bus) &&
+ (dev->path.i2c.device == addr)) {
+ result = dev;
+ break;
+ }
+ }
+ return result;
+}
+
diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c
index bada546..2ea05d4 100644
--- a/src/devices/oprom/x86_interrupts.c
+++ b/src/devices/oprom/x86_interrupts.c
@@ -114,9 +114,7 @@
}
#define PCI_CONFIG_SPACE_TYPE1 (1 << 0)
-#define PCI_CONFIG_SPACE_TYPE2 (1 << 1)
#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4)
-#define PCI_SPECIAL_CYCLE_TYPE2 (1 << 5)
int int1a_handler(struct eregs *regs)
{
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 7fa7384..4ced6b0 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -656,7 +656,10 @@
((device & 0xffff) << 16) | (vendor & 0xffff));
}
-/** Default handler: only runs the relevant PCI BIOS. */
+
+int oprom_is_loaded;
+
+/* Default handler: only runs the relevant PCI BIOS. */
void pci_dev_init(struct device *dev)
{
#if CONFIG_PCI_ROM_RUN == 1 || CONFIG_VGA_ROM_RUN == 1
@@ -675,8 +678,11 @@
* we don't run (VGA) option ROMs, unless we have to print
* something on the screen before the kernel is loaded.
*/
- if (!developer_mode_enabled() && !recovery_mode_enabled())
+ if (!developer_mode_enabled() && !recovery_mode_enabled() &&
+ !vboot_wants_oprom()) {
+ printk(BIOS_DEBUG, "Not loading VGA Option ROM\n");
return;
+ }
#endif
rom = pci_rom_probe(dev);
@@ -696,6 +702,8 @@
return;
#endif
run_bios(dev, (unsigned long)ram);
+ oprom_is_loaded = 1;
+ printk(BIOS_DEBUG, "VGA Option ROM has been loaded\n");
#endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
}
diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig
index 60e5b65..99cdaa0 100644
--- a/src/drivers/Kconfig
+++ b/src/drivers/Kconfig
@@ -27,3 +27,4 @@
source src/drivers/trident/Kconfig
source src/drivers/ics/Kconfig
source src/drivers/spi/Kconfig
+source src/drivers/elog/Kconfig
diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc
index 851a4df..e329e1b 100644
--- a/src/drivers/Makefile.inc
+++ b/src/drivers/Makefile.inc
@@ -27,4 +27,5 @@
subdirs-y += trident
subdirs-y += ics
subdirs-y += spi
+subdirs-y += elog
subdirs-$(CONFIG_ARCH_X86) += pc80
diff --git a/src/drivers/elog/Kconfig b/src/drivers/elog/Kconfig
new file mode 100644
index 0000000..02274c4
--- /dev/null
+++ b/src/drivers/elog/Kconfig
@@ -0,0 +1,105 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+config ELOG
+ depends on SPI_FLASH
+ bool "Support for flash based event log"
+ default n
+ help
+ Enable support for flash based event logging.
+
+if ELOG
+
+config ELOG_DEBUG
+ bool "Enable debug output for event logging"
+ default n
+
+config ELOG_FLASH_BASE
+ hex "Event log offset into flash"
+ default 0
+ help
+ Offset into the flash chip for the ELOG block.
+ This should be allocated in the FMAP.
+
+config ELOG_AREA_SIZE
+ hex "Size of Event Log area in flash"
+ default 0x1000
+ help
+ This should be a multiple of flash block size.
+
+ Default is 4K.
+
+config ELOG_FULL_THRESHOLD
+ hex "Threshold at which flash is considered full"
+ default 0xC00
+ help
+ When the Event Log size is larger than this it will be shrunk
+ to ELOG_SHRINK_SIZE. Must be greater than ELOG_AREA_SIZE, and
+ ELOG_AREA_SIZE - ELOG_FULL_THRESHOLD must be greater than the
+ maximum event size of 128.
+
+ Default is 75% of the log, or 3K.
+
+config ELOG_SHRINK_SIZE
+ hex "Resulting size when the event log is shrunk"
+ default 0x400
+ help
+ When the Event Log is shrunk it will go to this size.
+ ELOG_AREA_SIZE - ELOG_SHRINK_SIZE must be less than
+ CONFIG_ELOG_FULL_THRESHOLD.
+
+ Default is 1K.
+
+config ELOG_CBMEM
+ bool "Store a copy of ELOG in CBMEM"
+ default n
+ help
+ This option will have ELOG store a copy of the flash event log
+ in a CBMEM region and export that address in SMBIOS to the OS.
+ This is useful if the ELOG location is not in memory mapped flash,
+ but it means that events added at runtime via the SMI handler
+ will not be reflected in the CBMEM copy of the log.
+
+endif
+
+config ELOG_GSMI
+ depends on ELOG && SPI_FLASH_SMM && SMM_TSEG
+ bool "SMI interface to write and clear event log"
+ default n
+ help
+ This interface is compatible with the linux kernel driver
+ available with CONFIG_GOOGLE_GSMI and can be used to write
+ kernel reset/shutdown messages to the event log.
+
+config ELOG_BOOT_COUNT
+ depends on ELOG
+ bool "Maintain a monotonic boot number in CMOS"
+ default n
+ help
+ Store a monotonic boot number in CMOS and provide an interface
+ to read the current value and increment the counter. This boot
+ counter will be logged as part of the System Boot event.
+
+config ELOG_BOOT_COUNT_CMOS_OFFSET
+ depends on ELOG && ELOG_BOOT_COUNT && !USE_OPTION_TABLE
+ int "Offset in CMOS to store the boot count"
+ default 0
+ help
+ This value must be greater than 16 bytes so as not to interfere
+ with the standard RTC region. Requires 8 bytes.
diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc
new file mode 100644
index 0000000..79a7cc0
--- /dev/null
+++ b/src/drivers/elog/Makefile.inc
@@ -0,0 +1,6 @@
+ramstage-$(CONFIG_ELOG) += elog.c
+
+smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c
+
+romstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c
+ramstage-$(CONFIG_ELOG_BOOT_COUNT) += boot_count.c
diff --git a/src/drivers/elog/boot_count.c b/src/drivers/elog/boot_count.c
new file mode 100644
index 0000000..9ea828d
--- /dev/null
+++ b/src/drivers/elog/boot_count.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <ip_checksum.h>
+#include <pc80/mc146818rtc.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <elog.h>
+
+/*
+ * We need a region in CMOS to store the boot counter.
+ *
+ * This can either be declared as part of the option
+ * table or statically defined in the board config.
+ */
+#if CONFIG_USE_OPTION_TABLE
+# include "option_table.h"
+# define BOOT_COUNT_CMOS_OFFSET (CMOS_VSTART_boot_count_offset >> 3)
+#else
+# if defined(CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET)
+# define BOOT_COUNT_CMOS_OFFSET CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET
+# else
+# error "Must define CONFIG_ELOG_BOOT_COUNT_CMOS_OFFSET"
+# endif
+#endif
+
+#define BOOT_COUNT_SIGNATURE 0x4342 /* 'BC' */
+
+struct boot_count {
+ u16 signature;
+ u32 count;
+ u16 checksum;
+} __attribute__ ((packed));
+
+/* Read and validate boot count structure from CMOS */
+static int boot_count_cmos_read(struct boot_count *bc)
+{
+ u8 i, *p;
+ u16 csum;
+
+ for (p = (u8*)bc, i = 0; i < sizeof(*bc); i++, p++)
+ *p = cmos_read(BOOT_COUNT_CMOS_OFFSET + i);
+
+ /* Verify signature */
+ if (bc->signature != BOOT_COUNT_SIGNATURE) {
+ printk(BIOS_DEBUG, "Boot Count invalid signature\n");
+ return -1;
+ }
+
+ /* Verify checksum over signature and counter only */
+ csum = compute_ip_checksum(bc, offsetof(struct boot_count, checksum));
+
+ if (csum != bc->checksum) {
+ printk(BIOS_DEBUG, "Boot Count checksum mismatch\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Write boot count structure to CMOS */
+static void boot_count_cmos_write(struct boot_count *bc)
+{
+ u8 i, *p;
+
+ /* Checksum over signature and counter only */
+ bc->checksum = compute_ip_checksum(
+ bc, offsetof(struct boot_count, checksum));
+
+ for (p = (u8*)bc, i = 0; i < sizeof(*bc); i++, p++)
+ cmos_write(*p, BOOT_COUNT_CMOS_OFFSET + i);
+}
+
+/* Increment boot count and return the new value */
+u32 boot_count_increment(void)
+{
+ struct boot_count bc;
+
+ /* Read and increment boot count */
+ if (boot_count_cmos_read(&bc) < 0) {
+ /* Structure invalid, re-initialize */
+ bc.signature = BOOT_COUNT_SIGNATURE;
+ bc.count = 0;
+ }
+
+ /* Increment boot counter */
+ bc.count++;
+
+ /* Write the new count to CMOS */
+ boot_count_cmos_write(&bc);
+
+ printk(BIOS_DEBUG, "Boot Count incremented to %u\n", bc.count);
+ return bc.count;
+}
+
+/* Return the current boot count */
+u32 boot_count_read(void)
+{
+ struct boot_count bc;
+
+ if (boot_count_cmos_read(&bc) < 0)
+ return 0;
+
+ return bc.count;
+}
diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c
new file mode 100644
index 0000000..e6baace
--- /dev/null
+++ b/src/drivers/elog/elog.c
@@ -0,0 +1,977 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <pc80/mc146818rtc.h>
+#include <smbios.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <stdint.h>
+#include <string.h>
+#include <elog.h>
+#include "elog_internal.h"
+
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
+#elif CONFIG_ELOG_FLASH_BASE == 0
+#error "CONFIG_ELOG_FLASH_BASE is invalid"
+#endif
+#if CONFIG_ELOG_FULL_THRESHOLD >= CONFIG_ELOG_AREA_SIZE
+#error "CONFIG_ELOG_FULL_THRESHOLD is larger than CONFIG_ELOG_AREA_SIZE"
+#endif
+#if (CONFIG_ELOG_AREA_SIZE - CONFIG_ELOG_FULL_THRESHOLD) < (MAX_EVENT_SIZE + 1)
+#error "CONFIG_ELOG_FULL_THRESHOLD is too small"
+#endif
+#if CONFIG_ELOG_SHRINK_SIZE >= CONFIG_ELOG_AREA_SIZE
+#error "CONFIG_ELOG_SHRINK_SIZE is larger than CONFIG_ELOG_AREA_SIZE"
+#endif
+#if (CONFIG_ELOG_AREA_SIZE - CONFIG_ELOG_SHRINK_SIZE) > \
+ CONFIG_ELOG_FULL_THRESHOLD
+#error "CONFIG_ELOG_SHRINK_SIZE is too large"
+#endif
+
+#if CONFIG_ELOG_DEBUG
+#define elog_debug(STR...) printk(BIOS_DEBUG, STR)
+#else
+#define elog_debug(STR...)
+#endif
+
+/*
+ * Static variables for ELOG state
+ */
+static int elog_initialized;
+static struct spi_flash *elog_spi;
+static struct elog_descriptor elog_flash_area;
+static struct elog_descriptor elog_mem_area;
+
+static inline struct elog_descriptor* elog_get_mem(void)
+{
+ return &elog_mem_area;
+}
+
+static inline struct elog_descriptor* elog_get_flash(void)
+{
+ return &elog_flash_area;
+}
+
+/*
+ * Convert a memory mapped flash address into a flash offset
+ */
+static inline u32 elog_flash_address_to_offset(u8 *address)
+{
+ if (!elog_spi)
+ return 0;
+ return (u32)address - ((u32)~0UL - elog_spi->size + 1);
+}
+
+/*
+ * Convert a flash offset into a memory mapped flash address
+ */
+static inline u8* elog_flash_offset_to_address(u32 offset)
+{
+ if (!elog_spi)
+ return NULL;
+ return (u8*)((u32)~0UL - elog_spi->size + 1 + offset);
+}
+
+/*
+ * The ELOG header is at the very beginning of the area
+ */
+static inline struct elog_header*
+elog_get_header(struct elog_descriptor *elog)
+{
+ return elog->backing_store;
+}
+
+/*
+ * Pointer to an event log header in the event data area
+ */
+static inline struct event_header*
+elog_get_event_base(struct elog_descriptor *elog, u32 offset)
+{
+ return (struct event_header *)&elog->data[offset];
+}
+
+/*
+ * Pointer to where the next event should be stored
+ */
+static inline struct event_header*
+elog_get_next_event_base(struct elog_descriptor *elog)
+{
+ return elog_get_event_base(elog, elog->next_event_offset);
+}
+
+/*
+ * Pointer to the last logged event
+ */
+static inline struct event_header*
+elog_get_last_event_base(struct elog_descriptor *elog)
+{
+ return elog_get_event_base(elog, elog->last_event_offset);
+}
+
+/*
+ * Update the checksum at the last byte
+ */
+static void elog_update_checksum(struct event_header *event, u8 checksum)
+{
+ u8 *event_data = (u8*)event;
+ event_data[event->length - 1] = checksum;
+}
+
+/*
+ * Simple byte checksum for events
+ */
+static u8 elog_checksum_event(struct event_header *event)
+{
+ u8 index, checksum = 0;
+ u8 *data = (u8*)event;
+
+ for (index = 0; index < event->length; index++)
+ checksum += data[index];
+ return checksum;
+}
+
+/*
+ * Check if a raw buffer is filled with ELOG_TYPE_EOL byte
+ */
+static int elog_is_buffer_clear(u8 *base, u32 size)
+{
+ u8 *current = base;
+ u8 *end = current + size;
+
+ elog_debug("elog_is_buffer_clear(base=0x%p size=%u)\n", base, size);
+
+ for (; current != end; current++) {
+ if (*current != ELOG_TYPE_EOL)
+ return 0;
+ }
+ return 1;
+}
+
+/*
+ * Verify whether ELOG area is filled with ELOG_TYPE_EOL byte
+ */
+static int elog_is_area_clear(struct elog_descriptor *elog)
+{
+ return elog_is_buffer_clear(elog->backing_store, elog->total_size);
+}
+
+/*
+ * Check that the ELOG area has been initialized and is valid.
+ */
+static int elog_is_area_valid(struct elog_descriptor *elog)
+{
+ elog_debug("elog_is_area_valid()\n");
+
+ if (elog->area_state != ELOG_AREA_HAS_CONTENT)
+ return 0;
+ if (elog->header_state != ELOG_HEADER_VALID)
+ return 0;
+ if (elog->event_buffer_state != ELOG_EVENT_BUFFER_OK)
+ return 0;
+ return 1;
+}
+
+/*
+ * Verify the contents of an ELOG Header structure
+ * Returns 1 if the header is valid, 0 otherwise
+ */
+static int elog_is_header_valid(struct elog_header *header)
+{
+ elog_debug("elog_is_header_valid()\n");
+
+ if (header->magic != ELOG_SIGNATURE) {
+ printk(BIOS_ERR, "ELOG: header magic 0x%X != 0x%X\n",
+ header->magic, ELOG_SIGNATURE);
+ return 0;
+ }
+ if (header->version != ELOG_VERSION) {
+ printk(BIOS_ERR, "ELOG: header version %u != %u\n",
+ header->version, ELOG_VERSION);
+ return 0;
+ }
+ if (header->header_size != sizeof(*header)) {
+ printk(BIOS_ERR, "ELOG: header size mismatch %u != %u\n",
+ header->header_size, sizeof(*header));
+ return 0;
+ }
+ return 1;
+}
+
+/*
+ * Validate the event header and data.
+ */
+static int elog_is_event_valid(struct elog_descriptor *elog, u32 offset)
+{
+ struct event_header *event;
+
+ event = elog_get_event_base(elog, offset);
+ if (!event)
+ return 0;
+
+ /* Validate event length */
+ if ((offsetof(struct event_header, type) +
+ sizeof(event->type) - 1 + offset) >= elog->data_size)
+ return 0;
+
+ /* End of event marker has been found */
+ if (event->type == ELOG_TYPE_EOL)
+ return 0;
+
+ /* Check if event fits in area */
+ if ((offsetof(struct event_header, length) +
+ sizeof(event->length) - 1 + offset) >= elog->data_size)
+ return 0;
+
+ /*
+ * If the current event length + the current offset exceeds
+ * the area size then the event area is corrupt.
+ */
+ if ((event->length + offset) >= elog->data_size)
+ return 0;
+
+ /* Event length must be at least header size + checksum */
+ if (event->length < (sizeof(*event) + 1))
+ return 0;
+
+ /* If event checksum is invalid the area is corrupt */
+ if (elog_checksum_event(event) != 0)
+ return 0;
+
+ /* Event is valid */
+ return 1;
+}
+
+/*
+ * Write 'size' bytes of data provided in 'buffer' into flash
+ * device at offset 'offset'. This will not erase the flash and
+ * it assumes the flash area is erased appropriately.
+ */
+static void elog_flash_write(u8 *address, u8 *buffer, u32 size)
+{
+ struct elog_descriptor *flash = elog_get_flash();
+ u32 offset;
+
+ if (!address || !buffer || !size || !elog_spi)
+ return;
+
+ offset = flash->flash_base;
+ offset += address - (u8*)flash->backing_store;
+
+ elog_debug("elog_flash_write(address=0x%p offset=0x%08x buffer=0x%p "
+ "size=%u)\n", address, offset, buffer, size);
+
+ /* Write the data to flash */
+ elog_spi->write(elog_spi, offset, size, buffer);
+
+ /* Update the copy in memory */
+ memcpy(address, buffer, size);
+}
+
+/*
+ * Erase the first block specified in the address.
+ * Only handles flash area within a single flash block.
+ */
+static void elog_flash_erase(u8 *address, u32 size)
+{
+ struct elog_descriptor *flash = elog_get_flash();
+ u32 offset;
+
+ if (!address || !size || !elog_spi)
+ return;
+
+ offset = flash->flash_base;
+ offset += address - (u8*)flash->backing_store;
+
+ elog_debug("elog_flash_erase(address=0x%p offset=0x%08x size=%u)\n",
+ address, offset, size);
+
+ /* Erase the sectors in this region */
+ elog_spi->erase(elog_spi, offset, size);
+}
+
+/*
+ * Scan the event area and validate each entry and
+ * update the ELOG descriptor state.
+ */
+static void elog_update_event_buffer_state(struct elog_descriptor *elog)
+{
+ u32 count = 0;
+ u32 offset = 0;
+ u32 last_offset = 0;
+ u32 last_event_size = 0;
+ struct event_header *event;
+
+ elog_debug("elog_update_event_buffer_state()\n");
+
+ /* Go through each event and validate it */
+ while (1) {
+ event = elog_get_event_base(elog, offset);
+
+ /* Do not de-reference anything past the area length */
+ if ((offsetof(struct event_header, type) +
+ sizeof(event->type) - 1 + offset) >= elog->data_size) {
+ elog->event_buffer_state = ELOG_EVENT_BUFFER_CORRUPTED;
+ break;
+ }
+
+ /* The end of the event marker has been found */
+ if (event->type == ELOG_TYPE_EOL)
+ break;
+
+ /* Validate the event */
+ if (!elog_is_event_valid(elog, offset)) {
+ elog->event_buffer_state = ELOG_EVENT_BUFFER_CORRUPTED;
+ break;
+ }
+
+ /* Move to the next event */
+ count++;
+ last_offset = offset;
+ last_event_size = event->length;
+ offset += event->length;
+ }
+
+ /* Ensure the remaining buffer is empty */
+ if (!elog_is_buffer_clear(&elog->data[offset],
+ elog->data_size - offset))
+ elog->event_buffer_state = ELOG_EVENT_BUFFER_CORRUPTED;
+
+ /* Update data into elog descriptor */
+ elog->event_count = count;
+ elog->next_event_offset = offset;
+ elog->last_event_offset = last_offset;
+ elog->last_event_size = last_event_size;
+}
+
+static void elog_validate_and_fill(struct elog_descriptor *elog)
+{
+ elog_debug("elog_validate_and_fill()\n");
+
+ /* Check if the area is empty or not */
+ if (elog_is_area_clear(elog)) {
+ elog->area_state = ELOG_AREA_EMPTY;
+ return;
+ }
+
+ elog->area_state = ELOG_AREA_HAS_CONTENT;
+
+ /* Validate the header */
+ if (!elog_is_header_valid(elog->staging_header)) {
+ elog->header_state = ELOG_HEADER_INVALID;
+ return;
+ }
+
+ elog->header_state = ELOG_HEADER_VALID;
+ elog_update_event_buffer_state(elog);
+}
+
+/*
+ * Initialize a new ELOG descriptor
+ */
+static void elog_init_descriptor(struct elog_descriptor *elog,
+ elog_descriptor_type type,
+ u8 *buffer, u32 size,
+ struct elog_header *header)
+{
+ elog_debug("elog_init_descriptor(type=%u buffer=0x%p size=%u)\n",
+ type, buffer, size);
+
+ elog->type = type;
+ elog->area_state = ELOG_AREA_UNDEFINED;
+ elog->header_state = ELOG_HEADER_INVALID;
+ elog->event_buffer_state = ELOG_EVENT_BUFFER_OK;
+ elog->backing_store = buffer;
+ elog->total_size = size;
+
+ /* Fill memory buffer by reading from SPI */
+ if (type == ELOG_DESCRIPTOR_FLASH)
+ elog_spi->read(elog_spi, elog->flash_base, size, buffer);
+
+ /* Get staging header from backing store */
+ elog->staging_header = header;
+ memcpy(header, buffer, sizeof(struct elog_header));
+
+ /* Data starts immediately after header */
+ elog->data = &buffer[sizeof(struct elog_header)];
+ elog->data_size = size - sizeof(struct elog_header);
+
+ elog->next_event_offset = 0;
+ elog->last_event_offset = 0;
+ elog->last_event_size = 0;
+ elog->event_count = 0;
+
+ elog_validate_and_fill(elog);
+}
+
+/*
+ * Re-initialize an existing ELOG descriptor
+ */
+static void elog_reinit_descriptor(struct elog_descriptor *elog)
+{
+ elog_debug("elog_reinit_descriptor()\n");
+ elog_init_descriptor(elog, elog->type, elog->backing_store,
+ elog->total_size, elog->staging_header);
+}
+
+/*
+ * Create ELOG descriptor data structures for all ELOG areas.
+ */
+static int elog_setup_descriptors(u32 flash_base, u32 area_size)
+{
+ struct elog_header *staging_header;
+ u8 *area;
+
+ elog_debug("elog_setup_descriptors(base=0x%08x size=%u)\n",
+ flash_base, area_size);
+
+ /* Prepare flash descriptors */
+ if (flash_base == 0) {
+ printk(BIOS_ERR, "ELOG: Invalid flash base\n");
+ return -1;
+ }
+
+ staging_header = malloc(sizeof(struct elog_header));
+ if (!staging_header) {
+ printk(BIOS_ERR, "ELOG: Unable to allocate header\n");
+ return -1;
+ }
+
+ area = malloc(area_size);
+ if (!area) {
+ printk(BIOS_ERR, "ELOG: Unable to determine flash address\n");
+ return -1;
+ }
+ elog_get_flash()->flash_base = flash_base;
+ elog_init_descriptor(elog_get_flash(), ELOG_DESCRIPTOR_FLASH,
+ area, area_size, staging_header);
+
+ /* Initialize the memory area to look like a cleared flash area */
+ area = malloc(area_size);
+ if (!area) {
+ printk(BIOS_ERR, "ELOG: Unable to allocate mem area\n");
+ return -1;
+ }
+ memset(area, ELOG_TYPE_EOL, area_size);
+ elog_init_descriptor(elog_get_mem(), ELOG_DESCRIPTOR_MEMORY,
+ area, area_size, (struct elog_header *)area);
+
+ return 0;
+}
+
+static void elog_flash_erase_area(void)
+{
+ struct elog_descriptor *elog = elog_get_flash();
+
+ elog_debug("elog_flash_erase_area()\n");
+
+ elog_flash_erase(elog->backing_store, elog->total_size);
+ memset(elog->backing_store, ELOG_TYPE_EOL, elog->total_size);
+ elog_reinit_descriptor(elog);
+}
+
+static void elog_prepare_empty(struct elog_descriptor *elog,
+ u8 *data, u32 data_size)
+{
+ struct elog_header *header;
+
+ elog_debug("elog_prepare_empty(%u bytes)\n", data_size);
+
+ if (!elog_is_area_clear(elog))
+ return;
+
+ /* Write out the header */
+ header = elog->staging_header;
+ header->magic = ELOG_SIGNATURE;
+ header->version = ELOG_VERSION;
+ header->header_size = sizeof(struct elog_header);
+ header->reserved[0] = ELOG_TYPE_EOL;
+ header->reserved[1] = ELOG_TYPE_EOL;
+ elog_flash_write(elog->backing_store, (u8*)header,
+ header->header_size);
+
+ /* Write out the data */
+ if (data)
+ elog_flash_write(elog->data, data, data_size);
+
+ elog_reinit_descriptor(elog);
+
+ /* Clear the log if corrupt */
+ if (!elog_is_area_valid(elog))
+ elog_flash_erase_area();
+}
+
+static int elog_sync_flash_to_mem(void)
+{
+ struct elog_descriptor *mem = elog_get_mem();
+ struct elog_descriptor *flash = elog_get_flash();
+
+ elog_debug("elog_sync_flash_to_mem()\n");
+
+ /* Fill with empty pattern first */
+ memset(mem->backing_store, ELOG_TYPE_EOL, mem->total_size);
+
+ /* Read the header from SPI to memory */
+ elog_spi->read(elog_spi, flash->flash_base,
+ sizeof(struct elog_header), mem->backing_store);
+
+ /* Read the valid flash contents from SPI to memory */
+ elog_spi->read(elog_spi, flash->flash_base + sizeof(struct elog_header),
+ flash->next_event_offset, mem->data);
+
+ elog_reinit_descriptor(mem);
+
+ return elog_is_area_valid(mem) ? 0 : -1;
+}
+
+static int elog_sync_mem_to_flash(void)
+{
+ struct elog_descriptor *mem = elog_get_mem();
+ struct elog_descriptor *flash = elog_get_flash();
+ u8 *src, *dest;
+ u32 size;
+
+ elog_debug("elog_sync_mem_to_flash()\n");
+
+ /*
+ * In the case of a BIOS flash the active area will be cleared.
+ * One can catch this case and log the proper shutdown event by
+ * checking if the active flash elog is empty. Note that if the
+ * header size changes we will have corrupted the flash area.
+ * However that will be corrected on the next boot.
+ */
+ if (elog_is_area_clear(flash)) {
+ elog_prepare_empty(flash,
+ (u8*)elog_get_last_event_base(mem),
+ mem->last_event_size);
+ elog_sync_flash_to_mem();
+ return 0;
+ }
+
+ /* Calculate the destination and source bases */
+ dest = (u8*)elog_get_next_event_base(flash);
+ src = (u8*)elog_get_event_base(mem, flash->next_event_offset);
+
+ /* Calculate how much data to sync */
+ size = mem->next_event_offset - flash->next_event_offset;
+
+ /* Write the log data */
+ elog_flash_write(dest, src, size);
+
+ /* Update descriptor */
+ flash->event_count = mem->event_count;
+ flash->next_event_offset = mem->next_event_offset;
+ flash->last_event_offset = mem->last_event_offset;
+ flash->last_event_size = mem->last_event_size;
+
+ return 0;
+}
+
+/*
+ * Called during ELOG entry handler to prepare state for flash.
+ */
+static int elog_flash_area_bootstrap(void)
+{
+ struct elog_descriptor *elog = elog_get_flash();
+
+ elog_debug("elog_flash_area_bootstrap()\n");
+
+ switch (elog->area_state) {
+ case ELOG_AREA_UNDEFINED:
+ printk(BIOS_ERR, "ELOG: flash area undefined\n");
+ return -1;
+
+ case ELOG_AREA_EMPTY:
+ /* Write a new header with no data */
+ elog_prepare_empty(elog, NULL, 0);
+ break;
+
+ case ELOG_AREA_HAS_CONTENT:
+ break;
+ }
+
+ if (elog->header_state == ELOG_HEADER_INVALID) {
+ /* If the header is invalid no events can be salvaged
+ * so erase the entire area. */
+ printk(BIOS_ERR, "ELOG: flash area header invalid\n");
+ elog_flash_erase_area();
+ elog_prepare_empty(elog, NULL, 0);
+ }
+
+ if (elog->event_buffer_state == ELOG_EVENT_BUFFER_CORRUPTED) {
+ /* Wipe the source flash area */
+ elog_flash_erase_area();
+ elog_prepare_empty(elog, elog_get_mem()->data,
+ elog_get_mem()->next_event_offset);
+ }
+
+ return 0;
+}
+
+/*
+ * Shrink the log, deleting old entries and moving the
+ * remining ones to the front of the log.
+ */
+static int elog_shrink(void)
+{
+ struct elog_descriptor *mem = elog_get_mem();
+ struct event_header *event;
+ u16 discard_count = 0;
+ u16 offset = 0;
+
+ elog_debug("elog_shrink()\n");
+
+ if (mem->next_event_offset < CONFIG_ELOG_SHRINK_SIZE)
+ return 0;
+
+ while (1) {
+ /* Next event has exceeded constraints */
+ if (offset > CONFIG_ELOG_SHRINK_SIZE)
+ break;
+
+ event = elog_get_event_base(mem, offset);
+
+ /* Reached the end of the area */
+ if (!event || event->type == ELOG_TYPE_EOL)
+ break;
+
+ offset += event->length;
+ discard_count++;
+ }
+
+ /* Erase flash area */
+ elog_flash_erase_area();
+
+ /* Write new flash area */
+ elog_prepare_empty(elog_get_flash(),
+ (u8*)elog_get_event_base(mem, offset),
+ mem->next_event_offset - offset);
+
+ /* Update memory area from flash */
+ if (elog_sync_flash_to_mem() < 0) {
+ printk(BIOS_ERR, "Unable to update memory area from flash\n");
+ return -1;
+ }
+
+ /* Add clear event */
+ elog_add_event_word(ELOG_TYPE_LOG_CLEAR, offset);
+
+ return 0;
+}
+
+/*
+ * Initialize the SPI bus and probe for a flash chip
+ */
+static int elog_spi_init(void)
+{
+ elog_debug("elog_spi_init()\n");
+
+ /* Prepare SPI subsystem */
+ spi_init();
+
+ /* Look for flash chip */
+ elog_spi = spi_flash_probe(0, 0, 0, 0);
+
+ return elog_spi ? 0 : -1;
+}
+
+#ifndef __SMM__
+/*
+ * Fill out SMBIOS Type 15 table entry so the
+ * event log can be discovered at runtime.
+ */
+int elog_smbios_write_type15(unsigned long *current, int handle)
+{
+ struct elog_descriptor *flash = elog_get_flash();
+ struct smbios_type15 *t = (struct smbios_type15 *)*current;
+ int len = sizeof(struct smbios_type15);
+
+#if CONFIG_ELOG_CBMEM
+ /* Save event log buffer into CBMEM for the OS to read */
+ void *cbmem = cbmem_add(CBMEM_ID_ELOG, flash->total_size);
+ if (!cbmem)
+ return 0;
+ memcpy(cbmem, flash->backing_store, flash->total_size);
+#endif
+
+ memset(t, 0, len);
+ t->type = SMBIOS_EVENT_LOG;
+ t->length = len - 2;
+ t->handle = handle;
+ t->area_length = flash->total_size - 1;
+ t->header_offset = 0;
+ t->data_offset = sizeof(struct elog_header);
+ t->access_method = SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32;
+ t->log_status = SMBIOS_EVENTLOG_STATUS_VALID;
+ t->change_token = 0;
+#if CONFIG_ELOG_CBMEM
+ t->address = (u32)cbmem;
+#else
+ t->address = (u32)elog_flash_offset_to_address(flash->flash_base);
+#endif
+ t->header_format = ELOG_HEADER_TYPE_OEM;
+ t->log_type_descriptors = 0;
+ t->log_type_descriptor_length = 2;
+
+ *current += len;
+ return len;
+}
+#endif
+
+/*
+ * Clear the entire event log
+ */
+int elog_clear(void)
+{
+ struct elog_descriptor *flash = elog_get_flash();
+
+ elog_debug("elog_clear()\n");
+
+ /* Erase flash area */
+ elog_flash_erase_area();
+
+ /* Prepare new empty area */
+ elog_prepare_empty(flash, NULL, 0);
+
+ /* Update memory area from flash */
+ if (elog_sync_flash_to_mem() < 0)
+ return -1;
+
+ /* Log the clear event */
+ elog_add_event_word(ELOG_TYPE_LOG_CLEAR, flash->total_size);
+
+ return 0;
+}
+
+/*
+ * Event log main entry point
+ */
+int elog_init(void)
+{
+ u32 flash_base = CONFIG_ELOG_FLASH_BASE;
+ int flash_size = CONFIG_ELOG_AREA_SIZE;
+#if CONFIG_CHROMEOS
+ u8 *flash_base_ptr;
+#endif
+
+ if (elog_initialized)
+ return 0;
+
+ elog_debug("elog_init()\n");
+
+ /* Find SPI flash chip for backing store */
+ if (elog_spi_init() < 0) {
+ printk(BIOS_ERR, "ELOG: Unable to find SPI flash\n");
+ return -1;
+ }
+
+#if CONFIG_CHROMEOS
+ /* Find the ELOG base and size in FMAP */
+ flash_size = find_fmap_entry("RW_ELOG", (void **)&flash_base_ptr);
+ if (flash_size < 0) {
+ printk(BIOS_WARNING, "ELOG: Unable to find RW_ELOG in FMAP, "
+ "using CONFIG_ELOG_FLASH_BASE instead\n");
+ flash_size = CONFIG_ELOG_AREA_SIZE;
+ } else {
+ flash_base = elog_flash_address_to_offset(flash_base_ptr);
+
+ /* Use configured size if smaller than FMAP size */
+ if (flash_size > CONFIG_ELOG_AREA_SIZE)
+ flash_size = CONFIG_ELOG_AREA_SIZE;
+ }
+#endif
+
+ /* Setup descriptors for flash and memory areas */
+ if (elog_setup_descriptors(flash_base, flash_size) < 0) {
+ printk(BIOS_ERR, "ELOG: Unable to initialize descriptors\n");
+ return -1;
+ }
+
+ /* Bootstrap the flash area */
+ if (elog_flash_area_bootstrap() < 0) {
+ printk(BIOS_ERR, "ELOG: Unable to bootstrap flash area\n");
+ return -1;
+ }
+
+ /* Initialize the memory area */
+ if (elog_sync_flash_to_mem() < 0) {
+ printk(BIOS_ERR, "ELOG: Unable to initialize memory area\n");
+ return -1;
+ }
+
+ elog_initialized = 1;
+
+ printk(BIOS_INFO, "ELOG: MEM @0x%p FLASH @0x%p [SPI 0x%08x]\n",
+ elog_get_mem()->backing_store,
+ elog_get_flash()->backing_store, elog_get_flash()->flash_base);
+
+ printk(BIOS_INFO, "ELOG: areas are %d bytes, full threshold %d,"
+ " shrink size %d\n", CONFIG_ELOG_AREA_SIZE,
+ CONFIG_ELOG_FULL_THRESHOLD, CONFIG_ELOG_SHRINK_SIZE);
+
+ /* Log a clear event if necessary */
+ if (elog_get_flash()->event_count == 0)
+ elog_add_event_word(ELOG_TYPE_LOG_CLEAR,
+ elog_get_flash()->total_size);
+
+ /* Shrink the log if we are getting too full */
+ if (elog_get_mem()->next_event_offset >= CONFIG_ELOG_FULL_THRESHOLD)
+ elog_shrink();
+
+#if CONFIG_ELOG_BOOT_COUNT && !defined(__SMM__)
+ /* Log boot count event except in S3 resume */
+ if (acpi_slp_type != 3)
+ elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read());
+#endif
+
+#if CONFIG_CMOS_POST && !defined(__SMM__)
+ /* Check and log POST codes from previous boot */
+ cmos_post_log();
+#endif
+
+ return 0;
+}
+
+/*
+ * Populate timestamp in event header with current time
+ */
+static void elog_fill_timestamp(struct event_header *event)
+{
+ event->second = cmos_read(RTC_CLK_SECOND);
+ event->minute = cmos_read(RTC_CLK_MINUTE);
+ event->hour = cmos_read(RTC_CLK_HOUR);
+ event->day = cmos_read(RTC_CLK_DAYOFMONTH);
+ event->month = cmos_read(RTC_CLK_MONTH);
+ event->year = cmos_read(RTC_CLK_YEAR);
+
+ /* Basic sanity check of expected ranges */
+ if (event->month > 0x12 || event->day > 0x31 || event->hour > 0x23 ||
+ event->minute > 0x59 || event->second > 0x59) {
+ event->year = 0;
+ event->month = 0;
+ event->day = 0;
+ event->hour = 0;
+ event->minute = 0;
+ event->second = 0;
+ }
+}
+
+/*
+ * Add an event to the memory area
+ */
+static int elog_add_event_mem(u8 event_type, void *data, u8 data_size)
+{
+ struct event_header *event;
+ struct elog_descriptor *mem = elog_get_mem();
+ u8 event_size;
+
+ elog_debug("elog_add_event_mem(type=%X)\n", event_type);
+
+ /* Make sure ELOG structures are initialized */
+ if (elog_init() < 0)
+ return -1;
+
+ /* Header + Data + Checksum */
+ event_size = sizeof(*event) + data_size + 1;
+ if (event_size > MAX_EVENT_SIZE) {
+ printk(BIOS_ERR, "ELOG: Event(%X) data size too "
+ "big (%d)\n", event_type, event_size);
+ return -1;
+ }
+
+ /* Make sure event data can fit */
+ if ((mem->next_event_offset + event_size) >= mem->data_size) {
+ printk(BIOS_ERR, "ELOG: Event(%X) does not fit\n",
+ event_type);
+ return -1;
+ }
+
+ /* Fill out event data */
+ event = elog_get_next_event_base(mem);
+ event->type = event_type;
+ event->length = event_size;
+ elog_fill_timestamp(event);
+
+ if (data_size)
+ memcpy(&event[1], data, data_size);
+
+ /* Zero the checksum byte and then compute checksum */
+ elog_update_checksum(event, 0);
+ elog_update_checksum(event, -(elog_checksum_event(event)));
+
+ /* Update memory descriptor parameters */
+ mem->event_count++;
+ mem->last_event_offset = mem->next_event_offset;
+ mem->last_event_size = event_size;
+ mem->next_event_offset += event_size;
+
+ printk(BIOS_INFO, "ELOG: Event(%X) added with size %d\n",
+ event_type, event_size);
+ return 0;
+}
+
+void elog_add_event_raw(u8 event_type, void *data, u8 data_size)
+{
+ elog_debug("elog_add_event_raw(type=%X)\n", event_type);
+
+ /* Add event to the memory area */
+ if (elog_add_event_mem(event_type, data, data_size) < 0) {
+ printk(BIOS_ERR, "Unable to add event to memory area\n");
+ return;
+ }
+
+ /* Sync the memory buffer to flash */
+ elog_sync_mem_to_flash();
+
+ /* Shrink the log if we are getting too full */
+ if (elog_get_mem()->next_event_offset >= CONFIG_ELOG_FULL_THRESHOLD)
+ elog_shrink();
+}
+
+void elog_add_event(u8 event_type)
+{
+ elog_add_event_raw(event_type, NULL, 0);
+}
+
+void elog_add_event_byte(u8 event_type, u8 data)
+{
+ elog_add_event_raw(event_type, &data, sizeof(data));
+}
+
+void elog_add_event_word(u8 event_type, u16 data)
+{
+ elog_add_event_raw(event_type, &data, sizeof(data));
+}
+
+void elog_add_event_dword(u8 event_type, u32 data)
+{
+ elog_add_event_raw(event_type, &data, sizeof(data));
+}
+
+void elog_add_event_wake(u8 source, u32 instance)
+{
+ struct elog_event_data_wake wake = {
+ .source = source,
+ .instance = instance
+ };
+ elog_add_event_raw(ELOG_TYPE_WAKE_SOURCE, &wake, sizeof(wake));
+}
diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h
new file mode 100644
index 0000000..f6aa051
--- /dev/null
+++ b/src/drivers/elog/elog_internal.h
@@ -0,0 +1,92 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef ELOG_INTERNAL_H_
+#define ELOG_INTERNAL_H_
+
+/* ELOG header */
+struct elog_header {
+ u32 magic;
+ u8 version;
+ u8 header_size;
+ u8 reserved[2];
+} __attribute__ ((packed));
+
+/* ELOG related constants */
+#define ELOG_SIGNATURE 0x474f4c45 /* 'ELOG' */
+#define ELOG_VERSION 1
+
+/* SMBIOS event log header */
+struct event_header {
+ u8 type;
+ u8 length;
+ u8 year;
+ u8 month;
+ u8 day;
+ u8 hour;
+ u8 minute;
+ u8 second;
+} __attribute__ ((packed));
+
+/* SMBIOS Type 15 related constants */
+#define ELOG_HEADER_TYPE_OEM 0x88
+
+typedef enum elog_descriptor_type {
+ ELOG_DESCRIPTOR_UNKNOWN,
+ ELOG_DESCRIPTOR_MEMORY,
+ ELOG_DESCRIPTOR_FLASH,
+} elog_descriptor_type;
+
+typedef enum elog_area_state {
+ ELOG_AREA_UNDEFINED, /* Initial boot strap state */
+ ELOG_AREA_EMPTY, /* Entire area is empty */
+ ELOG_AREA_HAS_CONTENT, /* Area has some content */
+} elog_area_state;
+
+typedef enum elog_header_state {
+ ELOG_HEADER_INVALID,
+ ELOG_HEADER_VALID,
+} elog_header_state;
+
+typedef enum elog_event_buffer_state {
+ ELOG_EVENT_BUFFER_OK,
+ ELOG_EVENT_BUFFER_CORRUPTED,
+} elog_event_buffer_state;
+
+/*
+ * Internal handler for event log buffers
+ */
+struct elog_descriptor {
+ elog_descriptor_type type;
+ elog_area_state area_state;
+ elog_header_state header_state;
+ elog_event_buffer_state event_buffer_state;
+ struct elog_header *staging_header;
+ void *backing_store;
+ u8 *data;
+ u32 flash_base;
+ u16 total_size;
+ u16 data_size;
+ u16 next_event_offset;
+ u16 last_event_offset;
+ u16 last_event_size;
+ u16 event_count;
+};
+
+#endif /* ELOG_INTERNAL_H_ */
diff --git a/src/drivers/elog/gsmi.c b/src/drivers/elog/gsmi.c
new file mode 100644
index 0000000..dac1af4
--- /dev/null
+++ b/src/drivers/elog/gsmi.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+
+#define GSMI_RET_SUCCESS 0x00
+#define GSMI_RET_INVALID_PARAMETER 0x82
+#define GSMI_RET_UNSUPPORTED 0x83
+
+#define GSMI_CMD_SET_EVENT_LOG 0x08
+#define GSMI_CMD_CLEAR_EVENT_LOG 0x09
+#define GSMI_CMD_HANDSHAKE_TYPE 0xc1
+
+#define GSMI_HANDSHAKE_NONE 0x7f
+#define GSMI_LOG_ENTRY_TYPE_KERNEL 0xDEAD
+
+struct gsmi_set_eventlog_param {
+ u32 data_ptr;
+ u32 data_len;
+ u32 type;
+} __attribute__ ((packed));
+
+struct gsmi_set_eventlog_type1 {
+ u16 type;
+ u32 instance;
+} __attribute__ ((packed));
+
+struct gsmi_clear_eventlog_param {
+ u32 percentage;
+ u32 data_type;
+} __attribute__ ((packed));
+
+/* Param is usually EBX, ret in EAX */
+u32 gsmi_exec(u8 command, u32 *param)
+{
+ struct gsmi_set_eventlog_param *sel;
+ struct gsmi_set_eventlog_type1 *type1;
+ struct gsmi_clear_eventlog_param *cel;
+ u32 ret = GSMI_RET_UNSUPPORTED;
+
+ switch (command) {
+ case GSMI_CMD_HANDSHAKE_TYPE:
+ /* Used by kernel to verify basic SMI functionality */
+ printk(BIOS_DEBUG, "GSMI Handshake\n");
+ ret = GSMI_HANDSHAKE_NONE;
+ break;
+
+ case GSMI_CMD_SET_EVENT_LOG:
+ /* Look for a type1 event */
+ sel = (struct gsmi_set_eventlog_param *)(*param);
+ if (!sel)
+ break;
+
+ /* Make sure the input is usable */
+ if (sel->type != 1 && sel->data_ptr != 0 &&
+ sel->data_len != sizeof(struct gsmi_set_eventlog_type1))
+ break;
+
+ /* Event structure within the data buffer */
+ type1 = (struct gsmi_set_eventlog_type1 *)(sel->data_ptr);
+ if (!type1)
+ break;
+
+ printk(BIOS_DEBUG, "GSMI Set Event Log "
+ "(type=0x%x instance=0x%x)\n",
+ type1->type, type1->instance);
+
+ if (type1->type == GSMI_LOG_ENTRY_TYPE_KERNEL) {
+ /* Special case for linux kernel shutdown reason */
+ elog_add_event_dword(ELOG_TYPE_OS_EVENT,
+ type1->instance);
+ } else {
+ /* Add other events that may be used for testing */
+ elog_add_event_dword(type1->type, type1->instance);
+ }
+ ret = GSMI_RET_SUCCESS;
+ break;
+
+ case GSMI_CMD_CLEAR_EVENT_LOG:
+ /* Get paramter buffer even though we don't use it */
+ cel = (struct gsmi_clear_eventlog_param *)(*param);
+ if (!cel)
+ break;
+
+ printk(BIOS_DEBUG, "GSMI Clear Event Log (%u%% type=%u)\n",
+ cel->percentage, cel->data_type);
+
+ if (elog_clear() == 0)
+ ret = GSMI_RET_SUCCESS;
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "GSMI Unknown: 0x%02x\n", command);
+ break;
+ }
+
+ return ret;
+}
diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
index 8afdd1f..5ce4f62 100644
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -38,6 +38,7 @@
(read32(res->base) >> 8), (read32(res->base) & 0xff));
printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n",
(read32(res->base + 4) & 3));
+ printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base);
}
diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc
index 8ca21bf..0c1a1f0 100644
--- a/src/drivers/pc80/Makefile.inc
+++ b/src/drivers/pc80/Makefile.inc
@@ -14,3 +14,6 @@
cmos.default-type = 0xaa
smm-y += mc146818rtc.c
+
+$(obj)/drivers/pc80/mc146818rtc.ramstage.o : $(obj)/build.h
+$(obj)/drivers/pc80/mc146818rtc.smm.o : $(obj)/build.h
diff --git a/src/drivers/pc80/i8254.c b/src/drivers/pc80/i8254.c
index f75216d..ca993f4 100644
--- a/src/drivers/pc80/i8254.c
+++ b/src/drivers/pc80/i8254.c
@@ -35,7 +35,7 @@
outb(0x12, TIMER1_PORT);
}
-#if defined(CONFIG_UDELAY_TIMER2) && CONFIG_UDELAY_TIMER2
+#if CONFIG_UDELAY_TIMER2
static void load_timer2(unsigned int ticks)
{
/* Set up the timer gate, turn off the speaker */
diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c
index 99d670d..cde13b7 100644
--- a/src/drivers/pc80/mc146818rtc.c
+++ b/src/drivers/pc80/mc146818rtc.c
@@ -1,4 +1,5 @@
#include <stdint.h>
+#include <build.h>
#include <console/console.h>
#include <pc80/mc146818rtc.h>
#include <boot/coreboot_tables.h>
@@ -7,6 +8,9 @@
#include "option_table.h"
#include <cbfs.h>
#endif
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
/* control registers - Moto names
*/
@@ -113,11 +117,13 @@
#endif
#endif
+#ifndef __SMM__
void rtc_init(int invalid)
{
+ int cmos_invalid = 0;
+ int checksum_invalid = 0;
#if CONFIG_USE_OPTION_TABLE
unsigned char x;
- int cmos_invalid, checksum_invalid;
#endif
printk(BIOS_DEBUG, "RTC Init\n");
@@ -132,38 +138,47 @@
PC_CKS_RANGE_END,PC_CKS_LOC);
#define CLEAR_CMOS 0
+#else
+#define CLEAR_CMOS 1
+#endif
+
if (invalid || cmos_invalid || checksum_invalid) {
+#if CLEAR_CMOS
+ int i;
+
+ cmos_write(0, 0x01);
+ cmos_write(0, 0x03);
+ cmos_write(0, 0x05);
+ for(i = 10; i < 128; i++) {
+ cmos_write(0, i);
+ }
+
+ /* Now setup a default date equals to the build date */
+ cmos_write(0, RTC_CLK_SECOND);
+ cmos_write(0, RTC_CLK_MINUTE);
+ cmos_write(1, RTC_CLK_HOUR);
+ cmos_write(RTC_TO_BCD(COREBOOT_BUILD_WEEKDAY),
+ RTC_CLK_DAYOFWEEK);
+ cmos_write(RTC_TO_BCD(COREBOOT_BUILD_DAY),
+ RTC_CLK_DAYOFMONTH);
+ cmos_write(RTC_TO_BCD(COREBOOT_BUILD_MONTH),
+ RTC_CLK_MONTH);
+ cmos_write(RTC_TO_BCD(COREBOOT_BUILD_YEAR),
+ RTC_CLK_YEAR);
+#endif
printk(BIOS_WARNING, "RTC:%s%s%s%s\n",
invalid?" Clear requested":"",
cmos_invalid?" Power Problem":"",
checksum_invalid?" Checksum invalid":"",
CLEAR_CMOS?" zeroing cmos":"");
-#if CLEAR_CMOS
- cmos_write(0, 0x01);
- cmos_write(0, 0x03);
- cmos_write(0, 0x05);
- for(i = 10; i < 48; i++) {
- cmos_write(0, i);
- }
-
- if (cmos_invalid) {
- /* Now setup a default date of Sat 1 January 2000 */
- cmos_write(0, 0x00); /* seconds */
- cmos_write(0, 0x02); /* minutes */
- cmos_write(1, 0x04); /* hours */
- cmos_write(7, 0x06); /* day of week */
- cmos_write(1, 0x07); /* day of month */
- cmos_write(1, 0x08); /* month */
- cmos_write(0, 0x09); /* year */
- }
-#endif
}
-#endif
/* Setup the real time clock */
cmos_write(RTC_CONTROL_DEFAULT, RTC_CONTROL);
/* Setup the frequency it operates at */
cmos_write(RTC_FREQ_SELECT_DEFAULT, RTC_FREQ_SELECT);
+ /* Ensure all reserved bits are 0 in register D */
+ cmos_write(RTC_VRT, RTC_VALID);
#if CONFIG_USE_OPTION_TABLE
/* See if there is a LB CMOS checksum error */
@@ -177,9 +192,20 @@
PC_CKS_RANGE_END,PC_CKS_LOC);
#endif
+#if CONFIG_HAVE_ACPI_RESUME
+ /*
+ * Avoid clearing pending interrupts in the resume path because
+ * the Linux kernel relies on this to know if it should restart
+ * the RTC timerqueue if the wake was due to the RTC alarm.
+ */
+ if (acpi_slp_type == 3)
+ return;
+#endif
+
/* Clear any pending interrupts */
(void) cmos_read(RTC_INTR_FLAGS);
}
+#endif
#if CONFIG_USE_OPTION_TABLE
diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig
index ee7584c..8e6191e 100644
--- a/src/drivers/spi/Kconfig
+++ b/src/drivers/spi/Kconfig
@@ -24,6 +24,13 @@
Select this option if your chipset driver needs to store certain
data in the SPI flash.
+config SPI_FLASH_SMM
+ bool "SPI flash driver support in SMM"
+ default n
+ depends on SPI_FLASH && HAVE_SMI_HANDLER
+ help
+ Select this option if you want SPI flash support in SMM.
+
config SPI_FLASH_EON
bool
default y
@@ -73,9 +80,17 @@
data in the SPI flash and your SPI flash is made by Winbond.
config SPI_FLASH_NO_FAST_READ
- bool
+ bool "Disable Fast Read command"
default n
depends on SPI_FLASH
help
Select this option if your setup requires to avoid "fast read"s
from the SPI flash parts.
+
+config SPI_FLASH_GIGADEVICE
+ bool
+ default y
+ depends on SPI_FLASH
+ help
+ Select this option if your chipset driver needs to store certain
+ data in the SPI flash and your SPI flash is made by Gigadevice.
diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc
index 1814e80..1a34ab5 100644
--- a/src/drivers/spi/Makefile.inc
+++ b/src/drivers/spi/Makefile.inc
@@ -8,5 +8,20 @@
ramstage-$(CONFIG_SPI_FLASH_SST) += sst.c
ramstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c
ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c
+ramstage-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c
ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
+ifeq ($(CONFIG_SPI_FLASH_SMM),y)
+# SPI flash driver interface
+smm-$(CONFIG_SPI_FLASH) += spi_flash.c
+
+# drivers
+smm-$(CONFIG_SPI_FLASH_EON) += eon.c
+smm-$(CONFIG_SPI_FLASH_MACRONIX) += macronix.c
+smm-$(CONFIG_SPI_FLASH_SPANSION) += spansion.c
+smm-$(CONFIG_SPI_FLASH_SST) += sst.c
+smm-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c
+smm-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c
+smm-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c
+smm-$(CONFIG_SPI_FLASH_GIGADEVICE) += gigadevice.c
+endif
\ No newline at end of file
diff --git a/src/drivers/spi/eon.c b/src/drivers/spi/eon.c
index 4056953..7d9bc44 100644
--- a/src/drivers/spi/eon.c
+++ b/src/drivers/spi/eon.c
@@ -85,9 +85,11 @@
cmd[2] = page_addr;
cmd[3] = byte_addr;
+#if CONFIG_DEBUG_SPI_FLASH
printk(BIOS_SPEW,
- "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+ "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
ret = spi_flash_cmd(flash->spi, CMD_EN25Q128_WREN, NULL, 0);
if (ret < 0) {
diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c
new file mode 100644
index 0000000..0647baf
--- /dev/null
+++ b/src/drivers/spi/gigadevice.c
@@ -0,0 +1,241 @@
+/*
+ * Copyright (c) 2012, Google Inc.
+ *
+ * Based on drivers/spi/winbond.c
+ *
+ * Copyright 2008, Network Appliance Inc.
+ * Jason McMullan <mcmullan@netapp.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <stdlib.h>
+#include <spi_flash.h>
+#include "spi_flash_internal.h"
+
+/* GD25Pxx-specific commands */
+#define CMD_GD25_WREN 0x06 /* Write Enable */
+#define CMD_GD25_WRDI 0x04 /* Write Disable */
+#define CMD_GD25_RDSR 0x05 /* Read Status Register */
+#define CMD_GD25_WRSR 0x01 /* Write Status Register */
+#define CMD_GD25_READ 0x03 /* Read Data Bytes */
+#define CMD_GD25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */
+#define CMD_GD25_PP 0x02 /* Page Program */
+#define CMD_GD25_SE 0x20 /* Sector (4K) Erase */
+#define CMD_GD25_BE 0xd8 /* Block (64K) Erase */
+#define CMD_GD25_CE 0xc7 /* Chip Erase */
+#define CMD_GD25_DP 0xb9 /* Deep Power-down */
+#define CMD_GD25_RES 0xab /* Release from DP, and Read Signature */
+
+struct gigadevice_spi_flash_params {
+ uint16_t id;
+ /* Log2 of page size in power-of-two mode */
+ uint8_t l2_page_size;
+ uint16_t pages_per_sector;
+ uint16_t sectors_per_block;
+ uint16_t nr_blocks;
+ const char *name;
+};
+
+/* spi_flash needs to be first so upper layers can free() it */
+struct gigadevice_spi_flash {
+ struct spi_flash flash;
+ const struct gigadevice_spi_flash_params *params;
+};
+
+static inline struct gigadevice_spi_flash *
+to_gigadevice_spi_flash(struct spi_flash *flash)
+{
+ return container_of(flash, struct gigadevice_spi_flash, flash);
+}
+
+static const struct gigadevice_spi_flash_params gigadevice_spi_flash_table[] = {
+ {
+ .id = 0x4014,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 16,
+ .name = "GD25Q80",
+ },
+ {
+ .id = 0x4015,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 32,
+ .name = "GD25Q16(B)",
+ },
+ {
+ .id = 0x4016,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "GD25Q32(B)",
+ },
+ {
+ .id = 0x6016,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 64,
+ .name = "GD25LQ32",
+ },
+ {
+ .id = 0x4017,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 128,
+ .name = "GD25Q64(B)",
+ },
+ {
+ .id = 0x4018,
+ .l2_page_size = 8,
+ .pages_per_sector = 16,
+ .sectors_per_block = 16,
+ .nr_blocks = 256,
+ .name = "GD25Q128(B)",
+ },
+};
+
+static int gigadevice_write(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ struct gigadevice_spi_flash *stm = to_gigadevice_spi_flash(flash);
+ unsigned long byte_addr;
+ unsigned long page_size;
+ size_t chunk_len;
+ size_t actual;
+ int ret;
+ u8 cmd[4];
+
+ page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT);
+ byte_addr = offset % page_size;
+
+ ret = spi_claim_bus(flash->spi);
+ if (ret) {
+ printk(BIOS_WARNING,
+ "SF gigadevice.c: Unable to claim SPI bus\n");
+ return ret;
+ }
+
+ for (actual = 0; actual < len; actual += chunk_len) {
+ chunk_len = min(len - actual, page_size - byte_addr);
+
+ ret = spi_flash_cmd(flash->spi, CMD_GD25_WREN, NULL, 0);
+ if (ret < 0) {
+ printk(BIOS_WARNING,
+ "SF gigadevice.c: Enabling Write failed\n");
+ goto out;
+ }
+
+ cmd[0] = CMD_GD25_PP;
+ cmd[1] = (offset >> 16) & 0xff;
+ cmd[2] = (offset >> 8) & 0xff;
+ cmd[3] = offset & 0xff;
+#if CONFIG_DEBUG_SPI_FLASH
+ printk(BIOS_SPEW,
+ "PP gigadevice.c: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+ " chunk_len = %zu\n", buf + actual,
+ cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
+
+ ret = spi_flash_cmd_write(flash->spi, cmd, 4,
+ buf + actual, chunk_len);
+ if (ret < 0) {
+ printk(BIOS_WARNING,
+ "SF gigadevice.c: Page Program failed\n");
+ goto out;
+ }
+
+ ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
+ if (ret)
+ goto out;
+
+ offset += chunk_len;
+ byte_addr = 0;
+ }
+
+ printk(BIOS_INFO,
+ "SF gigadevice.c: Successfully programmed %zu bytes @ %#x\n",
+ len, (unsigned int)(offset - len));
+ ret = 0;
+
+out:
+ spi_release_bus(flash->spi);
+ return ret;
+}
+
+static int gigadevice_erase(struct spi_flash *flash, u32 offset, size_t len)
+{
+ return spi_flash_cmd_erase(flash, CMD_GD25_SE, offset, len);
+}
+
+struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi, u8 *idcode)
+{
+ const struct gigadevice_spi_flash_params *params;
+ unsigned page_size;
+ struct gigadevice_spi_flash *stm;
+ unsigned int i;
+
+ for (i = 0; i < ARRAY_SIZE(gigadevice_spi_flash_table); i++) {
+ params = &gigadevice_spi_flash_table[i];
+ if (params->id == ((idcode[1] << 8) | idcode[2]))
+ break;
+ }
+
+ if (i == ARRAY_SIZE(gigadevice_spi_flash_table)) {
+ printk(BIOS_WARNING,
+ "SF gigadevice.c: Unsupported ID %#02x%02x\n",
+ idcode[1], idcode[2]);
+ return NULL;
+ }
+
+ stm = malloc(sizeof(struct gigadevice_spi_flash));
+ if (!stm) {
+ printk(BIOS_WARNING,
+ "SF gigadevice.c: Failed to allocate memory\n");
+ return NULL;
+ }
+
+ stm->params = params;
+ stm->flash.spi = spi;
+ stm->flash.name = params->name;
+
+ /* Assuming power-of-two page size initially. */
+ page_size = 1 << params->l2_page_size;
+
+ stm->flash.write = gigadevice_write;
+ stm->flash.erase = gigadevice_erase;
+#if CONFIG_SPI_FLASH_NO_FAST_READ
+ stm->flash.read = spi_flash_cmd_read_slow;
+#else
+ stm->flash.read = spi_flash_cmd_read_fast;
+#endif
+ stm->flash.sector_size = (1 << stm->params->l2_page_size) *
+ stm->params->pages_per_sector;
+ stm->flash.size = page_size * params->pages_per_sector
+ * params->sectors_per_block
+ * params->nr_blocks;
+
+ return &stm->flash;
+}
diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c
index 130e746..baee0a5 100644
--- a/src/drivers/spi/macronix.c
+++ b/src/drivers/spi/macronix.c
@@ -141,8 +141,11 @@
cmd[2] = (offset >> 8) & 0xff;
cmd[3] = offset & 0xff;
- printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+#if CONFIG_DEBUG_SPI_FLASH
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+ " chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
ret = spi_flash_cmd(flash->spi, CMD_MX25XX_WREN, NULL, 0);
if (ret < 0) {
@@ -165,8 +168,9 @@
byte_addr = 0;
}
- printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @ 0x%lx\n",
- len, offset - len);
+ printk(BIOS_INFO, "SF: Macronix: Successfully programmed %zu bytes @"
+ " 0x%x\n",
+ len, (unsigned int)(offset - len));
spi_release_bus(flash->spi);
return ret;
@@ -207,7 +211,7 @@
mcx->flash.write = macronix_write;
mcx->flash.erase = macronix_erase;
-#ifdef CONFIG_SPI_FLASH_NO_FAST_READ
+#if CONFIG_SPI_FLASH_NO_FAST_READ
mcx->flash.read = spi_flash_cmd_read_slow;
#else
mcx->flash.read = spi_flash_cmd_read_fast;
diff --git a/src/drivers/spi/spansion.c b/src/drivers/spi/spansion.c
index a4f370a..511091b 100644
--- a/src/drivers/spi/spansion.c
+++ b/src/drivers/spi/spansion.c
@@ -162,8 +162,11 @@
cmd[2] = page_addr;
cmd[3] = byte_addr;
- printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+#if CONFIG_DEBUG_SPI_FLASH
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+ " chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
ret = spi_flash_cmd(flash->spi, CMD_S25FLXX_WREN, NULL, 0);
if (ret < 0) {
diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c
index 7384cbc..2ebd7fd 100644
--- a/src/drivers/spi/spi_flash.c
+++ b/src/drivers/spi/spi_flash.c
@@ -12,6 +12,9 @@
#include <spi.h>
#include <spi_flash.h>
#include <delay.h>
+#ifdef __SMM__
+#include <cpu/x86/smm.h>
+#endif
#include "spi_flash_internal.h"
static void spi_flash_addr(u32 addr, u8 *cmd)
@@ -115,7 +118,7 @@
if ((status & poll_bit) == 0)
break;
- mdelay(1);
+ udelay(500);
} while (timebase--);
if ((status & poll_bit) == 0)
@@ -206,7 +209,7 @@
*/
#define IDCODE_CONT_LEN 0
#define IDCODE_PART_LEN 5
-static const struct {
+static struct {
const u8 shift;
const u8 idcode;
struct spi_flash *(*probe) (struct spi_slave *spi, u8 *idcode);
@@ -215,6 +218,9 @@
#if CONFIG_SPI_FLASH_EON
{ 0, 0x1c, spi_flash_probe_eon, },
#endif
+#if CONFIG_SPI_FLASH_GIGADEVICE
+ { 0, 0xc8, spi_flash_probe_gigadevice, },
+#endif
#if CONFIG_SPI_FLASH_MACRONIX
{ 0, 0xc2, spi_flash_probe_macronix, },
#endif
@@ -264,7 +270,6 @@
#if CONFIG_DEBUG_SPI_FLASH
printk(BIOS_SPEW, "SF: Got idcodes\n");
- print_buffer(0, idcode, 1, sizeof(idcode), 0);
#endif
/* count the number of continuation bytes */
@@ -276,6 +281,10 @@
/* search the table for matches in shift and id */
for (i = 0; i < ARRAY_SIZE(flashes); ++i)
if (flashes[i].shift == shift && flashes[i].idcode == *idp) {
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Need to relocate this function */
+ tseg_relocate((void **)&flashes[i].probe);
+#endif
/* we have a match, call probe */
flash = flashes[i].probe(spi, idp);
if (flash)
@@ -287,6 +296,14 @@
goto err_manufacturer_probe;
}
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ /* Ensure flash handlers are valid for TSEG */
+ tseg_relocate((void **)&flash->read);
+ tseg_relocate((void **)&flash->write);
+ tseg_relocate((void **)&flash->erase);
+ tseg_relocate((void **)&flash->name);
+#endif
+
printk(BIOS_INFO, "SF: Detected %s with page size %x, total %x\n",
flash->name, flash->sector_size, flash->size);
@@ -298,12 +315,5 @@
err_read_id:
spi_release_bus(spi);
err_claim_bus:
- spi_free_slave(spi);
return NULL;
}
-
-void spi_flash_free(struct spi_flash *flash)
-{
- spi_free_slave(flash->spi);
- free(flash);
-}
diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h
index b895e2b..37ffee6 100644
--- a/src/drivers/spi/spi_flash_internal.h
+++ b/src/drivers/spi/spi_flash_internal.h
@@ -78,4 +78,6 @@
struct spi_flash *spi_flash_probe_sst(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode);
struct spi_flash *spi_flash_probe_winbond(struct spi_slave *spi, u8 *idcode);
+struct spi_flash *spi_flash_probe_gigadevice(struct spi_slave *spi,
+ u8 *idcode);
struct spi_flash *spi_fram_probe_ramtron(struct spi_slave *spi, u8 *idcode);
diff --git a/src/drivers/spi/sst.c b/src/drivers/spi/sst.c
index 56cc851..07050fc 100644
--- a/src/drivers/spi/sst.c
+++ b/src/drivers/spi/sst.c
@@ -194,8 +194,8 @@
ret = sst_byte_write(flash, offset, buf + actual);
done:
- printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%lx\n",
- ret ? "failure" : "success", len, offset - actual);
+ printk(BIOS_INFO, "SF: SST: program %s %zu bytes @ 0x%x\n",
+ ret ? "failure" : "success", len, (unsigned int)(offset - actual));
spi_release_bus(flash->spi);
return ret;
diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c
index 8cbdad5..ccdfa00 100644
--- a/src/drivers/spi/stmicro.c
+++ b/src/drivers/spi/stmicro.c
@@ -163,8 +163,11 @@
cmd[2] = page_addr;
cmd[3] = byte_addr;
- printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zd\n",
+#if CONFIG_DEBUG_SPI_FLASH
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+ " chunk_len = %zu\n",
buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0);
if (ret < 0) {
diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c
index 65818d5..ac9cf30 100644
--- a/src/drivers/spi/winbond.c
+++ b/src/drivers/spi/winbond.c
@@ -130,9 +130,11 @@
cmd[1] = (offset >> 16) & 0xff;
cmd[2] = (offset >> 8) & 0xff;
cmd[3] = offset & 0xff;
- printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %ld\n",
- buf + actual,
+#if CONFIG_DEBUG_SPI_FLASH
+ printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }"
+ " chunk_len = %zu\n", buf + actual,
cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
+#endif
ret = spi_flash_cmd(flash->spi, CMD_W25_WREN, NULL, 0);
if (ret < 0) {
@@ -155,8 +157,8 @@
byte_addr = 0;
}
- printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%lx\n",
- len, offset - len);
+ printk(BIOS_INFO, "SF: Winbond: Successfully programmed %zu bytes @ 0x%x\n",
+ len, (unsigned int)(offset - len));
ret = 0;
out:
@@ -203,7 +205,7 @@
stm->flash.write = winbond_write;
stm->flash.erase = winbond_erase;
-#ifdef CONFIG_SPI_FLASH_NO_FAST_READ
+#if CONFIG_SPI_FLASH_NO_FAST_READ
stm->flash.read = spi_flash_cmd_read_slow;
#else
stm->flash.read = spi_flash_cmd_read_fast;
diff --git a/src/ec/Kconfig b/src/ec/Kconfig
index 935b40b..d3ac471 100644
--- a/src/ec/Kconfig
+++ b/src/ec/Kconfig
@@ -1,3 +1,6 @@
source src/ec/acpi/Kconfig
+source src/ec/compal/Kconfig
+source src/ec/google/Kconfig
source src/ec/lenovo/Kconfig
source src/ec/smsc/Kconfig
+source src/ec/quanta/Kconfig
diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc
index b334c1f..b363016 100644
--- a/src/ec/Makefile.inc
+++ b/src/ec/Makefile.inc
@@ -1,2 +1,2 @@
subdirs-$(CONFIG_EC_ACPI) += acpi
-subdirs-y += lenovo smsc
+subdirs-y += compal google lenovo smsc quanta
diff --git a/src/ec/compal/Kconfig b/src/ec/compal/Kconfig
new file mode 100644
index 0000000..5b7899a
--- /dev/null
+++ b/src/ec/compal/Kconfig
@@ -0,0 +1 @@
+source src/ec/compal/ene932/Kconfig
diff --git a/src/ec/compal/Makefile.inc b/src/ec/compal/Makefile.inc
new file mode 100644
index 0000000..ce75ca6
--- /dev/null
+++ b/src/ec/compal/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_EC_COMPAL_ENE932) += ene932
diff --git a/src/ec/compal/ene932/Kconfig b/src/ec/compal/ene932/Kconfig
new file mode 100644
index 0000000..47e4b7b
--- /dev/null
+++ b/src/ec/compal/ene932/Kconfig
@@ -0,0 +1,4 @@
+config EC_COMPAL_ENE932
+ bool
+ help
+ Interface to COMPAL ENE932 Embedded Controller.
diff --git a/src/ec/compal/ene932/Makefile.inc b/src/ec/compal/ene932/Makefile.inc
new file mode 100644
index 0000000..0a8d0ca
--- /dev/null
+++ b/src/ec/compal/ene932/Makefile.inc
@@ -0,0 +1,3 @@
+driver-y += ec.c
+smm-y += ec.c
+smm-y += ../../../lib/delay.c
diff --git a/src/mainboard/getac/p470/chip.h b/src/ec/compal/ene932/acpi/ac.asl
similarity index 72%
copy from src/mainboard/getac/p470/chip.h
copy to src/ec/compal/ene932/acpi/ac.asl
index b75c381..8c85fc3 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/ec/compal/ene932/acpi/ac.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,5 +19,21 @@
* MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR)
+ {
+ Store(ADPT, Local0)
+ Return(Local0)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/ec/compal/ene932/acpi/battery.asl b/src/ec/compal/ene932/acpi/battery.asl
new file mode 100644
index 0000000..90d8adb
--- /dev/null
+++ b/src/ec/compal/ene932/acpi/battery.asl
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (BATX)
+{
+ Name (_HID, EISAID ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ Name (PBIF, Package () {
+ 0x00000001, // Power Unit: mAh
+ 0xFFFFFFFF, // Design Capacity
+ 0xFFFFFFFF, // Last Full Charge Capacity
+ 0x00000001, // Battery Technology: Rechargeable
+ 0xFFFFFFFF, // Design Voltage
+ 0x00000003, // Design Capacity of Warning
+ 0xFFFFFFFF, // Design Capacity of Low
+ 0x00000001, // Capacity Granularity 1
+ 0x00000001, // Capacity Granularity 2
+ "", // Model Number
+ "", // Serial Number
+ "LION", // Battery Type
+ "" // OEM Information
+ })
+
+ Name (PBST, Package () {
+ 0x00000000, // Battery State
+ 0xFFFFFFFF, // Battery Present Rate
+ 0xFFFFFFFF, // Battery Remaining Capacity
+ 0xFFFFFFFF, // Battery Present Voltage
+ })
+ Name (BTNM, Zero) // Battery number
+
+ // Workaround for full battery status, enabled by default
+ Name (BFWK, One)
+
+ // Method to enable full battery workaround
+ Method (BFWE)
+ {
+ Store (One, BFWK)
+ }
+
+ // Method to disable full battery workaround
+ Method (BFWD)
+ {
+ Store (Zero, BFWK)
+ }
+
+ Method (_STA, 0, Serialized)
+ {
+ If (BOL0) {
+ Return (0x1F)
+ } Else {
+ Return (0x0F)
+ }
+ }
+
+ Method (_BIF, 0, Serialized)
+ {
+ // Update fields from EC
+ Store (BAM0, Index (PBIF, 0))
+ Store (BDC0, Index (PBIF, 1))
+ Store (BFC0, Index (PBIF, 2))
+ Store (BDV0, Index (PBIF, 4))
+ Divide(BFC0, 0x64, Local0, Local1)
+ Multiply(Local1, 0x0A, Local1)
+ Store(Local1, Index(PBIF, 5))
+ Divide(BFC0, 0x64, Local0, Local1)
+ Multiply(Local1, 0x03, Local1)
+ Store (Local1, Index (PBIF, 6))
+
+ Store (ToString(BATD), Index (PBIF, 9)) // model
+ Store (ToHexString(BSN0), Index (PBIF, 10)) // serial
+ Store (ToString(BMFN), Index (PBIF, 12)) // venor
+
+ Store(BDN0, BTNM) // Save the battery number
+
+ Return (PBIF)
+ }
+
+ Method (_BST, 0, Serialized)
+ {
+ //
+ // 0: BATTERY STATE
+ //
+ // bit 0 = discharging
+ // bit 1 = charging
+ // bit 2 = critical level
+ //
+
+ // Get battery state from EC and save it for the charging workaround
+ Store (BST0, Local0)
+ Store (Local0, Index (PBST, 0))
+
+ //
+ // 1: BATTERY PRESENT RATE/CURRENT
+ //
+
+ Store (BAC0, Local1)
+ Subtract(0xFFFF, Local1, Local1)
+ Store (Local1, Index (PBST, 1))
+
+ //
+ // 2: BATTERY REMAINING CAPACITY
+ //
+ Multiply(BFC0, GAU0, Local1)
+ Divide(Local1, 0x64, Local2, Local1)
+
+ If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) {
+ // On AC power and battery is neither charging
+ // nor discharging. Linux expects a full battery
+ // to report same capacity as last full charge.
+ // https://bugzilla.kernel.org/show_bug.cgi?id=12632
+ Store (GAU0, Local2)
+
+ // See if within ~3% of full
+ ShiftRight (Local2, 5, Local3)
+ If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+ LLess (Local1, Add (Local2, Local3))))
+ {
+ Store (Local2, Local1)
+ }
+ }
+ Store (Local1, Index (PBST, 2))
+
+ //
+ // 3: BATTERY PRESENT VOLTAGE
+ //
+ Store (BPV0, Index (PBST, 3))
+
+ // Check the Battery Number
+ If(LNotEqual(BDN0, BTNM)) {
+ Notify(BATX, 0x81)
+ }
+
+ Return (PBST)
+ }
+}
diff --git a/src/ec/compal/ene932/acpi/ec.asl b/src/ec/compal/ene932/acpi/ec.asl
new file mode 100644
index 0000000..cb50a21
--- /dev/null
+++ b/src/ec/compal/ene932/acpi/ec.asl
@@ -0,0 +1,355 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 1)
+ Name (_GPE, EC_SCI) // GPE for Runtime SCI
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ // EC Name Space Configuration
+ Offset(0x00),
+ , 1, // Reserved ; 00h.0
+ LCDS, 1, // 1= BACKLIGHT ON , 0= BACKLIGHT OFF ; 00h.1
+ , 6, // Reserved ; 00h.2 ~ 00h.6
+ HTBN, 8, // HOTKEY_BUTTON_NUMBER ; 01h For ABO Hot Key Function
+ HTBT, 8, // HOTKEY_BUTTON_TYPE ; 02h For ABO Hot Key Function
+ LMEN, 1, // Launch Manager enable .(1=Enable ) ; 03h.0, Lauanch manage
+ , 7, // Reserved ; 03h.1 ~ 03h.7
+ ADAP, 2, // Adaptor Type ; 04h.0 ~ 1
+ // 0x00 = default(65w)
+ // 0x01 = 65w
+ // 0x02 = 90w
+ // 0x03 = 120w
+ , 6, // Reserved ; 04h.2 ~ 04h.7
+ Offset(0x08), // Project Common Name space definition ; 08h - 2Ch
+ Offset(0x2D),
+ DSPM, 1, // Display Mode.(0=dGPU, 1=iGPU ) ; 2Dh.0
+ Offset(0x2E),
+ EFP1, 4, // Turbo Off P-State ; 2Eh.3-0
+ Offset(0x40), // ABO Common Name space definition ; 2F - 5Ch
+ Offset(0x5D),
+ ENIB, 16, // Ext_NameSpace_Index ; 5Dh
+ // Ext_NameSpace_Bank ; 5Eh
+ ENDD, 8, // Ext_NameSpace_Data ; 5Fh
+ Offset(0x60),
+ SMPR, 8, // SMBus protocol register ; 60h
+ SMST, 8, // SMBus status register ; 61h
+ SMAD, 8, // SMBus address register ; 62h
+ SMCM, 8, // SMBus command register ; 63h
+ SMD0, 0x100, // SMBus data regs (32) ; 64h - 83h
+ BCNT, 8, // SMBus Block Count ; 84h
+ SMAA, 24, // SMBus Alarm Address ; 85h - 87h
+ Offset(0x90),
+ BMFN, 72, // Battery Manufacture name ; 90h - 98h
+ BATD, 56, // Battery Device name ; 99h - 9fh
+ Offset(0xA1),
+ , 1, // Reserve ; A1h.0
+ VIDO, 1, // Video Out Button (1=Pressed) ; A1h.1
+ TOUP, 1, // Touch Pad Button (0=On, 1=Off) ; A1h.2
+ Offset(0xA2),
+ ODTS, 8, // OS Shutdown Temp2 (DTS) ; A2h
+ Offset(0xA3),
+ OSTY, 3, // OSTYPE : 000- XP ; A3h.0-2
+ // 001- Vista
+ // 010- Linux
+ // 011- Win7
+ , 4, // Reserve ; A3h.3-6
+ ADPT, 1, // AC Adapter (0=OffLine, 1=OnLine) ; A3h.7
+ Offset(0xA4),
+ PWAK, 1, // PME Wake Enable(0=Disable, 1=Enable) ; A4h.0
+ MWAK, 1, // Modem Wake Enable(0/1=Disable/Enable); A4h.1
+ LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); A4h.2
+ RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; A4h.3
+ WWAK, 1, // WLAN wake Enable (0=Disable,1=Enable); A4h.4
+ UWAK, 1, // USB WAKE(0=Disable, 1=Enable) ; A4h.5
+ KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; A4h.6
+ TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; A4h.7
+ Offset(0xA5),
+ CCAC, 1, // Charge Current (1=AC OFF) ; A5h.0
+ AOAC, 1, // Adapter OVP (1=AC OFF) ; A5h.1
+ BLAC, 1, // Batt learning (1=AC OFF) ; A5h.2
+ PSRC, 1, // Command (1=AC OFF) ; A5h.3
+ BOAC, 1, // Batt OVP (1=AC OFF) ; A5h.4
+ LCAC, 1, // Leak Current (1=AC OFF) ; A5h.5
+ AAAC, 1, // Air Adapter (1=AC OFF) ; A5h.6
+ ACAC, 1, // AC Off (1=AC OFF) ; A5h.7
+ Offset(0xA6),
+ S3ST, 1, // System entry S3 State : A6.0
+ S3RM, 1, // System resume from S3 State : A6.1
+ S4ST, 1, // System entry S4 State : A6.2
+ S4RM, 1, // System resume from S4 State : A6.3
+ S5ST, 1, // System entry S4 State : A6.4
+ S5RM, 1, // System resume from S4 State : A6.5
+ , 2, // Reserve ; A6h.6-7
+ Offset(0xA7),
+ OSTT, 8, // OS Throttling Temp ; A7h
+ OSST, 8, // OS Shutdown Temp ; A8h
+ THLT, 8, // Throttling Temp ; A9h
+ TCNL, 8, // Tcontrol Temp ; AAh
+ MODE, 1, // Mode(0=Local, 1=Remote) ; ABh.0
+ , 2, // Reserve ; ABh.1-2
+ INIT, 1, // INITOK(0/1=Controlled by OS/EC) ; ABh.3
+ FAN1, 1, // FAN1 Active ; ABh.4
+ FAN2, 1, // FAN2 Active ; ABh.5
+ FANT, 1, // FAN Speed Time OK ; ABh.6
+ SKNM, 1, // Skin Mode (0/1=Skin Address 90/92) ; ABh.7
+ SDTM, 8, // Shutdown Thermal Temperature ; ACh
+ FSSN, 4, // Fan Speed Step Number ; ADh.0-3
+ // 00 : Fan Off
+ // 01 : Fan On Speed 1
+ // 10 : Fan On Speed 2
+ // 11 : Fan On Speed 3
+ FANU, 4, // Machine Fan's number ; ADh.4-7
+ PCVL, 4, // Throttling Level ; AEh.0-3
+ // 0000 : Nothing
+ // 0001 : Clock throttling 12.5%
+ // 0010 : Clock throttling 25%
+ // 0011 : Clock throttling 37.5%
+ // 0100 : Clock throttling 50%
+ , 2, // Reserved ; AEh.4-5
+ SWTO, 1, // SW Throttling (1=Active) ; AEh.6
+ TTHR, 1, // HW (THRM#) Throttling (1=Active) ; AEh.7
+ TTHM, 1, // TS_THERMAL(1:Throttling for thermal) ; AFh.0
+ THTL, 1, // THROTTLING(1:Ctrl H/W throtting act) ; AFh.1
+ , 2, // Reserved ; AFh.2-3
+ NPST, 4, // Number of P-State level ; AFh.4-7
+ CTMP, 8, // Current CPU Temperature ; B0h
+ CTML, 8, // CPU local temperature ; B1h
+ SKTA, 8, // Skin Temperature A ; B2h
+ SKTB, 8, // GPU Temperature ; B3h
+ SKTC, 8, // Skin Temperature C ; B4h
+ , 8, // Reserved ; B5h
+ NTMP, 8, // North Bridge Diode Temp ; B6h
+ Offset(0xB7),
+ , 1, // Reserved ; B7h.0
+ SKEY, 1, // Security key event ; B7h.1
+ DIGM, 1, // Digital Mode (1=Selected) ; B7h.2
+ CDLE, 1, // CD lock mode enable ; B7h.3
+ , 4, // Reserved ; B7h.4-7
+ , 1, // Reserved ; B8h.0
+ LIDF, 1, // LID flag (1=Closed, 0=Opened) ; B8h.1
+ PMEE, 1, // PME event (0=off, 1=On) ; B8h.2
+ PWBE, 1, // Power button event (0=off, 1=On) ; B8h.3
+ RNGE, 1, // Ring in event (0=off, 1=On) ; B8h.4
+ BTWE, 1, // Bluetooth wake event (0=off, 1=On) ; B8h.5
+ , 2, // Reserved ; B8h.6-7
+ Offset(0xB9),
+ BRTS, 8, // Brightness Value ; B9h
+ S35M, 1, // S3.5 HotKey test mode ; BAh.0
+ S35S, 1, // S3.5 function status ; BAh.1
+ , 2, // Reserved ; BAh.2-3
+ FFEN, 1, // IRST support bit (1= Support) ; BAh.4
+ FFST, 1, // IRST status flag ; BAh.5
+ , 2, // Reserved ; BAh.6-7
+ WLAT, 1, // Wireless LAN (0=Inactive, 1=Active) ; BBh.0
+ BTAT, 1, // BlueTooth (0=Inactive, 1=Active) ; BBh.1
+ WLEX, 1, // Wireless LAN (0=Not Exist, 1=Exist) ; BBh.2
+ BTEX, 1, // BlueTooth (0=Not Exist, 1=Exist) ; BBh.3
+ KLSW, 1, // Kill Switch (0=Off, 1=On) ; BBh.4
+ WLOK, 1, // Wireless LAN Initialize OK ; BBh.5
+ AT3G, 1, // 3G (0=non-active, 1=active) ; BBh.6
+ EX3G, 1, // 3G (0=Not Exist, 1=Exist) ; BBh.7
+ PJID, 8, // Project ID ; BCh
+ CPUJ, 3, // CPU Type ; BDh.0-2
+ // 00, Tj85,
+ // 01, Tj90,
+ // 02, Tj100,
+ // 03, Tj105,
+ // 04 - 07, Reserved
+ CPNM, 3, // CPU Core number ; BDh.3-5
+ // 00, Single Core
+ // 01, Dual Core
+ // 02, Quad Core
+ // 03 - 07, Reserved
+ GATY, 2, // VGA Type ; BDh.6-7
+ // 00, UMA
+ // 01. Discrete
+ // 02 - 03, Reserved
+ Offset(0xBE),
+ BOL0, 1, // Batt0 (0=OffLine, 1=OnLine) ; BEh.0
+ BOL1, 1, // Batt1 (0=OffLine, 1=OnLine) ; BEh.1
+ , 2, // Reserved ; BEh.2-3
+ BCC0, 1, // Batt0 be charging (1=Charging) ; BEh.4
+ BCC1, 1, // Batt1 be charging (1=Charging) ; BEh.5
+ , 2, // Reserved ; BEh.6-7
+ BPU0, 1, // Batt0 (1=PowerUp) ; BFh.0
+ BPU1, 1, // Batt1 (1=PowerUp) ; BFh.1
+ , 2, // Reserved ; BFh.2-3
+ BOS0, 1, // Batt0 (1=OnSMBUS) ; BFh.4
+ BOS1, 1, // Batt1 (1=OnSMBUS) ; BFh.5
+ , 2, // Reserved ; BFh.6-7
+ Offset(0xC0),
+ BTY0, 1, // Batt Type (0=NiMh, 1=LiIon) ; C0h.0
+ BAM0, 1, // Battery mode (0=mA, 1=mW) ; C0h.1
+ BAL0, 1, // Low Battery ; C0h.2
+ , 1, // Reserved ; C0h.3
+ BMF0, 3, // Battery Manufacturer ; C0h.4-6
+ // 001 : Sanyo
+ // 010 : Sony
+ // 100 : Pansonic
+ // 101 : CPT
+ , 1, // Reserved ; C0h.7
+ BST0, 8, // Battery Status ; C1h
+ // Bit0 : Discharging
+ // Bit1 : Charging
+ // Bit2 : Discharg and Critical Low
+ // Bit3-7 : Reserved
+ BRC0, 16, // Batt Remaining Capacity ; C2h, C3h
+ BSN0, 16, // Batt Serial Number ; C4h, C5h
+ BPV0, 16, // Batt Present Voltage ; C6h, C7h
+ BDV0, 16, // Batt Design Voltage ; C8h, C9h
+ BDC0, 16, // Batt Design Capacity ; CAh, CBh
+ BFC0, 16, // Batt Last Full Charge Capacity ; CCh, CDh
+ GAU0, 8, // Batt Gasgauge ; CEh
+ CYC0, 8, // Batt Cycle Counter ; CFh
+ BPC0, 16, // Batt Current ; D0h, D1h
+ BAC0, 16, // Batt Average Current ; D2h, D3h
+ BTW0, 8, // Batt Comsuption ; D4h
+ BVL0, 8, // Batt Battery Volt ; D5h
+ BTM0, 8, // Batt Battery Temp ; D6h
+ BAT0, 8, // Batt Average Temp (Degree C) ; D7h
+ BCG0, 16, // Batt charge current ; D8h, D9h
+ BCT0, 8, // Batt Current Temp Semple counter ; DAh
+ BCI0, 8, // BATT CMD Index for read BATT(SMB) ; DBh
+ BCM0, 8, // Count up to Communicate BATT ; DCh
+ BOT0, 8, // Count up if BATT over Temp ; DDh
+ BSSB, 16, // BATT Battery Status SMB ; DEh, DFh
+ BOV0, 8, // BATT Over Voltage Count ; E0h
+ BCF0, 8, // BATT Communication Fail Counter ; E1h
+ BAD0, 8, // Battery Voltage of ADC ; E2h
+ BCV1, 16, // Cell Voltage 1 (mV) ; E3h, E4h
+ BCV2, 16, // Cell Voltage 2 (mV) ; E5h, E6h
+ BCV3, 16, // Cell Voltage 3 (mV) ; E7h, E8h
+ BCV4, 16, // Cell Voltage 4 (mV) ; E9h, EAh
+ Offset(0xF4),
+ BMD0, 16, // Manufacture Date ; F4h, F5h
+ // Batt Day ; BIT[4:0] (Day)
+ // Batt Month ; BIT[9:5] (Month)
+ // Batt Year ; BIT[15:10] (Year)
+ BACV, 16, // Charging Voltage ; F6h, F7h
+ BDN0, 8, // Battery Cell Number ; F8h
+ , 8 // Last byte for Reserved.
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+ Return (ECMD)
+ }
+
+ Method (_REG, 2, NotSerialized)
+ {
+ // Initialize AC power state
+ Store (ADPT, \PWRS)
+
+ // Initialize LID switch state
+ Store (GP15, \LIDS)
+
+ // Force a read of CPU temperature
+ Store (CTML, Local0)
+ }
+
+
+/*
+ * EC Query Responses
+ *
+ * DTS temperature update 10h
+ * Decrease brightness event 11h
+ * Increase brightness event 12h
+ * Cover lid open 15h
+ * Cover lid close 16h
+ * External device plugged 17h
+ * External device removed 18h
+ * Bluetooth wake up event 19h
+ * Scr expand event 1Bh
+ * Display toggle 1Ch
+ * CPU fast/slow event 1Dh
+ * Battery in critical low 22h
+ * Battery in low state 23h
+ * Battery pack plug in 25h
+ * Docking in 2Ah
+ * Undock 2Bh
+ * Power button pressed 32h
+ * AC plug in 37h
+ * AC removed 38h
+ * Modem ring in 3Ah
+ * PME signal active 3Eh
+ * Hotkey make Function 45h
+ * Hotkey break Function 46h
+ */
+
+ // AC Power Connected
+ Method (_Q37, 0, NotSerialized)
+ {
+ Store (One, \PWRS)
+ Notify (AC, 0x80)
+ Notify (BATX, 0x80)
+ // TODO ADD CPU power profile
+ \PNOT ()
+ }
+
+ // AC Power Removed
+ Method (_Q38, 0, NotSerialized)
+ {
+ Store (Zero, \PWRS)
+ Notify (AC, 0x80)
+ Notify (BATX, 0x80)
+ // TODO ADD CPU power profile
+ \PNOT ()
+ }
+
+ // Battery at critical low state
+ Method (_Q22, 0, NotSerialized)
+ {
+ Notify (BATX, 0x80)
+ }
+
+ // Battery insert
+ Method(_Q25, 0, NotSerialized)
+ {
+ Notify(BATX, 0x81)
+ Notify(BATX, 0x80)
+ }
+
+ // Commuation Device Disable/Enable Event
+ Method(_Q60, 0, NotSerialized)
+ {
+ IF(WLEX) //if Wlan exist
+ {
+ //TODO Store(WLAT, LANE)
+ }
+ }
+
+ #include "ac.asl"
+ #include "battery.asl"
+}
diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl
new file mode 100644
index 0000000..db4b412
--- /dev/null
+++ b/src/ec/compal/ene932/acpi/superio.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+
+#ifdef SIO_EC_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0) {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+}
diff --git a/src/mainboard/getac/p470/chip.h b/src/ec/compal/ene932/chip.h
similarity index 66%
copy from src/mainboard/getac/p470/chip.h
copy to src/ec/compal/ene932/chip.h
index b75c381..5d209ff 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/ec/compal/ene932/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,5 +19,17 @@
* MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+#ifndef _EC_COMPAL_ENE932_CHIP_H
+#define _EC_COMPAL_ENE932_CHIP_H
+
+#include <device/device.h>
+#include <pc80/keyboard.h>
+
+struct chip_operations;
+extern struct chip_operations ec_compal_ene932_ops;
+
+struct ec_compal_ene932_config {
+ struct pc_keyboard keyboard;
+};
+
+#endif /* _EC_COMPAL_ENE932_CHIP_H */
diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c
new file mode 100644
index 0000000..c3087e9
--- /dev/null
+++ b/src/ec/compal/ene932/ec.c
@@ -0,0 +1,180 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __PRE_RAM__
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "ec.h"
+#include "chip.h"
+
+/* kbc helper functions from drivers/pc80/keyboard.c. TODO: share functions. */
+static int kbc_input_buffer_empty(void)
+{
+ u32 timeout;
+ for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS) & KBD_IBF);
+ timeout--) {
+ mdelay(1);
+ }
+
+ if (!timeout) {
+ printk(BIOS_WARNING,
+ "Unexpected Keyboard controller input buffer full\n");
+ }
+ return !!timeout;
+}
+
+
+static int kbc_output_buffer_full(void)
+{
+ u32 timeout;
+ for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(KBD_STATUS)
+ & KBD_OBF) == 0); timeout--) {
+ mdelay(1);
+ }
+
+ if (!timeout) {
+ printk(BIOS_INFO, "Keyboard controller output buffer result timeout\n");
+ }
+ return !!timeout;
+}
+
+int kbc_cleanup_buffers(void)
+{
+ u32 timeout;
+ for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(KBD_STATUS)
+ & (KBD_OBF | KBD_IBF)); timeout--) {
+ mdelay(1);
+ inb(KBD_DATA);
+ }
+
+ if (!timeout) {
+ printk(BIOS_ERR, "Couldn't cleanup the keyboard controller buffers\n");
+ printk(BIOS_ERR, "Status (0x%x): 0x%x, Buffer (0x%x): 0x%x\n",
+ KBD_STATUS, inb(KBD_STATUS), KBD_DATA, inb(KBD_DATA));
+ }
+
+ return !!timeout;
+}
+
+
+/* The ENE 60/64 EC registers are the same comand/status IB/OB KBC pair.
+ * Check status from 64 port before each command.
+ *
+ * Ex. Get panel ID command C43/D77
+ * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port
+ * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port
+ * Check OBF set. Then Get Data(0x03:panel ID) from 0x60
+ * Different commands return may or maynot respond and may have multiple
+ * bytes. Keep it simple for nor
+ */
+
+u8 ec_kbc_read_ob(void)
+{
+ if (!kbc_output_buffer_full()) return 0;
+ return inb(KBD_DATA);
+}
+
+void ec_kbc_write_cmd(u8 cmd)
+{
+ if (!kbc_input_buffer_empty()) return;
+ outb(cmd, KBD_COMMAND);
+}
+
+void ec_kbc_write_ib(u8 data)
+{
+ if (!kbc_input_buffer_empty()) return;
+ outb(data, KBD_DATA);
+}
+
+
+/*
+ * These functions are for accessing the ENE932 device space, but are not
+ * currently used.
+ */
+/*
+static u8 ec_io_read(u16 addr)
+{
+ outb(addr >> 8, EC_IO_HIGH);
+ outb(addr & 0xff, EC_IO_LOW);
+ return inb(EC_IO_DATA);
+}
+*/
+/*static void ec_write(u16 addr, u8 data)
+{
+ outb(addr >> 8, EC_IO_HIGH);
+ outb(addr & 0xff, EC_IO_LOW;
+ outb(data, EC_IO_DATA);
+}
+*/
+
+#ifndef __SMM__
+static void ene932_init(device_t dev)
+{
+ struct ec_compal_ene932_config *conf = dev->chip_info;
+
+
+ if (!dev->enabled)
+ return;
+
+ printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n");
+ pc_keyboard_init(&conf->keyboard);
+
+}
+
+
+static void ene932_read_resources(device_t dev)
+{
+ /* This function avoids an error on serial console. */
+}
+
+
+static void ene932_enable_resources(device_t dev)
+{
+ /* This function avoids an error on serial console. */
+}
+
+static struct device_operations ops = {
+ .init = ene932_init,
+ .read_resources = ene932_read_resources,
+ .enable_resources = ene932_enable_resources
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, 0, 0, { 0, 0 }, }
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
+ pnp_dev_info);
+}
+
+struct chip_operations ec_compal_ene932_ops = {
+ CHIP_NAME("COMPAL ENE932 EC")
+ .enable_dev = enable_dev
+};
+#endif /* ! __SMM__ */
+#endif /* ! __PRE_RAM__ */
diff --git a/src/ec/compal/ene932/ec.h b/src/ec/compal/ene932/ec.h
new file mode 100644
index 0000000..879925f
--- /dev/null
+++ b/src/ec/compal/ene932/ec.h
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * EC communication interface for COMPAL ENE932 Embedded Controller.
+ */
+
+#ifndef _EC_COMPAL_ENE932_EC_H
+#define _EC_COMPAL_ENE932_EC_H
+
+#define EC_IO 0xfd60 /* Mainboard specific. Could be Kconfig option */
+#define EC_IO_HIGH EC_IO + 1
+#define EC_IO_LOW EC_IO + 2
+#define EC_IO_DATA EC_IO + 3
+
+/* ENE EC internal address space */
+#define REG_SPI_DATA 0xfeab
+#define REG_SPI_COMMAND 0xfeac
+#define REG_SPI_CONFIG 0xfead
+#define CFG_CSn_FORCE_LOW (1 << 4)
+#define CFG_COMMAND_WRITE_ENABLE (1 << 3)
+#define CFG_STATUS (1 << 1)
+
+
+#define KBD_DATA 0x60
+#define KBD_COMMAND 0x64
+#define KBD_STATUS 0x64
+#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec)
+#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
+
+
+/* Wait 400ms for keyboard controller answers */
+#define KBC_TIMEOUT_IN_MS 400
+
+u8 ec_kbc_read_ob(void);
+void ec_kbc_write_cmd(u8 cmd);
+void ec_kbc_write_ib(u8 data);
+int kbc_cleanup_buffers(void);
+
+#endif /* _EC_COMPAL_ENE932_EC_H */
diff --git a/src/ec/google/Kconfig b/src/ec/google/Kconfig
new file mode 100644
index 0000000..f83741e
--- /dev/null
+++ b/src/ec/google/Kconfig
@@ -0,0 +1 @@
+source src/ec/google/chromeec/Kconfig
diff --git a/src/ec/google/Makefile.inc b/src/ec/google/Makefile.inc
new file mode 100644
index 0000000..9ca3f0f
--- /dev/null
+++ b/src/ec/google/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_EC_GOOGLE_CHROMEEC) += chromeec
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
new file mode 100644
index 0000000..b8d3444
--- /dev/null
+++ b/src/ec/google/chromeec/Kconfig
@@ -0,0 +1,11 @@
+config EC_GOOGLE_CHROMEEC
+ bool
+ help
+ Google's Chrome EC
+
+config EC_GOOGLE_API_ROOT
+ depends on EC_GOOGLE_CHROMEEC
+ string "Path to the EC API include file"
+ default "/usr/include"
+ help
+ Path to the ec API file (ec/ec_commands.h).
diff --git a/src/ec/google/chromeec/Makefile.inc b/src/ec/google/chromeec/Makefile.inc
new file mode 100644
index 0000000..db7ba51
--- /dev/null
+++ b/src/ec/google/chromeec/Makefile.inc
@@ -0,0 +1,5 @@
+driver-y += ec.c
+smm-y += ec.c
+romstage-y += ec.c
+
+CFLAGS += -I $(call strip_quotes,$(CONFIG_EC_GOOGLE_API_ROOT))
diff --git a/src/mainboard/intel/emeraldlake2/chip.h b/src/ec/google/chromeec/acpi/ac.asl
similarity index 81%
copy from src/mainboard/intel/emeraldlake2/chip.h
copy to src/ec/google/chromeec/acpi/ac.asl
index fbe2477..34b9080 100644
--- a/src/mainboard/intel/emeraldlake2/chip.h
+++ b/src/ec/google/chromeec/acpi/ac.asl
@@ -17,5 +17,20 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR)
+ {
+ Return (ACEX)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl
new file mode 100644
index 0000000..341911c
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/battery.asl
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (BAT0)
+{
+ Name (_HID, EISAID ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ Name (PBIF, Package () {
+ 0x00000001, // 0x00: Power Unit: mAh
+ 0xFFFFFFFF, // 0x01: Design Capacity
+ 0xFFFFFFFF, // 0x02: Last Full Charge Capacity
+ 0x00000001, // 0x03: Battery Technology: Rechargeable
+ 0xFFFFFFFF, // 0x04: Design Voltage
+ 0x00000003, // 0x05: Design Capacity of Warning
+ 0xFFFFFFFF, // 0x06: Design Capacity of Low
+ 0x00000001, // 0x07: Capacity Granularity 1
+ 0x00000001, // 0x08: Capacity Granularity 2
+ "", // 0x09: Model Number
+ "", // 0x0a: Serial Number
+ "LION", // 0x0b: Battery Type
+ "" // 0x0c: OEM Information
+ })
+
+ Name (PBIX, Package () {
+ 0x00000000, // 0x00: Revision
+ 0x00000001, // 0x01: Power Unit: mAh
+ 0xFFFFFFFF, // 0x02: Design Capacity
+ 0xFFFFFFFF, // 0x03: Last Full Charge Capacity
+ 0x00000001, // 0x04: Battery Technology: Rechargeable
+ 0xFFFFFFFF, // 0x05: Design Voltage
+ 0x00000003, // 0x06: Design Capacity of Warning
+ 0xFFFFFFFF, // 0x07: Design Capacity of Low
+ 0x00000000, // 0x08: Cycle Count
+ 0x00018000, // 0x09: Measurement Accuracy (98.3%?)
+ 0x000001F4, // 0x0a: Max Sampling Time (500ms)
+ 0x0000000a, // 0x0b: Min Sampling Time (10ms)
+ 0xFFFFFFFF, // 0x0c: Max Averaging Interval
+ 0xFFFFFFFF, // 0x0d: Min Averaging Interval
+ 0x00000001, // 0x0e: Capacity Granularity 1
+ 0x00000001, // 0x0f: Capacity Granularity 2
+ "", // 0x10 Model Number
+ "", // 0x11: Serial Number
+ "LION", // 0x12: Battery Type
+ "" // 0x13: OEM Information
+ })
+
+ Name (PBST, Package () {
+ 0x00000000, // 0x00: Battery State
+ 0xFFFFFFFF, // 0x01: Battery Present Rate
+ 0xFFFFFFFF, // 0x02: Battery Remaining Capacity
+ 0xFFFFFFFF, // 0x03: Battery Present Voltage
+ })
+ Name (BSTP, Zero)
+
+ // Workaround for full battery status, enabled by default
+ Name (BFWK, One)
+
+ // Method to enable full battery workaround
+ Method (BFWE)
+ {
+ Store (One, BFWK)
+ }
+
+ // Method to disable full battery workaround
+ Method (BFWD)
+ {
+ Store (Zero, BFWK)
+ }
+
+ Method (_STA, 0, Serialized)
+ {
+ If (BTEX) {
+ Return (0x1F)
+ } Else {
+ Return (0x0F)
+ }
+ }
+
+ Method (_BIF, 0, Serialized)
+ {
+ // Last Full Charge Capacity
+ Store (BTDF, Index (PBIF, 2))
+
+ // Design Voltage
+ Store (BTDV, Index (PBIF, 4))
+
+ // Design Capacity
+ Store (BTDA, Local0)
+ Store (Local0, Index (PBIF, 1))
+
+ // Design Capacity of Warning
+ Divide (Multiply (Local0, DWRN), 100, Local1, Local2)
+ Store (Local2, Index (PBIF, 5))
+
+ // Design Capacity of Low
+ Divide (Multiply (Local0, DLOW), 100, Local1, Local2)
+ Store (Local2, Index (PBIF, 6))
+
+ // Get battery info from mainboard
+ Store (ToString(BMOD), Index (PBIF, 9))
+ Store (ToString(BSER), Index (PBIF, 10))
+ Store (ToString(BMFG), Index (PBIF, 12))
+
+ Return (PBIF)
+ }
+
+ // Extended Battery info method is disabled for now due to
+ // a bug in the Linux kernel: http://crosbug.com/28747
+ Method (XBIX, 0, Serialized)
+ {
+ // Last Full Charge Capacity
+ Store (BTDF, Index (PBIX, 3))
+
+ // Design Voltage
+ Store (BTDV, Index (PBIX, 5))
+
+ // Design Capacity
+ Store (BTDA, Local0)
+ Store (Local0, Index (PBIX, 2))
+
+ // Design Capacity of Warning
+ Divide (Multiply (Local0, DWRN), 100, Local1, Local2)
+ Store (Local2, Index (PBIX, 6))
+
+ // Design Capacity of Low
+ Divide (Multiply (Local0, DLOW), 100, Local1, Local2)
+ Store (Local2, Index (PBIX, 7))
+
+ // Cycle Count
+ Store (BTCC, Index (PBIX, 8))
+
+ // Get battery info from mainboard
+ Store (ToString(BMOD), Index (PBIX, 16))
+ Store (ToString(BSER), Index (PBIX, 17))
+ Store (ToString(BMFG), Index (PBIX, 19))
+
+ Return (PBIX)
+ }
+
+ Method (_BST, 0, Serialized)
+ {
+ //
+ // 0: BATTERY STATE
+ //
+ // bit 0 = discharging
+ // bit 1 = charging
+ // bit 2 = critical level
+ //
+ Store (Zero, Local1)
+
+ // Check if AC is present
+ If (ACEX) {
+ If (BFCG) {
+ Store (0x02, Local1)
+ } ElseIf (BFDC) {
+ Store (0x01, Local1)
+ }
+ } Else {
+ // Always discharging when on battery power
+ Store (0x01, Local1)
+ }
+
+ // Check for critical battery level
+ If (BFCR) {
+ Or (Local1, 0x04, Local1)
+ }
+ Store (Local1, Index (PBST, 0))
+
+ // Notify if battery state has changed since last time
+ If (LNotEqual (Local1, BSTP)) {
+ Store (Local1, BSTP)
+ Notify (BAT0, 0x80)
+ }
+
+ //
+ // 1: BATTERY PRESENT RATE
+ //
+ Store (BTPR, Index (PBST, 1))
+
+ //
+ // 2: BATTERY REMAINING CAPACITY
+ //
+ Store (BTRA, Local1)
+ If (LAnd (BFWK, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) {
+ // On AC power and battery is neither charging
+ // nor discharging. Linux expects a full battery
+ // to report same capacity as last full charge.
+ // https://bugzilla.kernel.org/show_bug.cgi?id=12632
+ Store (BTDF, Local2)
+
+ // See if within ~3% of full
+ ShiftRight (Local2, 5, Local3)
+ If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+ LLess (Local1, Add (Local2, Local3))))
+ {
+ Store (Local2, Local1)
+ }
+ }
+ Store (Local1, Index (PBST, 2))
+
+ //
+ // 3: BATTERY PRESENT VOLTAGE
+ //
+ Store (BTVO, Index (PBST, 3))
+
+ Return (PBST)
+ }
+}
diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
new file mode 100644
index 0000000..2fb8e79
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 1)
+ Name (_GPE, Add(EC_SCI_GPI, 16))
+ Name (TOFS, EC_TEMP_SENSOR_OFFSET)
+ Name (TNOP, 0xFD) // Thermal sensor has no power
+ Name (TBAD, 0xFE) // Thermal sensor bad reading
+ Name (TNPR, 0xFF) // Thermal sensor not present
+ Name (DWRN, 15) // Battery capacity warning at 15%
+ Name (DLOW, 10) // Battery capacity low at 10%
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x00),
+ RAMV, 8, // EC RAM Version
+ TSTB, 8, // Test Byte
+ TSTC, 8, // Complement of Test Byte
+ KBLV, 8, // Keyboard Backlight
+ }
+
+ OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+ Field (EMEM, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x00),
+ TIN0, 8, // Temperature 0
+ TIN1, 8, // Temperature 1
+ TIN2, 8, // Temperature 2
+ TIN3, 8, // Temperature 3
+ TIN4, 8, // Temperature 4
+ TIN5, 8, // Temperature 5
+ TIN6, 8, // Temperature 6
+ TIN7, 8, // Temperature 7
+ TIN8, 8, // Temperature 8
+ TIN9, 8, // Temperature 9
+ Offset (0x10),
+ FAN0, 16, // Fan Speed 0
+ Offset (0x30),
+ LIDS, 1, // Lid Switch State
+ PBTN, 1, // Power Button Pressed
+ WPDI, 1, // Write Protect Disabled
+ RECK, 1, // Keyboard Initiated Recovery
+ RECD, 1, // Dedicated Recovery Mode
+ Offset (0x40),
+ BTVO, 32, // Battery Present Voltage
+ BTPR, 32, // Battery Present Rate
+ BTRA, 32, // Battery Remaining Capacity
+ ACEX, 1, // AC Present
+ BTEX, 1, // Battery Present
+ BFDC, 1, // Battery Discharging
+ BFCG, 1, // Battery Charging
+ BFCR, 1, // Battery Level Critical
+ Offset (0x50),
+ BTDA, 32, // Battery Design Capacity
+ BTDV, 32, // Battery Design Voltage
+ BTDF, 32, // Battery Last Full Charge Capacity
+ BTCC, 32, // Battery Cycle Count
+ BMFG, 64, // Battery Manufacturer String
+ BMOD, 64, // Battery Model String
+ BSER, 64, // Battery Serial String
+ BTYP, 64, // Battery Type String
+ }
+
+ Method (TINS, 1, Serialized)
+ {
+ Switch (ToInteger (Arg0))
+ {
+ Case (0) { Return (TIN0) }
+ Case (1) { Return (TIN1) }
+ Case (2) { Return (TIN2) }
+ Case (3) { Return (TIN3) }
+ Case (4) { Return (TIN4) }
+ Case (5) { Return (TIN5) }
+ Case (6) { Return (TIN6) }
+ Case (7) { Return (TIN7) }
+ Case (8) { Return (TIN8) }
+ Case (9) { Return (TIN9) }
+ Default { Return (TIN0) }
+ }
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16,
+ EC_LPC_ADDR_ACPI_DATA,
+ EC_LPC_ADDR_ACPI_DATA,
+ 0, 1)
+ IO (Decode16,
+ EC_LPC_ADDR_ACPI_CMD,
+ EC_LPC_ADDR_ACPI_CMD,
+ 0, 1)
+ })
+ Return (ECMD)
+ }
+
+ Method (_REG, 2, NotSerialized)
+ {
+ // Initialize AC power state
+ Store (ACEX, \PWRS)
+
+ // Initialize LID switch state
+ Store (LIDS, \LIDS)
+ }
+
+ // Lid Closed Event
+ Method (_Q01, 0, NotSerialized)
+ {
+ Store ("EC: LID CLOSE", Debug)
+ Store (LIDS, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ // Lid Open Event
+ Method (_Q02, 0, NotSerialized)
+ {
+ Store ("EC: LID OPEN", Debug)
+ Store (LIDS, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ // Power Button
+ Method (_Q03, 0, NotSerialized)
+ {
+ Store ("EC: POWER BUTTON", Debug)
+ Notify (\_SB.PWRB, 0x80)
+ }
+
+ // AC Connected
+ Method (_Q04, 0, NotSerialized)
+ {
+ Store ("EC: AC CONNECTED", Debug)
+ Store (ACEX, \PWRS)
+ Notify (AC, 0x80)
+ \PNOT ()
+ }
+
+ // AC Disconnected
+ Method (_Q05, 0, NotSerialized)
+ {
+ Store ("EC: AC DISCONNECTED", Debug)
+ Store (ACEX, \PWRS)
+ Notify (AC, 0x80)
+ \PNOT ()
+ }
+
+ // Battery Low Event
+ Method (_Q06, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY LOW", Debug)
+ Notify (BAT0, 0x80)
+ }
+
+ // Battery Critical Event
+ Method (_Q07, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY CRITICAL", Debug)
+ Notify (BAT0, 0x80)
+ }
+
+ // Battery Info Event
+ Method (_Q08, 0, NotSerialized)
+ {
+ Store ("EC: BATTERY INFO", Debug)
+ Notify (BAT0, 0x81)
+ }
+
+ // Thermal Treshold Event
+ Method (_Q09, 0, NotSerialized)
+ {
+ Store ("EC: THERMAL THRESHOLD", Debug)
+ Notify (\_TZ, 0x80)
+ }
+
+ // Thermal Overload Event
+ Method (_Q0A, 0, NotSerialized)
+ {
+ Store ("EC: THERMAL OVERLOAD", Debug)
+ Notify (\_TZ, 0x80)
+ }
+
+ // Thermal Event
+ Method (_Q0B, 0, NotSerialized)
+ {
+ Store ("EC: THERMAL", Debug)
+ Notify (\_TZ, 0x80)
+ }
+
+ // USB Charger
+ Method (_Q0C, 0, NotSerialized)
+ {
+ Store ("EC: USB CHARGER", Debug)
+ }
+
+ // Key Pressed
+ Method (_Q0D, 0, NotSerialized)
+ {
+ Store ("EC: KEY PRESSED", Debug)
+ }
+
+ #include "ac.asl"
+ #include "battery.asl"
+}
diff --git a/src/ec/google/chromeec/acpi/superio.asl b/src/ec/google/chromeec/acpi/superio.asl
new file mode 100644
index 0000000..56f0f18
--- /dev/null
+++ b/src/ec/google/chromeec/acpi/superio.asl
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Chrome OS Embedded Controller interface
+ *
+ * Constants that should be defined:
+ *
+ * SIO_EC_MEMMAP_ENABLE : Enable EC LPC memory map resources
+ * EC_LPC_ADDR_MEMMAP : Base address of memory map range
+ * EC_MEMMAP_SIZE : Size of memory map range
+ *
+ * SIO_EC_HOST_ENABLE : Enable EC host command interface resources
+ * EC_LPC_ADDR_HOST_DATA : EC host command interface data port
+ * EC_LPC_ADDR_HOST_CMD : EC host command interface command port
+ * EC_LPC_ADDR_OLD_PARAM : EC host command parameter range base (old)
+ * EC_OLD_PARAM_SIZE : Parameter buffer size (old)
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+#ifdef SIO_EC_MEMMAP_ENABLE
+ Device (ECMM) {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 1)
+ Name (_ADR, 0)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ FixedIO (EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ FixedIO (EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE)
+ })
+ }
+#endif
+
+#ifdef SIO_EC_HOST_ENABLE
+ Device (ECUI) {
+ Name (_HID, EISAID ("PNP0C02"))
+ Name (_UID, 3)
+ Name (_ADR, 0)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
+ FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
+ FixedIO (EC_LPC_ADDR_OLD_PARAM,
+ EC_OLD_PARAM_SIZE)
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0, 0) {
+ FixedIO (EC_LPC_ADDR_HOST_DATA, 1)
+ FixedIO (EC_LPC_ADDR_HOST_CMD, 1)
+ FixedIO (EC_LPC_ADDR_OLD_PARAM,
+ EC_OLD_PARAM_SIZE)
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+#ifdef SIO_EC_ENABLE_COM1
+ Device (COM1) {
+ Name (_HID, EISAID ("PNP0501"))
+ Name (_UID, 1)
+ Name (_ADR, 0)
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate ()
+ {
+ FixedIO (0x03F8, 0x08)
+ IRQNoFlags () {4}
+ })
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0, 0) {
+ FixedIO (0x03F8, 0x08)
+ IRQNoFlags () {4}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+#ifdef SIO_EC_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0) {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+}
diff --git a/src/mainboard/amd/inagua/chip.h b/src/ec/google/chromeec/chip.h
similarity index 69%
rename from src/mainboard/amd/inagua/chip.h
rename to src/ec/google/chromeec/chip.h
index a252705..0ca2183 100644
--- a/src/mainboard/amd/inagua/chip.h
+++ b/src/ec/google/chromeec/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,7 +17,16 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef EC_GOOGLE_CHROMEEC_CHIP_H
+#define EC_GOOGLE_CHROMEEC_CHIP_H
-extern struct chip_operations mainboard_ops;
+#include <device/device.h>
+#include <pc80/keyboard.h>
-struct mainboard_config {};
+extern struct chip_operations ec_google_chromeec_ops;
+
+struct ec_google_chromeec_config {
+ struct pc_keyboard keyboard;
+};
+
+#endif
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
new file mode 100644
index 0000000..62ef875
--- /dev/null
+++ b/src/ec/google/chromeec/ec.c
@@ -0,0 +1,498 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <delay.h>
+
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pnp.h>
+#include <elog.h>
+#include <stdlib.h>
+#include <string.h>
+#include <reset.h>
+#include <arch/hlt.h>
+#include "chip.h"
+#endif
+#include "ec.h"
+#include "ec_commands.h"
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* an internal API to send a command to the EC and wait for response. */
+struct chromeec_command {
+ u8 cmd_code; /* command code in, status out */
+ u8 cmd_version; /* command version */
+ const void* cmd_data_in; /* command data, if any */
+ void* cmd_data_out; /* command response, if any */
+ u16 cmd_size_in; /* size of command data */
+ u16 cmd_size_out; /* expected size of command response in,
+ * actual received size out */
+};
+
+static int google_chromeec_wait_ready(u16 port)
+{
+ u8 ec_status = inb(port);
+ u32 time_count = 0;
+
+ /*
+ * One second is more than plenty for any EC operation to complete
+ * (and the bus accessing/code execution) overhead will make the
+ * timeout even longer.
+ */
+#define MAX_EC_TIMEOUT_US 1000000
+
+ while (ec_status &
+ (EC_LPC_CMDR_PENDING | EC_LPC_CMDR_BUSY)) {
+ udelay(1);
+ if (time_count++ == MAX_EC_TIMEOUT_US)
+ return -1;
+ ec_status = inb(port);
+ }
+ return 0;
+}
+
+static int google_chromeec_cmd_args_supported(void)
+{
+ if (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID) == 'E' &&
+ inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_ID + 1) == 'C' &&
+ (inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_HOST_CMD_FLAGS) &
+ EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED))
+ return 1;
+
+ return 0;
+}
+
+static int google_chromeec_command_old(struct chromeec_command *cec_command)
+{
+ int i;
+
+ if (cec_command->cmd_version) {
+ printk(BIOS_ERR, "Invalid version for command protocol!\n");
+ return 1;
+ }
+
+ if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) {
+ printk(BIOS_ERR, "Timeout waiting for EC ready!\n");
+ return 1;
+ }
+
+ /* Copy command data, if any. */
+ for (i = 0; i < cec_command->cmd_size_in; i++)
+ outb(((char*)cec_command->cmd_data_in)[i],
+ EC_LPC_ADDR_OLD_PARAM + i);
+
+ /* Issue the command. */
+ outb(cec_command->cmd_code, EC_LPC_ADDR_HOST_CMD);
+
+ if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) {
+ printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n",
+ cec_command->cmd_code);
+ return 1;
+ }
+
+ for (i = 0; i < cec_command->cmd_size_out; i++)
+ ((char*)cec_command->cmd_data_out)[i] =
+ inb(EC_LPC_ADDR_OLD_PARAM + i);
+ cec_command->cmd_code = inb(EC_LPC_ADDR_HOST_DATA);
+ return 0;
+}
+
+static int google_chromeec_command(struct chromeec_command *cec_command)
+{
+ struct ec_lpc_host_args args;
+ const u8 *d;
+ u8 *dout;
+ u8 cmd_code = cec_command->cmd_code;
+ int csum;
+ int i;
+
+ /* Fall back to old command protocol if necessary */
+ if (!google_chromeec_cmd_args_supported())
+ return google_chromeec_command_old(cec_command);
+
+ /* Fill in args */
+ args.flags = EC_HOST_ARGS_FLAG_FROM_HOST;
+ args.command_version = cec_command->cmd_version;
+ args.data_size = cec_command->cmd_size_in;
+
+ /* Initialize checksum */
+ csum = cmd_code + args.flags + args.command_version + args.data_size;
+
+ /* Write data and update checksum */
+ for (i = 0, d = (const u8 *)cec_command->cmd_data_in;
+ i < cec_command->cmd_size_in; i++, d++) {
+ outb(*d, EC_LPC_ADDR_HOST_PARAM + i);
+ csum += *d;
+ }
+
+ /* Finalize checksum and write args */
+ args.checksum = (u8)csum;
+ for (i = 0, d = (const u8 *)&args; i < sizeof(args); i++, d++)
+ outb(*d, EC_LPC_ADDR_HOST_ARGS + i);
+
+
+ /* Issue the command */
+ outb(cmd_code, EC_LPC_ADDR_HOST_CMD);
+
+ if (google_chromeec_wait_ready(EC_LPC_ADDR_HOST_CMD)) {
+ printk(BIOS_ERR, "Timeout waiting for EC process command %d!\n",
+ cec_command->cmd_code);
+ return 1;
+ }
+
+ /* Check result */
+ cec_command->cmd_code = inb(EC_LPC_ADDR_HOST_DATA);
+ if (cec_command->cmd_code)
+ return 1;
+
+ /* Read back args */
+ for (i = 0, dout = (u8 *)&args; i < sizeof(args); i++, dout++)
+ *dout = inb(EC_LPC_ADDR_HOST_ARGS + i);
+
+ /*
+ * If EC didn't modify args flags, then somehow we sent a new-style
+ * command to an old EC, which means it would have read its params
+ * from the wrong place.
+ */
+ if (!(args.flags & EC_HOST_ARGS_FLAG_TO_HOST)) {
+ printk(BIOS_ERR, "EC protocol mismatch\n");
+ return 1;
+ }
+
+ if (args.data_size > cec_command->cmd_size_out) {
+ printk(BIOS_ERR, "EC returned too much data\n");
+ return 1;
+ }
+ cec_command->cmd_size_out = args.data_size;
+
+ /* Start calculating response checksum */
+ csum = cmd_code + args.flags + args.command_version + args.data_size;
+
+ /* Read data, if any */
+ for (i = 0, dout = (u8 *)cec_command->cmd_data_out;
+ i < args.data_size; i++, dout++) {
+ *dout = inb(EC_LPC_ADDR_HOST_PARAM + i);
+ csum += *dout;
+ }
+
+ /* Verify checksum */
+ if (args.checksum != (u8)csum) {
+ printk(BIOS_ERR, "EC response has invalid checksum\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+int google_chromeec_kbbacklight(int percent)
+{
+ struct chromeec_command cec_cmd;
+ struct ec_params_pwm_set_keyboard_backlight cmd_backlight;
+ struct ec_response_pwm_get_keyboard_backlight rsp_backlight;
+ /* if they were dumb, help them out */
+ percent = percent % 101;
+ cec_cmd.cmd_code = EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT;
+ cec_cmd.cmd_version = 0;
+ cmd_backlight.percent = percent;
+ cec_cmd.cmd_data_in = &cmd_backlight;
+ cec_cmd.cmd_data_out = &rsp_backlight;
+ cec_cmd.cmd_size_in = sizeof(cmd_backlight);
+ cec_cmd.cmd_size_out = sizeof(rsp_backlight);
+ google_chromeec_command(&cec_cmd);
+ printk(BIOS_DEBUG, "Google Chrome set keyboard backlight: %x status (%x)\n",
+ rsp_backlight.percent, cec_cmd.cmd_code);
+ return cec_cmd.cmd_code;
+
+}
+
+void google_chromeec_post(u8 postcode)
+{
+ /* backlight is a percent. postcode is a u8.
+ * Convert the u8 to %.
+ */
+ postcode = (postcode/4) + (postcode/8);
+ google_chromeec_kbbacklight(postcode);
+}
+
+/*
+ * Query the EC for specified mask indicating enabled events.
+ * The EC maintains separate event masks for SMI, SCI and WAKE.
+ */
+static u32 google_chromeec_get_mask(u8 type)
+{
+ struct ec_params_host_event_mask req;
+ struct ec_response_host_event_mask rsp;
+ struct chromeec_command cmd;
+
+ cmd.cmd_code = type;
+ cmd.cmd_version = 0;
+ cmd.cmd_data_in = &req;
+ cmd.cmd_size_in = sizeof(req);
+ cmd.cmd_data_out = &rsp;
+ cmd.cmd_size_out = sizeof(rsp);
+
+ if (google_chromeec_command(&cmd) == 0)
+ return rsp.mask;
+ return 0;
+}
+
+u32 google_chromeec_get_events_b(void)
+{
+ return google_chromeec_get_mask(EC_CMD_HOST_EVENT_GET_B);
+}
+
+#ifndef __PRE_RAM__
+
+static int google_chromeec_set_mask(u8 type, u32 mask)
+{
+ struct ec_params_host_event_mask req;
+ struct ec_response_host_event_mask rsp;
+ struct chromeec_command cmd;
+
+ req.mask = mask;
+ cmd.cmd_code = type;
+ cmd.cmd_version = 0;
+ cmd.cmd_data_in = &req;
+ cmd.cmd_size_in = sizeof(req);
+ cmd.cmd_data_out = &rsp;
+ cmd.cmd_size_out = sizeof(rsp);
+
+ return google_chromeec_command(&cmd);
+}
+
+int google_chromeec_set_sci_mask(u32 mask)
+{
+ printk(BIOS_DEBUG, "Chrome EC: Set SCI mask to 0x%08x\n", mask);
+ return google_chromeec_set_mask(
+ EC_CMD_HOST_EVENT_SET_SCI_MASK, mask);
+}
+
+int google_chromeec_set_smi_mask(u32 mask)
+{
+ printk(BIOS_DEBUG, "Chrome EC: Set SMI mask to 0x%08x\n", mask);
+ return google_chromeec_set_mask(
+ EC_CMD_HOST_EVENT_SET_SMI_MASK, mask);
+}
+
+int google_chromeec_set_wake_mask(u32 mask)
+{
+ printk(BIOS_DEBUG, "Chrome EC: Set WAKE mask to 0x%08x\n", mask);
+ return google_chromeec_set_mask(
+ EC_CMD_HOST_EVENT_SET_WAKE_MASK, mask);
+}
+
+u32 google_chromeec_get_wake_mask(void)
+{
+ return google_chromeec_get_mask(
+ EC_CMD_HOST_EVENT_GET_WAKE_MASK);
+}
+
+/* Find the last port80 code from the previous boot */
+static u16 google_chromeec_get_port80_last_boot(void)
+{
+ struct ec_response_port80_last_boot rsp;
+ struct chromeec_command cmd = {
+ .cmd_code = EC_CMD_PORT80_LAST_BOOT,
+ .cmd_data_out = &rsp,
+ .cmd_size_out = sizeof(rsp),
+ };
+
+ /* Get last port80 code */
+ if (google_chromeec_command(&cmd) == 0)
+ return rsp.code;
+
+ return 0;
+}
+
+void google_chromeec_log_events(u32 mask)
+{
+#if CONFIG_ELOG
+ u8 event;
+ u16 code;
+
+ /* Find the last port80 code */
+ code = google_chromeec_get_port80_last_boot();
+
+ /* Log the last post code only if it is abornmal */
+ if (code > 0 && code != POST_OS_BOOT && code != POST_OS_RESUME)
+ elog_add_event_word(ELOG_TYPE_LAST_POST_CODE, code);
+
+ while ((event = google_chromeec_get_event()) != 0) {
+ if (EC_HOST_EVENT_MASK(event) & mask)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
+ }
+#endif
+}
+
+u8 google_chromeec_get_event(void)
+{
+ if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) {
+ printk(BIOS_ERR, "Timeout waiting for EC ready!\n");
+ return 1;
+ }
+
+ /* Issue the ACPI query-event command */
+ outb(EC_CMD_ACPI_QUERY_EVENT, EC_LPC_ADDR_ACPI_CMD);
+
+ if (google_chromeec_wait_ready(EC_LPC_ADDR_ACPI_CMD)) {
+ printk(BIOS_ERR, "Timeout waiting for EC QUERY_EVENT!\n");
+ return 0;
+ }
+
+ /* Event (or 0 if none) is returned directly in the data byte */
+ return inb(EC_LPC_ADDR_ACPI_DATA);
+}
+
+u16 google_chromeec_get_board_version(void)
+{
+ struct chromeec_command cmd;
+ struct ec_response_board_version board_v;
+
+ cmd.cmd_code = EC_CMD_GET_BOARD_VERSION;
+ cmd.cmd_version = 0;
+ cmd.cmd_size_in = 0;
+ cmd.cmd_size_out = sizeof(board_v);
+ cmd.cmd_data_out = &board_v;
+
+ if (google_chromeec_command(&cmd) != 0)
+ return 0;
+
+ return board_v.board_version;
+}
+
+#ifndef __SMM__
+
+static
+int google_chromeec_hello(void)
+{
+ struct chromeec_command cec_cmd;
+ struct ec_params_hello cmd_hello;
+ struct ec_response_hello rsp_hello;
+ cmd_hello.in_data = 0x10203040;
+ cec_cmd.cmd_code = EC_CMD_HELLO;
+ cec_cmd.cmd_version = 0;
+ cec_cmd.cmd_data_in = &cmd_hello.in_data;
+ cec_cmd.cmd_data_out = &rsp_hello.out_data;
+ cec_cmd.cmd_size_in = sizeof(cmd_hello.in_data);
+ cec_cmd.cmd_size_out = sizeof(rsp_hello.out_data);
+ google_chromeec_command(&cec_cmd);
+ printk(BIOS_DEBUG, "Google Chrome EC: Hello got back %x status (%x)\n",
+ rsp_hello.out_data, cec_cmd.cmd_code);
+ return cec_cmd.cmd_code;
+}
+
+static int ec_image_type; /* Cached EC image type (ro or rw). */
+
+static void google_chromeec_init(device_t dev)
+{
+ struct chromeec_command cec_cmd;
+ struct ec_google_chromeec_config *conf = dev->chip_info;
+ struct ec_response_get_version lpcv_cmd;
+
+ if (!dev->enabled)
+ return;
+
+ printk(BIOS_DEBUG, "Google Chrome EC: Initializing keyboard.\n");
+ pc_keyboard_init(&conf->keyboard);
+
+ google_chromeec_hello();
+
+ memset(&lpcv_cmd, 0, sizeof(lpcv_cmd));
+ cec_cmd.cmd_code = EC_CMD_GET_VERSION;
+ cec_cmd.cmd_version = 0;
+ cec_cmd.cmd_data_out = &lpcv_cmd;
+ cec_cmd.cmd_size_in = 0;
+ cec_cmd.cmd_size_out = sizeof(lpcv_cmd);
+ google_chromeec_command(&cec_cmd);
+
+ if (cec_cmd.cmd_code) {
+ printk(BIOS_DEBUG,
+ "Google Chrome EC: version command failed!\n");
+ } else {
+ printk(BIOS_DEBUG, "Google Chrome EC: version:\n");
+ printk(BIOS_DEBUG, " ro: %s\n", lpcv_cmd.version_string_ro);
+ printk(BIOS_DEBUG, " rw: %s\n", lpcv_cmd.version_string_rw);
+ printk(BIOS_DEBUG, " running image: %d\n",
+ lpcv_cmd.current_image);
+ ec_image_type = lpcv_cmd.current_image;
+ }
+
+ if (cec_cmd.cmd_code ||
+ (recovery_mode_enabled() &&
+ (lpcv_cmd.current_image != EC_IMAGE_RO))) {
+ struct ec_params_reboot_ec reboot_ec;
+ /* Reboot the EC and make it come back in RO mode */
+ reboot_ec.cmd = EC_REBOOT_COLD;
+ reboot_ec.flags = 0;
+ cec_cmd.cmd_code = EC_CMD_REBOOT_EC;
+ cec_cmd.cmd_version = 0;
+ cec_cmd.cmd_data_in = &reboot_ec;
+ cec_cmd.cmd_size_in = sizeof(reboot_ec);
+ cec_cmd.cmd_size_out = 0; /* ignore response, if any */
+ printk(BIOS_DEBUG, "Rebooting with EC in RO mode:\n");
+ google_chromeec_command(&cec_cmd);
+ udelay(1000);
+ hard_reset();
+ hlt();
+ }
+
+}
+
+static void google_chromeec_read_resources(device_t dev)
+{
+ /* Nothing, but this function avoids an error on serial console. */
+}
+
+static void google_chromeec_enable_resources(device_t dev)
+{
+ /* Nothing, but this function avoids an error on serial console. */
+}
+
+static struct device_operations ops = {
+ .init = google_chromeec_init,
+ .read_resources = google_chromeec_read_resources,
+ .enable_resources = google_chromeec_enable_resources
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, 0, 0, { 0, 0 }, }
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
+ pnp_dev_info);
+}
+
+struct chip_operations ec_google_chromeec_ops = {
+ CHIP_NAME("Google Chrome EC")
+ .enable_dev = enable_dev,
+};
+
+int google_ec_running_ro(void)
+{
+ return (ec_image_type == EC_IMAGE_RO);
+}
+#endif /* ! __SMM__ */
+
+#endif /* ! __PRE_RAM__ */
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
new file mode 100644
index 0000000..8d6749a
--- /dev/null
+++ b/src/ec/google/chromeec/ec.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Mailbox EC communication interface for Google Chrome Embedded Controller.
+ */
+
+#ifndef _EC_GOOGLE_CHROMEEC_EC_H
+#define _EC_GOOGLE_CHROMEEC_EC_H
+
+#ifndef __PRE_RAM__
+u32 google_chromeec_get_wake_mask(void);
+int google_chromeec_set_sci_mask(u32 mask);
+int google_chromeec_set_smi_mask(u32 mask);
+int google_chromeec_set_wake_mask(u32 mask);
+u8 google_chromeec_get_event(void);
+int google_ec_running_ro(void);
+u16 google_chromeec_get_board_version(void);
+#endif
+
+u32 google_chromeec_get_events_b(void);
+int google_chromeec_kbbacklight(int percent);
+void google_chromeec_post(u8 postcode);
+void google_chromeec_log_events(u32 mask);
+
+#endif /* _EC_GOOGLE_CHROMEEC_EC_H */
diff --git a/src/ec/google/chromeec/ec_commands.h b/src/ec/google/chromeec/ec_commands.h
new file mode 100644
index 0000000..c1b19bc
--- /dev/null
+++ b/src/ec/google/chromeec/ec_commands.h
@@ -0,0 +1,1069 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Host communication command constants for Chrome EC */
+
+#ifndef __CROS_EC_COMMANDS_H
+#define __CROS_EC_COMMANDS_H
+
+/*
+ * Protocol overview
+ *
+ * request: CMD [ P0 P1 P2 ... Pn S ]
+ * response: ERR [ P0 P1 P2 ... Pn S ]
+ *
+ * where the bytes are defined as follow :
+ * - CMD is the command code. (defined by EC_CMD_ constants)
+ * - ERR is the error code. (defined by EC_RES_ constants)
+ * - Px is the optional payload.
+ * it is not sent if the error code is not success.
+ * (defined by ec_params_ and ec_response_ structures)
+ * - S is the checksum which is the sum of all payload bytes.
+ *
+ * On LPC, CMD and ERR are sent/received at EC_LPC_ADDR_KERNEL|USER_CMD
+ * and the payloads are sent/received at EC_LPC_ADDR_KERNEL|USER_PARAM.
+ * On I2C, all bytes are sent serially in the same message.
+ */
+
+/* Current version of this protocol */
+#define EC_PROTO_VERSION 0x00000002
+
+/* Command version mask */
+#define EC_VER_MASK(version) (1UL << (version))
+
+/* I/O addresses for ACPI commands */
+#define EC_LPC_ADDR_ACPI_DATA 0x62
+#define EC_LPC_ADDR_ACPI_CMD 0x66
+
+/* I/O addresses for host command */
+#define EC_LPC_ADDR_HOST_DATA 0x200
+#define EC_LPC_ADDR_HOST_CMD 0x204
+
+/* I/O addresses for host command args and params */
+#define EC_LPC_ADDR_HOST_ARGS 0x800
+#define EC_LPC_ADDR_HOST_PARAM 0x804
+#define EC_HOST_PARAM_SIZE 0x0fc /* Size of param area in bytes */
+
+/* I/O addresses for host command params, old interface */
+#define EC_LPC_ADDR_OLD_PARAM 0x880
+#define EC_OLD_PARAM_SIZE 0x080 /* Size of param area in bytes */
+
+/* EC command register bit functions */
+#define EC_LPC_CMDR_DATA (1 << 0) /* Data ready for host to read */
+#define EC_LPC_CMDR_PENDING (1 << 1) /* Write pending to EC */
+#define EC_LPC_CMDR_BUSY (1 << 2) /* EC is busy processing a command */
+#define EC_LPC_CMDR_CMD (1 << 3) /* Last host write was a command */
+#define EC_LPC_CMDR_ACPI_BRST (1 << 4) /* Burst mode (not used) */
+#define EC_LPC_CMDR_SCI (1 << 5) /* SCI event is pending */
+#define EC_LPC_CMDR_SMI (1 << 6) /* SMI event is pending */
+
+#define EC_LPC_ADDR_MEMMAP 0x900
+#define EC_MEMMAP_SIZE 255 /* ACPI IO buffer max is 255 bytes */
+#define EC_MEMMAP_TEXT_MAX 8 /* Size of a string in the memory map */
+
+/* The offset address of each type of data in mapped memory. */
+#define EC_MEMMAP_TEMP_SENSOR 0x00 /* Temp sensors */
+#define EC_MEMMAP_FAN 0x10 /* Fan speeds */
+#define EC_MEMMAP_TEMP_SENSOR_B 0x18 /* Temp sensors (second set) */
+#define EC_MEMMAP_ID 0x20 /* 'E' 'C' */
+#define EC_MEMMAP_ID_VERSION 0x22 /* Version of data in 0x20 - 0x2f */
+#define EC_MEMMAP_THERMAL_VERSION 0x23 /* Version of data in 0x00 - 0x1f */
+#define EC_MEMMAP_BATTERY_VERSION 0x24 /* Version of data in 0x40 - 0x7f */
+#define EC_MEMMAP_SWITCHES_VERSION 0x25 /* Version of data in 0x30 - 0x33 */
+#define EC_MEMMAP_EVENTS_VERSION 0x26 /* Version of data in 0x34 - 0x3f */
+#define EC_MEMMAP_HOST_CMD_FLAGS 0x27 /* Host command interface flags */
+#define EC_MEMMAP_SWITCHES 0x30
+#define EC_MEMMAP_HOST_EVENTS 0x34
+#define EC_MEMMAP_BATT_VOLT 0x40 /* Battery Present Voltage */
+#define EC_MEMMAP_BATT_RATE 0x44 /* Battery Present Rate */
+#define EC_MEMMAP_BATT_CAP 0x48 /* Battery Remaining Capacity */
+#define EC_MEMMAP_BATT_FLAG 0x4c /* Battery State, defined below */
+#define EC_MEMMAP_BATT_DCAP 0x50 /* Battery Design Capacity */
+#define EC_MEMMAP_BATT_DVLT 0x54 /* Battery Design Voltage */
+#define EC_MEMMAP_BATT_LFCC 0x58 /* Battery Last Full Charge Capacity */
+#define EC_MEMMAP_BATT_CCNT 0x5c /* Battery Cycle Count */
+#define EC_MEMMAP_BATT_MFGR 0x60 /* Battery Manufacturer String */
+#define EC_MEMMAP_BATT_MODEL 0x68 /* Battery Model Number String */
+#define EC_MEMMAP_BATT_SERIAL 0x70 /* Battery Serial Number String */
+#define EC_MEMMAP_BATT_TYPE 0x78 /* Battery Type String */
+
+/* Number of temp sensors at EC_MEMMAP_TEMP_SENSOR */
+#define EC_TEMP_SENSOR_ENTRIES 16
+/*
+ * Number of temp sensors at EC_MEMMAP_TEMP_SENSOR_B.
+ *
+ * Valid only if EC_MEMMAP_THERMAL_VERSION returns >= 2.
+ */
+#define EC_TEMP_SENSOR_B_ENTRIES 8
+#define EC_TEMP_SENSOR_NOT_PRESENT 0xff
+#define EC_TEMP_SENSOR_ERROR 0xfe
+#define EC_TEMP_SENSOR_NOT_POWERED 0xfd
+/*
+ * The offset of temperature value stored in mapped memory. This allows
+ * reporting a temperature range of 200K to 454K = -73C to 181C.
+ */
+#define EC_TEMP_SENSOR_OFFSET 200
+
+#define EC_FAN_SPEED_ENTRIES 4 /* Number of fans at EC_MEMMAP_FAN */
+#define EC_FAN_SPEED_NOT_PRESENT 0xffff /* Entry not present */
+#define EC_FAN_SPEED_STALLED 0xfffe /* Fan stalled */
+
+/* Battery bit flags at EC_MEMMAP_BATT_FLAG. */
+#define EC_BATT_FLAG_AC_PRESENT 0x01
+#define EC_BATT_FLAG_BATT_PRESENT 0x02
+#define EC_BATT_FLAG_DISCHARGING 0x04
+#define EC_BATT_FLAG_CHARGING 0x08
+#define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
+
+/* Switch flags at EC_MEMMAP_SWITCHES */
+#define EC_SWITCH_LID_OPEN 0x01
+#define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
+#define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
+/* Recovery requested via keyboard */
+#define EC_SWITCH_KEYBOARD_RECOVERY 0x08
+/* Recovery requested via dedicated signal (from servo board) */
+#define EC_SWITCH_DEDICATED_RECOVERY 0x10
+/* Was fake developer mode switch; now unused. Remove in next refactor. */
+#define EC_SWITCH_IGNORE0 0x20
+
+/* Host command interface flags */
+/* Host command interface supports LPC args (LPC interface only) */
+#define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
+
+/* Wireless switch flags */
+#define EC_WIRELESS_SWITCH_WLAN 0x01
+#define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
+
+/*
+ * This header file is used in coreboot both in C and ACPI code. The ACPI code
+ * is pre-processed to handle constants but the ASL compiler is unable to
+ * handle actual C code so keep it separate.
+ */
+#ifndef __ACPI__
+
+/*
+ * Define __packed if someone hasn't beat us to it. Linux kernel style
+ * checking prefers __packed over __attribute__((packed)).
+ */
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+/* LPC command status byte masks */
+/* EC has written a byte in the data register and host hasn't read it yet */
+#define EC_LPC_STATUS_TO_HOST 0x01
+/* Host has written a command/data byte and the EC hasn't read it yet */
+#define EC_LPC_STATUS_FROM_HOST 0x02
+/* EC is processing a command */
+#define EC_LPC_STATUS_PROCESSING 0x04
+/* Last write to EC was a command, not data */
+#define EC_LPC_STATUS_LAST_CMD 0x08
+/* EC is in burst mode. Unsupported by Chrome EC, so this bit is never set */
+#define EC_LPC_STATUS_BURST_MODE 0x10
+/* SCI event is pending (requesting SCI query) */
+#define EC_LPC_STATUS_SCI_PENDING 0x20
+/* SMI event is pending (requesting SMI query) */
+#define EC_LPC_STATUS_SMI_PENDING 0x40
+/* (reserved) */
+#define EC_LPC_STATUS_RESERVED 0x80
+
+/*
+ * EC is busy. This covers both the EC processing a command, and the host has
+ * written a new command but the EC hasn't picked it up yet.
+ */
+#define EC_LPC_STATUS_BUSY_MASK \
+ (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING)
+
+/* Host command response codes */
+enum ec_status {
+ EC_RES_SUCCESS = 0,
+ EC_RES_INVALID_COMMAND = 1,
+ EC_RES_ERROR = 2,
+ EC_RES_INVALID_PARAM = 3,
+ EC_RES_ACCESS_DENIED = 4,
+ EC_RES_INVALID_RESPONSE = 5,
+ EC_RES_INVALID_VERSION = 6,
+ EC_RES_INVALID_CHECKSUM = 7,
+};
+
+/*
+ * Host event codes. Note these are 1-based, not 0-based, because ACPI query
+ * EC command uses code 0 to mean "no event pending". We explicitly specify
+ * each value in the enum listing so they won't change if we delete/insert an
+ * item or rearrange the list (it needs to be stable across platforms, not
+ * just within a single compiled instance).
+ */
+enum host_event_code {
+ EC_HOST_EVENT_LID_CLOSED = 1,
+ EC_HOST_EVENT_LID_OPEN = 2,
+ EC_HOST_EVENT_POWER_BUTTON = 3,
+ EC_HOST_EVENT_AC_CONNECTED = 4,
+ EC_HOST_EVENT_AC_DISCONNECTED = 5,
+ EC_HOST_EVENT_BATTERY_LOW = 6,
+ EC_HOST_EVENT_BATTERY_CRITICAL = 7,
+ EC_HOST_EVENT_BATTERY = 8,
+ EC_HOST_EVENT_THERMAL_THRESHOLD = 9,
+ EC_HOST_EVENT_THERMAL_OVERLOAD = 10,
+ EC_HOST_EVENT_THERMAL = 11,
+ EC_HOST_EVENT_USB_CHARGER = 12,
+ EC_HOST_EVENT_KEY_PRESSED = 13,
+ /*
+ * EC has finished initializing the host interface. The host can check
+ * for this event following sending a EC_CMD_REBOOT_EC command to
+ * determine when the EC is ready to accept subsequent commands.
+ */
+ EC_HOST_EVENT_INTERFACE_READY = 14,
+ /* Keyboard recovery combo has been pressed */
+ EC_HOST_EVENT_KEYBOARD_RECOVERY = 15,
+
+ /* Shutdown due to thermal overload */
+ EC_HOST_EVENT_THERMAL_SHUTDOWN = 16,
+ /* Shutdown due to battery level too low */
+ EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
+
+ /*
+ * The high bit of the event mask is not used as a host event code. If
+ * it reads back as set, then the entire event mask should be
+ * considered invalid by the host. This can happen when reading the
+ * raw event status via EC_MEMMAP_HOST_EVENTS but the LPC interface is
+ * not initialized on the EC, or improperly configured on the host.
+ */
+ EC_HOST_EVENT_INVALID = 32
+};
+/* Host event mask */
+#define EC_HOST_EVENT_MASK(event_code) (1UL << ((event_code) - 1))
+
+/* Arguments at EC_LPC_ADDR_HOST_ARGS */
+struct ec_lpc_host_args {
+ uint8_t flags;
+ uint8_t command_version;
+ uint8_t data_size;
+ /*
+ * Checksum; sum of command + flags + command_version + data_size +
+ * all params/response data bytes.
+ */
+ uint8_t checksum;
+} __packed;
+
+/* Flags for ec_lpc_host_args.flags */
+/*
+ * Args are from host. Data area at EC_LPC_ADDR_HOST_PARAM contains command
+ * params.
+ *
+ * If EC gets a command and this flag is not set, this is an old-style command.
+ * Command version is 0 and params from host are at EC_LPC_ADDR_OLD_PARAM with
+ * unknown length. EC must respond with an old-style response (that is,
+ * withouth setting EC_HOST_ARGS_FLAG_TO_HOST).
+ */
+#define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
+/*
+ * Args are from EC. Data area at EC_LPC_ADDR_HOST_PARAM contains response.
+ *
+ * If EC responds to a command and this flag is not set, this is an old-style
+ * response. Command version is 0 and response data from EC is at
+ * EC_LPC_ADDR_OLD_PARAM with unknown length.
+ */
+#define EC_HOST_ARGS_FLAG_TO_HOST 0x02
+
+/*
+ * Notes on commands:
+ *
+ * Each command is an 8-byte command value. Commands which take params or
+ * return response data specify structs for that data. If no struct is
+ * specified, the command does not input or output data, respectively.
+ * Parameter/response length is implicit in the structs. Some underlying
+ * communication protocols (I2C, SPI) may add length or checksum headers, but
+ * those are implementation-dependent and not defined here.
+ */
+
+/*****************************************************************************/
+/* General / test commands */
+
+/*
+ * Get protocol version, used to deal with non-backward compatible protocol
+ * changes.
+ */
+#define EC_CMD_PROTO_VERSION 0x00
+
+struct ec_response_proto_version {
+ uint32_t version;
+} __packed;
+
+/*
+ * Hello. This is a simple command to test the EC is responsive to
+ * commands.
+ */
+#define EC_CMD_HELLO 0x01
+
+struct ec_params_hello {
+ uint32_t in_data; /* Pass anything here */
+} __packed;
+
+struct ec_response_hello {
+ uint32_t out_data; /* Output will be in_data + 0x01020304 */
+} __packed;
+
+/* Get version number */
+#define EC_CMD_GET_VERSION 0x02
+
+enum ec_current_image {
+ EC_IMAGE_UNKNOWN = 0,
+ EC_IMAGE_RO,
+ EC_IMAGE_RW
+};
+
+struct ec_response_get_version {
+ /* Null-terminated version strings for RO, RW */
+ char version_string_ro[32];
+ char version_string_rw[32];
+ char reserved[32]; /* Was previously RW-B string */
+ uint32_t current_image; /* One of ec_current_image */
+} __packed;
+
+/* Read test */
+#define EC_CMD_READ_TEST 0x03
+
+struct ec_params_read_test {
+ uint32_t offset; /* Starting value for read buffer */
+ uint32_t size; /* Size to read in bytes */
+} __packed;
+
+struct ec_response_read_test {
+ uint32_t data[32];
+} __packed;
+
+/*
+ * Get build information
+ *
+ * Response is null-terminated string.
+ */
+#define EC_CMD_GET_BUILD_INFO 0x04
+
+/* Get chip info */
+#define EC_CMD_GET_CHIP_INFO 0x05
+
+struct ec_response_get_chip_info {
+ /* Null-terminated strings */
+ char vendor[32];
+ char name[32];
+ char revision[32]; /* Mask version */
+} __packed;
+
+/* Get board HW version */
+#define EC_CMD_GET_BOARD_VERSION 0x06
+
+struct ec_response_board_version {
+ uint16_t board_version; /* A monotonously incrementing number. */
+} __packed;
+
+/*
+ * Read memory-mapped data.
+ *
+ * This is an alternate interface to memory-mapped data for bus protocols
+ * which don't support direct-mapped memory - I2C, SPI, etc.
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_READ_MEMMAP 0x07
+
+struct ec_params_read_memmap {
+ uint8_t offset; /* Offset in memmap (EC_MEMMAP_*) */
+ uint8_t size; /* Size to read in bytes */
+} __packed;
+
+/* Read versions supported for a command */
+#define EC_CMD_GET_CMD_VERSIONS 0x08
+
+struct ec_params_get_cmd_versions {
+ uint8_t cmd; /* Command to check */
+} __packed;
+
+struct ec_response_get_cmd_versions {
+ /*
+ * Mask of supported versions; use EC_VER_MASK() to compare with a
+ * desired version.
+ */
+ uint32_t version_mask;
+} __packed;
+
+/*****************************************************************************/
+/* Flash commands */
+
+/* Get flash info */
+#define EC_CMD_FLASH_INFO 0x10
+
+struct ec_response_flash_info {
+ /* Usable flash size, in bytes */
+ uint32_t flash_size;
+ /*
+ * Write block size. Write offset and size must be a multiple
+ * of this.
+ */
+ uint32_t write_block_size;
+ /*
+ * Erase block size. Erase offset and size must be a multiple
+ * of this.
+ */
+ uint32_t erase_block_size;
+ /*
+ * Protection block size. Protection offset and size must be a
+ * multiple of this.
+ */
+ uint32_t protect_block_size;
+} __packed;
+
+/*
+ * Read flash
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_FLASH_READ 0x11
+
+struct ec_params_flash_read {
+ uint32_t offset; /* Byte offset to read */
+ uint32_t size; /* Size to read in bytes */
+} __packed;
+
+/* Write flash */
+#define EC_CMD_FLASH_WRITE 0x12
+
+struct ec_params_flash_write {
+ uint32_t offset; /* Byte offset to write */
+ uint32_t size; /* Size to write in bytes */
+ /*
+ * Data to write. Could really use EC_PARAM_SIZE - 8, but tidiest to
+ * use a power of 2 so writes stay aligned.
+ */
+ uint8_t data[64];
+} __packed;
+
+/* Erase flash */
+#define EC_CMD_FLASH_ERASE 0x13
+
+struct ec_params_flash_erase {
+ uint32_t offset; /* Byte offset to erase */
+ uint32_t size; /* Size to erase in bytes */
+} __packed;
+
+/*
+ * Get/set flash protection.
+ *
+ * If mask!=0, sets/clear the requested bits of flags. Depending on the
+ * firmware write protect GPIO, not all flags will take effect immediately;
+ * some flags require a subsequent hard reset to take effect. Check the
+ * returned flags bits to see what actually happened.
+ *
+ * If mask=0, simply returns the current flags state.
+ */
+#define EC_CMD_FLASH_PROTECT 0x15
+#define EC_VER_FLASH_PROTECT 1 /* Command version 1 */
+
+/* Flags for flash protection */
+/* RO flash code protected when the EC boots */
+#define EC_FLASH_PROTECT_RO_AT_BOOT (1 << 0)
+/*
+ * RO flash code protected now. If this bit is set, at-boot status cannot
+ * be changed.
+ */
+#define EC_FLASH_PROTECT_RO_NOW (1 << 1)
+/* RW flash code protected now, until reboot. */
+#define EC_FLASH_PROTECT_RW_NOW (1 << 2)
+/* Flash write protect GPIO is asserted now */
+#define EC_FLASH_PROTECT_GPIO_ASSERTED (1 << 3)
+/* Error - at least one bank of flash is stuck locked, and cannot be unlocked */
+#define EC_FLASH_PROTECT_ERROR_STUCK (1 << 4)
+/*
+ * Error - flash protection is in inconsistent state. At least one bank of
+ * flash which should be protected is not protected. Usually fixed by
+ * re-requesting the desired flags, or by a hard reset if that fails.
+ */
+#define EC_FLASH_PROTECT_ERROR_INCONSISTENT (1 << 5)
+/* RW flash code protected when the EC boots */
+#define EC_FLASH_PROTECT_RW_AT_BOOT (1 << 6)
+
+struct ec_params_flash_protect {
+ uint32_t mask; /* Bits in flags to apply */
+ uint32_t flags; /* New flags to apply */
+} __packed;
+
+struct ec_response_flash_protect {
+ /* Current value of flash protect flags */
+ uint32_t flags;
+ /*
+ * Flags which are valid on this platform. This allows the caller
+ * to distinguish between flags which aren't set vs. flags which can't
+ * be set on this platform.
+ */
+ uint32_t valid_flags;
+ /* Flags which can be changed given the current protection state */
+ uint32_t writable_flags;
+} __packed;
+
+/*
+ * Note: commands 0x14 - 0x19 version 0 were old commands to get/set flash
+ * write protect. These commands may be reused with version > 0.
+ */
+
+/* Get the region offset/size */
+#define EC_CMD_FLASH_REGION_INFO 0x16
+#define EC_VER_FLASH_REGION_INFO 1
+
+enum ec_flash_region {
+ /* Region which holds read-only EC image */
+ EC_FLASH_REGION_RO,
+ /* Region which holds rewritable EC image */
+ EC_FLASH_REGION_RW,
+ /*
+ * Region which should be write-protected in the factory (a superset of
+ * EC_FLASH_REGION_RO)
+ */
+ EC_FLASH_REGION_WP_RO,
+};
+
+struct ec_params_flash_region_info {
+ uint32_t region; /* enum ec_flash_region */
+} __packed;
+
+struct ec_response_flash_region_info {
+ uint32_t offset;
+ uint32_t size;
+} __packed;
+
+
+/*****************************************************************************/
+/* PWM commands */
+
+/* Get fan target RPM */
+#define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x20
+
+struct ec_response_pwm_get_fan_rpm {
+ uint32_t rpm;
+} __packed;
+
+/* Set target fan RPM */
+#define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x21
+
+struct ec_params_pwm_set_fan_target_rpm {
+ uint32_t rpm;
+} __packed;
+
+/* Get keyboard backlight */
+#define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x22
+
+struct ec_response_pwm_get_keyboard_backlight {
+ uint8_t percent;
+ uint8_t enabled;
+} __packed;
+
+/* Set keyboard backlight */
+#define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x23
+
+struct ec_params_pwm_set_keyboard_backlight {
+ uint8_t percent;
+} __packed;
+
+/* Set target fan PWM duty cycle */
+#define EC_CMD_PWM_SET_FAN_DUTY 0x24
+
+struct ec_params_pwm_set_fan_duty {
+ uint32_t percent;
+} __packed;
+
+/*****************************************************************************/
+/*
+ * Lightbar commands. This looks worse than it is. Since we only use one LPC
+ * command to say "talk to the lightbar", we put the "and tell it to do X" part
+ * into a subcommand. We'll make separate structs for subcommands with
+ * different input args, so that we know how much to expect.
+ */
+#define EC_CMD_LIGHTBAR_CMD 0x28
+
+struct ec_params_lightbar_cmd {
+ union {
+ union {
+ uint8_t cmd;
+ struct {
+ uint8_t cmd;
+ } dump, off, on, init, get_seq;
+ struct num {
+ uint8_t cmd;
+ uint8_t num;
+ } brightness, seq;
+
+ struct reg {
+ uint8_t cmd;
+ uint8_t ctrl, reg, value;
+ } reg;
+ struct rgb {
+ uint8_t cmd;
+ uint8_t led, red, green, blue;
+ } rgb;
+ } in;
+ union {
+ struct dump {
+ struct {
+ uint8_t reg;
+ uint8_t ic0;
+ uint8_t ic1;
+ } vals[23];
+ } dump;
+ struct get_seq {
+ uint8_t num;
+ } get_seq;
+ struct {
+ /* no return params */
+ } off, on, init, brightness, seq, reg, rgb;
+ } out;
+ };
+} __packed;
+
+/*****************************************************************************/
+/* Verified boot commands */
+
+/*
+ * Note: command code 0x29 version 0 was VBOOT_CMD in Link EVT; it may be
+ * reused for other purposes with version > 0.
+ */
+
+/* Verified boot hash command */
+#define EC_CMD_VBOOT_HASH 0x2A
+
+struct ec_params_vboot_hash {
+ uint8_t cmd; /* enum ec_vboot_hash_cmd */
+ uint8_t hash_type; /* enum ec_vboot_hash_type */
+ uint8_t nonce_size; /* Nonce size; may be 0 */
+ uint8_t reserved0; /* Reserved; set 0 */
+ uint32_t offset; /* Offset in flash to hash */
+ uint32_t size; /* Number of bytes to hash */
+ uint8_t nonce_data[64]; /* Nonce data; ignored if nonce_size=0 */
+} __packed;
+
+struct ec_response_vboot_hash {
+ uint8_t status; /* enum ec_vboot_hash_status */
+ uint8_t hash_type; /* enum ec_vboot_hash_type */
+ uint8_t digest_size; /* Size of hash digest in bytes */
+ uint8_t reserved0; /* Ignore; will be 0 */
+ uint32_t offset; /* Offset in flash which was hashed */
+ uint32_t size; /* Number of bytes hashed */
+ uint8_t hash_digest[64]; /* Hash digest data */
+} __packed;
+
+enum ec_vboot_hash_cmd {
+ EC_VBOOT_HASH_GET, /* Get current hash status */
+ EC_VBOOT_HASH_ABORT, /* Abort calculating current hash */
+ EC_VBOOT_HASH_START, /* Start computing a new hash */
+ EC_VBOOT_HASH_RECALC, /* Synchronously compute a new hash */
+};
+
+enum ec_vboot_hash_type {
+ EC_VBOOT_HASH_TYPE_SHA256, /* SHA-256 */
+};
+
+enum ec_vboot_hash_status {
+ EC_VBOOT_HASH_STATUS_NONE, /* No hash (not started, or aborted) */
+ EC_VBOOT_HASH_STATUS_DONE, /* Finished computing a hash */
+ EC_VBOOT_HASH_STATUS_BUSY, /* Busy computing a hash */
+};
+
+/*****************************************************************************/
+/* USB charging control commands */
+
+/* Set USB port charging mode */
+#define EC_CMD_USB_CHARGE_SET_MODE 0x30
+
+struct ec_params_usb_charge_set_mode {
+ uint8_t usb_port_id;
+ uint8_t mode;
+} __packed;
+
+/*****************************************************************************/
+/* Persistent storage for host */
+
+/* Maximum bytes that can be read/written in a single command */
+#define EC_PSTORE_SIZE_MAX 64
+
+/* Get persistent storage info */
+#define EC_CMD_PSTORE_INFO 0x40
+
+struct ec_response_pstore_info {
+ /* Persistent storage size, in bytes */
+ uint32_t pstore_size;
+ /* Access size; read/write offset and size must be a multiple of this */
+ uint32_t access_size;
+} __packed;
+
+/*
+ * Read persistent storage
+ *
+ * Response is params.size bytes of data.
+ */
+#define EC_CMD_PSTORE_READ 0x41
+
+struct ec_params_pstore_read {
+ uint32_t offset; /* Byte offset to read */
+ uint32_t size; /* Size to read in bytes */
+} __packed;
+
+/* Write persistent storage */
+#define EC_CMD_PSTORE_WRITE 0x42
+
+struct ec_params_pstore_write {
+ uint32_t offset; /* Byte offset to write */
+ uint32_t size; /* Size to write in bytes */
+ uint8_t data[EC_PSTORE_SIZE_MAX];
+} __packed;
+
+/*****************************************************************************/
+/* Real-time clock */
+
+/* RTC params and response structures */
+struct ec_params_rtc {
+ uint32_t time;
+} __packed;
+
+struct ec_response_rtc {
+ uint32_t time;
+} __packed;
+
+/* These use ec_response_rtc */
+#define EC_CMD_RTC_GET_VALUE 0x44
+#define EC_CMD_RTC_GET_ALARM 0x45
+
+/* These all use ec_params_rtc */
+#define EC_CMD_RTC_SET_VALUE 0x46
+#define EC_CMD_RTC_SET_ALARM 0x47
+
+/*****************************************************************************/
+/* Port80 log access */
+
+/* Get last port80 code from previous boot */
+#define EC_CMD_PORT80_LAST_BOOT 0x48
+
+struct ec_response_port80_last_boot {
+ uint16_t code;
+} __packed;
+
+/*****************************************************************************/
+/* Thermal engine commands */
+
+/* Set thershold value */
+#define EC_CMD_THERMAL_SET_THRESHOLD 0x50
+
+struct ec_params_thermal_set_threshold {
+ uint8_t sensor_type;
+ uint8_t threshold_id;
+ uint16_t value;
+} __packed;
+
+/* Get threshold value */
+#define EC_CMD_THERMAL_GET_THRESHOLD 0x51
+
+struct ec_params_thermal_get_threshold {
+ uint8_t sensor_type;
+ uint8_t threshold_id;
+} __packed;
+
+struct ec_response_thermal_get_threshold {
+ uint16_t value;
+} __packed;
+
+/* Toggle automatic fan control */
+#define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x52
+
+/*****************************************************************************/
+/* MKBP - Matrix KeyBoard Protocol */
+
+/*
+ * Read key state
+ *
+ * Returns raw data for keyboard cols; see ec_response_mkbp_info.cols for
+ * expected response size.
+ */
+#define EC_CMD_MKBP_STATE 0x60
+
+/* Provide information about the matrix : number of rows and columns */
+#define EC_CMD_MKBP_INFO 0x61
+
+struct ec_response_mkbp_info {
+ uint32_t rows;
+ uint32_t cols;
+ uint8_t switches;
+} __packed;
+
+/* Simulate key press */
+#define EC_CMD_MKBP_SIMULATE_KEY 0x62
+
+struct ec_params_mkbp_simulate_key {
+ uint8_t col;
+ uint8_t row;
+ uint8_t pressed;
+} __packed;
+
+/*****************************************************************************/
+/* Temperature sensor commands */
+
+/* Read temperature sensor info */
+#define EC_CMD_TEMP_SENSOR_GET_INFO 0x70
+
+struct ec_params_temp_sensor_get_info {
+ uint8_t id;
+} __packed;
+
+struct ec_response_temp_sensor_get_info {
+ char sensor_name[32];
+ uint8_t sensor_type;
+} __packed;
+
+/*****************************************************************************/
+
+/*
+ * Note: host commands 0x80 - 0x87 are reserved to avoid conflict with ACPI
+ * commands accidentally sent to the wrong interface. See the ACPI section
+ * below.
+ */
+
+/*****************************************************************************/
+/* Host event commands */
+
+/*
+ * Host event mask params and response structures, shared by all of the host
+ * event commands below.
+ */
+struct ec_params_host_event_mask {
+ uint32_t mask;
+} __packed;
+
+struct ec_response_host_event_mask {
+ uint32_t mask;
+} __packed;
+
+/* These all use ec_response_host_event_mask */
+#define EC_CMD_HOST_EVENT_GET_B 0x87
+#define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x88
+#define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x89
+#define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x8d
+
+/* These all use ec_params_host_event_mask */
+#define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x8a
+#define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x8b
+#define EC_CMD_HOST_EVENT_CLEAR 0x8c
+#define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x8e
+#define EC_CMD_HOST_EVENT_CLEAR_B 0x8f
+
+/*****************************************************************************/
+/* Switch commands */
+
+/* Enable/disable LCD backlight */
+#define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x90
+
+struct ec_params_switch_enable_backlight {
+ uint8_t enabled;
+} __packed;
+
+/* Enable/disable WLAN/Bluetooth */
+#define EC_CMD_SWITCH_ENABLE_WIRELESS 0x91
+
+struct ec_params_switch_enable_wireless {
+ uint8_t enabled;
+} __packed;
+
+/*****************************************************************************/
+/* GPIO commands. Only available on EC if write protect has been disabled. */
+
+/* Set GPIO output value */
+#define EC_CMD_GPIO_SET 0x92
+
+struct ec_params_gpio_set {
+ char name[32];
+ uint8_t val;
+} __packed;
+
+/* Get GPIO value */
+#define EC_CMD_GPIO_GET 0x93
+
+struct ec_params_gpio_get {
+ char name[32];
+} __packed;
+struct ec_response_gpio_get {
+ uint8_t val;
+} __packed;
+
+/*****************************************************************************/
+/* I2C commands. Only available when flash write protect is unlocked. */
+
+/* Read I2C bus */
+#define EC_CMD_I2C_READ 0x94
+
+struct ec_params_i2c_read {
+ uint16_t addr;
+ uint8_t read_size; /* Either 8 or 16. */
+ uint8_t port;
+ uint8_t offset;
+} __packed;
+struct ec_response_i2c_read {
+ uint16_t data;
+} __packed;
+
+/* Write I2C bus */
+#define EC_CMD_I2C_WRITE 0x95
+
+struct ec_params_i2c_write {
+ uint16_t data;
+ uint16_t addr;
+ uint8_t write_size; /* Either 8 or 16. */
+ uint8_t port;
+ uint8_t offset;
+} __packed;
+
+/*****************************************************************************/
+/* Charge state commands. Only available when flash write protect unlocked. */
+
+/* Force charge state machine to stop in idle mode */
+#define EC_CMD_CHARGE_FORCE_IDLE 0x96
+
+struct ec_params_force_idle {
+ uint8_t enabled;
+} __packed;
+
+/*****************************************************************************/
+/* Console commands. Only available when flash write protect is unlocked. */
+
+/* Snapshot console output buffer for use by EC_CMD_CONSOLE_READ. */
+#define EC_CMD_CONSOLE_SNAPSHOT 0x97
+
+/*
+ * Read next chunk of data from saved snapshot.
+ *
+ * Response is null-terminated string. Empty string, if there is no more
+ * remaining output.
+ */
+#define EC_CMD_CONSOLE_READ 0x98
+
+/*****************************************************************************/
+/* System commands */
+
+/*
+ * TODO: this is a confusing name, since it doesn't necessarily reboot the EC.
+ * Rename to "set image" or something similar.
+ */
+#define EC_CMD_REBOOT_EC 0xd2
+
+/* Command */
+enum ec_reboot_cmd {
+ EC_REBOOT_CANCEL = 0, /* Cancel a pending reboot */
+ EC_REBOOT_JUMP_RO, /* Jump to RO without rebooting */
+ EC_REBOOT_JUMP_RW, /* Jump to RW without rebooting */
+ /* (command 3 was jump to RW-B) */
+ EC_REBOOT_COLD = 4, /* Cold-reboot */
+ EC_REBOOT_DISABLE_JUMP, /* Disable jump until next reboot */
+};
+
+/* Flags for ec_params_reboot_ec.reboot_flags */
+#define EC_REBOOT_FLAG_RESERVED0 (1 << 0) /* Was recovery request */
+#define EC_REBOOT_FLAG_ON_AP_SHUTDOWN (1 << 1)
+#define EC_REBOOT_FLAG_POWER_ON (1 << 2)
+
+struct ec_params_reboot_ec {
+ uint8_t cmd; /* enum ec_reboot_cmd */
+ uint8_t flags; /* See EC_REBOOT_FLAG_* */
+} __packed;
+
+/*****************************************************************************/
+/*
+ * ACPI commands
+ *
+ * These are valid ONLY on the ACPI command/data port.
+ */
+
+/*
+ * ACPI Read Embedded Controller
+ *
+ * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
+ *
+ * Use the following sequence:
+ *
+ * - Write EC_CMD_ACPI_READ to EC_LPC_ADDR_ACPI_CMD
+ * - Wait for EC_LPC_CMDR_PENDING bit to clear
+ * - Write address to EC_LPC_ADDR_ACPI_DATA
+ * - Wait for EC_LPC_CMDR_DATA bit to set
+ * - Read value from EC_LPC_ADDR_ACPI_DATA
+ */
+#define EC_CMD_ACPI_READ 0x80
+
+/*
+ * ACPI Write Embedded Controller
+ *
+ * This reads from ACPI memory space on the EC (EC_ACPI_MEM_*).
+ *
+ * Use the following sequence:
+ *
+ * - Write EC_CMD_ACPI_WRITE to EC_LPC_ADDR_ACPI_CMD
+ * - Wait for EC_LPC_CMDR_PENDING bit to clear
+ * - Write address to EC_LPC_ADDR_ACPI_DATA
+ * - Wait for EC_LPC_CMDR_PENDING bit to clear
+ * - Write value to EC_LPC_ADDR_ACPI_DATA
+ */
+#define EC_CMD_ACPI_WRITE 0x81
+
+/*
+ * ACPI Query Embedded Controller
+ *
+ * This clears the lowest-order bit in the currently pending host events, and
+ * sets the result code to the 1-based index of the bit (event 0x00000001 = 1,
+ * event 0x80000000 = 32), or 0 if no event was pending.
+ */
+#define EC_CMD_ACPI_QUERY_EVENT 0x84
+
+/* Valid addresses in ACPI memory space, for read/write commands */
+/* Memory space version; set to EC_ACPI_MEM_VERSION_CURRENT */
+#define EC_ACPI_MEM_VERSION 0x00
+/*
+ * Test location; writing value here updates test compliment byte to (0xff -
+ * value).
+ */
+#define EC_ACPI_MEM_TEST 0x01
+/* Test compliment; writes here are ignored. */
+#define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
+/* Keyboard backlight brightness percent (0 - 100) */
+#define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
+
+/* Current version of ACPI memory address space */
+#define EC_ACPI_MEM_VERSION_CURRENT 1
+
+
+/*****************************************************************************/
+/*
+ * Special commands
+ *
+ * These do not follow the normal rules for commands. See each command for
+ * details.
+ */
+
+/*
+ * Reboot NOW
+ *
+ * This command will work even when the EC LPC interface is busy, because the
+ * reboot command is processed at interrupt level. Note that when the EC
+ * reboots, the host will reboot too, so there is no response to this command.
+ *
+ * Use EC_CMD_REBOOT_EC to reboot the EC more politely.
+ */
+#define EC_CMD_REBOOT 0xd1 /* Think "die" */
+
+/*
+ * This header byte on a command indicate version 0. Any header byte less
+ * than this means that we are talking to an old EC which doesn't support
+ * versioning. In that case, we assume version 0.
+ *
+ * Header bytes greater than this indicate a later version. For example,
+ * EC_CMD_VERSION0 + 1 means we are using version 1.
+ *
+ * The old EC interface must not use commands 0dc or higher.
+ */
+#define EC_CMD_VERSION0 0xdc
+
+#endif /* !__ACPI__ */
+
+#endif /* __CROS_EC_COMMANDS_H */
diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c
index 844e233..28f38140 100644
--- a/src/ec/lenovo/pmh7/pmh7.c
+++ b/src/ec/lenovo/pmh7/pmh7.c
@@ -19,8 +19,12 @@
#include <arch/io.h>
#include <console/console.h>
+#ifndef __PRE_RAM__
+#ifndef __SMM__
#include <device/device.h>
#include <device/pnp.h>
+#endif
+#endif
#include <stdlib.h>
#include "pmh7.h"
#include "chip.h"
diff --git a/src/ec/quanta/Kconfig b/src/ec/quanta/Kconfig
new file mode 100644
index 0000000..00c3dbf
--- /dev/null
+++ b/src/ec/quanta/Kconfig
@@ -0,0 +1,2 @@
+source src/ec/quanta/ene_kb3940q/Kconfig
+source src/ec/quanta/it8518/Kconfig
diff --git a/src/ec/quanta/Makefile.inc b/src/ec/quanta/Makefile.inc
new file mode 100644
index 0000000..c128aec
--- /dev/null
+++ b/src/ec/quanta/Makefile.inc
@@ -0,0 +1,2 @@
+subdirs-$(CONFIG_EC_QUANTA_ENE_KB3940Q) += ene_kb3940q
+subdirs-$(CONFIG_EC_QUANTA_IT8518) += it8518
diff --git a/src/ec/quanta/ene_kb3940q/Kconfig b/src/ec/quanta/ene_kb3940q/Kconfig
new file mode 100644
index 0000000..4258948
--- /dev/null
+++ b/src/ec/quanta/ene_kb3940q/Kconfig
@@ -0,0 +1,4 @@
+config EC_QUANTA_ENE_KB3940Q
+ bool
+ help
+ Interface to QUANTA ENE KB3940Q Embedded Controller.
diff --git a/src/ec/quanta/ene_kb3940q/Makefile.inc b/src/ec/quanta/ene_kb3940q/Makefile.inc
new file mode 100644
index 0000000..3052859
--- /dev/null
+++ b/src/ec/quanta/ene_kb3940q/Makefile.inc
@@ -0,0 +1,4 @@
+driver-y += ec.c
+smm-y += ec.c
+
+smm-y += ../../../lib/delay.c
diff --git a/src/mainboard/getac/p470/chip.h b/src/ec/quanta/ene_kb3940q/acpi/ac.asl
similarity index 72%
copy from src/mainboard/getac/p470/chip.h
copy to src/ec/quanta/ene_kb3940q/acpi/ac.asl
index b75c381..8c85fc3 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/ec/quanta/ene_kb3940q/acpi/ac.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,5 +19,21 @@
* MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR)
+ {
+ Store(ADPT, Local0)
+ Return(Local0)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl
new file mode 100644
index 0000000..8fbd9bb
--- /dev/null
+++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl
@@ -0,0 +1,159 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define strings in the root scope to
+ * report device-specific battery information to the OS.
+ *
+ * BATV: Vendor
+ */
+
+// Scope (EC0)
+
+Device (BATX)
+{
+ Name (_HID, EISAID ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ Name (PBIF, Package () {
+ 0x00000001, // 0 Power Unit: mAh
+ 0xFFFFFFFF, // 1 Design Capacity
+ 0xFFFFFFFF, // 2 Last Full Charge Capacity
+ 0x00000001, // 3 Battery Technology: Rechargeable
+ 0xFFFFFFFF, // 4 Design Voltage
+ 0x000000FA, // 5 Design Capacity of Warning
+ 0x00000096, // 6 Design Capacity of Low
+ 0x0000000A, // 7 Capacity Granularity 1
+ 0x00000019, // 8 Capacity Granularity 2
+ "", // 9 Model Number
+ "", // 10 Serial Number
+ "", // 11 Battery Type
+ "" // 12 OEM Information
+ })
+
+ Name (PBST, Package () {
+ 0x00000000, // Battery State
+ 0xFFFFFFFF, // Battery Present Rate
+ 0xFFFFFFFF, // Battery Remaining Capacity
+ 0xFFFFFFFF, // Battery Present Voltage
+ })
+
+ // Workaround for full battery status, enabled by default
+ Name (BFWK, One)
+
+ // Method to enable full battery workaround
+ Method (BFWE)
+ {
+ Store (One, BFWK)
+ }
+
+ // Method to disable full battery workaround
+ Method (BFWD)
+ {
+ Store (Zero, BFWK)
+ }
+
+ // Device insertion/removal control method that returns a device’s status.
+ // Power resource object that evaluates to the current on or off state of
+ // the Power Resource.
+ Method (_STA, 0, Serialized)
+ {
+ If (BTIN) {
+ Return (0x1F)
+ } Else {
+ Return (0x0F)
+ }
+ }
+
+ Method (_BIF, 0, Serialized)
+ {
+ // Update fields from EC
+ Store (BDC0, Index (PBIF, 1)) // Batt Design Capacity
+ Store (BFC0, Index (PBIF, 2)) // Batt Last Full Charge Capacity
+ Store (BDV0, Index (PBIF, 4)) // Batt Design Voltage
+ Divide(BFC0, 0x64, Local0, Local1)
+ Multiply(Local1, 0x0A, Local0)
+ Store(Local0, Index(PBIF, 5))
+ Multiply(Local1, 0x05, Local0)
+ Store (Local0, Index (PBIF, 6))
+ Store (ToString(BATD), Index (PBIF, 9)) // Model Number
+ Store (ToDecimalString(BSN0), Index (PBIF, 10)) // Serial Number
+ Store (ToString(BCHM), Index (PBIF, 11)) // Battery Type
+ Store (\BATV, Index (PBIF, 12)) // OEM information
+
+ Return (PBIF)
+ }
+
+ Method (_BST, 0, Serialized)
+ {
+ //
+ // 0: BATTERY STATE
+ //
+ // bit 0 = discharging
+ // bit 1 = charging
+ // bit 2 = critical level
+ //
+
+ // Get battery state from EC
+ Store (BST0, Local0)
+ Store (Local0, Index (PBST, 0))
+
+ //
+ // 1: BATTERY PRESENT RATE/CURRENT
+ //
+ Store (BPC0, Local1)
+ If (LAnd (Local1, 0x8000)) {
+ Xor (Local1, 0xFFFF, Local1)
+ Increment (Local1)
+ }
+ Store (Local1, Index (PBST, 1))
+
+ //
+ // 2: BATTERY REMAINING CAPACITY
+ //
+ Store (BRC0, Local1)
+
+ If (LAnd (BFWK, LAnd (ADPT, LNot (Local0)))) {
+ // On AC power and battery is neither charging
+ // nor discharging. Linux expects a full battery
+ // to report same capacity as last full charge.
+ // https://bugzilla.kernel.org/show_bug.cgi?id=12632
+ Store (BFC0, Local2)
+
+ // See if within ~3% of full
+ ShiftRight (Local2, 5, Local3)
+ If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+ LLess (Local1, Add (Local2, Local3))))
+ {
+ Store (Local2, Local1)
+ }
+ }
+ Store (Local1, Index (PBST, 2))
+
+ //
+ // 3: BATTERY PRESENT VOLTAGE
+ //
+ Store (BPV0, Index (PBST, 3))
+
+ Return (PBST)
+ }
+}
diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
new file mode 100644
index 0000000..4e703fe
--- /dev/null
+++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl
@@ -0,0 +1,280 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+External (\_PR.CPU0._PPC, IntObj)
+
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 1)
+ Name (_GPE, Add(EC_SCI_GPI, 16)) // GPE for Runtime SCI
+
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ // EC Name Space Configuration
+
+ Offset(0x40),
+ BDC0, 16, // Batt Design Capacity ; 40h, 41h
+ BDV0, 16, // Batt Design Voltage ; 42h, 43h
+ BFC0, 16, // Batt Last Full Charge Capacity ; 44h, 45h
+ BPC0, 16, // Batt Current ; 46h, 47h
+ BRC0, 16, // Batt Remaining Capacity ; 48h, 49h
+ BPV0, 16, // Batt Present Voltage ; 4Ah, 4Bh
+ BCG0, 16, // Batt Charge current ; 4Ch, 4Dh
+ BACV, 16, // Batt Charging Voltage ; 4Eh, 4Fh
+ BTM0, 16, // Batt Battery Temp ; 50h, 51h
+ BSN0, 16, // Batt Serial Number ; 52h, 53h
+ BPCT, 16, // Batt Percentage of full charge ; 54h, 55h
+ BSSB, 16, // BATT Battery Status SMB ; 56h, 57h
+ CYC0, 16, // Batt Cycle Counter ; 58h, 59h
+ BMD0, 16, // Manufacture Date ; 5Ah, 5Bh
+ // Batt Day ; BIT[4:0] (Day)
+ // Batt Month ; BIT[9:5] (Month)
+ // Batt Year ; BIT[15:10] (Year)
+
+
+ Offset(0x60),
+ BCHM, 32, // Battery Chemistry ; 60h - 64h
+ BATD, 56, // Battery Device name ; 64h - 6Ah
+
+ Offset(0x70),
+ ADPT, 1, // AC Adapter Status for OS ; 70h.0
+ ADPN, 1, // AC Adapter H/W status ; 70h.1
+ BTIN, 1, // Battery Present ; 70h.2
+ BTBD, 1, // Battery Malfunction ; 70h.3
+ ACMD, 1, // ACPI Mode ; 70h.4
+ , 1, // Reserved ; 70h.5
+ SSBS, 1, // 1=Standard BIOS, 0=Coreboot ; 70h.6
+ PSTH, 1, // Passive Thermal Policy ; 70h.7
+ BST0, 8, // Battery Status ; 71h
+ // Bit0 : Discharging
+ // Bit1 : Charging
+ // Bit2 : Discharging and Critical Low
+ // Bit3-7 : Reserved
+ LIDF, 1, // Lid is open ; 72h.0
+ GPRC, 1, // Recovery GPI Status ; 72h.1
+ , 6, // Reserved ; 72h.2-7
+ TPLD, 1, // TouchPad LED Activation ; 73h.0
+ TPST, 1, // Touchpad LED Status ; 73h.1
+ , 6, // Reserved ; 73h.2-7
+
+ Offset(0x78),
+ CTMP, 8, // Current CPU Temperature ; 78h
+ SKTB, 8, // GPU Temperature ; 79h
+ LTM1, 8, // Local Temp 1 ; 7Ah
+ LTM2, 8, // Local Temp 2 ; 7Bh
+ FTCH, 16, // Fan Tachometer value ; 7Ch - 7Dh
+ FDBG, 16, // Fan Debug - Override Fan Tach value ; 7Eh - 7Fh
+ , 1, // Reserved ; 80h.0
+ KBID, 1, // 0=EN KBD, 1=JP KBD ; 80h.1
+ , 6, // Reserved ; 80h.2-7
+ NPST, 8, // Number of P-State level ; 81h
+ MPST, 8, // Maxumum P-State ; 82h
+ KWAK, 1, // Keyboard WAKE(0=Disable,1=Enable) ; 83h.0
+ TWAK, 1, // TouchPad WAKE(0=Disable,1=Enable) ; 83h.1
+ , 1, // Reserved ; 83h.2
+ LWAK, 1, // LAN Wake Enable (0=Disable, 1=Enable); 83h.3
+ RWAK, 1, // RTC Wake Enable(0=DIsable,1=Enable) ; 83h.4
+ , 3, // Reserved ; 83h.5-7
+ KBEV, 1, // Keyboard Wake Event ; 84h.0
+ TPEV, 1, // TouchPad Wake Event ; 84h.1
+ LDEV, 1, // Lid Wake Event ; 84h.2
+ , 4, // Reserved ; 84h.3-6
+ PBEV, 1, // Power Button Wake Event ; 84h.7
+
+ ECCD, 8, // EC Code State ; 85h
+ ROFW, 8, // RO FW Reason ID ; 86h
+
+ Offset(0xBA),
+ FWVR, 48, // EC Firmware Version ; BAh-BFh
+
+ Offset(0xC0),
+ SMPR, 8, // SMBus protocol register ; C0h
+ SMST, 8, // SMBus status register ; C1h
+ SMAD, 8, // SMBus address register ; C2h
+ SMCM, 8, // SMBus command register ; C3h
+ SMD0, 0x100, // SMBus data regs (32) ; C4h - E3h
+ BCNT, 8, // SMBus Block Count ; E4h
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+ Return (ECMD)
+ }
+
+ Method(_STA)
+ {
+ Return(0x0F)
+ }
+
+
+ Method (_REG, 2, NotSerialized)
+ {
+ // Initialize AC power state
+ Store (ADPT, \PWRS)
+
+ // Initialize LID switch state
+ Store (LIDF, \LIDS)
+
+ // Force a read of CPU temperature
+ Store (CTMP, Local0)
+
+ // Find and program number of P-States
+ Store (SizeOf (\_PR.CPU0._PSS), MPST)
+ Store ("Programming number of P-states: ", Debug)
+ Store (MPST, Debug)
+
+ // Find and program the current P-State
+ Store(\_PR.CPU0._PPC, NPST)
+ Store ("Programming Current P-state: ", Debug)
+ Store (NPST, Debug)
+ }
+
+/*
+ * EC Query Responses
+ *
+ * Lid Status Change 06h
+ * Wifi Button Event (F12) 07h
+ * TZ Event Update CPU Temp 08h
+ * CPU P-State Down 0Eh
+ * CPU P-State UP 0Fh
+
+ * AC plug in 10h
+ * AC removed 11h
+ * Battery Plugged in 12h
+ * Battery Removed 13h
+ * Battery State Change 14h
+ */
+
+ // Wifi Button Event
+ Method (_Q07)
+ {
+ Store ("Wifi Button Event 0x07", Debug)
+ }
+
+ // Thermal Event
+ Method (_Q08)
+ {
+ Store ("Thermal Event 0x08", Debug)
+ Notify(\_TZ.THRM, 0x80)
+ }
+
+ // Pstate Down
+ Method (_Q0E)
+ {
+ Store ("Pstate Event 0x0E", Debug)
+
+ Store(\_PR.CPU0._PPC, Local0)
+ Subtract(PPCM, 0x01, Local1)
+
+ If(LLess(Local0, Local1)) {
+ Increment(Local0)
+ \PPCN ()
+ }
+
+ Store(Local0, NPST)
+ }
+
+ // Pstate Up
+ Method (_Q0F)
+ {
+ Store ("Pstate Event 0x0F", Debug)
+ Store(\_PR.CPU0._PPC, Local0)
+
+ If(Local0) {
+ Decrement(Local0)
+ \PPCN ()
+ }
+
+ Store(Local0, NPST)
+ }
+
+ // AC Power Connected
+ Method (_Q10, 0, NotSerialized)
+ {
+ Store ("AC Insertion Event 0x10", Debug)
+ Store (One, \PWRS)
+ Notify (AC, 0x80)
+ Notify (BATX, 0x80)
+ \PNOT ()
+ }
+
+ // AC Power Removed
+ Method (_Q11, 0, NotSerialized)
+ {
+ Store ("AC Detach Event 0x11", Debug)
+ Store (Zero, \PWRS)
+ Notify (AC, 0x80)
+ Notify (BATX, 0x80)
+ \PNOT ()
+ }
+
+ // Battery State Change - Attach Event
+ Method (_Q12, 0, NotSerialized)
+ {
+ Store ("Battery Insertion Event 0x12", Debug)
+
+ Notify (BATX, 0x81)
+ Notify (BATX, 0x80)
+ \PNOT ()
+ }
+
+ // Battery State Change - Detach Event
+ Method (_Q13, 0, NotSerialized)
+ {
+ Store ("Battery Detach Event 0x13", Debug)
+
+ Notify (BATX, 0x81)
+ Notify (BATX, 0x80)
+ \PNOT ()
+ }
+
+
+ // Battery State Change Event
+ Method (_Q14, 0, NotSerialized)
+ {
+ Store ("Battery State Change Event 0x14", Debug)
+
+ Notify (BATX, 0x80)
+ }
+
+ // Lid Switch Event
+ Method (_Q06)
+ {
+ Store ("Lid Switch Event 0x06", Debug)
+ sleep(20)
+ Store (LIDF, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ #include "ac.asl"
+ #include "battery.asl"
+}
diff --git a/src/ec/quanta/ene_kb3940q/acpi/superio.asl b/src/ec/quanta/ene_kb3940q/acpi/superio.asl
new file mode 100644
index 0000000..db4b412
--- /dev/null
+++ b/src/ec/quanta/ene_kb3940q/acpi/superio.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+
+#ifdef SIO_EC_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized) {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0) {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+}
diff --git a/src/mainboard/getac/p470/chip.h b/src/ec/quanta/ene_kb3940q/chip.h
similarity index 64%
copy from src/mainboard/getac/p470/chip.h
copy to src/ec/quanta/ene_kb3940q/chip.h
index b75c381..ce95c1c 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/ec/quanta/ene_kb3940q/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,5 +19,17 @@
* MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+#ifndef _EC_QUANTA_ENE_KB3940Q_CHIP_H
+#define _EC_QUANTA_ENE_KB3940Q_CHIP_H
+
+#include <device/device.h>
+#include <pc80/keyboard.h>
+
+struct chip_operations;
+extern struct chip_operations ec_quanta_ene_kb3940q_ops;
+
+struct ec_quanta_ene_kb3940q_config {
+ struct pc_keyboard keyboard;
+};
+
+#endif /* _EC_QUANTA_ENE_KB3940Q_CHIP_H */
diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c
new file mode 100644
index 0000000..efacac1
--- /dev/null
+++ b/src/ec/quanta/ene_kb3940q/ec.c
@@ -0,0 +1,178 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __PRE_RAM__
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "ec.h"
+#include "chip.h"
+
+/* kbc helper functions from drivers/pc80/keyboard.c */
+static int ec_input_buffer_empty(u8 status_port)
+{
+ u32 timeout;
+ for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_port) & KBD_IBF);
+ timeout--) {
+ mdelay(1);
+ }
+
+ if (!timeout) {
+ printk(BIOS_WARNING, "Unexpected EC/KBD input buffer full\n");
+ }
+ return !!timeout;
+}
+
+
+static int ec_output_buffer_full(u8 status_port)
+{
+ u32 timeout;
+ for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_port)
+ & KBD_OBF) == 0); timeout--) {
+ mdelay(1);
+ }
+
+ if (!timeout) {
+ printk(BIOS_INFO, "EC/KBD output buffer result timeout\n");
+ }
+ return !!timeout;
+}
+
+
+
+/* The ENE 60/64 EC registers are the same command/status IB/OB KBC pair.
+ * Check status from 64 port before each command.
+ *
+ * Ex. Get panel ID command C43/D77
+ * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port
+ * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port
+ * Check OBF set. Then Get Data(0x03:panel ID) from 0x60
+ * Different commands return may or may not respond and may have multiple
+ * bytes. Keep it simple for now
+ */
+
+u8 ec_kbc_read_ob(void)
+{
+ if (!ec_output_buffer_full(KBD_STATUS)) return 0;
+ return inb(KBD_DATA);
+}
+
+void ec_kbc_write_cmd(u8 cmd)
+{
+ if (!ec_input_buffer_empty(KBD_STATUS)) return;
+ outb(cmd, KBD_COMMAND);
+}
+
+void ec_kbc_write_ib(u8 data)
+{
+ if (!ec_input_buffer_empty(KBD_STATUS)) return;
+ outb(data, KBD_DATA);
+}
+
+/* EC Host Control Protocol routines */
+u8 ec_read_ob(void)
+{
+ if (!ec_output_buffer_full(EC_SC)) return 0;
+ return inb(EC_DATA);
+}
+
+void ec_write_cmd(u8 cmd)
+{
+ if (!ec_input_buffer_empty(EC_SC)) return;
+ outb(cmd, EC_COMMAND);
+}
+
+void ec_write_ib(u8 data)
+{
+ if (!ec_input_buffer_empty(EC_SC)) return;
+ outb(data, EC_DATA);
+}
+
+/*
+ * These functions are for accessing the ENE932 device RAM space
+ */
+u8 ec_mem_read(u8 addr)
+{
+ ec_write_cmd(EC_CMD_READ_RAM);
+ ec_write_ib(addr);
+ return ec_read_ob();
+}
+
+void ec_mem_write(u8 addr, u8 data)
+{
+ ec_write_cmd(EC_CMD_WRITE_RAM);
+ ec_write_ib(addr);
+ ec_write_ib(data);
+ return;
+}
+
+#ifndef __SMM__
+static void ene_kb3940q_init(device_t dev)
+{
+ struct ec_quanta_ene_kb3940q_config *conf = dev->chip_info;
+
+
+ if (!dev->enabled)
+ return;
+
+ printk(BIOS_DEBUG, "Quanta EnE KB3940Q: Initializing keyboard.\n");
+ pc_keyboard_init(&conf->keyboard);
+
+}
+
+
+static void ene_kb3940q_read_resources(device_t dev)
+{
+ /* This function avoids an error on serial console. */
+}
+
+
+static void ene_kb3940q_enable_resources(device_t dev)
+{
+ /* This function avoids an error on serial console. */
+}
+
+static struct device_operations ops = {
+ .init = ene_kb3940q_init,
+ .read_resources = ene_kb3940q_read_resources,
+ .enable_resources = ene_kb3940q_enable_resources
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, 0, 0, { 0, 0 }, }
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
+ pnp_dev_info);
+}
+
+struct chip_operations ec_quanta_ene_kb3940q_ops = {
+ CHIP_NAME("QUANTA EnE KB3940Q EC")
+ .enable_dev = enable_dev
+};
+#endif /* ! __SMM__ */
+#endif /* ! __PRE_RAM__ */
diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h
new file mode 100644
index 0000000..e3d20c0
--- /dev/null
+++ b/src/ec/quanta/ene_kb3940q/ec.h
@@ -0,0 +1,212 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * EC communication interface for QUANTA EnE KB3940Q Embedded Controller.
+ */
+
+#ifndef _EC_QUANTA_ENE_KB3940Q_EC_H
+#define _EC_QUANTA_ENE_KB3940Q_EC_H
+
+#define EC_IO 0x380 /* Mainboard specific. Could be Kconfig option */
+#define EC_IO_HIGH EC_IO + 1
+#define EC_IO_LOW EC_IO + 2
+#define EC_IO_DATA EC_IO + 3
+
+
+
+// 60h/64h Command Interface
+#define KBD_DATA 0x60
+#define KBD_COMMAND 0x64
+#define KBD_STATUS 0x64
+#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec)
+#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
+
+// 62h/66h Command Interface
+#define EC_DATA 0x62
+#define EC_COMMAND 0x66
+#define EC_SC 0x66
+
+/* Wait 400ms for keyboard controller answers */
+#define KBC_TIMEOUT_IN_MS 400
+
+u8 ec_kbc_read_ob(void);
+void ec_kbc_write_cmd(u8 cmd);
+void ec_kbc_write_ib(u8 data);
+u8 ec_read_ob(void);
+void ec_write_cmd(u8 cmd);
+void ec_write_ib(u8 data);
+
+u8 ec_mem_read(u8 addr);
+void ec_mem_write(u8 addr, u8 data);
+
+/*****************************************************************************
+ * EC Internal memory
+ */
+
+#define EC_BAT_DCAP_LO 0x40
+#define EC_BAT_DCAP_HI 0x41
+#define EC_BAT_DVOLT_LO 0x42
+#define EC_BAT_DVOLT_HI 0x43
+#define EC_BAT_FULL_CAP_LO 0x44
+#define EC_BAT_FULL_CAP_HI 0x45
+#define EC_BAT_RATE_LO 0x46
+#define EC_BAT_RATE_HI 0x47
+#define EC_BAT_RMC_LO 0x48
+#define EC_BAT_RMC_HI 0x49
+#define EC_BAT_VOLT_LO 0x4A
+#define EC_BAT_VOLT_HI 0x4B
+#define EC_BAT_CHRG_CURT_LO 0x4C
+#define EC_BAT_CHRG_CURT_HI 0x4D
+#define EC_BAT_CHRG_VOLT_LO 0x4E
+#define EC_BAT_CHRG_VOLT_HI 0x4F
+#define EC_BAT_TEMP_LO 0x50
+#define EC_BAT_TEMP_HI 0x51
+#define EC_BAT_SN_LO 0x52
+#define EC_BAT_SN_HI 0x53
+#define EC_BAT_RSOC_LO 0x54
+#define EC_BAT_RSOC_HI 0x55
+#define EC_BAT_STATUS_LO 0x56
+#define EC_BAT_STATUS_HI 0x57
+#define EC_BAT_CYCLE_COUNT_LO 0x58
+#define EC_BAT_CYCLE_COUNT_HI 0x59
+#define EC_BAT_MFG_DATE_LO 0x5A
+#define EC_BAT_MFG_DATE_HI 0x5B
+#define EC_BAT_CHEMISTRY0 0x60
+#define EC_BAT_CHEMISTRY1 0x61
+#define EC_BAT_CHEMISTRY2 0x62
+#define EC_BAT_CHEMISTRY3 0x63
+#define EC_BAT_DEVICE_NAME0 0x64
+#define EC_BAT_DEVICE_NAME1 0x65
+#define EC_BAT_DEVICE_NAME2 0x66
+#define EC_BAT_DEVICE_NAME3 0x67
+#define EC_BAT_DEVICE_NAME4 0x68
+#define EC_BAT_DEVICE_NAME5 0x69
+#define EC_BAT_DEVICE_NAME6 0x6A
+
+#define EC_POWER_FLAG 0x70
+#define EC_PF_ADAPTER_IN (1 << 0)
+#define EC_PF_ADAPTER_PIN (1 << 1)
+#define EC_PF_BATT_IN (1 << 2)
+#define EC_PF_BATT_DESTROY (1 << 3)
+#define EC_PF_ACPI_MODE (1 << 4)
+#define EC_PF_X86_BIOS (1 << 6)
+#define EC_PF_COREBOOT 0
+#define EC_PF_PASSIVE_THERM (1 << 7)
+
+#define EC_CHARGER_STATUS 0x71
+#define EC_CHS_BAT_DISCHARGING (1 << 0)
+#define EC_CHS_BAT_CHARGING (1 << 1)
+#define EC_CHS_BAT_CRITICAL (1 << 2)
+
+#define EC_HW_GPI_STATUS 0x72
+#define EC_GPI_LID_STAT_BIT 0
+#define EC_GPI_RECOVERY_MODE_BIT 1
+#define EC_GPI_LID_OPEN (1 << EC_GPI_LID_STAT_BIT)
+#define EC_GPI_RECOVERY_STATUS (1 << EC_GPI_RECOVERY_MODE_BIT)
+
+#define EC_GPIO_STATUS 0x73
+#define EC_GPIO_TP_LED_ENABLE (1 << 0)
+#define EC_GPIO_TP_LED_STATUS (1 << 1)
+
+#define EC_CPU_TMP 0x78
+#define EC_GPU_TMP 0x79
+#define EC_LOCAL_TMP1 0x7A
+#define EC_LOCAL_TMP2 0x7B
+#define EC_FAN_TACH_LO 0x7C
+#define EC_FAN_TACH_HI 0x7D
+#define EC_FAN_DBG_RPM_LO 0x7E
+#define EC_FAN_DBG_RPM_HI 0x7F
+
+#define EC_KBID_REG 0x80
+#define EC_KBD_EN 0
+#define EC_KBD_JP (1 << 1)
+#define EC_CURR_PS 0x81
+#define EC_MAX_PS 0x82
+
+#define EC_EC_PSW 0x83
+#define EC_PSW_IKB (1 << 0)
+#define EC_PSW_TP (1 << 1)
+#define EC_PSW_LAN (1 << 3)
+#define EC_PSW_RTC (1 << 4)
+#define EC_PSW_USB (1 << 5)
+
+#define EC_WAKE_EVEN_TID 0x84
+#define EC_WID_IKB (1 << 0)
+#define EC_WID_TP (1 << 1)
+#define EC_WID_LID (1 << 2)
+#define EC_WID_PWRSW (1 << 7)
+
+#define EC_CODE_STATE 0x85
+#define EC_COS_INITIAL_STAGE 0xBB
+#define EC_COS_EC_RO 0xC0
+#define EC_COS_EC_RW 0xC1
+
+#define EC_FW_REASON_ID 0x86
+#define EC_FWR_NOT_RO 0x00
+#define EC_FWR_GPI_ASSERTED 0x01
+#define EC_FWR_HOTKEY_PRESSED 0x02
+#define EC_FWR_FIRMWARE_CORRUPT 0x03
+
+#define EC_FW_VER0 0xBA
+#define EC_FW_VER1 0xBB
+#define EC_FW_VER2 0xBC
+#define EC_FW_VER3 0xBD
+#define EC_FW_VER4 0xBE
+#define EC_FW_VER5 0xBF
+#define EC_SMBPTCL 0xC0
+#define EC_SMBSTA 0xC1
+#define EC_SMBADDR 0xC2
+#define EC_SMBCMD 0xC3
+#define EC_SMBDATA 0xC4
+#define EC_SMBBCNT 0xE4
+
+/*****************************************************************************
+ * SMI / SCI event status
+ */
+#define Q_EVENT_LID_STATUS 0x06
+#define Q_EVENT_WIFI_BUTTON 0x06
+#define Q_EVENT_THERM_EVENT 0x08
+#define Q_EVENT_PSTATE_DOWN 0x0E
+#define Q_EVENT_PSTATE_UP 0x0F
+#define Q_EVENT_AC_PLUGGED 0x10
+#define Q_EVENT_AC_UNPLUGGED 0x11
+#define Q_EVENT_BATTERY_PLUGGED 0x12
+#define Q_EVENT_BATTERY_UNPLUGGED 0x13
+#define Q_EVENT_BATTERY_STATUS 0x14
+
+/*****************************************************************************
+ * EC Commands
+ */
+#define EC_CMD_ENABLE_ACPI_MODE 0x71
+#define EC_CMD_DISABLE_ACPI_MODE 0x72
+#define EC_CMD_DISABLE_SMBUS_EVENT 0x73
+#define EC_CMD_ENABLE_SMBUS_EVENT 0x74
+#define EC_CMD_SYSTEM_RESET 0x78
+#define EC_CMD_SYSTEM_SHUTDOWN 0x79
+#define EC_CMD_RESET_FOR_FW_UPDATE 0x7D
+#define EC_CMD_IDLE_FOR SPI_UPDATE 0x7E
+#define EC_CMD_READ_RAM 0x80
+#define EC_CMD_WRITE_RAM 0x81
+#define EC_CMD_BURST_ENABLE 0x82
+#define EC_CMD_BURST_DISABLE 0x83
+#define EC_CMD_QUERY_EVENT 0x84
+
+
+#endif /* _EC_QUANTA_ENE_KB3940Q_EC_H */
diff --git a/src/ec/quanta/it8518/Kconfig b/src/ec/quanta/it8518/Kconfig
new file mode 100644
index 0000000..477e085
--- /dev/null
+++ b/src/ec/quanta/it8518/Kconfig
@@ -0,0 +1,4 @@
+config EC_QUANTA_IT8518
+ bool
+ help
+ Interface to QUANTA IT8518 Embedded Controller.
diff --git a/src/ec/quanta/it8518/Makefile.inc b/src/ec/quanta/it8518/Makefile.inc
new file mode 100644
index 0000000..3052859
--- /dev/null
+++ b/src/ec/quanta/it8518/Makefile.inc
@@ -0,0 +1,4 @@
+driver-y += ec.c
+smm-y += ec.c
+
+smm-y += ../../../lib/delay.c
diff --git a/src/mainboard/getac/p470/chip.h b/src/ec/quanta/it8518/acpi/ac.asl
similarity index 72%
copy from src/mainboard/getac/p470/chip.h
copy to src/ec/quanta/it8518/acpi/ac.asl
index b75c381..e736ff2 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/ec/quanta/it8518/acpi/ac.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,5 +19,21 @@
* MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Scope (EC0)
+
+Device (AC)
+{
+ Name (_HID, "ACPI0003")
+ Name (_PCL, Package () { \_SB })
+
+ Method (_PSR)
+ {
+ Store(ACPW, Local0)
+ Return(Local0)
+ }
+
+ Method (_STA)
+ {
+ Return (0x0F)
+ }
+}
diff --git a/src/ec/quanta/it8518/acpi/battery.asl b/src/ec/quanta/it8518/acpi/battery.asl
new file mode 100644
index 0000000..47ce281
--- /dev/null
+++ b/src/ec/quanta/it8518/acpi/battery.asl
@@ -0,0 +1,354 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (BATX)
+{
+ Name (_HID, EISAID ("PNP0C0A"))
+ Name (_UID, 1)
+ Name (_PCL, Package () { \_SB })
+
+ //
+ // Indicator of BATX attach/detach
+ // Battery X Information
+ // Battery X Status
+ //
+ Name (BXST, Zero)
+
+ //
+ // Default Static Battery Information
+ //
+ Name (PBIF, Package()
+ {
+ 0, // 0: Power Unit
+ 0xFFFFFFFF, // 1: Design Capacity
+ 0xFFFFFFFF, // 2: Last Full Charge Capacity
+ 1, // 3: Battery Technology(Rechargable)
+ 10800, // 4: Design Voltage 10.8V
+ 0, // 5: Design capacity of warning
+ 0, // 6: Design capacity of low
+ 1, // 7: Battery capacity granularity 1
+ 1, // 8: Battery capacity granularity 2
+ "", // 9: Model Number
+ "", // 10: Serial Number
+ "", // 11: Battery Type
+ "" // 12: OEM Infomration
+ })
+
+ Name (PBST, Package ()
+ {
+ 0x00000000, // Battery State
+ 0xFFFFFFFF, // Battery Present Rate
+ 0xFFFFFFFF, // Battery Remaining Capacity
+ 0xFFFFFFFF, // Battery Present Voltage
+ })
+
+ // Workaround for full battery status, enabled by default
+ Name (BFWK, One)
+
+ // Method to enable full battery workaround
+ Method (BFWE)
+ {
+ Store (One, BFWK)
+ }
+
+ // Method to disable full battery workaround
+ Method (BFWD)
+ {
+ Store (Zero, BFWK)
+ }
+
+ // Method to wait for EC to be ready after changing the Battery Info ID
+ // Selector
+ Method (WAEC)
+ {
+ Store (20, Local0) // Timeout 100 msec
+ While (LEqual (HSID, Zero))
+ {
+ // EC Is not ready
+ Sleep (5)
+ Decrement (Local0)
+ If (LEqual (Local0, Zero))
+ {
+ Break
+ }
+ }
+ }
+
+ // Battery Slot Status
+ Method (_STA, 0, Serialized)
+ {
+ Store (MBTS, BXST)
+ If (BXST)
+ {
+ // Battery is present
+ Return (0x1F)
+ }
+ Else
+ {
+ Return (0x0F)
+ }
+ }
+
+ Method (_BIF, 0, Serialized)
+ {
+ // Update fields from EC
+
+ //
+ // Information ID 1 -
+ //
+ Store (One, HIID)
+ WAEC ()
+
+ //
+ // Power Unit
+ // SMART battery : 1 - 10mWh : 0 - mAh
+ // ACPI spec : 0 - mWh : 1 - mAh
+ //
+ Store(SBCM, Local7)
+ XOr (Local7, One, Index (PBIF, 0))
+
+ //
+ // Information ID 0 -
+ //
+ Store (Zero, HIID)
+ WAEC ()
+
+ //
+ // Last Full Charge Capacity
+ //
+ If (Local7)
+ {
+ Multiply (SBFC, 10, Index (PBIF, 2))
+ }
+ Else
+ {
+ Store (SBFC, Index (PBIF, 2))
+ }
+
+ //
+ // Information ID 2 -
+ //
+ Store (2, HIID)
+ WAEC ()
+
+ //
+ // Design capacity
+ //
+ If (Local7)
+ {
+ Multiply (SBDC, 10, Local0)
+ }
+ Else
+ {
+ Store (SBDC, Local0)
+ }
+ Store (Local0, Index(PBIF, One))
+
+ //
+ // Design capacity of High (5%)
+ // Design capacity of Low (1%)
+ //
+ Divide (Local0, 20, Local1, Index (PBIF, 5))
+ Divide (Local0, 100, Local1, Index (PBIF, 6))
+
+ //
+ // Design voltage
+ //
+ Store (SBDV, Index (PBIF, 4))
+
+ //
+ // Serial Number
+ //
+ Store (ToHexString (SBSN), Index (PBIF, 10))
+
+ //
+ // Information ID 4 -
+ //
+ Store (4, HIID)
+ WAEC ()
+
+ //
+ // Battery Type - Device Chemistry
+ //
+ Store (SBCH, Index (PBIF, 11))
+
+ //
+ // Information ID 5 -
+ //
+ Store (5, HIID)
+ WAEC ()
+
+ //
+ // OEM Information - Manufacturer Name
+ //
+ Store (ToString (SBMN), Index (PBIF, 12))
+
+ //
+ // Information ID 6 -
+ //
+ Store (6, HIID)
+ WAEC ()
+
+ //
+ // Model Number - Device Name
+ //
+ Store (ToString (SBDN), Index (PBIF, 9))
+
+ Return (PBIF)
+ }
+
+ Method (_BST, 0, Serialized)
+ {
+ // Update Battery First Used Date, if requested
+ If (BFUD)
+ {
+ // TODO: Handle First Used Date Request
+ //\BFUD()
+ }
+
+ //
+ // 0: BATTERY STATE
+ //
+ // bit 0 = discharging
+ // bit 1 = charging
+ // bit 2 = critical level
+ //
+
+ // Get battery state from EC
+ If (And (HB0S, 0x20))
+ {
+ Store (2, Local0)
+ }
+ Else
+ {
+ if (And (HB0S, 0x40))
+ {
+ Store (One, Local0)
+ }
+ Else
+ {
+ Store (Zero, Local0)
+ }
+ }
+
+ // Set critical flag if battery is empty
+ If (LEqual (And (HB0S, 0x0F), 0))
+ {
+ Or (Local0, 4, Local0)
+ }
+
+ Store (Zero, Local1)
+
+ // Check if AC is present
+ If (ACPW)
+ {
+ // Set only charging/discharging bits
+ And (Local0, 0x03, Local1)
+ }
+ Else
+ {
+ // Always discharging when on battery power
+ Store (One, Local1)
+ }
+
+ // Flag if the battery level is critical
+ And (Local0, 0x04, Local4)
+ Or (Local1, Local4, Local1)
+ Store (Local1, Index (PBST, 0))
+
+ //
+ // 1: BATTERY PRESENT RATE/CURRENT
+ //
+ Store (ECAC, Local1)
+ If (LGreaterEqual (Local1, 0x8000))
+ {
+ If (And (Local0, 1))
+ {
+ Subtract (0x10000, Local1, Local1)
+ }
+ Else
+ {
+ // Error
+ Store (Zero, Local1)
+ }
+ }
+ Else
+ {
+ If (LNot (AND (Local0, 2)))
+ {
+ // Battery is not charging
+ Store (Zero, Local1)
+ }
+ }
+
+ XOr (DerefOf (Index (PBIF, Zero)), One, Local6)
+
+ If (Local6)
+ {
+ Multiply (ECVO, Local1, Local1)
+ Divide (Local1, 1000, Local7, Local1)
+ }
+ Store (Local1, Index (PBST, One))
+
+ //
+ // 2: BATTERY REMAINING CAPACITY
+ //
+ // Get Power unit from the battery static information
+ // SMART battery : 1 - 10mWh : 0 - mAh
+ // ACPI spec : 0 - mWh : 1 - mAh
+ If (Local6)
+ {
+ Multiply (ECRC, 10, Local1)
+ }
+ Else
+ {
+ Store (ECRC, Local1)
+ }
+
+ If (LAnd (BFWK, LAnd (ACPW, LNot (Local0))))
+ {
+ // On AC power and battery is neither charging
+ // nor discharging. Linux expects a full battery
+ // to report same capacity as last full charge.
+ // https://bugzilla.kernel.org/show_bug.cgi?id=12632
+ // TODO: Is SBRS the "battery gas gauge"?
+ Store (SBRS, Local2)
+
+ // See if within ~3% of full
+ ShiftRight (Local2, 5, Local3)
+ If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+ LLess (Local1, Add (Local2, Local3))))
+ {
+ Store (Local2, Local1)
+ }
+ }
+ Store (Local1, Index (PBST, 2))
+
+ //
+ // 3: BATTERY PRESENT VOLTAGE
+ //
+ Store (ECVO, Index (PBST, 3))
+
+ Return (PBST)
+ }
+}
diff --git a/src/ec/quanta/it8518/acpi/ec.asl b/src/ec/quanta/it8518/acpi/ec.asl
new file mode 100644
index 0000000..e649f97
--- /dev/null
+++ b/src/ec/quanta/it8518/acpi/ec.asl
@@ -0,0 +1,666 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+ Name (_HID, EISAID ("PNP0C09"))
+ Name (_UID, 1)
+ Name (_GPE, Add(EC_SCI_GPI, 16)) // GPE for Runtime SCI
+
+ // EC RAM fields
+ OperationRegion(ERAM, EmbeddedControl, 0, 0xFF)
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0x00), // [Configuration Space 0]
+ , 1, // Reserved bit[0]
+ ENGA, 1, // Enable Global attention
+ ENHY, 1, // Enable Hotkey function
+ HFNE, 1, // Enable Sticky Fn Key
+ DSEM, 1, // Disable embedded NumPad Emulation
+ EN3R, 1, // Enable 3rd Host interface and TWR registers
+ , 1, // Reserved bit[6]
+ ENTM, 1, // Enable Thermal monitoring
+
+ Offset(0x01), // [Configuration Space 1]
+ ENBK, 1, // Enable Panel backlight on/ off synchronized with LID state
+ , 3, // Reserved bits[1:3]
+ WPSW, 1, // Warning if the power switch is depressed
+ , 2, // Reserved bits[5:6]
+ NTKY, 1, // do not ignore any key while Fn key is held down
+
+ Offset(0x02), // [Configuration Space 2]
+ , 5, // Reserved bits[0:4]
+ SNLC, 1, // Smart NumLock Enable. 1:Enable 0:Disable
+ , 1, // Reserved bit[6]
+ TNKB, 1, // ThinkVantage button function bit
+ // 0: Scan code (Enter key)
+ // 1: SMI/SCI attention
+
+ Offset(0x03), // [Configuration Space 3]
+ DSHP, 1, // Disable to synchronize headphone state with the speaker mute
+ IGPK, 1, // Ignore phantom keys
+ , 2, // Reserved bits[2:3]
+ CBAT, 1, // Change discharge/charge preference to discharge primary battery first and charge secondary battery first if possible
+ ADO0, 1, // Audio button behavior mode 0
+ ADO1, 1, // Audio button behavior mode 1
+ , 1, // Enable to use PMH fan functions to get the fan speed
+
+ Offset(0x04), // [Sound Mask 0]
+ , 1, // reserved
+ CLBA, 1, // critical low battery alarm
+ LWBA, 1, // low battery alarm (YELLOW -> RED)
+ SUBE, 1, // suspend beep
+ PUBE, 1, // vm_suspend beep
+ RSBE, 1, // resume beep
+ DCBE, 1, // DC in/out beep
+ PFBE, 1, // power off beep
+
+ Offset(0x05), // [Sound Mask 1]
+ HSPA, 1, // power off alarm
+ NHDD, 1, // no HDD alarm
+ DEAD, 1, // dead
+ B440, 1, // 440 hz beep
+ B315, 1, // 315 hz beep
+ T315, 1, // two 315 hz beep
+ R315, 1, // three 315 hz beep
+ BYAM, 1, // inhibit swap
+
+ Offset(0x06), // [Sound ID (Write only)]
+ HSUN, 8, // Sound ID (Write Only)
+
+ Offset(0x07), // [Sound Repeat Interval (unit time 125ms)]
+ HSRP, 8, // Sound Repeat Interval (Unit time : 125ms )
+
+ Offset(0x08), // [Sound Mask 2]
+ Offset(0x09), // [KBD ID]
+ Offset(0x0A), // [KMC command control]
+ // Offset 0xOB : reserved
+
+ Offset(0x0C), // [LED On/Off/ Blinking Control (Write only)]
+ HLCL, 4, // 0: power LED
+ // 1: battery status 0
+ // 2: battery status 1
+ // 3: additional Bay LED (Venice) / reserved (Toronto-4) / Slicer LED (Tokyo)
+ // 4-6: reserved
+ // 7: suspend LED
+ // 8: dock LED 1
+ // 9: dock LED 2
+ // 10-13: reserved
+ // 14: microphone mute
+ // 15: reserved
+ , 1, // Reserved bit[4]
+ , 1, // Blink gradually
+ BLIK, 1, // Blinking
+ TONF, 1, // Turn on/off
+
+ Offset(0x0D), // [Peripheral control 3]
+ UONE, 1, // Bit0 - Enable to supply power through USB in S3, S4 and S5 state.
+ , 1, // Reserved bit[1]
+ , 1, // set USB_AO_SEL0 signal in S3, S4, and S5 state
+ , 1, // set USB_AO_SEL1 signal in S3, S4, and S5 state
+ , 4, // Reserved bits[4:7]
+
+ Offset(0x0E), // [Peripheral Status 4]
+ HFNS, 2, // Bit[1, 0] : Fn Key Status
+ // [0, 0] ... Unlock
+ // [0, 1] ... Sticky
+ // [1, 0] ... Lock
+ // [1, 1] ... Reserved
+ GSER, 1, // G-Sensor Diag Error. 1:Error / 0: No error
+ PSCS, 1, // Inhibit charging
+ , 1, // External power saving mode
+ GSUD, 1, // G-Sensor under Diag. 1: Diag is running/0: Diag comp(not running)
+ GSID, 2, // Bit[7,6] G-Sensor type ID
+ // [0,0] ... None
+ // [0,1] ... STMicro
+ // [1,0] ... Memsic
+ // [1,1] ... ADI
+
+ Offset(0x0F), // [Peripheral status 5 (read only)]
+ , 4, // Reserved bits[0:3]
+ HDSU, 1, // HDD was detached in suspend (this bit is cleared when the system enters into suspend)
+ BYSU, 1, // Bay HDD was detached in suspend (this bit is cleared when the system enters into suspend)
+ , 1, // NumLock state of the embedded keyboard
+ TMOD, 1, // Tablet mode switch
+
+ Offset(0x10), // [Attention Mask (00-127)]
+ HAM0, 8, // 10 : Attention Mask (00-07)
+ HAM1, 8, // 11 : Attention Mask (08-0F)
+ HAM2, 8, // 12 : Attention Mask (10-17)
+ HAM3, 8, // 13 : Attention Mask (18-1F)
+ HAM4, 8, // 14 : Attention Mask (20-27)
+ HAM5, 8, // 15 : Attention Mask (28-2F)
+ HAM6, 8, // 16 : Attention Mask (30-37)
+ HAM7, 8, // 17 : Attention Mask (38-3F)
+ HAM8, 8, // 18 : Attention Mask (40-47)
+ HAM9, 8, // 19 : Attention Mask (48-4F)
+ HAMA, 8, // 1A : Attention Mask (50-57)
+ HAMB, 8, // 1B : Attention Mask (58-5F)
+ HAMC, 8, // 1C : Attention Mask (60-67)
+ HAMD, 8, // 1D : Attention Mask (68-6F)
+ HAME, 8, // 1E : Attention Mask (70-77)
+ HAMF, 8, // 1F : Attention Mask (78-7F)
+
+ // Offset 0x20 : reserved
+ Offset(0x21), // [Inhibit Charge timer byte High (00h)] (timer is kicked when high byte is written)
+
+ Offset(0x23), // [Misc. control]
+ // 01h Reset charge inhibit
+ // 02h Inhibit to charge
+ // 03h Reset external power saving mode
+ // 04h Set to external power saving mode
+ // 09h Emulate pressing an eject button of optical device in the bay
+ // 0Ah Reset thermal state to control the fan
+ // 10h Start gravity sensor diagnostic program
+
+ // Offset 24-26 : reserved
+ Offset(0x27), // [Passward Scan Code]
+ // Offset 28-29 : reserved
+
+ Offset(0x2A), // [Attention Request]
+ HATR, 8, // 2A : Attention request
+
+ Offset(0x2B), // [Trip point of battery capacity]
+ HT0H, 8, // 2B : MSB of Trip Point Capacity for Battery 0
+ HT0L, 8, // 2C : LSB of Trip Point Capacity for Battery 0
+ HT1H, 8, // 2D : MSB of Trip Point Capacity for Battery 1
+ HT1L, 8, // 2E : LSB of Trip Point Capacity for Battery 1
+
+ Offset(0x2F), // [Fan Speed Control]
+ HFSP, 8, // bit 2-0: speed (0: stop, 7:highest speed)
+ // bit 5-3: reserved (should be 0)
+ // bit 6: max. speed
+ // bit 7: Automatic mode (fan speed controlled by thermal level)
+
+ Offset(0x30), // [Audio mute control]
+ , 7, // Reserved bits[0:6]
+ SMUT, 1, // Mute
+
+ Offset(0x31), // [Peripheral Control 2]
+ FANS, 2, // bit 0,1 Fan selector
+ // 00: Fan 1, 01: Fan 2
+ HUWB, 1, // UWB on
+ ENS4, 1, // Reserved bit[3]
+ DSEX, 1, // Disable Express Card
+ AYID, 1, // Always-on Card identified
+ , 1, // Select USB to Always On card
+ , 1, // Assert the express card slot power control standby signal
+
+ Offset(0x32), // [EC Event Mask 0]
+ HWPM, 1, // PME : Not used. PME# is connected to GPE directly.
+ HWLB, 1, // Critical Low Bat
+ HWLO, 1, // Lid Open
+ , 1, // Eject button
+ HWFN, 1, // FN key
+ , 1, // Portfino wake up
+ HWRI, 1, // Ring Indicator (UART)
+ HWBU, 1, // Bay Unlock
+
+ Offset(0x33), // [EC Event Mask 1]
+
+ Offset(0x34), // [Peripheral status 2 (read only)]
+ , 1, // Reserved bit[0]
+ , 1, // Beep is being sounded now
+ , 1, // SMBus is busy
+ , 1, // Reserved bit[3]
+ , 1, // Fan exists
+ , 1, // Gravity sensors exist
+ , 1, // Reserved bit[6]
+ HPLO, 1, // Power consumption warning
+
+ Offset(0x35), // [Peripheral status 3 (Read only)]
+ , 1, // Input devices (keyboard and mouse) are locked by password
+ , 1, // Input devices are frozen (input from devices are inhibited)
+ , 1, // Fan power on Reset is done
+ , 1, // Attention is disabled temporarily
+ , 1, // Fan error
+ , 2, // Reserved bit[5:6]
+ , 1, // Thermal sensor error
+
+ Offset(0x36), // [Copy register of EC Event Status (0x32)]
+ Offset(0x37), // [Copy register of EC Event Status (0x33)]
+
+ Offset(0x38), // [Battery 0 status (read only)]
+ HB0S, 7, // bit 3-0 level
+ // F: Unknown
+ // 2-n: battery level
+ // 1: low level
+ // 0: (critical low battery, suspend/ hibernate)
+ // bit 4 error
+ // bit 5 charge
+ // bit 6 discharge
+ MBTS, 1, // bit 7 battery attached
+
+ Offset(0x39), // [Battery 1 status (read only)]
+ // bit definition is the same as offset(0x38)
+
+ Offset(0x3A), // [Peripheral control 0]
+ MUTE, 1, // Mute
+ I2CS, 1, // I2C select ( 0:Dock EEPROM etc, 1:Thermal sensor etc )(Tokyo-2)
+ PWRF, 1, // Power off
+ WANO, 1, // H/W Override bit
+ // (enable to control wireless devices even if the global WAN disable switch is ON)
+ DCBD, 1, // Bluetooth On
+ DCWL, 1, // Wireless Lan On
+ DCWW, 1, // Wireless Wan On
+ , 1, // 2nd Battery Inhibit (Tokyo)
+
+ Offset(0x3B), // [Peripheral control 1]
+ SPKM, 1, // Speaker Mute
+ KBLH, 1, // Keyboard Light
+ , 1, // Reserved bit[2]
+ BTDH, 1, // Bluetooth detach
+ USBN, 1, // USB On
+ , 1, // Inhibit communication with battery 0
+ , 1, // Inhibit communication with battery 1
+ S3FG, 1, // Reserved bit[7]
+
+ Offset(0x3C), // [Resume reason (Read only)]
+ Offset(0x3D), // [Password Control byte]
+ Offset(0x3E), // [Password data (8 byte)~ offset:45h]
+
+ Offset(0x46), // [sense status 0]
+ FNKY, 1, // Fn key
+ , 1, // Reserved bit[1]
+ HPLD, 1, // LID open
+ PROF, 1, // Power off
+ ACPW, 1, // External power (AC status)
+ , 2, // Reserved bits[5:6]
+ CALR, 1, // LP mode (power consumption alert)
+
+ Offset(0x47), // [sense status 1]
+ HPBU, 1, // Bay Unlock
+ DKEV, 1, // Dock event
+ BYNO, 1, // Bay is not Attached
+ HDIB, 1, // HDD in the bay
+ , 4, // Reserved bits[4:7]
+
+ Offset(0x48), // [sense status 2]
+ HPHI, 1, // Head Phone In
+ GSTS, 1, // Global Wan Enable Switch
+ , 2, // Reserved bits[2:3]
+ EXGC, 1, // External Graphic Chip
+ DOKI, 1, // Dock attached
+ HDDT, 1, // HDD detect
+ , 1, // Reserved bit[7]
+
+ Offset(0x49), // [sense status 3]
+ // Offset 0x4A : reserved
+
+ Offset(0x4C), // [MSB of Event Timer]
+ ETHB, 8, // bit[14:0]=timer counter, bit[15], 0:ms, 1:sec
+
+ Offset(0x4D), // [LSB of Event Timer]
+ ETLB, 8, //
+
+ Offset(0x4E), // [EC Event Status 0]
+ Offset(0x4F), // [EC Event Status 1]
+
+ Offset(0x50), // [SMB_PRTCL (protocol register)]
+ SMPR, 8, // 00: Controller Not In use
+ // 01: reserved
+ // 02: Write Quick command
+ // 03: Read Quick command
+ // 04: Send Quick command
+ // 05: Receive Byte
+ // 06: Write Byte
+ // 07: Read Byte
+ // 08: Write Word
+ // 09: Read Word
+ // 0A: Write block
+
+ Offset(0x51), // [SMB_STS (status register)]
+ SMST, 8, // bits[0:4] Status
+ // bit[5] Reserved
+ // bit[6] Alarm Received
+ // bit[7] Done
+
+ Offset(0x52), // [SMB_ADDR (address register)]
+ SMAD, 8, //
+
+ Offset(0x53), // [SMB_CMD (Command register)]
+ SMCM, 8, //
+
+ Offset(0x54), // [SMB_DATA (Data Register (32 bytes))~ offset:73h]
+ SMD0, 100, //
+
+ Offset(0x74), // [SMB_BCNT (Block count register)]
+ BCNT, 8, //
+
+ Offset(0x75), // [SMB_ALRM_ADDR (Alarm address register)]
+ SMAA, 8, //
+
+ Offset(0x76), // [SMB_ALRM_DATA (Alarm data register (2 bytes))]
+ BATD, 16, //
+
+ Offset(0x78), // [Temperature of thermal sensor 0 (centigrade)]
+ TMP0, 8, // 78 : Temperature of thermal sensor 0
+ TMP1, 8, // 79 : Temperature of thermal sensor 1
+ TMP2, 8, // 7A : Temperature of thermal sensor 2
+ TMP3, 8, // 7B : Temperature of thermal sensor 3
+ TMP4, 8, // 7C : Temperature of thermal sensor 4
+ TMP5, 8, // 7D : Temperature of thermal sensor 5
+ TMP6, 8, // 7E : Temperature of thermal sensor 6
+ TMP7, 8, // 7F : Temperature of thermal sensor 7
+
+ // Offset 79-7F : reserved
+ Offset(0x80), // [Attention control byte]
+
+ Offset(0x81), // [Battery information ID for 0xA0-0xAF]
+ HIID, 8, // (this byte is depend on the interface, 62&66 and 1600&1604)
+
+ Offset(0x82), // [Fn Dual function - make time out time (100ms unit)]
+
+ Offset(0x83), // [Fn Dual function ID]
+ HFNI, 8, // 0: none
+ // 1-3: Reserved
+ // 4: ACPI Power
+ // 5: ACPI Sleep
+ // 6: ACPI Wake
+ // 7: Left Ctrl key
+
+ Offset(0x84), // [Fan Speed]
+ , 16, //
+ // (I/F Offset 3Bh bit5 => 0:Main Fan , 1:Second Fan)
+
+ Offset(0x86), // [password 0 - 7 status]
+ Offset(0x87), // [password 8 - 15 status]
+ Offset(0x88), // [Thermal Status of Level 0 (low)]
+ Offset(0x89), // [Thermal Status of Level 1 (middle)]
+ Offset(0x8A), // [Thermal Status of Level 2 (middle high)]
+ Offset(0x8B), // [Thermal Status of Level 3 (high)]
+ // Offset 0x8C : reserved
+
+ Offset(0x8D), // [Interval of polling Always-on cards in half minute]
+ HDAA, 3, // Warning Delay Period
+ HDAB, 3, // Stolen Delay Period
+ HDAC, 2, // Sensitivity
+
+ Offset(0x8E), // [Key-number assigned to the ThinkVantage button]
+ Offset(0x8F), // [EC Internal Use for Fan Duty Table Creation]
+ Offset(0x90), // [EC internal use]
+ Offset(0xA0), // [Battery Information Area]~ offset:0AFh
+ Offset(0xB0), // [Battery 0 charge start capacity]
+ Offset(0xB1), // [Battery 0 charge stop capacity]
+ Offset(0xB2), // [Battery 1 charge start capacity]
+ Offset(0xB3), // [Battery 1 charge stop capacity]
+
+ Offset(0xB4), // [Battery 0 control]
+ // 01h Stop refreshing the battery
+ // 02h Refresh the battery
+ // 07h Set long life span mode
+ // 08h Set long run time mode
+
+ Offset(0xB5), // [Battery 1 control]
+ // Offset B6-C7 : reserved
+
+ Offset(0xC8), // [Adaptive Thermal Management (ATM)]
+ ATMX, 8, // bit 7-4 - Thermal Table & bit 3-0 - Fan Speed Table
+
+ Offset(0xC9), // [Wattage of AC/DC]
+ AC65, 8, //
+
+ Offset(0xCA), // Reserved - but should be 0
+
+ Offset(0xCB), // [ATM configuration]
+ BFUD, 1, // bit 0 - Battery FUD Flag
+ , 7, // bit 1~7 - Reserved
+
+ Offset(0xCC), //
+ PWMH, 8, // CC : AC Power Consumption (MSB)
+ PWML, 8, // CD : AC Power Consumption (LSB) - unit: 100mW
+
+ Offset(0xCE), // [Configuration Space 4]
+ , 2, // Windows key mode
+ , 2, // Application key mode
+ , 1, // Swap the Fn key and the left Ctrl key
+ , 3, // Reserved bits[5:7]
+
+ Offset(0xCF), // [Configuration Space 5]
+ HSID, 8, // Hand shaking byte of system information ID
+
+ Offset(0xD0), // [EC Type]
+ // D1-DF : reserved
+
+ Offset(0xE0), // @@ Mapping to old EC RAM for battery information
+ ECRC, 16, // BAT1 Sys command [0] RC
+ ECAC, 16, // BAT1 Sys command [0] AV_I
+ ECVO, 16, // BAT1 Sys command [0] Voltage
+
+ // E1-E7 : reserved
+ Offset(0xE8), // [Version 0]
+ Offset(0xE9), // [Version 1]
+ Offset(0xEA), // [Machine ID]
+ Offset(0xEB), // [Function Specification Minor Version]
+ Offset(0xEC), // [EC capability 0]
+ Offset(0xED), // [EC capability 1]
+
+ Offset(0xEE), // [Highest battery level]
+ MBTH, 4, // bit 3-0: battery 0 highest level
+ SBTH, 4, // bit 7-4: battery 1 highest level
+ // note: if highest level is 0 or 0xF, it means not defined
+ // (in this case, use default hightest level, it is 6)
+
+ Offset(0xEF), // [EC Function Specification Major Version]
+ Offset(0xF0), // [Build ID]~ offset:0F7h
+
+ Offset(0xF8), // [Build Date (F8: MSB, F9:LSB)]
+ , 4, // bit 3-0: day(1-31)
+ , 4, // bit 7-4: month(1-12)
+ , 8, // bit 15-8: year(2000 base)
+
+ Offset(0xFA), // [Build Time (in 2seconds)]
+ // ex: when index FAh=5Ah and index FBh=ADh, Build Time is 5AADh .. 12:53:46
+
+ Offset(0xFC), // [reserved]~ offset:0FFh
+ } // End of ERAM
+
+ //
+ // Battery Information ID : 00/10
+ //
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xA0),
+ SBRC, 16, // Remaining Capacity
+ SBFC, 16, // Fully Charged Capacity
+ SBAE, 16, // Average Time To Empty
+ SBRS, 16, // Relative State Of Charge
+ SBAC, 16, // Average Current
+ SBVO, 16, // Voltage
+ SBAF, 16, // Average Time To Full
+ SBBS, 16, // Battery State
+ }
+
+ //
+ // Battery Information ID : 01/11
+ //
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xA0),
+ // Battery Mode(w)
+ , 15,
+ SBCM, 1, // bit 15 - CAPACITY_MODE
+ // 0: Report in mA/mAh ; 1: Enabled
+ SBMD, 16, // Manufacture Data
+ SBCC, 16, // Cycle Count
+ }
+
+ //
+ // Battery Information ID : 02/12
+ //
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xA0),
+ SBDC, 16, // Design Capacity
+ SBDV, 16, // Design Voltage
+ SBOM, 16, // Optional Mfg Function 1
+ SBSI, 16, // Specification Info
+ SBDT, 16, // Manufacture Date
+ SBSN, 16, // Serial Number
+ }
+
+ //
+ // Battery Information ID : 04/14
+ //
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xA0),
+ SBCH, 32, // Device Checmistory (string)
+ }
+
+ //
+ // Battery Information ID : 05/15
+ //
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xA0),
+ SBMN, 128, // Manufacture Name (s)
+ }
+
+ //
+ // Battery Information ID : 06/16
+ //
+ Field (ERAM, ByteAcc, NoLock, Preserve)
+ {
+ Offset(0xA0),
+ SBDN, 128, // Device Name (s)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+ Return (ECMD)
+ }
+
+ Method (_REG, 2, NotSerialized)
+ {
+ // Initialize AC power state
+ Store (ACPW, \PWRS)
+
+ // Initialize LID switch state
+ Store (NOT(HPLD), \LIDS)
+
+ // Enable OS control of fan speed
+ // TODO Store (One, FCOS)
+
+ // Force a read of CPU temperature
+ // TODO Which temperature corresponds to the CPU?
+ Store (TMP0, Local0)
+ }
+
+/* Attention Codes
+ * 00h No Event
+ * 01h-0Fh Reserved for ACPI Events
+ * 10h-1Fh Hotkey Events
+ * 22h Critical Low Battery
+ * 23h Battery Empty
+ * 24h Trip Point Capacity Event for Battery 0
+ * 26h AC Adapter Attached
+ * 27h AC Adapter Detached
+ * 28h Power Off Switch Pressed
+ * 29h Power Off Switch Released
+ * 2Ah LID Open
+ * 2Bh LID Close
+ * 3Eh PME Event
+ * 40h Thermal Event
+ * 41h Global Wireless Enable Switch
+ * 43h Mute State Change
+ * 4Ah Battery 0 Attach/Detach
+ * 4Bh Battery 0 State Change
+ * 66h Mute Button
+ */
+
+ // Battery at critical low state
+ Method (_Q22)
+ {
+ If (MBTS)
+ {
+ Notify (BATX, 0x80)
+ }
+ }
+
+ // AC Power Connected
+ Method (_Q26, 0, NotSerialized)
+ {
+ Store (One, \PWRS)
+ Notify (AC, 0x80)
+ Notify (BATX, 0x80)
+ \PNOT ()
+ }
+
+ // AC Power Removed
+ Method (_Q27, 0, NotSerialized)
+ {
+ Store (Zero, \PWRS)
+ Notify (AC, 0x80)
+ \PNOT ()
+ }
+
+ // LID Open
+ Method (_Q2A)
+ {
+ Store (One, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ // LID Close (Suspend Trigger)
+ Method (_Q2B)
+ {
+ Store (Zero, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ // Battery Attach/Detach Event
+ Method (_Q4A)
+ {
+ Notify (BATX, 0x80)
+ Notify (BATX, 0x81)
+ \PNOT ()
+ }
+
+ // Battery State Change Event
+ Method (_Q4B)
+ {
+ Notify (BATX, 0x80)
+ \PNOT ()
+ }
+
+ // Global Wireless Disable/Enable Event
+ Method (_Q41, 0, NotSerialized)
+ {
+ IF (DCWL) //if Wlan exist
+ {
+ //TODO Store (WLAT, LANE)
+ }
+ }
+
+ #include "ac.asl"
+ #include "battery.asl"
+ // TODO #include "fan.asl"
+}
diff --git a/src/ec/quanta/it8518/acpi/superio.asl b/src/ec/quanta/it8518/acpi/superio.asl
new file mode 100644
index 0000000..e580989
--- /dev/null
+++ b/src/ec/quanta/it8518/acpi/superio.asl
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO)
+{
+ Name (_UID, 0)
+ Name (_ADR, 0)
+
+#ifdef SIO_EC_ENABLE_PS2K
+ Device (PS2K) // Keyboard
+ {
+ Name (_UID, 0)
+ Name (_ADR, 0)
+ Name (_HID, EISAID("PNP0303"))
+ Name (_CID, EISAID("PNP030B"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+#ifdef SIO_ENABLE_PS2M
+ Device (PS2M) // Mouse
+ {
+ Name (_HID, EISAID("PNP0F13"))
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Name (_CRS, ResourceTemplate()
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ })
+
+ Name (_PRS, ResourceTemplate()
+ {
+ StartDependentFn (0, 0)
+ {
+ FixedIO (0x60, 0x01)
+ FixedIO (0x64, 0x01)
+ IRQNoFlags () {12}
+ }
+ EndDependentFn ()
+ })
+ }
+#endif
+
+}
diff --git a/src/mainboard/getac/p470/chip.h b/src/ec/quanta/it8518/chip.h
similarity index 66%
copy from src/mainboard/getac/p470/chip.h
copy to src/ec/quanta/it8518/chip.h
index b75c381..592b5e5 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/ec/quanta/it8518/chip.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,5 +19,17 @@
* MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+#ifndef _EC_QUANTA_IT8518_CHIP_H
+#define _EC_QUANTA_IT8518_CHIP_H
+
+#include <device/device.h>
+#include <pc80/keyboard.h>
+
+struct chip_operations;
+extern struct chip_operations ec_quanta_it8518_ops;
+
+struct ec_quanta_it8518_config {
+ struct pc_keyboard keyboard;
+};
+
+#endif /* _EC_QUANTA_IT8518_CHIP_H */
diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c
new file mode 100644
index 0000000..66077a0
--- /dev/null
+++ b/src/ec/quanta/it8518/ec.c
@@ -0,0 +1,189 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __PRE_RAM__
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <stdlib.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "ec.h"
+#include "chip.h"
+
+/* helper functions from drivers/pc80/keyboard.c */
+static int input_buffer_empty(u16 status_reg)
+{
+ u32 timeout;
+ for(timeout = KBC_TIMEOUT_IN_MS; timeout && (inb(status_reg) & KBD_IBF);
+ timeout--) {
+ mdelay(1);
+ }
+
+ if (!timeout) {
+ printk(BIOS_WARNING, "EC-IT8518 Unexpected input buffer full\n");
+ }
+ return !!timeout;
+}
+
+
+static int output_buffer_full(u16 status_reg)
+{
+ u32 timeout;
+ for(timeout = KBC_TIMEOUT_IN_MS; timeout && ((inb(status_reg)
+ & KBD_OBF) == 0); timeout--) {
+ mdelay(1);
+ }
+
+ if (!timeout) {
+ printk(BIOS_INFO, "EC-IT8518 output buffer result timeout\n");
+ }
+ return !!timeout;
+}
+
+
+
+/* The IT8518 60/64 EC registers are the same command/status IB/OB KBC pair.
+ * Check status from 64 port before each command.
+ *
+ * Ex. Get panel ID command C43/D77
+ * Check IBF empty. Then Write 0x43(CMD) to 0x64 Port
+ * Check IBF empty. Then Write 0x77(DATA) to 0x60 Port
+ * Check OBF set. Then Get Data(0x03:panel ID) from 0x60
+ * Different commands return may or may not respond and may have multiple
+ * bytes. Keep it simple for nor
+ */
+
+u8 ec_kbc_read_ob(void)
+{
+ if (!output_buffer_full(KBD_STATUS)) return 0;
+ return inb(KBD_DATA);
+}
+
+void ec_kbc_write_cmd(u8 cmd)
+{
+ if (!input_buffer_empty(KBD_STATUS)) return;
+ outb(cmd, KBD_COMMAND);
+}
+
+void ec_kbc_write_ib(u8 data)
+{
+ if (!input_buffer_empty(KBD_STATUS)) return;
+ outb(data, KBD_DATA);
+}
+
+
+/*
+ * These functions are for accessing the IT8518 device RAM space
+ */
+
+u8 ec_read_ob(void)
+{
+ if (!output_buffer_full(EC_SC)) return 0;
+ return inb(EC_DATA);
+}
+
+void ec_write_cmd(u8 cmd)
+{
+ if (!input_buffer_empty(EC_SC)) return;
+ outb(cmd, EC_SC);
+}
+
+void ec_write_ib(u8 data)
+{
+ if (!input_buffer_empty(EC_SC)) return;
+ outb(data, EC_DATA);
+}
+
+u8 ec_read(u16 addr)
+{
+ ec_write_cmd(RD_EC);
+ ec_write_ib(addr);
+ return ec_read_ob();
+}
+
+void ec_write(u16 addr, u8 data)
+{
+ ec_write_cmd(WR_EC);
+ ec_write_ib(addr);
+ ec_write_ib(data);
+}
+
+u8 ec_it8518_get_event(void)
+{
+ u8 cmd = 0;
+ u8 status = inb(EC_SC);
+ if ((status & SMI_EVT) || (status & SCI_EVT))
+ {
+ ec_write_cmd(QR_EC);
+ cmd = ec_read_ob();
+ }
+ return cmd;
+}
+
+#ifndef __SMM__
+static void it8518_init(device_t dev)
+{
+ struct ec_quanta_it8518_config *conf = dev->chip_info;
+
+
+ if (!dev->enabled)
+ return;
+
+ printk(BIOS_DEBUG, "Quanta IT8518: Initializing keyboard.\n");
+ pc_keyboard_init(&conf->keyboard);
+}
+
+
+static void it8518_read_resources(device_t dev)
+{
+ /* This function avoids an error on serial console. */
+}
+
+
+static void it8518_enable_resources(device_t dev)
+{
+ /* This function avoids an error on serial console. */
+}
+
+static struct device_operations ops = {
+ .init = it8518_init,
+ .read_resources = it8518_read_resources,
+ .enable_resources = it8518_enable_resources
+};
+
+static struct pnp_info pnp_dev_info[] = {
+ { &ops, 0, 0, { 0, 0 }, }
+};
+
+static void enable_dev(device_t dev)
+{
+ pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info),
+ pnp_dev_info);
+}
+
+struct chip_operations ec_quanta_it8518_ops = {
+ CHIP_NAME("QUANTA IT8518 EC")
+ .enable_dev = enable_dev
+};
+#endif /* ! __SMM__ */
+#endif /* ! __PRE_RAM__ */
diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h
new file mode 100644
index 0000000..f6762fc
--- /dev/null
+++ b/src/ec/quanta/it8518/ec.h
@@ -0,0 +1,84 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * EC communication interface for QUANTA IT8518 Embedded Controller.
+ */
+
+#ifndef _EC_QUANTA_IT8518_EC_H
+#define _EC_QUANTA_IT8518_EC_H
+
+#define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */
+#define EC_IO_HIGH EC_IO + 1
+#define EC_IO_LOW EC_IO + 2
+#define EC_IO_DATA EC_IO + 3
+
+/* Wait 400ms for keyboard controller answers */
+#define KBC_TIMEOUT_IN_MS 400
+
+// 60h/64h Command Interface
+#define KBD_DATA 0x60
+#define KBD_COMMAND 0x64
+#define KBD_STATUS 0x64
+#define KBD_IBF (1 << 1) // 1: input buffer full (data ready for ec)
+#define KBD_OBF (1 << 0) // 1: output buffer full (data ready for host)
+
+#define EC_KBD_CMD_UNMUTE 0xE8
+#define EC_KBD_CMD_MUTE 0xE9
+
+u8 ec_kbc_read_ob(void);
+void ec_kbc_write_cmd(u8 cmd);
+void ec_kbc_write_ib(u8 data);
+
+// 62h/66h Command Interface
+#define EC_DATA 0x62
+#define EC_SC 0x66 // Status & Control Register
+#define SMI_EVT (1 << 6) // 1: SMI event was triggered
+#define SCI_EVT (1 << 5) // 1: SCI event was triggered
+
+// EC Commands (defined in ec_function_spec v3.12)
+#define RD_EC 0x80
+#define WR_EC 0x81
+#define QR_EC 0x84
+
+#define EC_CMD_EXIT_BOOT_BLOCK 0x85
+#define EC_CMD_NOTIFY_ACPI_ENTER 0x86
+#define EC_CMD_NOTIFY_ACPI_EXIT 0x87
+#define EC_CMD_WARM_RESET 0x8C
+
+#define EC_FW_VER 0xE8 // 2 Bytes
+#define EC_IF_MIN_VER 0xEB
+#define EC_STATUS_REG 0xEC
+#define EC_IF_MAJ_VER 0xEF
+
+// EC 0.83b added status bits:
+// BIT0=EC in RO mode
+// BIT1=Recovery Key Sequence Detected
+#define EC_IN_RO_MODE 0x1
+#define EC_IN_RECOVERY_MODE 0x3
+
+u8 ec_read_ob(void);
+void ec_write_cmd(u8 cmd);
+void ec_write_ib(u8 data);
+
+u8 ec_read(u16 addr);
+void ec_write(u16 addr, u8 data);
+u8 ec_it8518_get_event(void);
+
+#endif /* _EC_QUANTA_IT8518_EC_H */
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index 1483177..b33e932 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -57,5 +57,6 @@
int cbfs_execute_stage(const char *name);
void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest);
int run_address(void *f);
+int selfboot(struct lb_memory *mem, struct cbfs_payload *payload);
#endif
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index a245232..21efe77 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -44,6 +44,7 @@
#define CBMEM_ID_FREESPACE 0x46524545
#define CBMEM_ID_GDT 0x4c474454
#define CBMEM_ID_ACPI 0x41435049
+#define CBMEM_ID_ACPI_GNVS 0x474e5653
#define CBMEM_ID_CBTABLE 0x43425442
#define CBMEM_ID_PIRQ 0x49525154
#define CBMEM_ID_MPTABLE 0x534d5054
@@ -53,6 +54,7 @@
#define CBMEM_ID_TIMESTAMP 0x54494d45
#define CBMEM_ID_MRCDATA 0x4d524344
#define CBMEM_ID_CONSOLE 0x434f4e53
+#define CBMEM_ID_ELOG 0x454c4f47
#define CBMEM_ID_NONE 0x00000000
#ifndef __ASSEMBLER__
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 56e202d..fa830ae 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -38,10 +38,6 @@
#endif
#ifndef __PRE_RAM__
-void console_tx_byte(unsigned char byte);
-void console_tx_flush(void);
-unsigned char console_rx_byte(void);
-int console_tst_byte(void);
struct console_driver {
void (*init)(void);
void (*tx_byte)(unsigned char byte);
@@ -68,7 +64,13 @@
#ifndef __ROMCC__
void console_init(void);
+void console_tx_byte(unsigned char byte);
+void console_tx_flush(void);
+unsigned char console_rx_byte(void);
+int console_tst_byte(void);
void post_code(u8 value);
+/* this function is weak and can be overridden by a mainboard function. */
+void mainboard_post(u8 value);
void __attribute__ ((noreturn)) die(const char *msg);
int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index 1d12e5a..8f18cd7 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -83,6 +83,14 @@
#define POST_ENTRY_C_START 0x13
/**
+ * \brief Pre call to hardwaremain()
+ *
+ * POSTed right before hardwaremain is called from c_start.S
+ * TODO: Change this code to a lower number
+ */
+#define POST_PRE_HARDWAREMAIN 0x79
+
+/**
* \brief Entry into coreboot in hardwaremain (RAM)
*
* This is the first call in hardwaremain.c. If this code is POSTed, then
@@ -134,6 +142,13 @@
#define POST_DEVICES_ENABLED 0x89
/**
+ * \brief Devices have been initialized
+ *
+ * Devices have been initialized.
+ */
+#define POST_DEVICES_INITIALIZED 0x8a
+
+/**
* \brief Entry into elf boot
*
* This POST code is called right before invoking jmp_to_elf_entry()
@@ -159,12 +174,18 @@
#define POST_DEAD_CODE 0xee
/**
- * \brief Pre call to hardwaremain()
+ * \brief Final code before OS resumes
*
- * POSTed right before hardwaremain is called from c_start.S
- * TODO: Change this code to a lower number
+ * Called right before jumping to the OS resume vector.
*/
-#define POST_PRE_HARDWAREMAIN 0xfe
+#define POST_OS_RESUME 0xfd
+
+/**
+ * \brief Final code before OS boots
+ *
+ * This may not be called depending on the payload used.
+ */
+#define POST_OS_BOOT 0xfe
/**
* \brief Elfload fail or die() called
diff --git a/src/include/cpu/cpu.h b/src/include/cpu/cpu.h
index c2113c1..c0be802 100644
--- a/src/include/cpu/cpu.h
+++ b/src/include/cpu/cpu.h
@@ -4,10 +4,10 @@
#include <arch/cpu.h>
#if !defined(__ROMCC__)
-void cpu_initialize(void);
+void cpu_initialize(unsigned int cpu_index);
struct bus;
void initialize_cpus(struct bus *cpu_bus);
-void secondary_cpu_init(void);
+void secondary_cpu_init(unsigned int cpu_index)__attribute__((regparm(0)));
#if !CONFIG_WAIT_BEFORE_CPUS_INIT
#define cpus_ready_for_init() do {} while(0)
diff --git a/src/include/cpu/intel/microcode.h b/src/include/cpu/intel/microcode.h
index 4139c01..289e919 100644
--- a/src/include/cpu/intel/microcode.h
+++ b/src/include/cpu/intel/microcode.h
@@ -1,6 +1,7 @@
/*
* This file is part of the coreboot project.
*
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
* Copyright (C) 2000 Ronald G. Minnich
*
* This program is free software; you can redistribute it and/or modify
@@ -16,7 +17,15 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef __CPU__INTEL__MICROCODE__
+#define __CPU__INTEL__MICROCODE__
-#if !defined(__ROMCC__)
+#ifndef __PRE_RAM__
+#if CONFIG_MICROCODE_IN_CBFS
+void intel_update_microcode_from_cbfs(void);
+#else
void intel_update_microcode(const void *microcode_updates);
#endif
+#endif
+
+#endif
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index 89257e5..b52a315 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -201,6 +201,96 @@
} __attribute__((packed)) em64t_smm_state_save_area_t;
+/* Intel Revision 30101 SMM State-Save Area
+ * Used in SandyBridge/IvyBridge architecture
+ * starts @ 0x7d00
+ */
+typedef struct {
+ u8 reserved0[208];
+
+ u32 gdtr_upper_base;
+ u32 ldtr_upper_base;
+ u32 idtr_upper_base;
+
+ u32 io_cf8;
+
+ u64 io_rdi;
+ u64 io_rip;
+ u64 io_rcx;
+ u64 io_rsi;
+
+ u8 reserved1[52];
+ u32 shutdown_auto_restart;
+ u8 reserved2[8];
+ u32 cr4;
+
+ u8 reserved3[72];
+
+ u32 gdtr_base;
+ u8 reserved4[4];
+ u32 idtr_base;
+ u8 reserved5[4];
+ u32 ldtr_base;
+
+ u8 reserved6[68];
+ u32 cs_base;
+ u8 reserved7[4];
+ u32 iedbase;
+
+ u8 reserved8[8];
+
+ u32 smbase;
+ u32 smm_revision;
+
+ u16 io_restart;
+ u16 autohalt_restart;
+
+ u8 reserved9[24];
+
+ u64 r15;
+ u64 r14;
+ u64 r13;
+ u64 r12;
+ u64 r11;
+ u64 r10;
+ u64 r9;
+ u64 r8;
+
+ u64 rax;
+ u64 rcx;
+ u64 rdx;
+ u64 rbx;
+
+ u64 rsp;
+ u64 rbp;
+ u64 rsi;
+ u64 rdi;
+
+
+ u64 io_mem_addr;
+ u32 io_misc_info;
+
+ u32 es_sel;
+ u32 cs_sel;
+ u32 ss_sel;
+ u32 ds_sel;
+ u32 fs_sel;
+ u32 gs_sel;
+
+ u32 ldtr_sel;
+ u32 tr_sel;
+
+ u64 dr7;
+ u64 dr6;
+ u64 rip;
+ u64 efer;
+ u64 rflags;
+
+ u64 cr3;
+ u64 cr0;
+} __attribute__((packed)) em64t101_smm_state_save_area_t;
+
+
/* Legacy x86 SMM State-Save Area
* starts @ 0x7e00
*/
@@ -243,6 +333,7 @@
typedef enum {
AMD64,
EM64T,
+ EM64T101,
LEGACY
} save_state_type_t;
@@ -252,6 +343,7 @@
union {
amd64_smm_state_save_area_t *amd64_state_save;
em64t_smm_state_save_area_t *em64t_state_save;
+ em64t101_smm_state_save_area_t *em64t101_state_save;
legacy_smm_state_save_area_t *legacy_state_save;
};
} smm_state_save_area_t;
@@ -284,6 +376,15 @@
#if !CONFIG_SMM_TSEG
void smi_release_lock(void);
+#define tseg_relocate(ptr)
+#else
+/* Return address of TSEG base */
+u32 smi_get_tseg_base(void);
+/* Adjust pointer with TSEG base */
+void tseg_relocate(void **ptr);
#endif
+/* Get PMBASE address */
+u16 smm_get_pmbase(void);
+
#endif
diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index c573627..615aa1c 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -10,10 +10,16 @@
static inline tsc_t rdtsc(void)
{
tsc_t res;
- __asm__ __volatile__ (
+ asm volatile (
+#if CONFIG_TSC_SYNC_MFENCE
+ "mfence\n"
+#endif
+#if CONFIG_TSC_SYNC_LFENCE
+ "lfence\n"
+#endif
"rdtsc"
: "=a" (res.lo), "=d"(res.hi) /* outputs */
- );
+ );
return res;
}
@@ -22,7 +28,16 @@
static inline unsigned long long rdtscll(void)
{
unsigned long long val;
- asm volatile ("rdtsc" : "=A" (val));
+ asm volatile (
+#if CONFIG_TSC_SYNC_MFENCE
+ "mfence\n"
+#endif
+#if CONFIG_TSC_SYNC_LFENCE
+ "lfence\n"
+#endif
+ "rdtsc"
+ : "=A" (val)
+ );
return val;
}
#endif
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 0aea1d6..8441745 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -2,11 +2,12 @@
#define DEVICE_H
#include <stdint.h>
+#include <stddef.h>
#include <device/resource.h>
#include <device/path.h>
-
struct device;
+#ifndef __PRE_RAM__
typedef struct device * device_t;
struct pci_operations;
struct pci_bus_operations;
@@ -41,12 +42,14 @@
const struct smbus_bus_operations *ops_smbus_bus;
const struct pci_bus_operations *ops_pci_bus;
};
+#endif
struct bus {
- device_t dev; /* This bridge device */
- device_t children; /* devices behind this bridge */
- struct bus *next; /* The next bridge on this device */
+
+ ROMSTAGE_CONST struct device * dev; /* This bridge device */
+ ROMSTAGE_CONST struct device * children; /* devices behind this bridge */
+ ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */
unsigned bridge_ctrl; /* Bridge control register */
unsigned char link_num; /* The index of this link */
uint16_t secondary; /* secondary bus number */
@@ -62,10 +65,12 @@
*/
struct device {
- struct bus * bus; /* bus this device is on, for bridge
+ ROMSTAGE_CONST struct bus * bus; /* bus this device is on, for bridge
* devices, it is the up stream bus */
- device_t sibling; /* next device on this bus */
- device_t next; /* chain of all devices */
+
+ ROMSTAGE_CONST struct device * sibling; /* next device on this bus */
+
+ ROMSTAGE_CONST struct device * next; /* chain of all devices */
struct device_path path;
unsigned vendor;
@@ -81,23 +86,26 @@
u8 command;
/* Base registers for this device. I/O, MEM and Expansion ROM */
- struct resource *resource_list;
+ ROMSTAGE_CONST struct resource *resource_list;
/* links are (downstream) buses attached to the device, usually a leaf
* device with no children has 0 buses attached and a bridge has 1 bus
*/
- struct bus *link_list;
+ ROMSTAGE_CONST struct bus *link_list;
struct device_operations *ops;
+#ifndef __PRE_RAM__
const struct chip_operations *chip_ops;
- void *chip_info;
+#endif
+ ROMSTAGE_CONST void *chip_info;
};
/**
* This is the root of the device tree. The device tree is defined in the
* static.c file and is generated by the config tool at compile time.
*/
-extern struct device dev_root;
+extern ROMSTAGE_CONST struct device dev_root;
+#ifndef __PRE_RAM__
extern struct device *all_devices; /* list of all devices */
extern struct resource *free_resources;
@@ -161,5 +169,10 @@
unsigned long basek, unsigned long sizek);
void tolm_test(void *gp, struct device *dev, struct resource *new);
u32 find_pci_tolm(struct bus *bus);
-
+#else
+ROMSTAGE_CONST struct device * dev_find_slot (unsigned int bus,
+ unsigned int devfn);
+ROMSTAGE_CONST struct device * dev_find_slot_on_smbus (unsigned int bus,
+ unsigned int addr);
+#endif
#endif /* DEVICE_H */
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index e864d6d..a215a2a 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -16,9 +16,11 @@
#define PCI_H
#include <stdint.h>
+#include <stddef.h>
#include <device/pci_def.h>
#include <device/resource.h>
#include <device/device.h>
+#ifndef __PRE_RAM__
#include <device/pci_ops.h>
#include <device/pci_rom.h>
@@ -100,11 +102,12 @@
bops = bus->dev->ops->ops_pci_bus;
}
if (!bops)
- bops = pci_remember_direct();
+ bops = pci_config_default();
return bops;
}
unsigned mainboard_pci_subsystem_vendor_id(struct device *dev);
unsigned mainboard_pci_subsystem_device_id(struct device *dev);
+#endif
#endif /* PCI_H */
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 1765293..a7d1074 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2504,6 +2504,8 @@
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN 0x1c41
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_TGP_LPC 0x27bc
/* Intel 82801E (C-ICH) */
diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h
index e5e54b6..2efbf9d 100644
--- a/src/include/device/pci_ops.h
+++ b/src/include/device/pci_ops.h
@@ -21,7 +21,4 @@
void pci_mmio_write_config32(device_t dev, unsigned int where, u32 val);
#endif
-/* This function lives in pci_ops_auto.c */
-const struct pci_bus_operations *pci_remember_direct(void);
-
#endif /* PCI_OPS_H */
diff --git a/src/include/device/resource.h b/src/include/device/resource.h
index ef95b53..36b687d 100644
--- a/src/include/device/resource.h
+++ b/src/include/device/resource.h
@@ -2,6 +2,7 @@
#define DEVICE_RESOURCE_H
#include <stdint.h>
+#include <stddef.h>
#define IORESOURCE_BITS 0x000000ff /* Bus-specific bits */
@@ -69,7 +70,7 @@
resource_t base; /* Base address of the resource */
resource_t size; /* Size of the resource */
resource_t limit; /* Largest valid value base + size -1 */
- struct resource* next; /* Next resource in the list */
+ ROMSTAGE_CONST struct resource* next; /* Next resource in the list */
unsigned long flags; /* Descriptions of the kind of resource */
unsigned long index; /* Bus specific per device resource id */
unsigned char align; /* Required alignment (log 2) of the resource */
diff --git a/src/include/elog.h b/src/include/elog.h
new file mode 100644
index 0000000..a5b5a77a
--- /dev/null
+++ b/src/include/elog.h
@@ -0,0 +1,163 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef ELOG_H_
+#define ELOG_H_
+
+#if CONFIG_ELOG
+
+/* SMI command code for GSMI event logging */
+#define ELOG_GSMI_APM_CNT 0xEF
+
+#define MAX_EVENT_SIZE 0x7F
+
+/* End of log */
+#define ELOG_TYPE_EOL 0xFF
+
+/*
+ * Standard SMBIOS event log types below 0x80
+ */
+#define ELOG_TYPE_UNDEFINED_EVENT 0x00
+#define ELOG_TYPE_SINGLE_BIT_ECC_MEM_ERR 0x01
+#define ELOG_TYPE_MULTI_BIT_ECC_MEM_ERR 0x02
+#define ELOG_TYPE_MEM_PARITY_ERR 0x03
+#define ELOG_TYPE_BUS_TIMEOUT 0x04
+#define ELOG_TYPE_IO_CHECK 0x05
+#define ELOG_TYPE_SW_NMI 0x06
+#define ELOG_TYPE_POST_MEM_RESIZE 0x07
+#define ELOG_TYPE_POST_ERR 0x08
+#define ELOG_TYPE_PCI_PERR 0x09
+#define ELOG_TYPE_PCI_SERR 0x0A
+#define ELOG_TYPE_CPU_FAIL 0x0B
+#define ELOG_TYPE_EISA_TIMEOUT 0x0C
+#define ELOG_TYPE_CORRECTABLE_MEMLOG_DIS 0x0D
+#define ELOG_TYPE_LOG_DISABLED 0x0E
+#define ELOG_TYPE_UNDEFINED_EVENT2 0x0F
+#define ELOG_TYPE_SYS_LIMIT_EXCEED 0x10
+#define ELOG_TYPE_ASYNC_HW_TIMER_EXPIRED 0x11
+#define ELOG_TYPE_SYS_CONFIG_INFO 0x12
+#define ELOG_TYPE_HDD_INFO 0x13
+#define ELOG_TYPE_SYS_RECONFIG 0x14
+#define ELOG_TYPE_CPU_ERROR 0x15
+#define ELOG_TYPE_LOG_CLEAR 0x16
+#define ELOG_TYPE_BOOT 0x17
+
+/*
+ * Extended defined OEM event types start at 0x80
+ */
+
+/* OS/kernel events */
+#define ELOG_TYPE_OS_EVENT 0x81
+
+/* Last event from coreboot */
+#define ELOG_TYPE_OS_BOOT 0x90
+
+/* Embedded controller event */
+#define ELOG_TYPE_EC_EVENT 0x91
+#define EC_EVENT_LID_CLOSED 0x01
+#define EC_EVENT_LID_OPEN 0x02
+#define EC_EVENT_POWER_BUTTON 0x03
+#define EC_EVENT_AC_CONNECTED 0x04
+#define EC_EVENT_AC_DISCONNECTED 0x05
+#define EC_EVENT_BATTERY_LOW 0x06
+#define EC_EVENT_BATTERY_CRITICAL 0x07
+#define EC_EVENT_BATTERY 0x08
+#define EC_EVENT_THERMAL_THRESHOLD 0x09
+#define EC_EVENT_THERMAL_OVERLOAD 0x0a
+#define EC_EVENT_THERMAL 0x0b
+#define EC_EVENT_USB_CHARGER 0x0c
+#define EC_EVENT_KEY_PRESSED 0x0d
+#define EC_EVENT_INTERFACE_READY 0x0e
+#define EC_EVENT_KEYBOARD_RECOVERY 0x0f
+#define EC_EVENT_THERMAL_SHUTDOWN 0x10
+#define EC_EVENT_BATTERY_SHUTDOWN 0x11
+
+/* Power */
+#define ELOG_TYPE_POWER_FAIL 0x92
+#define ELOG_TYPE_SUS_POWER_FAIL 0x93
+#define ELOG_TYPE_PWROK_FAIL 0x94
+#define ELOG_TYPE_SYS_PWROK_FAIL 0x95
+#define ELOG_TYPE_POWER_ON 0x96
+#define ELOG_TYPE_POWER_BUTTON 0x97
+#define ELOG_TYPE_POWER_BUTTON_OVERRIDE 0x98
+
+/* Reset */
+#define ELOG_TYPE_RESET_BUTTON 0x99
+#define ELOG_TYPE_SYSTEM_RESET 0x9a
+#define ELOG_TYPE_RTC_RESET 0x9b
+#define ELOG_TYPE_TCO_RESET 0x9c
+
+/* Sleep/Wake */
+#define ELOG_TYPE_ACPI_ENTER 0x9d
+#define ELOG_TYPE_ACPI_WAKE 0x9e
+#define ELOG_TYPE_WAKE_SOURCE 0x9f
+#define ELOG_WAKE_SOURCE_PCIE 0x00
+#define ELOG_WAKE_SOURCE_PME 0x01
+#define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02
+#define ELOG_WAKE_SOURCE_RTC 0x03
+#define ELOG_WAKE_SOURCE_GPIO 0x04
+#define ELOG_WAKE_SOURCE_SMBUS 0x05
+struct elog_event_data_wake {
+ u8 source;
+ u32 instance;
+} __attribute__ ((packed));
+
+/* Chrome OS related events */
+#define ELOG_TYPE_CROS_DEVELOPER_MODE 0xa0
+#define ELOG_TYPE_CROS_RECOVERY_MODE 0xa1
+#define ELOG_CROS_RECOVERY_MODE_BUTTON 0x02
+
+/* Management Engine Events */
+#define ELOG_TYPE_MANAGEMENT_ENGINE 0xa2
+#define ELOG_TYPE_MANAGEMENT_ENGINE_EXT 0xa4
+struct elog_event_data_me_extended {
+ u8 current_working_state;
+ u8 operation_state;
+ u8 operation_mode;
+ u8 error_code;
+ u8 progress_code;
+ u8 current_pmevent;
+ u8 current_state;
+} __attribute__ ((packed));
+
+/* Last post code from previous boot */
+#define ELOG_TYPE_LAST_POST_CODE 0xa3
+
+extern int elog_init(void);
+extern int elog_clear(void);
+extern void elog_add_event_raw(u8 event_type, void *data, u8 data_size);
+extern void elog_add_event(u8 event_type);
+extern void elog_add_event_byte(u8 event_type, u8 data);
+extern void elog_add_event_word(u8 event_type, u16 data);
+extern void elog_add_event_dword(u8 event_type, u32 data);
+extern void elog_add_event_wake(u8 source, u32 instance);
+extern int elog_smbios_write_type15(unsigned long *current, int handle);
+
+#if CONFIG_ELOG_GSMI
+extern u32 gsmi_exec(u8 command, u32 *param);
+#endif
+
+#if CONFIG_ELOG_BOOT_COUNT
+u32 boot_count_read(void);
+u32 boot_count_increment(void);
+#endif
+
+#endif /* !CONFIG_ELOG */
+
+#endif /* ELOG_H_ */
diff --git a/src/include/lib.h b/src/include/lib.h
index ea09887..b2f38a8 100644
--- a/src/include/lib.h
+++ b/src/include/lib.h
@@ -21,7 +21,7 @@
#ifndef __LIB_H__
#define __LIB_H__
-
+#include <stdint.h>
#ifndef __ROMCC__ /* romcc doesn't support prototypes. */
#ifndef __PRE_RAM__ /* Conflicts with romcc_io.h */
@@ -40,6 +40,12 @@
int ram_check_nodie(unsigned long start, unsigned long stop);
void quick_ram_check(void);
+/* Defined in src/lib/stack.c */
+int checkstack(void *top_of_stack, int stacksize);
+
+/* currently defined by a ldscript */
+extern u8 _estack;
+
/* Defined in romstage.c */
#if CONFIG_CPU_AMD_GEODE_LX
void cache_as_ram_main(void);
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index a1f06e7..6d2e8f8 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -63,6 +63,8 @@
# define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
# define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
+#define RTC_TO_BCD(value) (((value / 10) << 4) | (value % 10))
+
/**********************************************************************/
#define RTC_INTR_FLAGS RTC_REG_C
/* caution - cleared by read */
@@ -76,6 +78,18 @@
# define RTC_VRT 0x80 /* valid RAM and time */
/**********************************************************************/
+/* Date and Time in RTC CMOS */
+#define RTC_CLK_SECOND 0
+#define RTC_CLK_SECOND_ALARM 1
+#define RTC_CLK_MINUTE 2
+#define RTC_CLK_MINUTE_ALARM 3
+#define RTC_CLK_HOUR 4
+#define RTC_CLK_HOUR_ALARM 5
+#define RTC_CLK_DAYOFWEEK 6
+#define RTC_CLK_DAYOFMONTH 7
+#define RTC_CLK_MONTH 8
+#define RTC_CLK_YEAR 9
+
/* On PCs, the checksum is built only over bytes 16..45 */
#define PC_CKS_RANGE_START 16
#define PC_CKS_RANGE_END 45
@@ -139,4 +153,27 @@
#endif
#define read_option(name, default) read_option_lowlevel(CMOS_VSTART_ ##name, CMOS_VLEN_ ##name, (default))
+#if CONFIG_CMOS_POST
+#if CONFIG_USE_OPTION_TABLE
+# include "option_table.h"
+# define CMOS_POST_OFFSET (CMOS_VSTART_cmos_post_offset >> 3)
+#else
+# if defined(CONFIG_CMOS_POST_OFFSET)
+# define CMOS_POST_OFFSET CONFIG_CMOS_POST_OFFSET
+# else
+# error "Must define CONFIG_CMOS_POST_OFFSET"
+# endif
+#endif
+
+#define CMOS_POST_BANK_OFFSET (CMOS_POST_OFFSET)
+#define CMOS_POST_BANK_0_MAGIC 0x80
+#define CMOS_POST_BANK_0_OFFSET (CMOS_POST_OFFSET + 1)
+#define CMOS_POST_BANK_1_MAGIC 0x81
+#define CMOS_POST_BANK_1_OFFSET (CMOS_POST_OFFSET + 2)
+
+#if !defined(__ROMCC__)
+void cmos_post_log(void);
+#endif
+#endif /* CONFIG_CMOS_POST */
+
#endif /* PC80_MC146818RTC_H */
diff --git a/src/include/smbios.h b/src/include/smbios.h
index 1210f0f..2377bc3 100644
--- a/src/include/smbios.h
+++ b/src/include/smbios.h
@@ -28,6 +28,7 @@
SMBIOS_PROCESSOR_INFORMATION=4,
SMBIOS_CACHE_INFORMATION=7,
SMBIOS_SYSTEM_SLOTS=9,
+ SMBIOS_EVENT_LOG=15,
SMBIOS_PHYS_MEMORY_ARRAY=16,
SMBIOS_MEMORY_DEVICE=17,
SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19,
@@ -138,6 +139,36 @@
char eos[2];
} __attribute__((packed));
+struct smbios_type15 {
+ u8 type;
+ u8 length;
+ u16 handle;
+ u16 area_length;
+ u16 header_offset;
+ u16 data_offset;
+ u8 access_method;
+ u8 log_status;
+ u32 change_token;
+ u32 address;
+ u8 header_format;
+ u8 log_type_descriptors;
+ u8 log_type_descriptor_length;
+ char eos[2];
+} __attribute__((packed));
+
+enum {
+ SMBIOS_EVENTLOG_ACCESS_METHOD_IO8 = 0,
+ SMBIOS_EVENTLOG_ACCESS_METHOD_IO8X2,
+ SMBIOS_EVENTLOG_ACCESS_METHOD_IO16,
+ SMBIOS_EVENTLOG_ACCESS_METHOD_MMIO32,
+ SMBIOS_EVENTLOG_ACCESS_METHOD_GPNV,
+};
+
+enum {
+ SMBIOS_EVENTLOG_STATUS_VALID = 1, /* Bit 0 */
+ SMBIOS_EVENTLOG_STATUS_FULL = 2, /* Bit 1 */
+};
+
struct smbios_type16 {
u8 type;
u8 length;
diff --git a/src/include/spi.h b/src/include/spi.h
index bb84258..5fbe51e 100644
--- a/src/include/spi.h
+++ b/src/include/spi.h
@@ -44,6 +44,10 @@
#define SPI_XFER_BEGIN 0x01 /* Assert CS before transfer */
#define SPI_XFER_END 0x02 /* Deassert CS after transfer */
+/* SPI opcodes */
+#define SPI_OPCODE_WREN 0x06
+#define SPI_OPCODE_FAST_READ 0x0b
+
/*-----------------------------------------------------------------------
* Representation of a SPI slave, i.e. what we're communicating with.
*
@@ -84,13 +88,6 @@
unsigned int max_hz, unsigned int mode);
/*-----------------------------------------------------------------------
- * Free any memory associated with a SPI slave.
- *
- * slave: The SPI slave
- */
-void spi_free_slave(struct spi_slave *slave);
-
-/*-----------------------------------------------------------------------
* Claim the bus and prepare it for communication with a given slave.
*
* This must be called before doing any transfers with a SPI slave. It
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 2a1dcd4..b84bd96 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -68,7 +68,6 @@
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int spi_mode);
-void spi_flash_free(struct spi_flash *flash);
static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
size_t len, void *buf)
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index bd0ee30..bb57ab3 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -14,7 +14,6 @@
#if !defined(__PRE_RAM__)
void *memalign(size_t boundary, size_t size);
void *malloc(size_t size);
-void free(void *ptr);
#endif
#endif /* STDLIB_H */
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index 71b9a5f..8457530 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -125,6 +125,7 @@
*/
void uart8250_init(unsigned base_port, unsigned divisor);
void uart_init(void);
+void uartmem_init(void);
/* and the same for memory mapped uarts */
unsigned char uart8250_mem_rx_byte(unsigned base_port);
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 7c081ac..ec57bc2 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -32,6 +32,7 @@
ramstage-y += memcmp.c
ramstage-y += memmove.c
ramstage-y += malloc.c
+smm-$(CONFIG_SMM_TSEG) += malloc.c
ramstage-y += delay.c
ramstage-y += fallback_boot.c
ramstage-y += compute_ip_checksum.c
@@ -39,6 +40,7 @@
ramstage-y += cbfs.c
ramstage-y += lzma.c
#ramstage-y += lzmadecode.c
+ramstage-y += stack.c
ramstage-y += gcc.c
ramstage-y += clog2.c
ramstage-y += cbmem.c
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index bc38f35..f0b88c1 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -23,6 +23,11 @@
int res;
CLzmaDecoderState state;
SizeT mallocneeds;
+#if !defined(__PRE_RAM__)
+ /* in ramstage, this can go in BSS */
+ static
+#endif
+ /* in pre-ram, it must go on the stack */
unsigned char scratchpad[15980];
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
diff --git a/src/lib/malloc.c b/src/lib/malloc.c
index 2e700f7..43e514a 100644
--- a/src/lib/malloc.c
+++ b/src/lib/malloc.c
@@ -1,5 +1,8 @@
#include <stdlib.h>
#include <console/console.h>
+#ifdef __SMM__
+#include <cpu/x86/smm.h>
+#endif
#if CONFIG_DEBUG_MALLOC
#define MALLOCDBG(x...) printk(BIOS_SPEW, x)
@@ -18,20 +21,23 @@
{
void *p;
- MALLOCDBG("%s Enter, boundary %ld, size %ld, free_mem_ptr %p\n",
+ MALLOCDBG("%s Enter, boundary %zu, size %zu, free_mem_ptr %p\n",
__func__, boundary, size, free_mem_ptr);
- /* Overzealous linker check */
- if (free_mem_ptr <= 0)
- die("Error! memalign: Free_mem_ptr <= 0");
-
free_mem_ptr = (void *)ALIGN((unsigned long)free_mem_ptr, boundary);
p = free_mem_ptr;
free_mem_ptr += size;
- if (free_mem_ptr >= free_mem_end_ptr)
+ if (free_mem_ptr >= free_mem_end_ptr) {
+ printk(BIOS_ERR, "memalign(boundary=%zu, size=%zu): failed: ",
+ boundary, size);
+ printk(BIOS_ERR, "Tried to round up free_mem_ptr %p to %p\n",
+ p, free_mem_ptr);
+ printk(BIOS_ERR, "but free_mem_end_ptr is %p\n",
+ free_mem_end_ptr);
die("Error! memalign: Out of memory (free_mem_ptr >= free_mem_end_ptr)");
+ }
MALLOCDBG("memalign %p\n", p);
@@ -40,11 +46,11 @@
void *malloc(size_t size)
{
+#if CONFIG_SMM_TSEG && defined(__SMM__)
+ if (!free_mem_ptr) {
+ free_mem_ptr = &_heap + smi_get_tseg_base();
+ free_mem_end_ptr = &_eheap + smi_get_tseg_base();
+ }
+#endif
return memalign(sizeof(u64), size);
}
-
-void free(void *where)
-{
- /* Don't care */
- MALLOCDBG("free %p\n", where);
-}
diff --git a/src/lib/stack.c b/src/lib/stack.c
new file mode 100644
index 0000000..3f04b63
--- /dev/null
+++ b/src/lib/stack.c
@@ -0,0 +1,51 @@
+/*
+This software and ancillary information (herein called SOFTWARE )
+called LinuxBIOS is made available under the terms described
+here. The SOFTWARE has been approved for release with associated
+LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
+been authored by an employee or employees of the University of
+California, operator of the Los Alamos National Laboratory under
+Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
+U.S. Government has rights to use, reproduce, and distribute this
+SOFTWARE. The public may copy, distribute, prepare derivative works
+and publicly display this SOFTWARE without charge, provided that this
+Notice and any statement of authorship are reproduced on all copies.
+Neither the Government nor the University makes any warranty, express
+or implied, or assumes any liability or responsibility for the use of
+this SOFTWARE. If SOFTWARE is modified to produce derivative works,
+such modified SOFTWARE should be clearly marked, so as not to confuse
+it with the version available from LANL.
+ */
+/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
+ * rminnich@lanl.gov
+ */
+
+#include <lib.h>
+#include <console/console.h>
+
+int checkstack(void *top_of_stack, int core)
+{
+ int i;
+ u32 *stack = (u32 *) (top_of_stack - CONFIG_STACK_SIZE);
+
+ if (stack[0] != 0xDEADBEEF){
+ printk(BIOS_ERR, "Stack overrun on CPU%d."
+ "Increase stack from current %d bytes\n",
+ CONFIG_STACK_SIZE, core);
+ return -1;
+ }
+
+ for(i = 0; i < CONFIG_STACK_SIZE/sizeof(stack[0]); i++){
+ if (stack[i] == 0xDEADBEEF)
+ continue;
+ printk(BIOS_SPEW, "CPU%d: stack from %p to %p:",
+ core,
+ stack,
+ &stack[CONFIG_STACK_SIZE/sizeof(stack[0])]);
+ printk(BIOS_SPEW, "Lowest stack address %p\n", &stack[i]);
+ return -1;
+ }
+
+ return 0;
+
+}
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index c89d4a7..26827bc 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -42,6 +42,8 @@
bool "Biostar"
config VENDOR_BROADCOM
bool "Broadcom"
+config VENDOR_COMPAL
+ bool "Compal"
config VENDOR_COMPAQ
bool "Compaq"
config VENDOR_DIGITALLOGIC
@@ -56,6 +58,8 @@
bool "Getac"
config VENDOR_GIGABYTE
bool "GIGABYTE"
+config VENDOR_GOOGLE
+ bool "Google"
config VENDOR_HP
bool "HP"
config VENDOR_IBASE
@@ -155,6 +159,7 @@
source "src/mainboard/emulation/Kconfig"
source "src/mainboard/getac/Kconfig"
source "src/mainboard/gigabyte/Kconfig"
+source "src/mainboard/google/Kconfig"
source "src/mainboard/hp/Kconfig"
source "src/mainboard/ibase/Kconfig"
source "src/mainboard/ibm/Kconfig"
diff --git a/src/mainboard/a-trend/atc-6220/chip.h b/src/mainboard/a-trend/atc-6220/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/a-trend/atc-6220/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/a-trend/atc-6220/mainboard.c b/src/mainboard/a-trend/atc-6220/mainboard.c
index f30ebfa..26f18dd 100644
--- a/src/mainboard/a-trend/atc-6220/mainboard.c
+++ b/src/mainboard/a-trend/atc-6220/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("A-Trend ATC-6220 Mainboard")
diff --git a/src/mainboard/a-trend/atc-6240/chip.h b/src/mainboard/a-trend/atc-6240/chip.h
deleted file mode 100644
index 56e17ca..0000000
--- a/src/mainboard/a-trend/atc-6240/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/a-trend/atc-6240/mainboard.c b/src/mainboard/a-trend/atc-6240/mainboard.c
index 0e09ea33..13f6e3f 100644
--- a/src/mainboard/a-trend/atc-6240/mainboard.c
+++ b/src/mainboard/a-trend/atc-6240/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("A-Trend ATC-6240 Mainboard")
diff --git a/src/mainboard/aaeon/pfm-540i_revb/chip.h b/src/mainboard/aaeon/pfm-540i_revb/chip.h
deleted file mode 100644
index c8c54b0..0000000
--- a/src/mainboard/aaeon/pfm-540i_revb/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c b/src/mainboard/aaeon/pfm-540i_revb/mainboard.c
index 72e500c..8f1412f 100644
--- a/src/mainboard/aaeon/pfm-540i_revb/mainboard.c
+++ b/src/mainboard/aaeon/pfm-540i_revb/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/abit/be6-ii_v2_0/chip.h b/src/mainboard/abit/be6-ii_v2_0/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/abit/be6-ii_v2_0/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/abit/be6-ii_v2_0/mainboard.c b/src/mainboard/abit/be6-ii_v2_0/mainboard.c
index 6fc23ec..c70df95 100644
--- a/src/mainboard/abit/be6-ii_v2_0/mainboard.c
+++ b/src/mainboard/abit/be6-ii_v2_0/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Abit BE6-II V2.0 Mainboard")
diff --git a/src/mainboard/advansus/a785e-i/chip.h b/src/mainboard/advansus/a785e-i/chip.h
deleted file mode 100644
index 5957589..0000000
--- a/src/mainboard/advansus/a785e-i/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/advansus/a785e-i/mainboard.c b/src/mainboard/advansus/a785e-i/mainboard.c
index afa82f3..7af733f 100644
--- a/src/mainboard/advansus/a785e-i/mainboard.c
+++ b/src/mainboard/advansus/a785e-i/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
@@ -78,10 +77,6 @@
*************************************************/
static void a785e_i_enable(device_t dev)
{
- /* Leave it for furture use. */
- /* struct mainboard_config *mainboard =
- (struct mainboard_config *)dev->chip_info; */
-
printk(BIOS_INFO, "Mainboard A785E-I Enable. dev=0x%p\n", dev);
#if CONFIG_GFXUMA
diff --git a/src/mainboard/advantech/pcm-5820/chip.h b/src/mainboard/advantech/pcm-5820/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/advantech/pcm-5820/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/advantech/pcm-5820/mainboard.c b/src/mainboard/advantech/pcm-5820/mainboard.c
index 4256059..345c6f8 100644
--- a/src/mainboard/advantech/pcm-5820/mainboard.c
+++ b/src/mainboard/advantech/pcm-5820/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Advantech PCM-5820 Mainboard")
diff --git a/src/mainboard/amd/bimini_fam10/chip.h b/src/mainboard/amd/bimini_fam10/chip.h
deleted file mode 100644
index 2013516..0000000
--- a/src/mainboard/amd/bimini_fam10/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/bimini_fam10/mainboard.c b/src/mainboard/amd/bimini_fam10/mainboard.c
index 241d905..e26d280 100644
--- a/src/mainboard/amd/bimini_fam10/mainboard.c
+++ b/src/mainboard/amd/bimini_fam10/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb800/sb800.h>
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
@@ -128,10 +127,6 @@
*************************************************/
static void bimini_enable(device_t dev)
{
- /* Leave it for furture use. */
- /* struct mainboard_config *mainboard =
- (struct mainboard_config *)dev->chip_info; */
-
printk(BIOS_INFO, "Mainboard BIMINI Enable. dev=0x%p\n", dev);
#if CONFIG_GFXUMA
diff --git a/src/mainboard/amd/db800/chip.h b/src/mainboard/amd/db800/chip.h
deleted file mode 100644
index ae69536..0000000
--- a/src/mainboard/amd/db800/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/db800/mainboard.c b/src/mainboard/amd/db800/mainboard.c
index f95ea22..e841d07 100644
--- a/src/mainboard/amd/db800/mainboard.c
+++ b/src/mainboard/amd/db800/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/amd/dbm690t/chip.h b/src/mainboard/amd/dbm690t/chip.h
deleted file mode 100644
index 9ee2dc8..0000000
--- a/src/mainboard/amd/dbm690t/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/amd/dbm690t/mainboard.c b/src/mainboard/amd/dbm690t/mainboard.c
index 8841291..75b7d72 100644
--- a/src/mainboard/amd/dbm690t/mainboard.c
+++ b/src/mainboard/amd/dbm690t/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb600/sb600.h>
-#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
diff --git a/src/mainboard/amd/dinar/chip.h b/src/mainboard/amd/dinar/chip.h
deleted file mode 100644
index 42630fa..0000000
--- a/src/mainboard/amd/dinar/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/dinar/mainboard.c b/src/mainboard/amd/dinar/mainboard.c
index 360e1df..7c7d241 100644
--- a/src/mainboard/amd/dinar/mainboard.c
+++ b/src/mainboard/amd/dinar/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <NbPlatform.h>
-#include "chip.h"
#define ONE_MB 0x100000
//#define SMBUS_IO_BASE 0x6000
diff --git a/src/mainboard/amd/inagua/mainboard.c b/src/mainboard/amd/inagua/mainboard.c
index d35b175..bdab9d9 100644
--- a/src/mainboard/amd/inagua/mainboard.c
+++ b/src/mainboard/amd/inagua/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
//#include <southbridge/amd/sb800/sb800.h>
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
-#include "chip.h"
void set_pcie_reset(void);
void set_pcie_dereset(void);
diff --git a/src/mainboard/amd/mahogany/chip.h b/src/mainboard/amd/mahogany/chip.h
deleted file mode 100644
index 42664d0..0000000
--- a/src/mainboard/amd/mahogany/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index 989070c..0b9f286 100644
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/amd/mahogany_fam10/chip.h b/src/mainboard/amd/mahogany_fam10/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/amd/mahogany_fam10/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index 1f1941b..5b1e413 100644
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/amd/norwich/chip.h b/src/mainboard/amd/norwich/chip.h
deleted file mode 100644
index ae69536..0000000
--- a/src/mainboard/amd/norwich/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/norwich/mainboard.c b/src/mainboard/amd/norwich/mainboard.c
index 0814a16..c735abb 100644
--- a/src/mainboard/amd/norwich/mainboard.c
+++ b/src/mainboard/amd/norwich/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/amd/persimmon/chip.h b/src/mainboard/amd/persimmon/chip.h
deleted file mode 100644
index a252705..0000000
--- a/src/mainboard/amd/persimmon/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/persimmon/mainboard.c b/src/mainboard/amd/persimmon/mainboard.c
index 76a9ae6..08f463f 100644
--- a/src/mainboard/amd/persimmon/mainboard.c
+++ b/src/mainboard/amd/persimmon/mainboard.c
@@ -26,7 +26,6 @@
#include <device/pci_def.h>
#include <southbridge/amd/sb800/sb800.h>
#include <arch/acpi.h>
-#include "chip.h"
#include "BiosCallOuts.h"
#include <cpu/amd/agesa/s3_resume.h>
#include <cpu/amd/mtrr.h>
diff --git a/src/mainboard/amd/pistachio/chip.h b/src/mainboard/amd/pistachio/chip.h
deleted file mode 100644
index 05e1582..0000000
--- a/src/mainboard/amd/pistachio/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c
index e5d0efa..06f9e0c 100644
--- a/src/mainboard/amd/pistachio/mainboard.c
+++ b/src/mainboard/amd/pistachio/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb600/sb600.h>
-#include "chip.h"
#define ADT7475_ADDRESS 0x2E
#define SMBUS_IO_BASE 0x1000
diff --git a/src/mainboard/amd/rumba/chip.h b/src/mainboard/amd/rumba/chip.h
deleted file mode 100644
index 2094b23..0000000
--- a/src/mainboard/amd/rumba/chip.h
+++ /dev/null
@@ -1,5 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {
- int nicirq;
-};
diff --git a/src/mainboard/amd/rumba/mainboard.c b/src/mainboard/amd/rumba/mainboard.c
index 0e7bbb6..42547cc 100644
--- a/src/mainboard/amd/rumba/mainboard.c
+++ b/src/mainboard/amd/rumba/mainboard.c
@@ -4,18 +4,14 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
-#include "chip.h"
-static void init(struct device *dev) {
- struct mainboard_config *mainboard = (struct mainboard_config*)dev->chip_info;
+static void init(struct device *dev)
+{
device_t nic = NULL;
unsigned bus = 0;
unsigned devfn = PCI_DEVFN(0xd, 0);
int nicirq = 1;
- if (mainboard->nicirq)
- nicirq = mainboard->nicirq;
-
printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__);
if (nicirq) {
diff --git a/src/mainboard/amd/serengeti_cheetah/chip.h b/src/mainboard/amd/serengeti_cheetah/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/amd/serengeti_cheetah/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/serengeti_cheetah/mainboard.c b/src/mainboard/amd/serengeti_cheetah/mainboard.c
index 4fb715f..a156f2e 100644
--- a/src/mainboard/amd/serengeti_cheetah/mainboard.c
+++ b/src/mainboard/amd/serengeti_cheetah/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD Serengeti Cheetah Mainboard")
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/chip.h b/src/mainboard/amd/serengeti_cheetah_fam10/chip.h
deleted file mode 100644
index df1a3eb..0000000
--- a/src/mainboard/amd/serengeti_cheetah_fam10/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
index ba1ee9c..9984bd6 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c
@@ -23,7 +23,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("AMD family 10 Cheetah mainboard")
diff --git a/src/mainboard/amd/south_station/chip.h b/src/mainboard/amd/south_station/chip.h
deleted file mode 100644
index a252705..0000000
--- a/src/mainboard/amd/south_station/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/south_station/mainboard.c b/src/mainboard/amd/south_station/mainboard.c
index ed65b34..954550b 100644
--- a/src/mainboard/amd/south_station/mainboard.c
+++ b/src/mainboard/amd/south_station/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/amd/tilapia_fam10/chip.h b/src/mainboard/amd/tilapia_fam10/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/amd/tilapia_fam10/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/tilapia_fam10/mainboard.c b/src/mainboard/amd/tilapia_fam10/mainboard.c
index e2ef3f9..9844350 100644
--- a/src/mainboard/amd/tilapia_fam10/mainboard.c
+++ b/src/mainboard/amd/tilapia_fam10/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
diff --git a/src/mainboard/amd/torpedo/chip.h b/src/mainboard/amd/torpedo/chip.h
deleted file mode 100644
index a252705..0000000
--- a/src/mainboard/amd/torpedo/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/torpedo/mainboard.c b/src/mainboard/amd/torpedo/mainboard.c
index 7248bfb..1f62464 100644
--- a/src/mainboard/amd/torpedo/mainboard.c
+++ b/src/mainboard/amd/torpedo/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
//#include <southbridge/amd/sb900/sb900.h>
-#include "chip.h"
#define ONE_MB 0x100000
//#define SMBUS_IO_BASE 0x6000
diff --git a/src/mainboard/amd/union_station/chip.h b/src/mainboard/amd/union_station/chip.h
deleted file mode 100644
index a252705..0000000
--- a/src/mainboard/amd/union_station/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/amd/union_station/mainboard.c b/src/mainboard/amd/union_station/mainboard.c
index c5b481d..1aa9e23 100644
--- a/src/mainboard/amd/union_station/mainboard.c
+++ b/src/mainboard/amd/union_station/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h" /* Platfrom Specific Definitions */
-#include "chip.h"
void set_pcie_reset(void);
void set_pcie_dereset(void);
diff --git a/src/mainboard/aopen/dxplplusu/chip.h b/src/mainboard/aopen/dxplplusu/chip.h
deleted file mode 100644
index 06f11d0..0000000
--- a/src/mainboard/aopen/dxplplusu/chip.h
+++ /dev/null
@@ -1,4 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {
-};
diff --git a/src/mainboard/aopen/dxplplusu/mainboard.c b/src/mainboard/aopen/dxplplusu/mainboard.c
index 2d41509..0688914 100644
--- a/src/mainboard/aopen/dxplplusu/mainboard.c
+++ b/src/mainboard/aopen/dxplplusu/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("AOpen DXPL Plus-U Mainboard")
diff --git a/src/mainboard/arima/hdama/chip.h b/src/mainboard/arima/hdama/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/arima/hdama/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/arima/hdama/mainboard.c b/src/mainboard/arima/hdama/mainboard.c
index 688a01c..df658e2 100644
--- a/src/mainboard/arima/hdama/mainboard.c
+++ b/src/mainboard/arima/hdama/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Arima HDAMA Mainboard")
diff --git a/src/mainboard/artecgroup/dbe61/chip.h b/src/mainboard/artecgroup/dbe61/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/artecgroup/dbe61/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/artecgroup/dbe61/mainboard.c b/src/mainboard/artecgroup/dbe61/mainboard.c
index f49c215..649f955 100644
--- a/src/mainboard/artecgroup/dbe61/mainboard.c
+++ b/src/mainboard/artecgroup/dbe61/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/x86/msr.h>
#include <cpu/amd/lxdef.h>
#include "southbridge/amd/cs5536/cs5536.h"
-#include "chip.h"
static void init_gpio(void)
{
diff --git a/src/mainboard/asi/mb_5blgp/chip.h b/src/mainboard/asi/mb_5blgp/chip.h
deleted file mode 100644
index 56e17ca..0000000
--- a/src/mainboard/asi/mb_5blgp/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asi/mb_5blgp/mainboard.c b/src/mainboard/asi/mb_5blgp/mainboard.c
index 22bc52d..7a466bd 100644
--- a/src/mainboard/asi/mb_5blgp/mainboard.c
+++ b/src/mainboard/asi/mb_5blgp/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASI MB-5BLGP Mainboard")
diff --git a/src/mainboard/asi/mb_5blmp/chip.h b/src/mainboard/asi/mb_5blmp/chip.h
deleted file mode 100644
index 982cfb3..0000000
--- a/src/mainboard/asi/mb_5blmp/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asi/mb_5blmp/mainboard.c b/src/mainboard/asi/mb_5blmp/mainboard.c
index 78366ba..9aaf14d 100644
--- a/src/mainboard/asi/mb_5blmp/mainboard.c
+++ b/src/mainboard/asi/mb_5blmp/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASI/BCom MB-5BLMP Mainboard")
diff --git a/src/mainboard/asrock/939a785gmh/chip.h b/src/mainboard/asrock/939a785gmh/chip.h
deleted file mode 100644
index be42783..0000000
--- a/src/mainboard/asrock/939a785gmh/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c
index 0b566e4..26258c5 100644
--- a/src/mainboard/asrock/939a785gmh/mainboard.c
+++ b/src/mainboard/asrock/939a785gmh/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/asrock/e350m1/chip.h b/src/mainboard/asrock/e350m1/chip.h
deleted file mode 100644
index a252705..0000000
--- a/src/mainboard/asrock/e350m1/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c
index 8642e28..178db70 100644
--- a/src/mainboard/asrock/e350m1/mainboard.c
+++ b/src/mainboard/asrock/e350m1/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
//#include <southbridge/amd/sb800/sb800.h>
-#include "chip.h"
//#define SMBUS_IO_BASE 0x6000
diff --git a/src/mainboard/asus/a8n_e/chip.h b/src/mainboard/asus/a8n_e/chip.h
deleted file mode 100644
index 1b910e6..0000000
--- a/src/mainboard/asus/a8n_e/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Philipp Degler <pdegler@rumms.uni-mannheim.de>
- * (Thanks to LSRA University of Mannheim for their support)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/a8n_e/mainboard.c b/src/mainboard/asus/a8n_e/mainboard.c
index 4bd6311..aedca67 100644
--- a/src/mainboard/asus/a8n_e/mainboard.c
+++ b/src/mainboard/asus/a8n_e/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS A8N-E Mainboard")
diff --git a/src/mainboard/asus/a8v-e_deluxe/chip.h b/src/mainboard/asus/a8v-e_deluxe/chip.h
deleted file mode 100644
index c2849ef..0000000
--- a/src/mainboard/asus/a8v-e_deluxe/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/a8v-e_deluxe/mainboard.c b/src/mainboard/asus/a8v-e_deluxe/mainboard.c
index 0180a2f..cb38be2 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mainboard.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mainboard.c
@@ -21,7 +21,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS A8V-E Deluxe Mainboard")
diff --git a/src/mainboard/asus/a8v-e_se/chip.h b/src/mainboard/asus/a8v-e_se/chip.h
deleted file mode 100644
index c2849ef..0000000
--- a/src/mainboard/asus/a8v-e_se/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/a8v-e_se/mainboard.c b/src/mainboard/asus/a8v-e_se/mainboard.c
index b70f396..c119e1c 100644
--- a/src/mainboard/asus/a8v-e_se/mainboard.c
+++ b/src/mainboard/asus/a8v-e_se/mainboard.c
@@ -21,7 +21,6 @@
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS A8V-E SE Mainboard")
diff --git a/src/mainboard/asus/k8v-x/chip.h b/src/mainboard/asus/k8v-x/chip.h
deleted file mode 100644
index c2849ef..0000000
--- a/src/mainboard/asus/k8v-x/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/k8v-x/mainboard.c b/src/mainboard/asus/k8v-x/mainboard.c
index 3e294b8..82d8ba0 100644
--- a/src/mainboard/asus/k8v-x/mainboard.c
+++ b/src/mainboard/asus/k8v-x/mainboard.c
@@ -24,7 +24,6 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include "southbridge/via/vt8237r/vt8237r.h"
-#include "chip.h"
u32 vt8237_ide_80pin_detect(struct device *dev)
{
diff --git a/src/mainboard/asus/m2n-e/chip.h b/src/mainboard/asus/m2n-e/chip.h
deleted file mode 100644
index a69b9ef..0000000
--- a/src/mainboard/asus/m2n-e/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/m2n-e/mainboard.c b/src/mainboard/asus/m2n-e/mainboard.c
index aa0cc5c..0d7013f 100644
--- a/src/mainboard/asus/m2n-e/mainboard.c
+++ b/src/mainboard/asus/m2n-e/mainboard.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include "hda_verb.h"
-#include "chip.h"
static void verb_setup(void)
{
diff --git a/src/mainboard/asus/m2v-mx_se/chip.h b/src/mainboard/asus/m2v-mx_se/chip.h
deleted file mode 100644
index c2849ef..0000000
--- a/src/mainboard/asus/m2v-mx_se/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/m2v-mx_se/mainboard.c b/src/mainboard/asus/m2v-mx_se/mainboard.c
index c936fa9..cdbc5f9 100644
--- a/src/mainboard/asus/m2v-mx_se/mainboard.c
+++ b/src/mainboard/asus/m2v-mx_se/mainboard.c
@@ -22,7 +22,6 @@
#include <device/pci_ids.h>
#include <boot/tables.h>
#include <southbridge/via/k8t890/k8t890.h>
-#include "chip.h"
#if CONFIG_GFXUMA
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/asus/m2v/chip.h b/src/mainboard/asus/m2v/chip.h
deleted file mode 100644
index c2849ef..0000000
--- a/src/mainboard/asus/m2v/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Rudolf Marek <r.marek@assembler.cz>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/m2v/mainboard.c b/src/mainboard/asus/m2v/mainboard.c
index 2f20fe0..2a44851 100644
--- a/src/mainboard/asus/m2v/mainboard.c
+++ b/src/mainboard/asus/m2v/mainboard.c
@@ -23,7 +23,6 @@
#include <device/pci_ids.h>
#include <console/console.h>
#include "southbridge/via/vt8237r/vt8237r.h"
-#include "chip.h"
u32 vt8237_ide_80pin_detect(struct device *dev)
{
diff --git a/src/mainboard/asus/m4a78-em/chip.h b/src/mainboard/asus/m4a78-em/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/asus/m4a78-em/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/m4a78-em/mainboard.c b/src/mainboard/asus/m4a78-em/mainboard.c
index 10ecb64..08bb9a0 100644
--- a/src/mainboard/asus/m4a78-em/mainboard.c
+++ b/src/mainboard/asus/m4a78-em/mainboard.c
@@ -26,7 +26,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/asus/m4a785-m/chip.h b/src/mainboard/asus/m4a785-m/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/asus/m4a785-m/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/m4a785-m/mainboard.c b/src/mainboard/asus/m4a785-m/mainboard.c
index 3b68143..c8c4fdd 100644
--- a/src/mainboard/asus/m4a785-m/mainboard.c
+++ b/src/mainboard/asus/m4a785-m/mainboard.c
@@ -26,7 +26,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
diff --git a/src/mainboard/asus/m4a785t-m/chip.h b/src/mainboard/asus/m4a785t-m/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/asus/m4a785t-m/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/m5a88-v/chip.h b/src/mainboard/asus/m5a88-v/chip.h
deleted file mode 100644
index d5b991d..0000000
--- a/src/mainboard/asus/m5a88-v/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 QingPei Wang <wangqingpei@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 38b9648..d2df718 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/asus/mew-am/chip.h b/src/mainboard/asus/mew-am/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/asus/mew-am/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asus/mew-am/mainboard.c b/src/mainboard/asus/mew-am/mainboard.c
index e5008b9..8887218 100644
--- a/src/mainboard/asus/mew-am/mainboard.c
+++ b/src/mainboard/asus/mew-am/mainboard.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/asus/mew-vm/chip.h b/src/mainboard/asus/mew-vm/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/asus/mew-vm/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/asus/mew-vm/mainboard.c b/src/mainboard/asus/mew-vm/mainboard.c
index 831be01..e278565 100644
--- a/src/mainboard/asus/mew-vm/mainboard.c
+++ b/src/mainboard/asus/mew-vm/mainboard.c
@@ -1,6 +1,5 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/asus/p2b-d/chip.h b/src/mainboard/asus/p2b-d/chip.h
deleted file mode 100644
index 1c3876d..0000000
--- a/src/mainboard/asus/p2b-d/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asus/p2b-d/mainboard.c b/src/mainboard/asus/p2b-d/mainboard.c
index 58cce0a..3fe9dc4 100644
--- a/src/mainboard/asus/p2b-d/mainboard.c
+++ b/src/mainboard/asus/p2b-d/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS P2B-D Mainboard")
diff --git a/src/mainboard/asus/p2b-ds/chip.h b/src/mainboard/asus/p2b-ds/chip.h
deleted file mode 100644
index 56e17ca..0000000
--- a/src/mainboard/asus/p2b-ds/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asus/p2b-ds/mainboard.c b/src/mainboard/asus/p2b-ds/mainboard.c
index 910b130..c874137 100644
--- a/src/mainboard/asus/p2b-ds/mainboard.c
+++ b/src/mainboard/asus/p2b-ds/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS P2B-DS Mainboard")
diff --git a/src/mainboard/asus/p2b-f/chip.h b/src/mainboard/asus/p2b-f/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/asus/p2b-f/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asus/p2b-f/mainboard.c b/src/mainboard/asus/p2b-f/mainboard.c
index e2b022a..e5d2e14 100644
--- a/src/mainboard/asus/p2b-f/mainboard.c
+++ b/src/mainboard/asus/p2b-f/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS P2B-F Mainboard")
diff --git a/src/mainboard/asus/p2b-ls/chip.h b/src/mainboard/asus/p2b-ls/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/asus/p2b-ls/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asus/p2b-ls/mainboard.c b/src/mainboard/asus/p2b-ls/mainboard.c
index fec75e3..9f250f4 100644
--- a/src/mainboard/asus/p2b-ls/mainboard.c
+++ b/src/mainboard/asus/p2b-ls/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS P2B-LS Mainboard")
diff --git a/src/mainboard/asus/p2b/chip.h b/src/mainboard/asus/p2b/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/asus/p2b/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asus/p2b/mainboard.c b/src/mainboard/asus/p2b/mainboard.c
index 21e5a4e..527dc7a 100644
--- a/src/mainboard/asus/p2b/mainboard.c
+++ b/src/mainboard/asus/p2b/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS P2B Mainboard")
diff --git a/src/mainboard/asus/p3b-f/chip.h b/src/mainboard/asus/p3b-f/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/asus/p3b-f/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/asus/p3b-f/mainboard.c b/src/mainboard/asus/p3b-f/mainboard.c
index c234fc2..9b41c79 100644
--- a/src/mainboard/asus/p3b-f/mainboard.c
+++ b/src/mainboard/asus/p3b-f/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("ASUS P3B-F Mainboard")
diff --git a/src/mainboard/avalue/eax-785e/chip.h b/src/mainboard/avalue/eax-785e/chip.h
deleted file mode 100644
index 5957589..0000000
--- a/src/mainboard/avalue/eax-785e/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c
index 52befa5..f2e7ecf 100644
--- a/src/mainboard/avalue/eax-785e/mainboard.c
+++ b/src/mainboard/avalue/eax-785e/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include "SBPLATFORM.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
@@ -78,10 +77,6 @@
*************************************************/
static void eax_785e(device_t dev)
{
- /* Leave it for furture use. */
- /* struct mainboard_config *mainboard =
- (struct mainboard_config *)dev->chip_info; */
-
printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n");
#if CONFIG_GFXUMA
diff --git a/src/mainboard/axus/tc320/chip.h b/src/mainboard/axus/tc320/chip.h
deleted file mode 100644
index 6e6f190..0000000
--- a/src/mainboard/axus/tc320/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/axus/tc320/mainboard.c b/src/mainboard/axus/tc320/mainboard.c
index 89c3dca..af52755 100644
--- a/src/mainboard/axus/tc320/mainboard.c
+++ b/src/mainboard/axus/tc320/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("AXUS TC320 Mainboard")
diff --git a/src/mainboard/azza/pt-6ibd/chip.h b/src/mainboard/azza/pt-6ibd/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/azza/pt-6ibd/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/azza/pt-6ibd/mainboard.c b/src/mainboard/azza/pt-6ibd/mainboard.c
index 45efc16..483f328 100644
--- a/src/mainboard/azza/pt-6ibd/mainboard.c
+++ b/src/mainboard/azza/pt-6ibd/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("AZZA PT-6IBD Mainboard")
diff --git a/src/mainboard/bcom/winnet100/chip.h b/src/mainboard/bcom/winnet100/chip.h
deleted file mode 100644
index 4bce558..0000000
--- a/src/mainboard/bcom/winnet100/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/bcom/winnet100/mainboard.c b/src/mainboard/bcom/winnet100/mainboard.c
index 279701d..13089df 100644
--- a/src/mainboard/bcom/winnet100/mainboard.c
+++ b/src/mainboard/bcom/winnet100/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("BCOM WinNET100 Mainboard")
diff --git a/src/mainboard/bcom/winnetp680/chip.h b/src/mainboard/bcom/winnetp680/chip.h
deleted file mode 100644
index 0a2badb..0000000
--- a/src/mainboard/bcom/winnetp680/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/bcom/winnetp680/mainboard.c b/src/mainboard/bcom/winnetp680/mainboard.c
index f467e1b..26fc5e3 100644
--- a/src/mainboard/bcom/winnetp680/mainboard.c
+++ b/src/mainboard/bcom/winnetp680/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("BCOM WinNET P680 Mainboard")
diff --git a/src/mainboard/bifferos/bifferboard/chip.h b/src/mainboard/bifferos/bifferboard/chip.h
deleted file mode 100644
index be42783..0000000
--- a/src/mainboard/bifferos/bifferboard/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
diff --git a/src/mainboard/bifferos/bifferboard/mainboard.c b/src/mainboard/bifferos/bifferboard/mainboard.c
index 5840f95..f3387a3 100644
--- a/src/mainboard/bifferos/bifferboard/mainboard.c
+++ b/src/mainboard/bifferos/bifferboard/mainboard.c
@@ -18,7 +18,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Bifferos Bifferboard")
diff --git a/src/mainboard/biostar/m6tba/chip.h b/src/mainboard/biostar/m6tba/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/biostar/m6tba/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/biostar/m6tba/mainboard.c b/src/mainboard/biostar/m6tba/mainboard.c
index fb6896a..6795284 100644
--- a/src/mainboard/biostar/m6tba/mainboard.c
+++ b/src/mainboard/biostar/m6tba/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Biostar M6TBA Mainboard")
diff --git a/src/mainboard/broadcom/blast/chip.h b/src/mainboard/broadcom/blast/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/broadcom/blast/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/broadcom/blast/mainboard.c b/src/mainboard/broadcom/blast/mainboard.c
index 5f4b525..c556bd5 100644
--- a/src/mainboard/broadcom/blast/mainboard.c
+++ b/src/mainboard/broadcom/blast/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Broadcom Blast Mainboard")
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/chip.h b/src/mainboard/compaq/deskpro_en_sff_p600/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/compaq/deskpro_en_sff_p600/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c b/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c
index 75d7876..d4abb63 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Compaq Deskpro EN SFF P600 Mainboard")
diff --git a/src/mainboard/digitallogic/adl855pc/chip.h b/src/mainboard/digitallogic/adl855pc/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/digitallogic/adl855pc/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/digitallogic/adl855pc/mainboard.c b/src/mainboard/digitallogic/adl855pc/mainboard.c
index c6ab63e..41c34e4 100644
--- a/src/mainboard/digitallogic/adl855pc/mainboard.c
+++ b/src/mainboard/digitallogic/adl855pc/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("DIGITAL-LOGIC ADL855PC Mainboard")
diff --git a/src/mainboard/digitallogic/msm586seg/chip.h b/src/mainboard/digitallogic/msm586seg/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/digitallogic/msm586seg/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/digitallogic/msm586seg/mainboard.c b/src/mainboard/digitallogic/msm586seg/mainboard.c
index 2361059..8f2d8c6 100644
--- a/src/mainboard/digitallogic/msm586seg/mainboard.c
+++ b/src/mainboard/digitallogic/msm586seg/mainboard.c
@@ -4,7 +4,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/amd/sc520.h>
-#include "chip.h"
static void irqdump(void)
diff --git a/src/mainboard/digitallogic/msm800sev/chip.h b/src/mainboard/digitallogic/msm800sev/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/digitallogic/msm800sev/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/digitallogic/msm800sev/mainboard.c b/src/mainboard/digitallogic/msm800sev/mainboard.c
index f4d0e0e..3ade3d6 100644
--- a/src/mainboard/digitallogic/msm800sev/mainboard.c
+++ b/src/mainboard/digitallogic/msm800sev/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/eaglelion/5bcm/chip.h b/src/mainboard/eaglelion/5bcm/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/eaglelion/5bcm/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/eaglelion/5bcm/mainboard.c b/src/mainboard/eaglelion/5bcm/mainboard.c
index c0b3ae0..e1c499e 100644
--- a/src/mainboard/eaglelion/5bcm/mainboard.c
+++ b/src/mainboard/eaglelion/5bcm/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Eaglelion 5BCM Mainboard")
diff --git a/src/mainboard/ecs/p6iwp-fe/chip.h b/src/mainboard/ecs/p6iwp-fe/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/ecs/p6iwp-fe/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/ecs/p6iwp-fe/mainboard.c b/src/mainboard/ecs/p6iwp-fe/mainboard.c
index aec1250..9031ac7 100644
--- a/src/mainboard/ecs/p6iwp-fe/mainboard.c
+++ b/src/mainboard/ecs/p6iwp-fe/mainboard.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/emulation/qemu-x86/chip.h b/src/mainboard/emulation/qemu-x86/chip.h
index 56a14ed..ff9301f 100644
--- a/src/mainboard/emulation/qemu-x86/chip.h
+++ b/src/mainboard/emulation/qemu-x86/chip.h
@@ -1,7 +1,3 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
struct mainboard_emulation_qemu_x86_config {};
extern struct chip_operations mainboard_emulation_qemu_x86_ops;
diff --git a/src/mainboard/emulation/qemu-x86/mainboard.c b/src/mainboard/emulation/qemu-x86/mainboard.c
index e4c9785..f8d0da7 100644
--- a/src/mainboard/emulation/qemu-x86/mainboard.c
+++ b/src/mainboard/emulation/qemu-x86/mainboard.c
@@ -5,7 +5,6 @@
#include <device/pci_ops.h>
#include <pc80/keyboard.h>
#include <arch/io.h>
-#include "chip.h"
/* not sure how these are routed in qemu */
static const unsigned char enetIrqs[4] = { 11, 0, 0, 0 };
diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c
index b7a248d..83b4718 100644
--- a/src/mainboard/getac/p470/mainboard.c
+++ b/src/mainboard/getac/p470/mainboard.c
@@ -25,7 +25,6 @@
#include <arch/io.h>
#include <boot/tables.h>
#include <delay.h>
-#include "chip.h"
#include "hda_verb.h"
#include "ec_oem.c"
diff --git a/src/mainboard/gigabyte/ga-6bxc/chip.h b/src/mainboard/gigabyte/ga-6bxc/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/gigabyte/ga-6bxc/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ga-6bxc/mainboard.c b/src/mainboard/gigabyte/ga-6bxc/mainboard.c
index 01411f3..d43a577 100644
--- a/src/mainboard/gigabyte/ga-6bxc/mainboard.c
+++ b/src/mainboard/gigabyte/ga-6bxc/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("GIGABYTE GA-6BXC Mainboard")
diff --git a/src/mainboard/gigabyte/ga-6bxe/chip.h b/src/mainboard/gigabyte/ga-6bxe/chip.h
deleted file mode 100644
index 8e3af56..0000000
--- a/src/mainboard/gigabyte/ga-6bxe/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ga-6bxe/mainboard.c b/src/mainboard/gigabyte/ga-6bxe/mainboard.c
index 2d04794..281d841 100644
--- a/src/mainboard/gigabyte/ga-6bxe/mainboard.c
+++ b/src/mainboard/gigabyte/ga-6bxe/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("GIGABYTE GA-6BXE Mainboard")
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/chip.h b/src/mainboard/gigabyte/ga_2761gxdk/chip.h
deleted file mode 100644
index 3c303ee..0000000
--- a/src/mainboard/gigabyte/ga_2761gxdk/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Silicon Integrated Systems Corp. (SiS)
- * Written by Morgan Tsai <my_tsai@sis.com> for SiS.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
index e365575..e8b8969 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mainboard.c
@@ -24,7 +24,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("GIGABYTE GA-2761GXDK Mainboard")
diff --git a/src/mainboard/gigabyte/m57sli/chip.h b/src/mainboard/gigabyte/m57sli/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/gigabyte/m57sli/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/m57sli/mainboard.c b/src/mainboard/gigabyte/m57sli/mainboard.c
index b198fb6..dffa769 100644
--- a/src/mainboard/gigabyte/m57sli/mainboard.c
+++ b/src/mainboard/gigabyte/m57sli/mainboard.c
@@ -25,7 +25,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
// #include "hda_verb.h"
-#include "chip.h"
static void verb_setup(void)
{
diff --git a/src/mainboard/gigabyte/ma785gm/chip.h b/src/mainboard/gigabyte/ma785gm/chip.h
deleted file mode 100644
index 70102aa..0000000
--- a/src/mainboard/gigabyte/ma785gm/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index 254df00..4147f60 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/gigabyte/ma785gmt/chip.h b/src/mainboard/gigabyte/ma785gmt/chip.h
deleted file mode 100644
index 70102aa..0000000
--- a/src/mainboard/gigabyte/ma785gmt/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index 8d669ba..5992935 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
diff --git a/src/mainboard/gigabyte/ma78gm/chip.h b/src/mainboard/gigabyte/ma78gm/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/gigabyte/ma78gm/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index ee353ed..fb667c8 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig
new file mode 100644
index 0000000..5e41a8d
--- /dev/null
+++ b/src/mainboard/google/Kconfig
@@ -0,0 +1,25 @@
+if VENDOR_GOOGLE
+
+choice
+ prompt "Mainboard model"
+
+config BOARD_GOOGLE_BUTTERFLY
+ bool "Butterfly"
+config BOARD_GOOGLE_PARROT
+ bool "Parrot"
+config BOARD_GOOGLE_LINK
+ bool "Link"
+config BOARD_GOOGLE_STOUT
+ bool "Stout"
+endchoice
+
+source "src/mainboard/google/butterfly/Kconfig"
+source "src/mainboard/google/link/Kconfig"
+source "src/mainboard/google/parrot/Kconfig"
+source "src/mainboard/google/stout/Kconfig"
+
+config MAINBOARD_VENDOR
+ string
+ default "GOOGLE"
+
+endif # VENDOR_GOOGLE
diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig
new file mode 100644
index 0000000..defd3d6
--- /dev/null
+++ b/src/mainboard/google/butterfly/Kconfig
@@ -0,0 +1,61 @@
+if BOARD_GOOGLE_BUTTERFLY
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_QUANTA_ENE_KB3940Q
+ select BOARD_HAS_FADT
+ select BOARD_ROMSIZE_KB_1024
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_MAINBOARD_RESOURCES
+ select MMCONF_SUPPORT
+ select HAVE_SMI_HANDLER
+ select GFXUMA
+ select CHROMEOS
+ select EXTERNAL_MRC_BLOB
+
+ # Workaround for EC/KBC IRQ1.
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default google/butterfly
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Butterfly"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0xc000
+
+config MAINBOARD_VENDOR
+ string
+ default "Hewlett-Packard"
+
+endif # BOARD_GOOGLE_BUTTERFLY
diff --git a/src/mainboard/google/butterfly/Makefile.inc b/src/mainboard/google/butterfly/Makefile.inc
new file mode 100644
index 0000000..9e753fb
--- /dev/null
+++ b/src/mainboard/google/butterfly/Makefile.inc
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
+SRC_ROOT = $(src)/mainboard/google/butterfly
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/butterfly/acpi/chromeos.asl
similarity index 70%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/butterfly/acpi/chromeos.asl
index 3ae8657..27373e1 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/butterfly/acpi/chromeos.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+Name(OIPG, Package() {
+ Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
+ Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
+ Package() { 0x003, 0, 6, "PantherPoint" }, // firmware write protect
+})
-struct mainboard_config {};
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/butterfly/acpi/ec.asl
similarity index 74%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/butterfly/acpi/ec.asl
index 3ae8657..bb053cd 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/butterfly/acpi/ec.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+/* mainboard configuration */
+#include "../ec.h"
-struct mainboard_config {};
+#define EC_SCI 13 // GPIO13 -> Runtime SCI
+
+/* ACPI code for EC functions */
+#include <ec/quanta/ene_kb3940q/acpi/ec.asl>
diff --git a/src/mainboard/google/butterfly/acpi/mainboard.asl b/src/mainboard/google/butterfly/acpi/mainboard.asl
new file mode 100644
index 0000000..c6e35e8
--- /dev/null
+++ b/src/mainboard/google/butterfly/acpi/mainboard.asl
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+ Device (LID0)
+ {
+ Name (_HID, EisaId("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDF, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId("PNP0C0C"))
+ }
+
+ Device (TPAD)
+ {
+ Name (_ADR, 0x0)
+ Name (_UID, 1)
+
+ // Report as a Sleep Button device so Linux will
+ // automatically enable it as a wake source
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Trackpad Wake is GPIO11, wake from S3
+ Name(_PRW, Package(){0x1b, 0x03})
+
+ Name(_CRS, ResourceTemplate()
+ {
+ // PIRQG -> GSI22
+ Interrupt (ResourceConsumer, EDGE, ActiveLow) {22}
+
+ // SMBUS Address 0x67
+ VendorShort (ADDR) {0x67}
+ })
+ }
+
+}
+
+// Battery information
+Name (BATV, "GOOGLE")
diff --git a/src/mainboard/google/butterfly/acpi/platform.asl b/src/mainboard/google/butterfly/acpi/platform.asl
new file mode 100644
index 0000000..5c84ba1
--- /dev/null
+++ b/src/mainboard/google/butterfly/acpi/platform.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Update in case state changed while asleep */
+ /* Update AC status */
+ Store (\_SB.PCI0.LPCB.EC0.ADPT, Local0)
+ if (LNotEqual (Local0, \PWRS)) {
+ Store (Local0, \PWRS)
+ Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
+ }
+
+ /* Update LID status */
+ Store (\_SB.PCI0.LPCB.EC0.LIDF, Local0)
+ if (LNotEqual (Local0, \LIDS)) {
+ Store (Local0, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..ba725ac
--- /dev/null
+++ b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI)
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB
+ Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF
+ Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI)
+ Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH
+ Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/butterfly/acpi/superio.asl
similarity index 72%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/butterfly/acpi/superio.asl
index 3ae8657..2089604 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/butterfly/acpi/superio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,10 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+/* mainboard configuration */
+#include "../ec.h"
-struct mainboard_config {};
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/quanta/ene_kb3940q/acpi/superio.asl>
diff --git a/src/mainboard/google/butterfly/acpi/thermal.asl b/src/mainboard/google/butterfly/acpi/thermal.asl
new file mode 100644
index 0000000..5e0dd43
--- /dev/null
+++ b/src/mainboard/google/butterfly/acpi/thermal.asl
@@ -0,0 +1,81 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ // Get CPU Temperature from EC
+ Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0)
+
+ // Convert to 1/10 Kelvin
+ Multiply (Local0, 10, Local0)
+
+ // Adjust by offset to get Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+// The EC does all fan control. The is no Active Cooling Fan control (_ACx).
+ }
+}
+
diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/google/butterfly/acpi/video.asl
similarity index 71%
rename from src/mainboard/roda/rk886ex/chip.h
rename to src/mainboard/google/butterfly/acpi/video.asl
index 6f24f71..3ececa9 100644
--- a/src/mainboard/roda/rk886ex/chip.h
+++ b/src/mainboard/google/butterfly/acpi/video.asl
@@ -17,5 +17,27 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/butterfly/acpi_tables.c b/src/mainboard/google/butterfly/acpi_tables.c
new file mode 100644
index 0000000..30085ac
--- /dev/null
+++ b/src/mainboard/google/butterfly/acpi_tables.c
@@ -0,0 +1,306 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ /* EC handles all thermal and fan control on Butterfly. */
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs_ = gnvs;
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+ // TODO: MLR
+ // The firmware read/write status is a "virtual" switch and
+ // will be handled elsewhere. Until then hard-code to
+ // read/write instead of read-only for developer mode.
+ gnvs->chromeos.vbt2 = ACTIVE_ECFW_RW;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+ acpi_update_thermal_table(gnvs);
+
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfed00000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x8086a201; /* Intel */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0080;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_intel_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, "COREBOOT");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/google/butterfly/chromeos.c b/src/mainboard/google/butterfly/chromeos.c
new file mode 100644
index 0000000..41abd95
--- /dev/null
+++ b/src/mainboard/google/butterfly/chromeos.c
@@ -0,0 +1,171 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+#define WP_GPIO 6
+#define DEVMODE_GPIO 54
+#define FORCE_RECOVERY_MODE 0
+#define FORCE_DEVELOPER_MODE 0
+
+
+int get_pch_gpio(unsigned char gpio_num);
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT 6
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
+
+ int lidswitch=0;
+ if (!gpio_base)
+ return;
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ /* Write Protect: GPIO active Low */
+ gpios->gpios[0].port = WP_GPIO;
+ gpios->gpios[0].polarity = ACTIVE_LOW;
+ gpios->gpios[0].value = get_pch_gpio(WP_GPIO);
+ strncpy((char *)gpios->gpios[0].name,"write protect",
+ GPIO_MAX_NAME_LENGTH);
+
+ /* Recovery: virtual GPIO active high */
+ gpios->gpios[1].port = -1;
+ gpios->gpios[1].polarity = ACTIVE_HIGH;
+ gpios->gpios[1].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+ /* Developer: virtual GPIO active high */
+ gpios->gpios[2].port = -1;
+ gpios->gpios[2].polarity = ACTIVE_HIGH;
+ gpios->gpios[2].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[2].name,"developer",
+ GPIO_MAX_NAME_LENGTH);
+
+ /* lid switch value from EC */
+ lidswitch = (ec_mem_read(EC_HW_GPI_STATUS) >> EC_GPI_LID_STAT_BIT) & 1;
+ gpios->gpios[3].port = -1;
+ gpios->gpios[3].polarity = ACTIVE_HIGH;
+ gpios->gpios[3].value = lidswitch;
+ strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+ printk(BIOS_DEBUG,"LID SWITCH FROM EC: %x\n", lidswitch);
+
+ /* Power Button - Hardcode Low as power button may still be pressed
+ when read here.*/
+ gpios->gpios[4].port = -1;
+ gpios->gpios[4].polarity = ACTIVE_HIGH;
+ gpios->gpios[4].value = 0;
+ strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+
+ /* Was VGA Option ROM loaded? */
+ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[5].polarity = ACTIVE_HIGH;
+ gpios->gpios[5].value = oprom_is_loaded;
+ strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+
+}
+#endif
+
+int get_pch_gpio(unsigned char gpio_num)
+{
+ device_t dev;
+ int retval = 0;
+
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+ u16 gpio_base = pci_read_config16(dev, GPIOBASE) & 0xfffe;
+
+ if (!gpio_base)
+ return(0);
+
+ if (gpio_num > 64){
+ u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
+ retval = ((gp_lvl3 >> (gpio_num - 64)) & 1);
+ } else if (gpio_num > 32){
+ u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
+ retval = ((gp_lvl2 >> (gpio_num - 32)) & 1);
+ } else {
+ u32 gp_lvl = inl(gpio_base + GP_LVL);
+ retval = ((gp_lvl >> gpio_num) & 1);
+ }
+
+ return retval;
+}
+
+int get_developer_mode_switch(void)
+{
+ int dev_mode = 0;
+
+#if FORCE_DEVELOPER_MODE
+ printk(BIOS_DEBUG,"FORCING DEVELOPER MODE.\n");
+ return 1;
+#endif
+
+ /* Servo GPIO is active low, reverse it for intial state (request) */
+ dev_mode = !get_pch_gpio(DEVMODE_GPIO);
+ printk(BIOS_DEBUG,"DEVELOPER MODE FROM GPIO %d: %x\n",DEVMODE_GPIO,
+ dev_mode);
+
+ return dev_mode;
+}
+
+int get_recovery_mode_switch(void)
+{
+ int ec_rec_mode = 0;
+
+#if FORCE_RECOVERY_MODE
+ printk(BIOS_DEBUG,"FORCING RECOVERY MODE.\n");
+ return 1;
+#endif
+
+
+#ifndef __PRE_RAM__
+ if (ec_mem_read(EC_CODE_STATE) == EC_COS_EC_RO) {
+ ec_rec_mode = 1;
+ }
+ printk(BIOS_DEBUG,"RECOVERY MODE FROM EC: %x\n", ec_rec_mode);
+#endif
+
+ return ec_rec_mode;
+}
diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout
new file mode 100644
index 0000000..afdd3c6
--- /dev/null
+++ b/src/mainboard/google/butterfly/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb
new file mode 100644
index 0000000..d4e2ccd
--- /dev/null
+++ b/src/mainboard/google/butterfly/devicetree.cb
@@ -0,0 +1,105 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
+ register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
+ register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
+
+ device lapic_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Coordinate with HW_ALL
+ register "pstate_coord_type" = "0xfe"
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device pci_domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 01.0 off end # PCIe Bridge for discrete graphics
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0000"
+ #register "gpi1_routing" = "1" #SMI from EC
+ register "gpi13_routing" = "2" #SCI from EC
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ register "sata_port_map" = "0x3" #enable SATA ports 0 & 1
+
+ # Enable EC Port 0x68/0x6C
+ register "gen1_dec" = "0x00040069"
+
+ # EC range is 0x380-0387
+ register "gen2_dec" = "0x00040381"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug)
+ device pci 1c.1 on end # PCIe Port #2 (ETH0)
+ device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+ #force ASPM for PCIe bridge to Card Reader
+ register "pcie_aspm_f2" = "0x3"
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on #LPC bridge
+ chip ec/quanta/ene_kb3940q
+ # 60/64 KBC
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl
new file mode 100644
index 0000000..608827a
--- /dev/null
+++ b/src/mainboard/google/butterfly/dsdt.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include "acpi/thermal.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/butterfly/ec.c b/src/mainboard/google/butterfly/ec.c
new file mode 100644
index 0000000..dd2298d
--- /dev/null
+++ b/src/mainboard/google/butterfly/ec.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+void butterfly_ec_init(void)
+{
+ printk(BIOS_DEBUG, "Butterfly EC Init\n");
+
+ /* Report EC info */
+ /* EC version: 6 bytes */
+ printk(BIOS_DEBUG," EC version: %c%c%c%c%c%c\n",
+ ec_mem_read(EC_FW_VER0), ec_mem_read(EC_FW_VER1),
+ ec_mem_read(EC_FW_VER2), ec_mem_read(EC_FW_VER3),
+ ec_mem_read(EC_FW_VER4), ec_mem_read(EC_FW_VER5));
+
+ /* Disable wake on USB, LAN & RTC */
+ /* Enable Wake from Keyboard */
+ ec_mem_write(EC_EC_PSW, EC_PSW_IKB);
+
+}
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/butterfly/ec.h
similarity index 70%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/butterfly/ec.h
index 3ae8657..5bbbd5a 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/butterfly/ec.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+#ifndef BUTTERFLY_EC_H
+#define BUTTERFLY_EC_H
-struct mainboard_config {};
+#define EC_SCI_GPI 13 /* GPIO13 is EC_SCI# */
+
+/* EC SMI sources TODO: MLR- make defines */
+
+#ifndef __ACPI__
+extern void butterfly_ec_init(void);
+#endif
+
+#endif // BUTTERFLY_EC_H
diff --git a/src/mainboard/google/butterfly/fadt.c b/src/mainboard/google/butterfly/fadt.c
new file mode 100644
index 0000000..77f4d04
--- /dev/null
+++ b/src/mainboard/google/butterfly/fadt.c
@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT 0xb2
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
+#define ACPI_DISABLE 0x1e
+#define ACPI_ENABLE 0xe1
+#define GNVS_UPDATE 0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 101; /* c2 not supported */
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD |
+ ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER |
+ ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE |
+ ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/butterfly/gpio.h b/src/mainboard/google/butterfly/gpio.h
new file mode 100644
index 0000000..5448299
--- /dev/null
+++ b/src/mainboard/google/butterfly/gpio.h
@@ -0,0 +1,304 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_GPIO_H
+#define BUTTERFLY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NONE, /* Unused */
+ .gpio1 = GPIO_MODE_NONE, /* Unused */
+ .gpio2 = GPIO_MODE_NONE, /* Unused */
+ .gpio3 = GPIO_MODE_NONE, /* Unused */
+ .gpio4 = GPIO_MODE_NATIVE, /* Native - TPSINT# for TP SMBus IRQ */
+ .gpio5 = GPIO_MODE_NONE, /* Unused */
+ .gpio6 = GPIO_MODE_GPIO, /* Input - BOARD_ID4 */
+ .gpio7 = GPIO_MODE_GPIO, /* Input - BOARD_ID5 */
+ .gpio8 = GPIO_MODE_GPIO, /* Output - BT on/off */
+ .gpio9 = GPIO_MODE_NONE, /* Unused */
+ .gpio10 = GPIO_MODE_NONE, /* Unused */
+ .gpio11 = GPIO_MODE_GPIO, /* Input - TP WAKEUP Event */
+ .gpio12 = GPIO_MODE_NONE, /* Unused */
+ .gpio13 = GPIO_MODE_GPIO, /* Input - SCI from EC */
+ .gpio14 = GPIO_MODE_GPIO, /* Output - AOAC WLAN power control */
+ .gpio15 = GPIO_MODE_GPIO, /* Unused - Do not control WLAN*/
+ .gpio16 = GPIO_MODE_NONE, /* Unused */
+ .gpio17 = GPIO_MODE_GPIO, /* Input - DGPU_PWROK */
+ .gpio18 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ1# LAN clock pin*/
+ .gpio19 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 0 */
+ .gpio20 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ2# SDCard clock pin */
+ .gpio21 = GPIO_MODE_GPIO, /* Input - EC_ENTERING_RW for Google OS */
+ .gpio22 = GPIO_MODE_GPIO, /* Input - BIOS RECOVERY */
+ .gpio23 = GPIO_MODE_NONE, /* Unused */
+ .gpio24 = GPIO_MODE_GPIO, /* Output - DGPU_HOLD_RST# */
+ .gpio25 = GPIO_MODE_NONE, /* Unused */
+ .gpio26 = GPIO_MODE_NONE, /* Unused */
+ .gpio27 = GPIO_MODE_NONE, /* Unused */
+ .gpio28 = GPIO_MODE_NONE, /* Unused */
+ .gpio29 = GPIO_MODE_NONE, /* Unused */
+ .gpio30 = GPIO_MODE_NATIVE, /* Native - SUSWARN_EC# */
+ .gpio31 = GPIO_MODE_NONE, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT, /* Unused */
+ .gpio1 = GPIO_DIR_INPUT, /* Unused */
+ .gpio2 = GPIO_DIR_INPUT, /* Unused */
+ .gpio3 = GPIO_DIR_INPUT, /* Unused */
+ .gpio4 = GPIO_DIR_INPUT, /* Native */
+ .gpio5 = GPIO_DIR_INPUT, /* Unused */
+ .gpio6 = GPIO_DIR_INPUT, /* Input */
+ .gpio7 = GPIO_DIR_INPUT, /* Input */
+ .gpio8 = GPIO_DIR_INPUT, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_DIR_INPUT, /* Unused */
+ .gpio10 = GPIO_DIR_INPUT, /* Unused */
+ .gpio11 = GPIO_DIR_INPUT, /* Input */
+ .gpio12 = GPIO_DIR_INPUT, /* Unused */
+ .gpio13 = GPIO_DIR_INPUT, /* Input */
+ .gpio14 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio15 = GPIO_DIR_INPUT, /* Unused */
+ .gpio16 = GPIO_DIR_INPUT, /* Unused */
+ .gpio17 = GPIO_DIR_INPUT, /* Input */
+ .gpio18 = GPIO_DIR_INPUT, /* Native */
+ .gpio19 = GPIO_DIR_INPUT, /* Input */
+ .gpio20 = GPIO_DIR_INPUT, /* Native */
+ .gpio21 = GPIO_DIR_INPUT, /* Input */
+ .gpio22 = GPIO_DIR_INPUT, /* Input */
+ .gpio23 = GPIO_DIR_INPUT, /* Unused */
+ .gpio24 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio25 = GPIO_DIR_INPUT, /* Unused */
+ .gpio26 = GPIO_DIR_INPUT, /* Unused */
+ .gpio27 = GPIO_DIR_INPUT, /* Unused */
+ .gpio28 = GPIO_DIR_INPUT, /* Unused */
+ .gpio29 = GPIO_DIR_INPUT, /* Unused */
+ .gpio30 = GPIO_DIR_INPUT, /* Native */
+ .gpio31 = GPIO_DIR_INPUT, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio1 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio2 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio3 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio4 = GPIO_LEVEL_LOW, /* Native */
+ .gpio5 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio6 = GPIO_LEVEL_LOW, /* Input */
+ .gpio7 = GPIO_LEVEL_LOW, /* Input */
+ .gpio8 = GPIO_LEVEL_HIGH, /* Output HIGH - set in mainboard.c */
+ .gpio9 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio10 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio11 = GPIO_LEVEL_LOW, /* Input */
+ .gpio12 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio13 = GPIO_LEVEL_LOW, /* Input */
+ .gpio14 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio15 = GPIO_LEVEL_HIGH, /* Unused */
+ .gpio16 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio17 = GPIO_LEVEL_LOW, /* Input */
+ .gpio18 = GPIO_LEVEL_LOW, /* Native */
+ .gpio19 = GPIO_LEVEL_LOW, /* Input */
+ .gpio20 = GPIO_LEVEL_LOW, /* Native */
+ .gpio21 = GPIO_LEVEL_LOW, /* Input */
+ .gpio22 = GPIO_LEVEL_LOW, /* Input */
+ .gpio23 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio24 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio25 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio26 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio27 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio28 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio29 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio30 = GPIO_LEVEL_LOW, /* Native */
+ .gpio31 = GPIO_LEVEL_LOW, /* Unused */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio11 = GPIO_INVERT, /* invert touchpad wakeup pin */
+ .gpio13 = GPIO_INVERT, /* invert EC SCI pin */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE, /* Native - Connect to EC Clock Run */
+ .gpio33 = GPIO_MODE_GPIO, /* Input - (Google protect BIOS ROM) */
+ .gpio34 = GPIO_MODE_NONE, /* Unused */
+ .gpio35 = GPIO_MODE_NONE, /* Unused */
+ .gpio36 = GPIO_MODE_GPIO, /* Output - DGPU_PWR_EN */
+ .gpio37 = GPIO_MODE_GPIO, /* Input - FDI TERM / VOLTAGE OVERRIDE */
+ .gpio38 = GPIO_MODE_GPIO, /* Input - MFG_MODE test */
+ .gpio39 = GPIO_MODE_GPIO, /* Input - DGPU_PRSNT */
+ .gpio40 = GPIO_MODE_NONE, /* Unused */
+ .gpio41 = GPIO_MODE_NONE, /* Unused */
+ .gpio42 = GPIO_MODE_NONE, /* Unused */
+ .gpio43 = GPIO_MODE_NONE, /* Unused */
+ .gpio44 = GPIO_MODE_GPIO, /* Input - BOARD_ID0 */
+ .gpio45 = GPIO_MODE_GPIO, /* Input - BOARD_ID1 */
+ .gpio46 = GPIO_MODE_GPIO, /* Input - BOARD_ID2 */
+ .gpio47 = GPIO_MODE_NATIVE, /* Native - PEGA_GPU clock request */
+ .gpio48 = GPIO_MODE_NONE, /* Unused */
+ .gpio49 = GPIO_MODE_NONE, /* Unused */
+ .gpio50 = GPIO_MODE_NONE, /* Unused */
+ .gpio51 = GPIO_MODE_GPIO, /* Input - Boot BIOS Selection 1 */
+ .gpio52 = GPIO_MODE_GPIO, /* Input - Google recovery, Pull up +3V */
+ .gpio53 = GPIO_MODE_GPIO, /* Output - G Sensor LED */
+ .gpio54 = GPIO_MODE_GPIO, /* Input - Google Development */
+ .gpio55 = GPIO_MODE_GPIO, /* Input - Top-Block Swap Override */
+ .gpio56 = GPIO_MODE_NONE, /* Unused */
+ .gpio57 = GPIO_MODE_GPIO, /* Input - SV_DET */
+ .gpio58 = GPIO_MODE_NONE, /* Unused */
+ .gpio59 = GPIO_MODE_NONE, /* Unused */
+ .gpio60 = GPIO_MODE_NONE, /* GPO - DRAMRST_CNTRL_PCH */
+ .gpio61 = GPIO_MODE_NONE, /* Unused */
+ .gpio62 = GPIO_MODE_NATIVE, /* Native - Connect to EC 32.768KHz */
+ .gpio63 = GPIO_MODE_NATIVE, /* Native - SLP_S5 */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT, /* Native */
+ .gpio33 = GPIO_DIR_INPUT, /* Input */
+ .gpio34 = GPIO_DIR_INPUT, /* Unused */
+ .gpio35 = GPIO_DIR_INPUT, /* Unused */
+ .gpio36 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio37 = GPIO_DIR_INPUT, /* Input */
+ .gpio38 = GPIO_DIR_INPUT, /* Input */
+ .gpio39 = GPIO_DIR_INPUT, /* Input */
+ .gpio40 = GPIO_DIR_INPUT, /* Unused */
+ .gpio41 = GPIO_DIR_INPUT, /* Unused */
+ .gpio42 = GPIO_DIR_INPUT, /* Unused */
+ .gpio43 = GPIO_DIR_INPUT, /* Unused */
+ .gpio44 = GPIO_DIR_INPUT, /* Input */
+ .gpio45 = GPIO_DIR_INPUT, /* Input */
+ .gpio46 = GPIO_DIR_INPUT, /* Input */
+ .gpio47 = GPIO_DIR_INPUT, /* Native */
+ .gpio48 = GPIO_DIR_INPUT, /* Unused */
+ .gpio49 = GPIO_DIR_INPUT, /* Unused */
+ .gpio50 = GPIO_DIR_INPUT, /* Unused */
+ .gpio51 = GPIO_DIR_INPUT, /* Input */
+ .gpio52 = GPIO_DIR_INPUT, /* Input */
+ .gpio53 = GPIO_DIR_OUTPUT, /* Input */
+ .gpio54 = GPIO_DIR_INPUT, /* Input */
+ .gpio55 = GPIO_DIR_INPUT, /* Input */
+ .gpio56 = GPIO_DIR_INPUT, /* Unused */
+ .gpio57 = GPIO_DIR_INPUT, /* Input */
+ .gpio58 = GPIO_DIR_INPUT, /* Unused */
+ .gpio59 = GPIO_DIR_INPUT, /* Unused */
+ .gpio60 = GPIO_DIR_OUTPUT, /* Output HIGH */
+ .gpio61 = GPIO_DIR_INPUT, /* Unused */
+ .gpio62 = GPIO_DIR_INPUT, /* Native */
+ .gpio63 = GPIO_DIR_INPUT, /* Native */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW, /* Native */
+ .gpio33 = GPIO_LEVEL_LOW, /* Input */
+ .gpio34 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio35 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio36 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio37 = GPIO_LEVEL_LOW, /* Input */
+ .gpio38 = GPIO_LEVEL_LOW, /* Input */
+ .gpio39 = GPIO_LEVEL_LOW, /* Input */
+ .gpio40 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio41 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio42 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio43 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio44 = GPIO_LEVEL_LOW, /* Input */
+ .gpio45 = GPIO_LEVEL_LOW, /* Input */
+ .gpio46 = GPIO_LEVEL_LOW, /* Input */
+ .gpio47 = GPIO_LEVEL_LOW, /* Native */
+ .gpio48 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio49 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio50 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio51 = GPIO_LEVEL_LOW, /* Input */
+ .gpio52 = GPIO_LEVEL_LOW, /* Input */
+ .gpio53 = GPIO_LEVEL_HIGH, /* Input */
+ .gpio54 = GPIO_LEVEL_LOW, /* Input */
+ .gpio55 = GPIO_LEVEL_LOW, /* Input */
+ .gpio56 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio57 = GPIO_LEVEL_LOW, /* Input */
+ .gpio58 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio59 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio60 = GPIO_LEVEL_HIGH, /* Output HIGH */
+ .gpio61 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio62 = GPIO_LEVEL_LOW, /* Native */
+ .gpio63 = GPIO_LEVEL_LOW, /* Native */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NONE, /* Unused */
+ .gpio65 = GPIO_MODE_NONE, /* Unused */
+ .gpio66 = GPIO_MODE_NONE, /* Unused */
+ .gpio67 = GPIO_MODE_NONE, /* Unused */
+ .gpio68 = GPIO_MODE_GPIO, /* Input - DGPU_PWR_EN */
+ .gpio69 = GPIO_MODE_NONE, /* Unused */
+ .gpio70 = GPIO_MODE_NONE, /* Unused */
+ .gpio71 = GPIO_MODE_NONE, /* Unused */
+ .gpio72 = GPIO_MODE_NONE, /* Unused */
+ .gpio73 = GPIO_MODE_NATIVE, /* Native - PCIECLKRQ0# WLAN clock request */
+ .gpio74 = GPIO_MODE_NONE, /* Unused */
+ .gpio75 = GPIO_MODE_GPIO, /* Input - SMB_ME1_DAT */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT, /* Unused */
+ .gpio65 = GPIO_DIR_INPUT, /* Unused */
+ .gpio66 = GPIO_DIR_INPUT, /* Unused */
+ .gpio67 = GPIO_DIR_INPUT, /* Unused */
+ .gpio68 = GPIO_DIR_INPUT, /* Input */
+ .gpio69 = GPIO_DIR_INPUT, /* Unused */
+ .gpio70 = GPIO_DIR_INPUT, /* Unused */
+ .gpio71 = GPIO_DIR_INPUT, /* Unused */
+ .gpio72 = GPIO_DIR_INPUT, /* Unused */
+ .gpio73 = GPIO_DIR_INPUT, /* Native */
+ .gpio74 = GPIO_DIR_INPUT, /* Unused */
+ .gpio75 = GPIO_DIR_INPUT, /* Input */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio65 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio66 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio67 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio68 = GPIO_LEVEL_LOW, /* Input */
+ .gpio69 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio70 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio71 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio72 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio73 = GPIO_LEVEL_LOW, /* Native */
+ .gpio74 = GPIO_LEVEL_LOW, /* Unused */
+ .gpio75 = GPIO_LEVEL_LOW, /* Input */
+};
+
+const struct pch_gpio_map butterfly_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+#endif
diff --git a/src/mainboard/google/butterfly/hda_verb.h b/src/mainboard/google/butterfly/hda_verb.h
new file mode 100644
index 0000000..1901a68
--- /dev/null
+++ b/src/mainboard/google/butterfly/hda_verb.h
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Vendor Name : IDT
+ * Vendor ID : 0x111d76e5
+ * Subsystem ID : 0x103c18f9
+ * Revision ID : 0x100303
+ */
+
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x111D76E5, // Codec Vendor / Device ID: IDT 92HD99
+ 0x103C18F9, // Subsystem ID
+ 0x00000073, // Number of 4 dword sets
+
+/* Bits 31:28 - Codec Address */
+/* Bits 27:20 - NID */
+/* Bits 19:8 - Verb ID */
+/* Bits 7:0 - Payload */
+
+/* NID 0x01 - NodeInfo */
+ 0x001720F9,
+ 0x00172118,
+ 0x0017223C,
+ 0x00172310,
+
+/* NID 0x0A - External Microphone Connector
+ * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00A71C20,
+ 0x00A71D10,
+ 0x00A71EA1,
+ 0x00A71F04,
+
+/* NID 0x0B - Headphone Connector
+ * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
+ */
+ 0x00B71C1F,
+ 0x00B71D10,
+ 0x00B71E21,
+ 0x00B71F04,
+
+/* NID 0x0C - Not connected
+ * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
+ */
+ 0x00C71CF0,
+ 0x00C71D00,
+ 0x00C71EF0,
+ 0x00C71F40,
+
+/* NID 0x0D - Internal Speakers
+ * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
+ */
+ 0x00D71C10,
+ 0x00D71D01,
+ 0x00D71E17,
+ 0x00D71F90,
+
+/* NID 0x0F - Not connected
+ * Config=0x40F000F0
+ */
+ 0x00F71CF0,
+ 0x00F71D00,
+ 0x00F71EF0,
+ 0x00F71F40,
+
+/* NID 0x11 - Internal Microphone
+ * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
+ */
+ 0x01171C40,
+ 0x01171D01,
+ 0x01171EA3,
+ 0x01171FD5,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 88200
+ */
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80,
+ 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981,
+ 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80,
+ 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F,
+ 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80,
+ 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E,
+ 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80,
+ 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1,
+ 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80,
+ 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E,
+ 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80,
+ 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983,
+ 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80,
+ 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D,
+ 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80,
+ 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C,
+ 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80,
+ 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3,
+ 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80,
+ 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F,
+ 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80,
+ 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982,
+ 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80,
+ 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E,
+ 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80,
+ 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D,
+ 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80,
+ 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2,
+ 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80,
+ 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F,
+ 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80,
+ 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E,
+ 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80,
+ 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937,
+ 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80,
+ 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971,
+ 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80,
+ 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9,
+ 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80,
+ 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942,
+ 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80,
+ 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C,
+ 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80,
+ 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934,
+ 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80,
+ 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963,
+ 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80,
+ 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9,
+ 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80,
+
+ /*
+ * Hardware EQ Parameters
+ * Sample Rate 96000
+ */
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80,
+ 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981,
+ 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80,
+ 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F,
+ 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80,
+ 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E,
+ 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80,
+ 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1,
+ 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80,
+ 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E,
+ 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80,
+ 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983,
+ 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80,
+ 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D,
+ 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80,
+ 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C,
+ 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80,
+ 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3,
+ 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80,
+ 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F,
+ 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80,
+ 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982,
+ 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80,
+ 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E,
+ 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80,
+ 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D,
+ 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80,
+ 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1,
+ 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80,
+ 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F,
+ 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80,
+ 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D,
+ 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80,
+ 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938,
+ 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80,
+ 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972,
+ 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80,
+ 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8,
+ 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80,
+ 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941,
+ 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80,
+ 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999,
+ 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80,
+ 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934,
+ 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80,
+ 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966,
+ 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80,
+ 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9,
+ 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80,
+ 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940,
+ 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80,
+
+ /* SAFEDSP Parameters */
+ 0x022782C1, 0x02277127, 0x02277227, 0x02278801,
+ 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14,
+ 0x02278B0F, 0x0017B008,
+
+ /* Misc entries */
+ 0x00B707C0, /* Enable PortB as Output with HP amp */
+ 0x00D70740, /* Enable PortD as Output */
+ 0x0017A200, /* Disable ClkEn of PortSenseTst */
+ 0x0017C621, /* Slave Port - Port A used as microphone input for
+ combo Jack
+ Master Port - Port B used for Jack Presence Detect
+ Enable Combo Jack Detection */
+ 0x0017A208, /* Enable ClkEn of PortSenseTst */
+ 0x00170500, /* Set power state to D0 */
+
+ /* --- Next Codec --- */
+
+/* Vendor Name : Intel
+ * Vendor ID : 0x80862806
+ * Subsystem ID : 0x80860101
+ * Revision ID : 0x100000
+ */
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of IDs
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ 0x30172001,
+ 0x30172101,
+ 0x30172286,
+ 0x30172380,
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ 0x30571c10,
+ 0x30571d00,
+ 0x30571e56,
+ 0x30571f18,
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ 0x30671c20,
+ 0x30671d00,
+ 0x30671e56,
+ 0x30671f18,
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ 0x30771c30,
+ 0x30771d00,
+ 0x30771e56,
+ 0x30771f18
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
+};
+
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
+
+
diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c
new file mode 100644
index 0000000..dea4dc1
--- /dev/null
+++ b/src/mainboard/google/butterfly/mainboard.c
@@ -0,0 +1,513 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <device/pci.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include <vendorcode/google/chromeos/fmap.h>
+
+static unsigned int search(char *p, char *a, unsigned int lengthp,
+ unsigned int lengtha)
+{
+ int i, j;
+
+ /* Searching */
+ for (j = 0; j <= lengtha - lengthp; j++) {
+ for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ;
+ if (i >= lengthp)
+ return j;
+ }
+ return lengtha;
+}
+
+static unsigned char get_hex_digit(char *offset)
+{
+ unsigned char retval = 0;
+
+ retval = *offset - '0';
+ if (retval > 0x09) {
+ retval = *offset - 'A' + 0x0A;
+ if (retval > 0x0F)
+ retval = *offset - 'a' + 0x0a;
+ }
+ if (retval > 0x0F) {
+ printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", *offset,
+ (unsigned char)*offset);
+ retval = 0;
+ }
+
+ return retval;
+}
+
+static int get_mac_address(u32 *high_dword, u32 *low_dword,
+ u32 search_address, u32 search_length)
+{
+ char key[] = "ethernet_mac";
+ unsigned int offset;
+ int i;
+
+ offset = search(key, (char *)search_address,
+ sizeof(key) - 1, search_length);
+ if (offset == search_length) {
+ printk(BIOS_DEBUG,
+ "Error: Could not locate '%s' in VPD\n", key);
+ return 0;
+ }
+ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
+
+ offset += sizeof(key); /* move to next character */
+ *high_dword = 0;
+
+ /* Fetch the MAC address and put the octets in the correct order to
+ * be programmed.
+ *
+ * From RTL8105E_Series_EEPROM-Less_App_Note_1.1
+ * If the MAC address is 001122334455h:
+ * Write 33221100h to I/O register offset 0x00 via double word access
+ * Write 00005544h to I/O register offset 0x04 via double word access
+ */
+
+ for (i = 0; i < 4; i++) {
+ *high_dword |= (get_hex_digit((char *)(search_address + offset))
+ << (4 + (i * 8)));
+ *high_dword |= (get_hex_digit((char *)(search_address + offset + 1))
+ << (i * 8));
+ offset += 3;
+ }
+
+ *low_dword = 0;
+ for (i = 0; i < 2; i++) {
+ *low_dword |= (get_hex_digit((char *)(search_address + offset))
+ << (4 + (i * 8)));
+ *low_dword |= (get_hex_digit((char *)(search_address + offset + 1))
+ << (i * 8));
+ offset += 3;
+ }
+
+ return *high_dword | *low_dword;
+}
+
+static void program_mac_address(u16 io_base, u32 search_address,
+ u32 search_length)
+{
+ /* Default MAC Address of A0:00:BA:D0:0B:AD */
+ u32 high_dword = 0xD0BA00A0; /* high dword of mac address */
+ u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */
+
+ if (search_length != -1)
+ get_mac_address(&high_dword, &low_dword, search_address,
+ search_length);
+
+ if (io_base) {
+ printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base);
+ printk(BIOS_DEBUG, "Programming MAC Address\n");
+
+ outb(0xc0, io_base + 0x50); /* Disable register protection */
+ outl(high_dword, io_base);
+ outl(low_dword, io_base + 0x04);
+ outb(0x60, io_base + 54);
+ outb(0x00, io_base + 0x50); /* Enable register protection again */
+ }
+}
+
+static void program_keyboard_type(u32 search_address, u32 search_length)
+{
+ char key[] = "keyboard_layout";
+ char kbd_jpn[] = "xkb:jp::jpn";
+ unsigned int offset;
+ char kbd_type = EC_KBD_EN; /* Default keyboard type is English */
+
+ if (search_length != -1) {
+
+ /*
+ * Search for keyboard_layout identifier
+ * The only options in the EC are Japanese or English.
+ * The English keyboard layout is actually used for multiple
+ * different languages - English, Spanish, French... Because
+ * of this the code only searches for Japanese, and sets the
+ * keyboard type to English if Japanese is not found.
+ */
+ offset = search(key, (char *)search_address, sizeof(key) - 1,
+ search_length);
+ if (offset != search_length) {
+ printk(BIOS_DEBUG, "Located '%s' in VPD\n", key);
+
+ offset += sizeof(key); /* move to next character */
+ search_length = sizeof(kbd_jpn);
+ offset = search(kbd_jpn, (char *)(search_address + offset),
+ sizeof(kbd_jpn) - 1, search_length);
+ if (offset != search_length)
+ kbd_type = EC_KBD_JP;
+ }
+ } else
+ printk(BIOS_DEBUG, "Error: Could not locate VPD area\n");
+
+
+ printk(BIOS_DEBUG, "Setting Keyboard type in EC to ");
+ printk(BIOS_DEBUG, (kbd_type == EC_KBD_JP) ? "Japanese" : "English");
+ printk(BIOS_DEBUG, ".\n");
+
+ ec_mem_write(EC_KBID_REG, kbd_type);
+}
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res = -1;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, regs->eax & 0xffff);
+
+ switch (regs->eax & 0xffff) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffffff00;
+ regs->ecx |= 0x00; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0001; /* Int-LVDS */
+ res = 0;
+ break;
+ case 0x5f70:
+ switch ((regs->ecx >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ ((regs->ecx >> 8) & 0xff));
+ return 0;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x00;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 1; /* Int-LVDS */
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ return 0;
+ }
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+ M.x86.R_AX);
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ typedef int (*yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 *cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 *pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
+
+static void mainboard_init(device_t dev)
+{
+ char **vpd_region_ptr = NULL;
+ u32 search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr);
+ u32 search_address = (unsigned long)(*vpd_region_ptr);
+ u16 io_base = 0;
+ struct device *ethernet_dev = NULL;
+
+ /* Initialize the Embedded Controller */
+ butterfly_ec_init();
+
+ /* Program EC Keyboard locale based on VPD data */
+ program_keyboard_type(search_address, search_length);
+
+ /* Get NIC's IO base address */
+ ethernet_dev = dev_find_device(BUTTERFLY_NIC_VENDOR_ID,
+ BUTTERFLY_NIC_DEVICE_ID, dev);
+ if (ethernet_dev != NULL) {
+ io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe;
+
+ /*
+ * Battery life time - LAN PCIe should enter ASPM L1 to save
+ * power when LAN connection is idle.
+ * enable CLKREQ: LAN pci config space 0x81h=01
+ */
+ pci_write_config8(ethernet_dev, 0x81, 0x01);
+ }
+
+ if (io_base) {
+ /* Program MAC address based on VPD data */
+ program_mac_address(io_base, search_address, search_length);
+
+ /*
+ * Program NIC LEDS
+ *
+ * RTL8105E Series EEPROM-Less Application Note,
+ * Section 5.6 LED Mode Configuration
+ *
+ * Step1: Write C0h to I/O register 0x50 via byte access to
+ * disable 'register protection'
+ * Step2: Write xx001111b to I/O register 0x52 via byte access
+ * (bit7 is LEDS1 and bit6 is LEDS0)
+ * Step3: Write 0x00 to I/O register 0x50 via byte access to
+ * enable 'register protection'
+ */
+ outb(0xc0, io_base + 0x50); /* Disable protection */
+ outb((BUTTERFLY_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52);
+ outb(0x00, io_base + 0x50); /* Enable register protection */
+ }
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+}
+
+static int butterfly_smbios_type41(int *handle, unsigned long *current,
+ const char *name, u8 irq, u8 addr)
+{
+ struct smbios_type41 *t = (struct smbios_type41 *)*current;
+ int len = sizeof(struct smbios_type41);
+
+ memset(t, 0, sizeof(struct smbios_type41));
+ t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
+ t->handle = *handle;
+ t->length = len - 2;
+ t->reference_designation = smbios_add_string(t->eos, name);
+ t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
+ t->device_status = 1;
+ t->device_type_instance = irq;
+ t->segment_group_number = 0;
+ t->bus_number = addr;
+ t->function_number = 0;
+ t->device_number = 0;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+ *handle += 1;
+ return len;
+}
+
+static int butterfly_onboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += butterfly_smbios_type41(handle, current,
+ BUTTERFLY_TRACKPAD_NAME,
+ BUTTERFLY_TRACKPAD_IRQ,
+ BUTTERFLY_TRACKPAD_I2C_ADDR);
+
+ return len;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Google Butterfly ChromeBook")
+ .enable_dev = mainboard_enable,
+ .get_smbios_data = butterfly_onboard_smbios_data,
+};
diff --git a/src/mainboard/google/butterfly/mainboard_smi.c b/src/mainboard/google/butterfly/mainboard_smi.c
new file mode 100644
index 0000000..4e02a3c
--- /dev/null
+++ b/src/mainboard/google/butterfly/mainboard_smi.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Include EC functions */
+#include <ec/quanta/ene_kb3940q/ec.h>
+#include "ec.h"
+
+int mainboard_io_trap_handler(int smif)
+{
+ printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif);
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ printk(BIOS_DEBUG, "warn: unknown mainboard_smi_gpi: %x\n", gpi_sts);
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
+
+ /* Tell the EC to Enable USB power for S3 if requested */
+ if (smm_get_gnvs()->s3u0 != 0 || smm_get_gnvs()->s3u1 != 0)
+ ec_mem_write(EC_EC_PSW, ec_mem_read(EC_EC_PSW) | EC_PSW_USB);
+
+ /* Disable wake on USB, LAN & RTC */
+ /* Enable Wake from Keyboard */
+ if ((slp_typ == 4) || (slp_typ == 5)) {
+ printk(BIOS_DEBUG, "Disabling wake on RTC\n");
+ ec_mem_write(EC_EC_PSW, EC_PSW_IKB);
+ }
+}
+
+#define APMC_FINALIZE 0xcb
+#define APMC_ACPI_EN 0xe1
+#define APMC_ACPI_DIS 0x1e
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc);
+ switch (apmc) {
+ case APMC_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+
+ case APMC_ACPI_EN:
+ printk(BIOS_DEBUG, "APMC: ACPI_EN\n");
+ /* Clear all pending events and enable SCI */
+ ec_write_cmd(EC_CMD_ENABLE_ACPI_MODE);
+ break;
+
+ case APMC_ACPI_DIS:
+ printk(BIOS_DEBUG, "APMC: ACPI_DIS\n");
+ /* Clear all pending events and tell the EC that ACPI is disabled */
+ ec_write_cmd(EC_CMD_DISABLE_ACPI_MODE);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/butterfly/onboard.h b/src/mainboard/google/butterfly/onboard.h
new file mode 100644
index 0000000..e32e023
--- /dev/null
+++ b/src/mainboard/google/butterfly/onboard.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef BUTTERFLY_ONBOARD_H
+#define BUTTERFLY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+/* uses 7-bit I2C address */
+/* must be set to edge triggered */
+#define BUTTERFLY_TRACKPAD_NAME "trackpad"
+#define BUTTERFLY_TRACKPAD_I2C_ADDR 0x67
+#define BUTTERFLY_TRACKPAD_IRQ 22 /* PIRQG - 22 Edge triggered */
+
+/* defines for programming the MAC address */
+#define BUTTERFLY_NIC_VENDOR_ID 0x10EC
+#define BUTTERFLY_NIC_DEVICE_ID 0x8136
+
+/* 0x00: White LINK LED and Amber ACTIVE LED */
+#define BUTTERFLY_NIC_LED_MODE 0x00
+#endif
diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c
new file mode 100644
index 0000000..551d22c
--- /dev/null
+++ b/src/mainboard/google/butterfly/romstage.c
@@ -0,0 +1,306 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+
+static void pch_enable_lpc(void)
+{
+ /* EC Decode Range Port60/64 and Port62/66 */
+ /* Enable EC and PS/2 Keyboard/Mouse*/
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
+
+ /* EC Decode Range Port68/6C */
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 & ~3) | 0x40001);
+
+ /* EC Decode Range Port 380-387 */
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x380 | 0x40001);
+
+}
+
+static void rcba_config(void)
+{
+ u32 reg32;
+
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P1IP WLAN INTA -> PIRQB
+ * D28IP_P2IP ETH0 INTB -> PIRQF
+ * D28IP_P3IP SDCARD INTC -> PIRQD
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+ * Trackpad interrupt is edge triggered and cannot be shared.
+ * TRACKPAD -> PIRQG
+
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) |
+ (INTC << D28IP_P3IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+
+ /* Disable unused devices (board specific) */
+ reg32 = RCBA32(FD);
+ reg32 |= PCH_DISABLE_ALWAYS;
+ /* Disable PCI bridge so MRC does not probe this bus */
+ reg32 |= PCH_DISABLE_P2P;
+ RCBA32(FD) = reg32;
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ tsc_t start_romstage_time;
+ tsc_t before_dram_time;
+ tsc_t after_dram_time;
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+#endif
+ struct pei_data pei_data = {
+ pei_version: PEI_VERSION,
+ mchbar: DEFAULT_MCHBAR,
+ dmibar: DEFAULT_DMIBAR,
+ epbar: DEFAULT_EPBAR,
+ pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+ smbusbar: SMBUS_IO_BASE,
+ wdbbar: 0x4000000,
+ wdbsize: 0x1000,
+ hpet_address: HPET_ADDR,
+ rcba: DEFAULT_RCBABASE,
+ pmbase: DEFAULT_PMBASE,
+ gpiobase: DEFAULT_GPIOBASE,
+ thermalbase: 0xfed08000,
+ system_type: 0, // 0 Mobile, 1 Desktop/Server
+ tseg_size: CONFIG_SMM_TSEG_SIZE,
+ spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
+ ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+ ec_present: 1,
+ ddr3lv_support: 0,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ dimm_channel0_disabled: 2,
+ dimm_channel1_disabled: 2,
+ max_ddr3_freq: 1600,
+ usb_port_config: {
+ /* enabled usb oc pin length */
+ { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */
+ { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */
+ { 1, 0, 0x0040 }, /* P2: Camera (no OC) */
+ { 0, 0, 0x0000 }, /* P3: Empty */
+ { 0, 0, 0x0000 }, /* P4: Empty */
+ { 0, 0, 0x0000 }, /* P5: Empty */
+ { 0, 0, 0x0000 }, /* P6: Empty */
+ { 0, 0, 0x0000 }, /* P7: Empty */
+ { 0, 4, 0x0000 }, /* P8: Empty */
+ { 1, 4, 0x0040 }, /* P9: Left USB 1 (no OC) */
+ { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */
+ { 0, 4, 0x0000 }, /* P11: Empty */
+ { 0, 4, 0x0000 }, /* P12: Empty */
+ { 0, 4, 0x0000 }, /* P13: Empty */
+ },
+ };
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ start_romstage_time = rdtsc();
+#endif
+
+ if (bist == 0)
+ enable_lapic();
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+ setup_pch_gpios(&butterfly_gpio_map);
+
+ /* Initialize console device(s) */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected\n");
+ boot_mode = 1;
+
+ /* System is not happy after keyboard reset... */
+ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+ outb(0x6, 0xcf9);
+ hlt();
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ post_code(0x3a);
+ pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_dram_time = rdtsc();
+#endif
+ sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_dram_time = rdtsc();
+#endif
+ post_code(0x3c);
+
+ rcba_config();
+ post_code(0x3d);
+
+ quick_ram_check();
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+ cbmem_was_initted = !cbmem_initialize();
+#else
+ cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+ - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+#if CONFIG_CHROMEOS
+ init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(base_time);
+ timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+ timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+ timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+ /* Keep this the last thing this function does. */
+ cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/butterfly/thermal.h
similarity index 67%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/butterfly/thermal.h
index 3ae8657..c8ff1f4 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/butterfly/thermal.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+#ifndef BUTTERFLY_THERMAL_H
+#define BUTTERFLY_THERMAL_H
-struct mainboard_config {};
+/* Active Thermal and fans are controlled by the EC. */
+
+ /* Temperature which OS will shutdown at */
+ #define CRITICAL_TEMPERATURE 100
+
+ /* Temperature which OS will throttle CPU */
+ #define PASSIVE_TEMPERATURE 90
+
+#endif
diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig
new file mode 100644
index 0000000..a1ae077
--- /dev/null
+++ b/src/mainboard/google/link/Kconfig
@@ -0,0 +1,47 @@
+if BOARD_GOOGLE_LINK
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select BOARD_ROMSIZE_KB_8192
+ select EC_GOOGLE_CHROMEEC
+ select BOARD_HAS_FADT
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_MAINBOARD_RESOURCES
+ select MMCONF_SUPPORT
+ select HAVE_SMI_HANDLER
+ select GFXUMA
+ select CHROMEOS
+ select EXTERNAL_MRC_BLOB
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default google/link
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Link"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+endif # BOARD_GOOGLE_LINK
diff --git a/src/mainboard/google/link/Makefile.inc b/src/mainboard/google/link/Makefile.inc
new file mode 100644
index 0000000..7c6bf33
--- /dev/null
+++ b/src/mainboard/google/link/Makefile.inc
@@ -0,0 +1,44 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+SPD_BIN = $(obj)/spd.bin
+
+SRC_ROOT = $(src)/mainboard/google/link
+
+# Order of names in SPD_SOURCES is important!
+SPD_SOURCES = elpida_4Gb_1600_x16
+SPD_SOURCES += samsung_4Gb_1600_1.35v_x16
+SPD_SOURCES += micron_4Gb_1600_1.35v_x16
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), $(SRC_ROOT)/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $^; do for c in $$(cat $$f); do echo -e -n "\\x$$c"; done; done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := 0xab
+spd.bin-position := 0xfffec000
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/link/acpi/chromeos.asl
similarity index 75%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/link/acpi/chromeos.asl
index 3ae8657..6c6e3c7 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/link/acpi/chromeos.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
+Name(OIPG, Package() {
+ Package() { 0x001, 0, 9, "PantherPoint" }, // recovery button
+ Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect
+})
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/link/acpi/ec.asl
similarity index 77%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/link/acpi/ec.asl
index 3ae8657..10e3815 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/link/acpi/ec.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+/* mainboard configuration */
+#include "../ec.h"
-struct mainboard_config {};
+/* ACPI code for EC functions */
+#include "../../../../ec/google/chromeec/acpi/ec.asl"
diff --git a/src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl
new file mode 100644
index 0000000..dd32379
--- /dev/null
+++ b/src/mainboard/google/link/acpi/ivybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for IvyBridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 22 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 19 },
+ Package() { 0x001cffff, 1, 0, 20 },
+ Package() { 0x001cffff, 2, 0, 17 },
+ Package() { 0x001cffff, 3, 0, 18 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 20 },
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 21 },
+ Package() { 0x001fffff, 1, 0, 22 },
+ Package() { 0x001fffff, 2, 0, 23 },
+ Package() { 0x001fffff, 3, 0, 16 },
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/google/link/acpi/mainboard.asl b/src/mainboard/google/link/acpi/mainboard.asl
new file mode 100644
index 0000000..a2778a0
--- /dev/null
+++ b/src/mainboard/google/link/acpi/mainboard.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+ Device (LID0)
+ {
+ Name(_HID, EisaId("PNP0C0D"))
+ Method(_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+ Return (\LIDS)
+ }
+
+ // EC_LID_OUT is GPIO15
+ Name(_PRW, Package(){0x1f, 0x05})
+ }
+
+ Device (PWRB)
+ {
+ Name(_HID, EisaId("PNP0C0C"))
+ }
+
+ Device (TPAD)
+ {
+ Name (_ADR, 0x0)
+ Name (_UID, 1)
+
+ // Report as a Sleep Button device so Linux will
+ // automatically enable it as a wake source
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Trackpad Wake is GPIO12
+ Name(_PRW, Package(){0x1c, 0x03})
+
+ Name(_CRS, ResourceTemplate()
+ {
+ // PIRQE -> GSI20
+ Interrupt (ResourceConsumer, Edge, ActiveLow) {20}
+
+ // SMBUS Address 0x4b
+ VendorShort (ADDR) {0x4b}
+ })
+ }
+
+ Device (TSCR)
+ {
+ Name (_ADR, 0x0)
+ Name (_UID, 2)
+
+ // Report as a Sleep Button device so Linux will
+ // automatically enable it as a wake source
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Touchscreen Wake is GPIO14
+ Name(_PRW, Package(){0x1e, 0x03})
+
+ Name(_CRS, ResourceTemplate()
+ {
+ // PIRQG -> GSI22
+ Interrupt (ResourceConsumer, Edge, ActiveLow) {22}
+
+ // SMBUS Address 0x4a
+ VendorShort (ADDR) {0x4a}
+ })
+ }
+
+ // Keyboard Backlight interface via EC
+ Device (KBLT) {
+ Name (_HID, EisaId("GGL0002"))
+ Name (_UID, 1)
+ Name (_ADR, 0)
+
+ // Read current backlight value
+ Method (KBQC, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.KBLV)
+ }
+
+ // Write new backlight value
+ Method (KBCM, 1)
+ {
+ Store (Arg0, \_SB.PCI0.LPCB.EC0.KBLV)
+ }
+ }
+}
diff --git a/src/mainboard/google/link/acpi/platform.asl b/src/mainboard/google/link/acpi/platform.asl
new file mode 100644
index 0000000..51e13f2
--- /dev/null
+++ b/src/mainboard/google/link/acpi/platform.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ /* Disable WWAN */
+ Store (Zero, GP36)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Update AC status */
+ Store (\_SB.PCI0.LPCB.EC0.ACEX, Local0)
+ if (LNotEqual (Local0, \PWRS)) {
+ Store (Local0, \PWRS)
+ Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
+ }
+
+ /* Update LID status */
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, Local0)
+ if (LNotEqual (Local0, \LIDS)) {
+ Store (Local0, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..ee4221a
--- /dev/null
+++ b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 19 },
+ Package() { 0x001cffff, 1, 0, 20 },
+ Package() { 0x001cffff, 2, 0, 17 },
+ Package() { 0x001cffff, 3, 0, 18 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 },
+ Package() { 0x001fffff, 1, 0, 23 },
+ Package() { 0x001fffff, 2, 0, 16 },
+ Package() { 0x001fffff, 3, 0, 18 },
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/intel/emeraldlake2/chip.h b/src/mainboard/google/link/acpi/superio.asl
similarity index 61%
copy from src/mainboard/intel/emeraldlake2/chip.h
copy to src/mainboard/google/link/acpi/superio.asl
index fbe2477..3e9e66a 100644
--- a/src/mainboard/intel/emeraldlake2/chip.h
+++ b/src/mainboard/google/link/acpi/superio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,5 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+#define SIO_EC_ENABLE_COM1 // Enable Serial Port 1
+
+/* ACPI code for EC SuperIO functions */
+#include "../../../../ec/google/chromeec/acpi/superio.asl"
diff --git a/src/mainboard/google/link/acpi/thermal.asl b/src/mainboard/google/link/acpi/thermal.asl
new file mode 100644
index 0000000..e7cced8
--- /dev/null
+++ b/src/mainboard/google/link/acpi/thermal.asl
@@ -0,0 +1,204 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ // Get CPU Temperature from TIN9/PECI via EC
+ Store (\_SB.PCI0.LPCB.EC0.TIN9, Local0)
+
+ // Check for sensor not present
+ If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) {
+ Return (CTOK(0))
+ }
+
+ // Check for sensor not powered
+ If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) {
+ Return (CTOK(0))
+ }
+
+ // Check for sensor bad reading
+ If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) {
+ Return (CTOK(0))
+ }
+
+ // Adjust by offset to get Kelvin
+ Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
+
+ // Convert to 1/10 Kelvin
+ Multiply (Local0, 10, Local0)
+ Return (Local0)
+ }
+ }
+
+ ThermalZone (SKIN)
+ {
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ // Get Temperature from TIN# set in NVS
+ Store (\_SB.PCI0.LPCB.EC0.TINS (TMPS), Local0)
+
+ // Check for bad readings
+ If (LOr (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP),
+ LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD))) {
+ Return (0)
+ }
+
+ // Adjust by offset to get Kelvin
+ Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0)
+
+ // Convert to 1/10 Kelvin
+ Multiply (Local0, 10, Local0)
+ Return (Local0)
+ }
+
+ /* CTDP Down */
+ Method (_AC0) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (CTOK (\F0OF))
+ } Else {
+ Return (CTOK (\F0ON))
+ }
+ }
+
+ /* CTDP Nominal */
+ Method (_AC1) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (CTOK (\F1OF))
+ } Else {
+ Return (CTOK (\F1ON))
+ }
+ }
+
+ Name (_AL0, Package () { TDP0 })
+ Name (_AL1, Package () { TDP1 })
+
+ PowerResource (TNP0, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 0)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (0, \FLVL)
+ \_SB.PCI0.MCHC.STND ()
+ Notify (\_TZ.SKIN, 0x81)
+ }
+ Method (_OFF) {
+ Store (1, \FLVL)
+ \_SB.PCI0.MCHC.STDN ()
+ Notify (\_TZ.SKIN, 0x81)
+ }
+ }
+
+ PowerResource (TNP1, 0, 0)
+ {
+ Method (_STA) {
+ If (LLessEqual (\FLVL, 1)) {
+ Return (One)
+ } Else {
+ Return (Zero)
+ }
+ }
+ Method (_ON) {
+ Store (1, \FLVL)
+ Notify (\_TZ.SKIN, 0x81)
+ }
+ Method (_OFF) {
+ Store (1, \FLVL)
+ Notify (\_TZ.SKIN, 0x81)
+ }
+ }
+
+ Device (TDP0)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 0)
+ Name (_PR0, Package () { TNP0 })
+ }
+
+ Device (TDP1)
+ {
+ Name (_HID, EISAID ("PNP0C0B"))
+ Name (_UID, 1)
+ Name (_PR0, Package () { TNP1 })
+ }
+ }
+}
+
diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/google/link/acpi/video.asl
similarity index 71%
copy from src/mainboard/roda/rk886ex/chip.h
copy to src/mainboard/google/link/acpi/video.asl
index 6f24f71..3ececa9 100644
--- a/src/mainboard/roda/rk886ex/chip.h
+++ b/src/mainboard/google/link/acpi/video.asl
@@ -17,5 +17,27 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/link/acpi_tables.c b/src/mainboard/google/link/acpi_tables.c
new file mode 100644
index 0000000..2488bb2
--- /dev/null
+++ b/src/mainboard/google/link/acpi_tables.c
@@ -0,0 +1,314 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/google/chromeec/ec.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ gnvs->tmps = CTDP_SENSOR_ID;
+
+ gnvs->f1of = CTDP_NOMINAL_THRESHOLD_OFF;
+ gnvs->f1on = CTDP_NOMINAL_THRESHOLD_ON;
+
+ gnvs->f0of = CTDP_DOWN_THRESHOLD_OFF;
+ gnvs->f0on = CTDP_DOWN_THRESHOLD_ON;
+
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+ gnvs->tmax = MAX_TEMPERATURE;
+ gnvs->flvl = 1;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs_ = gnvs;
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /*
+ * Enable Front USB ports in S5 by default
+ * to be consistent with back port behavior
+ */
+ gnvs->s5u0 = 1;
+ gnvs->s5u1 = 1;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+ acpi_update_thermal_table(gnvs);
+
+ gnvs->chromeos.vbt2 = google_ec_running_ro() ?
+ ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfed00000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x8086a201; /* Intel */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0080;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_intel_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, "COREBOOT");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/google/link/chromeos.c b/src/mainboard/google/link/chromeos.c
new file mode 100644
index 0000000..1c90b3f
--- /dev/null
+++ b/src/mainboard/google/link/chromeos.c
@@ -0,0 +1,124 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT 6
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+
+static int get_lid_switch(void)
+{
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+
+ return !!(ec_switches & EC_SWITCH_LID_OPEN);
+}
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+ //u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+
+ if (!gpio_base)
+ return;
+
+ u32 gp_lvl2 = inl(gpio_base + 0x38);
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ /* Write Protect: GPIO57 = PCH_SPI_WP_D */
+ gpios->gpios[0].port = 57;
+ gpios->gpios[0].polarity = ACTIVE_HIGH;
+ gpios->gpios[0].value = (gp_lvl2 >> (57 - 32)) & 1;
+ strncpy((char *)gpios->gpios[0].name,"write protect",
+ GPIO_MAX_NAME_LENGTH);
+ /* Recovery: the "switch" comes from the EC */
+ gpios->gpios[1].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[1].polarity = ACTIVE_HIGH;
+ gpios->gpios[1].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+ /* Lid: the "switch" comes from the EC */
+ gpios->gpios[2].port = -1;
+ gpios->gpios[2].polarity = ACTIVE_HIGH;
+ gpios->gpios[2].value = get_lid_switch();
+ strncpy((char *)gpios->gpios[2].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+ /* Power Button: hard-coded as not pressed; we'll detect later presses
+ * via SMI. */
+ gpios->gpios[3].port = -1;
+ gpios->gpios[3].polarity = ACTIVE_HIGH;
+ gpios->gpios[3].value = 0;
+ strncpy((char *)gpios->gpios[3].name,"power", GPIO_MAX_NAME_LENGTH);
+
+ /* Developer: a tricky case on Link, there is no switch */
+ gpios->gpios[4].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[4].polarity = ACTIVE_HIGH;
+ gpios->gpios[4].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[4].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+ /* Did we load the VGA Option ROM? */
+ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[5].polarity = ACTIVE_HIGH;
+ gpios->gpios[5].value = oprom_is_loaded;
+ strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+}
+#endif
+
+/* The dev-switch is virtual on Link (and so handled elsewhere). */
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+/* There are actually two recovery switches. One is the magic keyboard chord,
+ * the other is driven by Servo. */
+int get_recovery_mode_switch(void)
+{
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+ u32 ec_events;
+
+ /* If a switch is set, we don't need to look at events. */
+ if (ec_switches & (EC_SWITCH_KEYBOARD_RECOVERY |
+ EC_SWITCH_DEDICATED_RECOVERY))
+ return 1;
+
+ /* Else check if the EC has posted the keyboard recovery event. */
+ ec_events = google_chromeec_get_events_b();
+
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout
new file mode 100644
index 0000000..afdd3c6
--- /dev/null
+++ b/src/mainboard/google/link/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb
new file mode 100644
index 0000000..630f671
--- /dev/null
+++ b/src/mainboard/google/link/devicetree.cb
@@ -0,0 +1,112 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as eDP and configure power delays
+ register "gpu_panel_port_select" = "1" # eDP_A
+ register "gpu_panel_power_cycle_delay" = "6" # 500ms
+ register "gpu_panel_power_up_delay" = "2000" # 200ms
+ register "gpu_panel_power_down_delay" = "500" # 50ms
+ register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
+ register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
+
+ # Set backlight PWM values for eDP
+ register "gpu_cpu_backlight" = "0x000010ce"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device lapic_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Coordinate with HW_ALL
+ register "pstate_coord_type" = "0xfe"
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "tcc_offset" = "15" # TCC at 90C
+ end
+ end
+
+ device pci_domain 0 on
+ subsystemid 0x1ae0 0xc000 inherit
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0100"
+ register "gpi7_routing" = "2"
+ register "gpi8_routing" = "1"
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ register "sata_port_map" = "0x1"
+
+ # Mobile Direct Connect Short 0.8-3.5 inches
+ register "sata_port0_gen3_tx" = "0x0088037F"
+
+ # EC range is 0x800-0x9ff
+ # Please note: you MUST not change this unless
+ # you also change romstage.c:pch_enable_lpc
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x00fc0901"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1 (WLAN remapped)
+ device pci 1c.1 off end # PCIe Port #2
+ device pci 1c.2 on end # PCIe Port #3 (WLAN actual)
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl
new file mode 100644
index 0000000..608827a
--- /dev/null
+++ b/src/mainboard/google/link/dsdt.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include "acpi/thermal.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/link/ec.c b/src/mainboard/google/link/ec.c
new file mode 100644
index 0000000..5a61eac
--- /dev/null
+++ b/src/mainboard/google/link/ec.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void link_ec_init(void)
+{
+ printk(BIOS_DEBUG, "link_ec_init\n");
+ post_code(0xf0);
+
+ /* Restore SCI event mask on resume. */
+ if (acpi_slp_type == 3) {
+ google_chromeec_log_events(LINK_EC_LOG_EVENTS |
+ LINK_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(LINK_EC_LOG_EVENTS |
+ LINK_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake events, these are enabled on entry to sleep */
+ google_chromeec_set_wake_mask(0);
+
+ post_code(0xf1);
+}
diff --git a/src/mainboard/google/link/ec.h b/src/mainboard/google/link/ec.h
new file mode 100644
index 0000000..3ca3543
--- /dev/null
+++ b/src/mainboard/google/link/ec.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LINK_EC_H
+#define LINK_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+#define EC_SCI_GPI 7 /* GPIO7 is EC_SCI# */
+#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */
+
+#define LINK_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
+
+#define LINK_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define LINK_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define LINK_EC_S3_WAKE_EVENTS \
+ (LINK_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define LINK_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#ifndef __ACPI__
+extern void link_ec_init(void);
+#endif
+
+#endif // LINK_EC_H
diff --git a/src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex b/src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex
new file mode 100644
index 0000000..03c2808
--- /dev/null
+++ b/src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex
@@ -0,0 +1,32 @@
+ 92 10 0b 03 04 19 02 02
+ 03 52 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 81
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 11 42 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 02 fe 00
+ 11 52 00 00 00 07 7f 37
+ 45 42 4a 32 30 55 47 36
+ 45 42 55 30 2d 47 4e 2d
+ 46 20 30 20 02 fe 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/link/fadt.c b/src/mainboard/google/link/fadt.c
new file mode 100644
index 0000000..06d3231
--- /dev/null
+++ b/src/mainboard/google/link/fadt.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT 0xb2
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
+#define ACPI_DISABLE 0x1e
+#define ACPI_ENABLE 0xe1
+#define GNVS_UPDATE 0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_DESKTOP;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/link/gpio.h b/src/mainboard/google/link/gpio.h
new file mode 100644
index 0000000..b208f88
--- /dev/null
+++ b/src/mainboard/google/link/gpio.h
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LINK_GPIO_H
+#define LINK_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, /* NMI_DBG# */
+ .gpio3 = GPIO_MODE_GPIO, /* ALS_INT# */
+ .gpio5 = GPIO_MODE_GPIO, /* SIM_DET */
+ .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
+ .gpio8 = GPIO_MODE_GPIO, /* EC_SMI# */
+ .gpio9 = GPIO_MODE_GPIO, /* RECOVERY# */
+ .gpio10 = GPIO_MODE_GPIO, /* SPD vector D3 */
+ .gpio11 = GPIO_MODE_GPIO, /* smbalert#, let's keep it initialized */
+ .gpio12 = GPIO_MODE_GPIO, /* TP_INT# */
+ .gpio14 = GPIO_MODE_GPIO, /* Touch_INT_L */
+ .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT# (EC_WAKE#) */
+ .gpio21 = GPIO_MODE_GPIO, /* EC_IN_RW */
+ .gpio24 = GPIO_MODE_GPIO, /* DDR3L_EN */
+ .gpio28 = GPIO_MODE_GPIO, /* SLP_ME_CSW_DEV# */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_OUTPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio1 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_HIGH,
+ .gpio24 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
+ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
+ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
+ .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
+ .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio36 = GPIO_DIR_OUTPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio36 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_map link_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+#endif
diff --git a/src/mainboard/google/link/hda_verb.h b/src/mainboard/google/link/hda_verb.h
new file mode 100644
index 0000000..d4e4258
--- /dev/null
+++ b/src/mainboard/google/link/hda_verb.h
@@ -0,0 +1,182 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x11020011, // Codec Vendor / Device ID: Creative CA0132
+ 0x144dc0c2, // Subsystem ID
+ 0x00000014, // Number of jacks + Number of Malcolm setup blocks.
+
+ /* Malcolm Setup */
+
+ 0x01570d09,
+ 0x01570c23,
+ 0x01570a01,
+ 0x01570df0,
+
+ 0x01570efe,
+ 0x01570775,
+ 0x015707d3,
+ 0x01570709,
+
+ 0x01570753,
+ 0x015707d4,
+ 0x015707ef,
+ 0x01570775,
+
+ 0x015707d3,
+ 0x01570709,
+ 0x01570702,
+ 0x01570737,
+
+ 0x01570778,
+ 0x01553cce,
+ 0x015575c9,
+ 0x01553dce,
+
+ 0x0155b7c9,
+ 0x01570de8,
+ 0x01570efe,
+ 0x01570702,
+
+ 0x01570768,
+ 0x01570762,
+ 0x01553ace,
+ 0x015546c9,
+
+ 0x01553bce,
+ 0x0155e8c9,
+ 0x01570d49,
+ 0x01570c88,
+
+ 0x01570d20,
+ 0x01570e19,
+ 0x01570700,
+ 0x01571a05,
+
+ 0x01571b29,
+ 0x01571a04,
+ 0x01571b29,
+ 0x01570a01,
+
+ /* Pin Widget Verb Table */
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144DC0C2 */
+ 0x001720c2,
+ 0x001721c0,
+ 0x0017224d,
+ 0x00172314,
+
+ /* Pin Complex (NID 0x0B) Port-G Analog Unknown Speaker at Int N/A */
+ 0x00b71cf0,
+ 0x00b71d00,
+ 0x00b71e17,
+ 0x00b71f90,
+
+ /* Pin Complex (NID 0x0C) N/C */
+ 0x00c71cf0,
+ 0x00c71d00,
+ 0x00c71ef0,
+ 0x00c71f70,
+
+ /* Pin Complex (NID 0x0D) N/C */
+ 0x00d71cf0,
+ 0x00d71d00,
+ 0x00d71ef0,
+ 0x00d71f70,
+
+ /* Pin Complex (NID 0x0E) N/C */
+ 0x00e71cf0,
+ 0x00e71d00,
+ 0x00e71ef0,
+ 0x00e71f70,
+
+ /* Pin Complex (NID 0x0F) N/C */
+ 0x00f71cf0,
+ 0x00f71d00,
+ 0x00f71ef0,
+ 0x00f71f70,
+
+ /* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */
+ 0x01071cf0,
+ 0x01071d10,
+ 0x01071e21,
+ 0x01071f03,
+
+ /* Pin Complex (NID 0x11) Port-B Click Mic */
+ 0x01171cf0,
+ 0x01171d00,
+ 0x01171ea7,
+ 0x01171f90,
+
+ /* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */
+ 0x01271cf0,
+ 0x01271d00,
+ 0x01271ea6,
+ 0x01271ff7,
+
+ /* Pin Complex (NID 0x13) What you hear */
+ 0x01371cf0,
+ 0x01371d00,
+ 0x01371ed6,
+ 0x01371f90,
+
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel CougarPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of jacks
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ 0x00172001,
+ 0x00172101,
+ 0x00172286,
+ 0x00172380,
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ 0x30571c10,
+ 0x30571d00,
+ 0x30571e56,
+ 0x30571f18,
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ 0x30671c20,
+ 0x30671d00,
+ 0x30671e56,
+ 0x30671f18,
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ 0x30771c30,
+ 0x30771d00,
+ 0x30771e56,
+ 0x30771f18
+};
+
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x00170500, /* power up codec */
+ 0x00270500, /* power up DAC */
+ 0x00b70500, /* power up speaker */
+ 0x00b70740, /* enable speaker out */
+ 0x00b78d00, /* enable EAPD pin */
+ 0x00b70c02, /* set EAPD pin */
+ 0x00b70740, /* enable speaker output */
+ 0x0023b04b, /* unmute DAC */
+};
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/google/link/mainboard.c b/src/mainboard/google/link/mainboard.c
new file mode 100644
index 0000000..04b8b95
--- /dev/null
+++ b/src/mainboard/google/link/mainboard.c
@@ -0,0 +1,361 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+
+/* placeholder for evenual link post. Not sure what we'll
+ * do but it will look nice
+ */
+void mainboard_post(u8 value)
+{
+ /*
+ * What you DO NOT want to do: push every post to the EC backlight.
+ * it seems cute but in practice it looks like a hardware failure.
+ * I'm leaving this here so we don't make this mistake again later.
+ * And it seems to break the SMP startup.
+ * google_chromeec_post(value);
+ */
+}
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res=-1;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, regs->eax & 0xffff);
+
+ switch(regs->eax & 0xffff) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffffff00;
+ regs->ecx |= 0x00; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0003; /* eDP */
+ res = 0;
+ break;
+ case 0x5f70:
+ switch ((regs->ecx >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ ((regs->ecx >> 8) & 0xff));
+ return 0;
+ }
+ break;
+ case 0x5fac:
+ res = 0;
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x00;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 3; /* eDP */
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ return 0;
+ }
+ break;
+ case 0x5fac:
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+ M.x86.R_AX);
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 * pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+}
+
+static void mainboard_init(device_t dev)
+{
+ /* Initialize the Embedded Controller */
+ link_ec_init();
+
+ if (google_chromeec_get_board_version() == 0) {
+ /* If running on proto1 - enable reversion of gpio11. */
+ u32 gpio_inv;
+ u16 gpio_base = pci_read_config16
+ (dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE) &
+ 0xfffc;
+ u16 gpio_inv_addr = gpio_base + GPI_INV;
+ gpio_inv = inl(gpio_inv_addr);
+ outl(gpio_inv | (1 << 11), gpio_inv_addr);
+ }
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+}
+
+static int link_smbios_type41(int *handle, unsigned long *current,
+ const char *name, u8 irq, u8 addr)
+{
+ struct smbios_type41 *t = (struct smbios_type41 *)*current;
+ int len = sizeof(struct smbios_type41);
+
+ memset(t, 0, sizeof(struct smbios_type41));
+ t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
+ t->handle = *handle;
+ t->length = len - 2;
+ t->reference_designation = smbios_add_string(t->eos, name);
+ t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
+ t->device_status = 1;
+ t->device_type_instance = irq;
+ t->segment_group_number = 0;
+ t->bus_number = addr;
+ t->function_number = 0;
+ t->device_number = 0;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+ *handle += 1;
+ return len;
+}
+
+static int link_onboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += link_smbios_type41(handle, current,
+ LINK_LIGHTSENSOR_NAME,
+ LINK_LIGHTSENSOR_IRQ,
+ LINK_LIGHTSENSOR_I2C_ADDR);
+
+ len += link_smbios_type41(handle, current,
+ LINK_TRACKPAD_NAME,
+ LINK_TRACKPAD_IRQ,
+ LINK_TRACKPAD_I2C_ADDR);
+
+ len += link_smbios_type41(handle, current,
+ LINK_TOUCHSCREEN_NAME,
+ LINK_TOUCHSCREEN_IRQ,
+ LINK_TOUCHSCREEN_I2C_ADDR);
+
+ return len;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Google Link ChromeBook")
+ .enable_dev = mainboard_enable,
+ .get_smbios_data = link_onboard_smbios_data,
+};
diff --git a/src/mainboard/google/link/mainboard_smi.c b/src/mainboard/google/link/mainboard_smi.c
new file mode 100644
index 0000000..cd21864
--- /dev/null
+++ b/src/mainboard/google/link/mainboard_smi.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <elog.h>
+
+/* Include romstage serial for SIO helper functions */
+#include <superio/ite/it8772f/early_serial.c>
+
+/* Include EC functions */
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+static u8 mainboard_smi_ec(void)
+{
+ u8 cmd = google_chromeec_get_event();
+ extern u16 pmbase; /* Set in southbridge SMI handler */
+ u32 pm1_cnt;
+
+#if CONFIG_ELOG_GSMI
+ /* Log this event */
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+#endif
+
+ switch (cmd) {
+ case EC_HOST_EVENT_LID_CLOSED:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+ /* Go to S5 */
+ pm1_cnt = inl(pmbase + PM1_CNT);
+ pm1_cnt |= (0xf << 10);
+ outl(pm1_cnt, pmbase + PM1_CNT);
+ break;
+ }
+
+ return cmd;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ if (gpi_sts & (1 << EC_SMI_GPI)) {
+ /* Process all pending events */
+ while (mainboard_smi_ec() != 0);
+ }
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ /* Disable SCI and SMI events */
+ google_chromeec_set_smi_mask(0);
+ google_chromeec_set_sci_mask(0);
+
+ /* Clear pending events that may trigger immediate wake */
+ while (google_chromeec_get_event() != 0);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(LINK_EC_S3_WAKE_EVENTS);
+}
+
+#define APMC_FINALIZE 0xcb
+#define APMC_ACPI_EN 0xe1
+#define APMC_ACPI_DIS 0x1e
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APMC_FINALIZE:
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ case APMC_ACPI_EN:
+ google_chromeec_set_smi_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(LINK_EC_SCI_EVENTS);
+ break;
+ case APMC_ACPI_DIS:
+ google_chromeec_set_sci_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_smi_mask(LINK_EC_SMI_EVENTS);;
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex
new file mode 100644
index 0000000..a66946a
--- /dev/null
+++ b/src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex
@@ -0,0 +1,32 @@
+ 92 11 0b 03 04 19 02 02
+ 03 11 01 08 0a 00 fe 00
+ 69 78 69 3c 69 11 18 81
+ 20 08 3c 3c 01 40 83 05
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 0f 01 02 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 80 2c 00
+ 00 00 00 00 00 00 ad 75
+ 34 4b 54 46 32 35 36 36
+ 34 48 5a 2d 31 47 36 45
+ 31 20 45 31 80 2c 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ 00 00 00 00 00 00 00 00
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
+ ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/link/onboard.h b/src/mainboard/google/link/onboard.h
new file mode 100644
index 0000000..962bbaa
--- /dev/null
+++ b/src/mainboard/google/link/onboard.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LINK_ONBOARD_H
+#define LINK_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+
+#define LINK_LIGHTSENSOR_NAME "lightsensor"
+#define LINK_LIGHTSENSOR_I2C_ADDR 0x44
+#define LINK_LIGHTSENSOR_IRQ 0
+
+#define LINK_TRACKPAD_NAME "trackpad"
+#define LINK_TRACKPAD_I2C_ADDR 0x4b
+#define LINK_TRACKPAD_IRQ 20
+
+#define LINK_TOUCHSCREEN_NAME "touchscreen"
+#define LINK_TOUCHSCREEN_I2C_ADDR 0x4a
+#define LINK_TOUCHSCREEN_IRQ 22
+
+#endif
diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
new file mode 100644
index 0000000..195971e
--- /dev/null
+++ b/src/mainboard/google/link/romstage.c
@@ -0,0 +1,348 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include "ec/google/chromeec/ec.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+
+#include <southbridge/intel/bd82x6x/chip.h>
+
+static void pch_enable_lpc(void)
+{
+ const struct device *lpc;
+ const struct southbridge_intel_bd82x6x_config *config = NULL;
+
+ lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ if (!lpc)
+ return;
+ if (lpc->chip_info)
+ config = lpc->chip_info;
+ if (!config)
+ return;
+
+ /* Set COM1/COM2 decode range */
+ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+
+ /* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \
+ GAMEL_LPC_EN | COMA_LPC_EN);
+
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, config->gen1_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, config->gen2_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, config->gen3_dec);
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
+}
+
+static void rcba_config(void)
+{
+ u32 reg32;
+
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P3IP WLAN INTA -> PIRQB
+ * D29IP_E1P EHCI1 INTA -> PIRQD
+ * D26IP_E2P EHCI2 INTA -> PIRQF
+ * D31IP_SIP SATA INTA -> PIRQF (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQH
+ * D31IP_TTIP THRT INTC -> PIRQA
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ *
+ * TRACKPAD -> PIRQE (Edge Triggered)
+ * TOUCHSCREEN -> PIRQG (Edge Triggered)
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (INTA << D28IP_P3IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+
+ /* Disable unused devices (board specific) */
+ reg32 = RCBA32(FD);
+ reg32 |= PCH_DISABLE_ALWAYS;
+ RCBA32(FD) = reg32;
+}
+
+static void copy_spd(struct pei_data *peid)
+{
+ const int gpio_vector[] = {41, 42, 43, 10, -1};
+ struct cbfs_file *spd_file;
+ int spd_index = get_gpios(gpio_vector);
+
+ printk(BIOS_DEBUG, "spd index %d\n", spd_index);
+ spd_file = cbfs_find("spd.bin");
+ if (!spd_file)
+ die("SPD data not found.");
+
+ if (ntohl(spd_file->len) < ((spd_index + 1) * sizeof(peid->spd_data[0]))) {
+ printk(BIOS_ERR, "spd index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ if (spd_file->len < sizeof(peid->spd_data[0]))
+ die("Missing SPD data.");
+
+ memcpy(peid->spd_data[0],
+ ((char*)CBFS_SUBHEADER(spd_file)) +
+ spd_index * sizeof(peid->spd_data[0]),
+ sizeof(peid->spd_data[0]));
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ tsc_t start_romstage_time;
+ tsc_t before_dram_time;
+ tsc_t after_dram_time;
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+#endif
+ struct pei_data pei_data = {
+ pei_version: PEI_VERSION,
+ mchbar: DEFAULT_MCHBAR,
+ dmibar: DEFAULT_DMIBAR,
+ epbar: DEFAULT_EPBAR,
+ pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+ smbusbar: SMBUS_IO_BASE,
+ wdbbar: 0x4000000,
+ wdbsize: 0x1000,
+ hpet_address: HPET_ADDR,
+ rcba: DEFAULT_RCBABASE,
+ pmbase: DEFAULT_PMBASE,
+ gpiobase: DEFAULT_GPIOBASE,
+ thermalbase: 0xfed08000,
+ system_type: 0, // 0 Mobile, 1 Desktop/Server
+ tseg_size: CONFIG_SMM_TSEG_SIZE,
+ ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+ ec_present: 1,
+ ddr3lv_support: 1,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ dimm_channel0_disabled: 2,
+ dimm_channel1_disabled: 2,
+ max_ddr3_freq: 1600,
+ usb_port_config: {
+ /* Empty and onboard Ports 0-7, set to un-used pin OC3 */
+ { 0, 3, 0x0000 }, /* P0: Empty */
+ { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
+ { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
+ { 1, 3, 0x0040 }, /* P3: SDCARD (no OC) */
+ { 0, 3, 0x0000 }, /* P4: Empty */
+ { 1, 3, 0x0040 }, /* P5: WWAN (no OC) */
+ { 0, 3, 0x0000 }, /* P6: Empty */
+ { 0, 3, 0x0000 }, /* P7: Empty */
+ /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
+ { 1, 4, 0x0040 }, /* P8: Camera (no OC) */
+ { 1, 4, 0x0040 }, /* P9: Bluetooth (no OC) */
+ { 0, 4, 0x0000 }, /* P10: Empty */
+ { 0, 4, 0x0000 }, /* P11: Empty */
+ { 0, 4, 0x0000 }, /* P12: Empty */
+ { 0, 4, 0x0000 }, /* P13: Empty */
+ },
+ };
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ start_romstage_time = rdtsc();
+#endif
+
+ if (bist == 0)
+ enable_lapic();
+
+ pch_enable_lpc();
+ /* This is the fastest way to let users know
+ * the Intel CPU is now alive.
+ */
+ google_chromeec_kbbacklight(100);
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+ setup_pch_gpios(&link_gpio_map);
+
+ /* Initialize console device(s) */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected\n");
+ boot_mode = 1;
+
+ /* System is not happy after keyboard reset... */
+ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+ outb(0x6, 0xcf9);
+ hlt();
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ copy_spd(&pei_data);
+
+ post_code(0x3a);
+ pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_dram_time = rdtsc();
+#endif
+ sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_dram_time = rdtsc();
+#endif
+ post_code(0x3c);
+
+ rcba_config();
+ post_code(0x3d);
+
+ quick_ram_check();
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+ cbmem_was_initted = !cbmem_initialize();
+#else
+ cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+ - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+#if CONFIG_CHROMEOS
+ init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(base_time);
+ timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+ timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+ timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+ /* Keep this the last thing this function does. */
+ cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex b/src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex
new file mode 100644
index 0000000..1ba9f83
--- /dev/null
+++ b/src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex
@@ -0,0 +1,33 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+f0 0a 3c 3c 01 40 83 01
+00 80 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ce 01
+00 00 00 00 00 00 6a 04
+4d 34 37 31 42 35 36 37
+34 42 48 30 2d 59 4b 30
+20 20 00 00 80 ce 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+
diff --git a/src/mainboard/google/link/thermal.h b/src/mainboard/google/link/thermal.h
new file mode 100644
index 0000000..14caaa1
--- /dev/null
+++ b/src/mainboard/google/link/thermal.h
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LINK_THERMAL_H
+#define LINK_THERMAL_H
+
+/* Config TDP Sensor ID */
+#define CTDP_SENSOR_ID 2 /* I2C_PCH-Die */
+
+/* Config TDP Nominal */
+#define CTDP_NOMINAL_THRESHOLD_OFF 0
+#define CTDP_NOMINAL_THRESHOLD_ON 0
+
+/* Config TDP Down */
+#define CTDP_DOWN_THRESHOLD_OFF 60
+#define CTDP_DOWN_THRESHOLD_ON 65
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 104
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 100
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE 105
+
+#endif
diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig
new file mode 100644
index 0000000..e141033
--- /dev/null
+++ b/src/mainboard/google/parrot/Kconfig
@@ -0,0 +1,57 @@
+if BOARD_GOOGLE_PARROT
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_COMPAL_ENE932
+ select BOARD_HAS_FADT
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_MAINBOARD_RESOURCES
+ select MMCONF_SUPPORT
+ select HAVE_SMI_HANDLER
+ select GFXUMA
+ select CHROMEOS
+ select EXTERNAL_MRC_BLOB
+
+ # Workaround for EC/KBC IRQ1.
+ select SERIRQ_CONTINUOUS_MODE
+
+config MAINBOARD_DIR
+ string
+ default google/parrot
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Parrot"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0xc000
+
+endif # BOARD_GOOGLE_PARROT
diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc
new file mode 100644
index 0000000..c4fb74d
--- /dev/null
+++ b/src/mainboard/google/parrot/Makefile.inc
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
+SRC_ROOT = $(src)/mainboard/google/parrot
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/parrot/acpi/chromeos.asl
similarity index 70%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/parrot/acpi/chromeos.asl
index 3ae8657..622b5d9 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/parrot/acpi/chromeos.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+Name(OIPG, Package() {
+ Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
+ Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
+ Package() { 0x003, 0, 70, "PantherPoint" }, // firmware write protect
+})
-struct mainboard_config {};
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/parrot/acpi/ec.asl
similarity index 72%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/parrot/acpi/ec.asl
index 3ae8657..522a0b9 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/parrot/acpi/ec.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+/* mainboard configuration */
+#include "../ec.h"
+#define EC_SCI 23 // GPIO7 << 16 to GPE bit for Runtime SCI
-struct mainboard_config {};
+/* ACPI code for EC functions */
+#include "../../../../ec/compal/ene932/acpi/ec.asl"
diff --git a/src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl
new file mode 100644
index 0000000..dd32379
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/ivybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for IvyBridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 22 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 19 },
+ Package() { 0x001cffff, 1, 0, 20 },
+ Package() { 0x001cffff, 2, 0, 17 },
+ Package() { 0x001cffff, 3, 0, 18 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 20 },
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 21 },
+ Package() { 0x001fffff, 1, 0, 22 },
+ Package() { 0x001fffff, 2, 0, 23 },
+ Package() { 0x001fffff, 3, 0, 16 },
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl
new file mode 100644
index 0000000..7b9aef0
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/mainboard.asl
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_GPE) {
+ Method(_L1F, 0x0, NotSerialized)
+ {
+ Notify(\_SB.LID0,0x80)
+ }
+}
+
+Scope (\_SB) {
+ Device (LID0)
+ {
+ Name(_HID, EisaId("PNP0C0D"))
+ Method(_LID, 0)
+ {
+ Store (GP15, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name(_HID, EisaId("PNP0C0C"))
+ }
+
+ Device (TPAD)
+ {
+ Name (_ADR, 0x0)
+ Name (_UID, 1)
+
+ // Report as a Sleep Button device so Linux will
+ // automatically enable it as a wake source
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Trackpad Wake is GPIO12, wake from S3
+ Name(_PRW, Package(){0x1c, 0x03})
+
+ Name(_CRS, ResourceTemplate()
+ {
+
+ // PIRQA -> GSI16
+ Interrupt (ResourceConsumer, Level, ActiveLow) {16}
+
+ // PIRQE -> GSI20
+ Interrupt (ResourceConsumer, Edge, ActiveLow) {20}
+
+ // SMBUS Address 0x67
+ VendorShort (ADDR) {0x67}
+ })
+ }
+
+}
diff --git a/src/mainboard/google/parrot/acpi/platform.asl b/src/mainboard/google/parrot/acpi/platform.asl
new file mode 100644
index 0000000..2d59ebe
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/platform.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Update in case state changed while asleep */
+ /* Update AC status */
+ Store (\_SB.PCI0.LPCB.EC0.ADPT, Local0)
+ if (LNotEqual (Local0, \PWRS)) {
+ Store (Local0, \PWRS)
+ Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
+ }
+
+ /* Update LID status */
+ Store (GP15, Local0)
+ if (LNotEqual (Local0, \LIDS)) {
+ Store (Local0, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..ee4221a
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 19 },
+ Package() { 0x001cffff, 1, 0, 20 },
+ Package() { 0x001cffff, 2, 0, 17 },
+ Package() { 0x001cffff, 3, 0, 18 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 },
+ Package() { 0x001fffff, 1, 0, 23 },
+ Package() { 0x001fffff, 2, 0, 16 },
+ Package() { 0x001fffff, 3, 0, 18 },
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/intel/emeraldlake2/chip.h b/src/mainboard/google/parrot/acpi/superio.asl
similarity index 72%
copy from src/mainboard/intel/emeraldlake2/chip.h
copy to src/mainboard/google/parrot/acpi/superio.asl
index fbe2477..e4856fc 100644
--- a/src/mainboard/intel/emeraldlake2/chip.h
+++ b/src/mainboard/google/parrot/acpi/superio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,5 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+/* mainboard configuration */
+#include "../ec.h"
+
+
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include "../../../../ec/compal/ene932/acpi/superio.asl"
diff --git a/src/mainboard/google/parrot/acpi/thermal.asl b/src/mainboard/google/parrot/acpi/thermal.asl
new file mode 100644
index 0000000..440612c
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi/thermal.asl
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Ignore critical temps for the first few reads
+ // at boot to prevent unexpected shutdown
+ Name (IRDC, 4)
+ Name (CRDC, 0)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ // Get CPU Temperature from the Embedded Controller
+ Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0)
+
+ // Re-read from EC if the temperature is very high to
+ // avoid OS shutdown if we got a bad reading.
+ If (LGreaterEqual (Local0, \TCRT)) {
+ Store (\_SB.PCI0.LPCB.EC0.CTMP, Local0)
+ If (LGreaterEqual (Local0, \TCRT)) {
+ // Check if this is an early read
+ If (LLess (CRDC, IRDC)) {
+ Store (0, Local0)
+ }
+ }
+ }
+
+ // Keep track of first few reads by the OS
+ If (LLess (CRDC, IRDC)) {
+ Increment (CRDC)
+ }
+
+ Return (CTOK (Local0))
+ }
+
+// The EC does all fan control. The is no Active Cooling Fan control (_ACx).
+
+ }
+}
+
diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/google/parrot/acpi/video.asl
similarity index 71%
copy from src/mainboard/roda/rk886ex/chip.h
copy to src/mainboard/google/parrot/acpi/video.asl
index 6f24f71..3ececa9 100644
--- a/src/mainboard/roda/rk886ex/chip.h
+++ b/src/mainboard/google/parrot/acpi/video.asl
@@ -17,5 +17,27 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c
new file mode 100644
index 0000000..c91a60c
--- /dev/null
+++ b/src/mainboard/google/parrot/acpi_tables.c
@@ -0,0 +1,306 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/compal/ene932/ec.h>
+#include "ec.h"
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ /* EC handles all active thermal and fan control on Parrot. */
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs_ = gnvs;
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /*
+ * Enable Front USB ports in S5 by default
+ * to be consistent with back port behavior
+ */
+ gnvs->s5u0 = 1;
+ gnvs->s5u1 = 1;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+ acpi_update_thermal_table(gnvs);
+
+ gnvs->chromeos.vbt2 = parrot_ec_running_ro() ?
+ ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfed00000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x8086a201; /* Intel */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0080;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_intel_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, "COREBOOT");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/google/parrot/chromeos.c b/src/mainboard/google/parrot/chromeos.c
new file mode 100644
index 0000000..1d5361c
--- /dev/null
+++ b/src/mainboard/google/parrot/chromeos.c
@@ -0,0 +1,189 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/compal/ene932/ec.h>
+#include "ec.h"
+
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT 6
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+ u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+ u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+
+ if (!gpio_base)
+ return;
+
+ u32 gp_lvl = inl(gpio_base + GP_LVL);
+ u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
+
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ /* Write Protect: GPIO70 active high */
+ gpios->gpios[0].port = 70;
+ gpios->gpios[0].polarity = ACTIVE_LOW;
+ gpios->gpios[0].value = (gp_lvl3 >> (70 - 64)) & 1;
+ strncpy((char *)gpios->gpios[0].name,"write protect", GPIO_MAX_NAME_LENGTH);
+
+ /* Recovery: Virtual GPIO in the EC (Servo GPIO69 active low) */
+ gpios->gpios[1].port = -1;
+ gpios->gpios[1].polarity = ACTIVE_HIGH;
+ gpios->gpios[1].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+ /* Developer: Virtual GPIO in the EC ( Servo GPIO17 active low) */
+ gpios->gpios[2].port = -1;
+ gpios->gpios[2].polarity = ACTIVE_HIGH;
+ gpios->gpios[2].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+ /* Lid switch GPIO active high (open). */
+ gpios->gpios[3].port = 15;
+ gpios->gpios[3].polarity = ACTIVE_HIGH;
+ gpios->gpios[3].value = ((gp_lvl >> 15) & 1);;
+ strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+ /* Power Button */
+ gpios->gpios[4].port = 101;
+ gpios->gpios[4].polarity = ACTIVE_LOW;
+ gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
+ strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+
+ /* Did we load the VGA Option ROM? */
+ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[5].polarity = ACTIVE_HIGH;
+ gpios->gpios[5].value = oprom_is_loaded;
+ strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+
+ /* EC RW: GPIO68 active low */
+ /* TODO: Add this once this is added to uboot and inc the GPIO count above.
+ * gpios->gpios[6].port = 68;
+ * gpios->gpios[6].polarity = ACTIVE_LOW;
+ * gpios->gpios[6].value = (gp_lvl3 >> (68 - 64)) & 1;
+ * strncpy((char *)gpios->gpios[1].name,"ec_in_rw", GPIO_MAX_NAME_LENGTH);
+ */
+}
+#endif
+
+
+int get_developer_mode_switch(void)
+{
+ device_t dev;
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+ u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+
+ if (!gpio_base)
+ return(0);
+
+/*
+ * Dev mode is controled by EC and uboot stores a flag in TPM. This GPIO is only
+ * for the debug header. It is AND'd to the EC request.
+ */
+
+ u32 gp_lvl = inl(gpio_base + GP_LVL);
+ printk(BIOS_DEBUG,"DEV MODE GPIO 17: %x\n", !((gp_lvl >> 17) & 1));
+
+ /* GPIO17, active low -- return active high reading and let
+ * it be inverted by the caller if needed. */
+ return !((gp_lvl >> 17) & 1);
+}
+
+int get_recovery_mode_switch(void)
+{
+ u8 rec_mode;
+
+ device_t dev;
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+ u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+
+ if (!gpio_base)
+ return(0);
+
+ /* GPIO69, active low. For Servo support
+ * Treat as active high and let the caller invert if needed. */
+ u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
+ rec_mode = !((gp_lvl3 >> (69 - 64)) & 1);
+ printk(BIOS_DEBUG,"REC MODE GPIO 69: %x\n", rec_mode);
+
+/*
+ * Check EC B3(command) FC(data) 2C(data) to EC. And then EC will return a byte.
+ * Bit0 – 0: Recovery mode (active low)
+ * Bit0 – 1: Normal mode
+ *
+ * OR this together to go to REC MODE from EC and Servo.
+ */
+#ifndef __PRE_RAM__
+ ec_kbc_write_cmd(0xB3);
+ ec_kbc_write_ib(0xFC);
+ ec_kbc_write_ib(0x2C);
+ rec_mode |= !(ec_kbc_read_ob() & 1);
+ printk(BIOS_DEBUG,"REC MODE (EC OR'd with GPIO): %x\n", rec_mode);
+#endif
+
+ return (rec_mode);
+}
+
+int parrot_ec_running_ro(void)
+{
+ device_t dev;
+#ifdef __PRE_RAM__
+ dev = PCI_DEV(0, 0x1f, 0);
+#else
+ dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+#endif
+ u16 gpio_base = pci_read_config32(dev, GPIOBASE) & 0xfffe;
+
+ if (!gpio_base)
+ return(0);
+
+ /* GPIO68 EC_RW is active low.
+ * Treat as active high and let the caller invert if needed. */
+ u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
+ return !((gp_lvl3 >> (68 - 64)) & 1);
+}
diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout
new file mode 100644
index 0000000..afdd3c6
--- /dev/null
+++ b/src/mainboard/google/parrot/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb
new file mode 100644
index 0000000..6d7f28a
--- /dev/null
+++ b/src/mainboard/google/parrot/devicetree.cb
@@ -0,0 +1,103 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DisplayPort B Hotplug with 6ms pulse
+ register "gpu_dp_b_hotplug" = "0x06"
+
+ # Enable Panel as eDP and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "5" # 400ms
+ register "gpu_panel_power_up_delay" = "500" # 50ms
+ register "gpu_panel_power_down_delay" = "150" # 15ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
+
+ # Set backlight PWM values
+ register "gpu_cpu_backlight" = "0x000001d4"
+ register "gpu_pch_backlight" = "0x03aa0000"
+
+ device lapic_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Coordinate with HW_ALL
+ register "pstate_coord_type" = "0xfe"
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device pci_domain 0 on
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x8b"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "alt_gp_smi_en" = "0x0100"
+ register "gpi7_routing" = "2"
+ register "gpi8_routing" = "1"
+ register "gpi15_routing" = "2" #lid switch gpe
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ register "sata_port_map" = "0x1"
+
+ # EC range is 0xFD60 (EC_IO) and 0x68/0x6C
+ register "gen1_dec" = "0x0004fd61"
+ register "gen2_dec" = "0x00040069"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 off end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2 (WLAN)
+ device pci 1c.2 on end # PCIe Port #3 (ETH0)
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 off end # PCIe Port #6
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip ec/compal/ene932
+ # 60/64 KBC
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA Controller 2
+ device pci 1f.6 on end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl
new file mode 100644
index 0000000..608827a
--- /dev/null
+++ b/src/mainboard/google/parrot/dsdt.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include "acpi/thermal.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/parrot/ec.c b/src/mainboard/google/parrot/ec.c
new file mode 100644
index 0000000..e6d2d38
--- /dev/null
+++ b/src/mainboard/google/parrot/ec.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <ec/compal/ene932/ec.h>
+#include "ec.h"
+
+
+void parrot_ec_init(void)
+{
+ printk(BIOS_DEBUG, "Parrot EC Init\n");
+
+ /* Clean up the buffers. We don't know the initial condition. */
+ kbc_cleanup_buffers();
+
+ /* Report EC info */
+ /* EC version: cmd 0x51 - returns three bytes */
+ ec_kbc_write_cmd(0x51);
+ printk(BIOS_DEBUG," EC version %x.%x.%x\n",
+ ec_kbc_read_ob(), ec_kbc_read_ob(), ec_kbc_read_ob());
+
+ /* EC Project name: cmd 0x52, 0xA0 - returns five bytes */
+ ec_kbc_write_cmd(0x52);
+ ec_kbc_write_ib(0xA0);
+ printk(BIOS_DEBUG," EC Project: %c%c%c%c%c\n",
+ ec_kbc_read_ob(),ec_kbc_read_ob(),ec_kbc_read_ob(),
+ ec_kbc_read_ob(), ec_kbc_read_ob());
+
+ /* Print the hardware revision */
+ printk(BIOS_DEBUG," Parrot Revision %x\n", parrot_rev());
+
+ /* US Keyboard */
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE5);
+
+ /* Enable IRQ1 */
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xD1);
+
+ /* TODO - Do device detection and device maintain state (nvs) */
+ /* Enable Wireless and Bluetooth */
+ ec_kbc_write_cmd(0x45);
+ ec_kbc_write_ib(0xAD);
+
+ /* Set Wireless and Bluetooth Available */
+ ec_kbc_write_cmd(0x45);
+ ec_kbc_write_ib(0xA8);
+
+ /* Set Wireless and Bluetooth Enable */
+ ec_kbc_write_cmd(0x45);
+ ec_kbc_write_ib(0xA2);
+}
+
+
+/* Parrot Hardware Revision */
+u8 parrot_rev(void)
+{
+ ec_kbc_write_cmd(0x45);
+ ec_kbc_write_ib(0x40);
+ return ec_kbc_read_ob();
+}
diff --git a/src/mainboard/google/parrot/ec.h b/src/mainboard/google/parrot/ec.h
new file mode 100644
index 0000000..4c086fd
--- /dev/null
+++ b/src/mainboard/google/parrot/ec.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef PARROT_EC_H
+#define PARROT_EC_H
+
+#define EC_SCI_GPI 7 /* GPIO7 is EC_SCI# */
+#define EC_SMI_GPI 8 /* GPIO8 is EC_SMI# */
+
+/* EC SMI sources TODO - make defines
+ * No event 80h
+*/
+#define EC_NO_EVENT 0x80
+/*
+ * DTS temperature update A0h
+ * Decrease brightness event A1h
+ * Increase brightness event A2h
+ * Lid open A5h
+ * Lid closed A6h
+ */
+#define EC_LID_CLOSE 0xA6
+ /* Bluetooth wake up event A9h
+ * Display change (LCD , CRT) ACh
+ * Cpu fast event ADh
+ * Cpu slow event ADh
+ * Battery life in critical low state (LLB) B2h
+ * Battery life in low power state (LB) B3h
+ * Battery Plug-In B5h
+ * Docked in request BAh
+ * Undock request BBh
+ * Power button pressed C2h
+ * AC power plug-in C7h
+ * AC power plug-out C8h
+ * Modem Ring In CAh
+ * PME signal active CEh
+ * Acer Hotkey Function – Make event D5h
+ * Acer Hotkey Function – Break event D6h
+ */
+
+#ifndef __ACPI__
+extern void parrot_ec_init(void);
+u8 parrot_rev(void);
+int parrot_ec_running_ro(void);
+#endif
+
+#endif // PARROT_EC_H
diff --git a/src/mainboard/google/parrot/fadt.c b/src/mainboard/google/parrot/fadt.c
new file mode 100644
index 0000000..06d3231
--- /dev/null
+++ b/src/mainboard/google/parrot/fadt.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT 0xb2
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
+#define ACPI_DISABLE 0x1e
+#define ACPI_ENABLE 0xe1
+#define GNVS_UPDATE 0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_DESKTOP;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/parrot/gpio.h b/src/mainboard/google/parrot/gpio.h
new file mode 100644
index 0000000..a9eb99b
--- /dev/null
+++ b/src/mainboard/google/parrot/gpio.h
@@ -0,0 +1,279 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef PARROT_GPIO_H
+#define PARROT_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio1 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio2 = GPIO_MODE_NATIVE, /* NOT USED / PIRQE# */
+ .gpio3 = GPIO_MODE_NONE, /* NOT USED / PIRQ#F */
+ .gpio4 = GPIO_MODE_NONE, /* NOT USED / PIRQG# */
+ .gpio5 = GPIO_MODE_NONE, /* NOT USED / PIRQH# */
+ .gpio6 = GPIO_MODE_NONE, /* NOT USED / FAN TACH2 */
+ .gpio7 = GPIO_MODE_GPIO, /* EC_SCI# */
+ .gpio8 = GPIO_MODE_GPIO, /* EC SMI# */
+ .gpio9 = GPIO_MODE_NATIVE, /* NOT USED / OC5# USB */
+ .gpio10 = GPIO_MODE_NATIVE, /* NOT USED / OC6# USB */
+ .gpio11 = GPIO_MODE_NONE, /* NOT USED / SMB_ALERT*/
+ .gpio12 = GPIO_MODE_GPIO, /* Track Pad IRQ / LAN_PHY_PWR_CTRL / SMB_ALERT */
+ .gpio13 = GPIO_MODE_NONE, /* NOT USED / HDA_DOCK_RST */
+ .gpio14 = GPIO_MODE_NATIVE, /* NOT USED / OC7# USB */
+ .gpio15 = GPIO_MODE_GPIO, /* EC_LID_OUT (INPUT to PantherPoint) */
+ .gpio16 = GPIO_MODE_NONE, /* NOT USED / SATA4GP */
+ .gpio17 = GPIO_MODE_GPIO, /* DEV MODE */
+ .gpio18 = GPIO_MODE_NATIVE, /* PCIECLKRQ1# */
+ .gpio19 = GPIO_MODE_NONE, /* BIOS BOOT STRAP (NOT USED)/ SATA1GP */
+ .gpio20 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ2# */
+ .gpio21 = GPIO_MODE_NONE, /* NOT USED / SATA0GP */
+ .gpio22 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio23 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio24 = GPIO_MODE_NONE, /* NOT USED / MEM_LED */
+ .gpio25 = GPIO_MODE_NATIVE, /* PCIECLKRQ3# */
+ .gpio26 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ4# */
+ .gpio27 = GPIO_MODE_NONE, /* S4,S5 WAKE? */
+ .gpio28 = GPIO_MODE_NONE, /* On-Die PLL Voltage Regulator */
+ .gpio29 = GPIO_MODE_NONE, /* NOT USED / SLP_LAN# */
+ .gpio30 = GPIO_MODE_NATIVE, /* SUS_WARN# */
+ .gpio31 = GPIO_MODE_NATIVE, /* ACPRESENT */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_INPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio23 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio25 = GPIO_DIR_INPUT,
+ .gpio26 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio0 = GPIO_LEVEL_LOW,
+ .gpio1 = GPIO_LEVEL_LOW,
+ .gpio2 = GPIO_LEVEL_LOW,
+ .gpio3 = GPIO_LEVEL_LOW,
+ .gpio4 = GPIO_LEVEL_LOW,
+ .gpio5 = GPIO_LEVEL_LOW,
+ .gpio6 = GPIO_LEVEL_LOW,
+ .gpio7 = GPIO_LEVEL_LOW,
+ .gpio8 = GPIO_LEVEL_LOW,
+ .gpio9 = GPIO_LEVEL_LOW,
+ .gpio10 = GPIO_LEVEL_LOW,
+ .gpio11 = GPIO_LEVEL_LOW,
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio13 = GPIO_LEVEL_LOW,
+ .gpio14 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio16 = GPIO_LEVEL_LOW,
+ .gpio17 = GPIO_LEVEL_LOW,
+ .gpio18 = GPIO_LEVEL_LOW,
+ .gpio19 = GPIO_LEVEL_LOW,
+ .gpio20 = GPIO_LEVEL_LOW,
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_LOW,
+ .gpio24 = GPIO_LEVEL_LOW,
+ .gpio25 = GPIO_LEVEL_LOW,
+ .gpio26 = GPIO_LEVEL_LOW,
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_LOW,
+ .gpio29 = GPIO_LEVEL_LOW,
+ .gpio30 = GPIO_LEVEL_LOW,
+ .gpio31 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio12 = GPIO_INVERT,
+ .gpio15 = GPIO_INVERT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio36 = GPIO_MODE_GPIO, /* W_DISABLE_L */
+ .gpio41 = GPIO_MODE_GPIO, /* SPD vector D0 */
+ .gpio42 = GPIO_MODE_GPIO, /* SPD vector D1 */
+ .gpio43 = GPIO_MODE_GPIO, /* SPD vector D2 */
+ .gpio57 = GPIO_MODE_GPIO, /* PCH_SPI_WP_D */
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+ .gpio42 = GPIO_DIR_INPUT,
+ .gpio43 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio47 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio58 = GPIO_DIR_INPUT,
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+ .gpio61 = GPIO_DIR_INPUT,
+ .gpio62 = GPIO_DIR_INPUT,
+ .gpio63 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio32 = GPIO_LEVEL_LOW,
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_LOW,
+ .gpio39 = GPIO_LEVEL_LOW,
+ .gpio40 = GPIO_LEVEL_LOW,
+ .gpio41 = GPIO_LEVEL_LOW,
+ .gpio42 = GPIO_LEVEL_LOW,
+ .gpio43 = GPIO_LEVEL_LOW,
+ .gpio44 = GPIO_LEVEL_LOW,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio46 = GPIO_LEVEL_LOW,
+ .gpio47 = GPIO_LEVEL_LOW,
+ .gpio48 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_LOW,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio52 = GPIO_LEVEL_LOW,
+ .gpio53 = GPIO_LEVEL_LOW,
+ .gpio54 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio56 = GPIO_LEVEL_LOW,
+ .gpio57 = GPIO_LEVEL_LOW,
+ .gpio58 = GPIO_LEVEL_LOW,
+ .gpio59 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_LOW,
+ .gpio61 = GPIO_LEVEL_LOW,
+ .gpio62 = GPIO_LEVEL_LOW,
+ .gpio63 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX0 */
+ .gpio65 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX1 */
+ .gpio66 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX2 */
+ .gpio67 = GPIO_MODE_NONE, /* NOT USED / CLK_FLEX3 */
+ .gpio68 = GPIO_MODE_NONE, /* NOT USED / FAN TACK4 */
+ .gpio69 = GPIO_MODE_GPIO, /* REC_MODE_L / FAN TACK5 */
+ .gpio70 = GPIO_MODE_GPIO, /* SPI_WP1#_RPCH / FAN TACK7 */
+ .gpio71 = GPIO_MODE_GPIO, /* LVDS/eDP / FAN TACK8 */
+ .gpio72 = GPIO_MODE_NONE, /* NOT USED / BATLOW# */
+ .gpio73 = GPIO_MODE_NONE, /* NOT USED / PCIECLKRQ0#*/
+ .gpio74 = GPIO_MODE_NONE, /* NOT USED / SML1ALERT# /PCHHOT# */
+ .gpio75 = GPIO_MODE_NATIVE, /* SML1DATA */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_INPUT,
+ .gpio65 = GPIO_DIR_INPUT,
+ .gpio66 = GPIO_DIR_INPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_INPUT,
+ .gpio73 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+ .gpio75 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_LOW,
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_LOW,
+ .gpio67 = GPIO_LEVEL_LOW,
+ .gpio68 = GPIO_LEVEL_LOW,
+ .gpio69 = GPIO_LEVEL_LOW,
+ .gpio70 = GPIO_LEVEL_LOW,
+ .gpio71 = GPIO_LEVEL_LOW,
+ .gpio72 = GPIO_LEVEL_LOW,
+ .gpio73 = GPIO_LEVEL_LOW,
+ .gpio74 = GPIO_LEVEL_LOW,
+ .gpio75 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_map parrot_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+#endif
diff --git a/src/mainboard/google/parrot/hda_verb.h b/src/mainboard/google/parrot/hda_verb.h
new file mode 100644
index 0000000..8860ec8
--- /dev/null
+++ b/src/mainboard/google/parrot/hda_verb.h
@@ -0,0 +1,152 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * Parrot audio ports:
+ * ALC269:
+ * out:
+ * Internal Speaker: PORT D (0x14)
+ * Headphone: PORT A - (0x21) (SenseA)
+ *
+ * in:
+ * Mic2: PORT F (0x19) (SenseB)
+ * Line2 (internal Mic): PORT E (0x1B)
+ * PCBeep
+ *
+ * HDMI PatherPoint
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269
+ 0x10250742, // Subsystem ID
+ 0x0000000B, // Number of jacks (NID entries)
+
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10250742 */
+ 0x00172042,
+ 0x00172107,
+ 0x00172225,
+ 0x00172310,
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12) DMIC */
+ 0x01271cf0,
+ 0x01271d11,
+ 0x01271e11,
+ 0x01271f41,
+
+ /* Pin Complex (NID 0x14) SPKR-OUT PORTD */
+ 0x01471c10, // group 1, front left/right
+ 0x01471d01, // no connector, no jack detect
+ 0x01471e17, // speaker out, analog
+ 0x01471f90, // fixed function, internal
+
+ /* Pin Complex (NID 0x17) */
+ 0x01771cf0,
+ 0x01771d11,
+ 0x01771e11,
+ 0x01771f41,
+
+ /* Pin Complex (NID 0x18) MIC1 PORTB */
+ 0x01871cf0,
+ 0x01871d11,
+ 0x01871e11,
+ 0x01871f41,
+
+ /* Pin Complex (NID 0x19) MIC2 PORTF */
+ 0x01971c21, // group 2, cap 1
+ 0x01971d10, // black, jack detect
+ 0x01971ea7, // mic in, analog
+ 0x01971f04, // connector, right panel
+
+ /* Pin Complex (NID 0x1A) LINE1 PORTC */
+ 0x01a71cf0,
+ 0x01a71d11,
+ 0x01a71e11,
+ 0x01a71f41,
+
+ /* Pin Complex (NID 0x1B) LINE2 PORTE */
+ 0x01b71c20, // group 2, cap 0
+ 0x01b71d01, // no connector, no jack detect
+ 0x01b71ea7, // mic in, analog
+ 0x01b71f90, // fixed function, internal
+
+ /* Pin Complex (NID 0x1d) PCBeep */
+ 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable
+ 0x01d71d81, // mute spkr on hpout
+ 0x01d71e15, // pcbeep en able, checksum
+ 0x01d71f40, // no physical, internal
+
+ /* Pin Complex (NID 0x1E) SPDIF-OUT */
+ 0x01e71cf0,
+ 0x01e71d11,
+ 0x01e71e11,
+ 0x01e71f41,
+
+ /* Pin Complex (NID 0x21) HPOUT PORTA? */
+ 0x02171c1f, // group1,
+ 0x02171d10, // black, jack detect
+ 0x02171e21, // HPOut, 1/8 stereo
+ 0x02171f04, // connector, right panel
+
+ /* --- Next Codec --- */
+
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of jacks
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ 0x00172001,
+ 0x00172101,
+ 0x00172286,
+ 0x00172380,
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ 0x30571c10,
+ 0x30571d00,
+ 0x30571e56,
+ 0x30571f18,
+
+ /* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+ 0x30671c20,
+ 0x30671d00,
+ 0x30671e56,
+ 0x30671f18,
+
+ /* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+ 0x30771c30,
+ 0x30771d00,
+ 0x30771e56,
+ 0x30771f18
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x00170500, /* power up everything (codec, dac, adc, mixers) */
+ 0x01470740, /* enable speaker out */
+ 0x01470c02, /* set speaker EAPD pin */
+ 0x0143b01f, /* unmute speaker */
+ 0x00c37100, /* unmute mixer nid 0xc input 1 */
+ 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
+};
+
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/google/parrot/mainboard.c b/src/mainboard/google/parrot/mainboard.c
new file mode 100644
index 0000000..624b187
--- /dev/null
+++ b/src/mainboard/google/parrot/mainboard.c
@@ -0,0 +1,330 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/compal/ene932/ec.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res=-1;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, regs->eax & 0xffff);
+
+ switch(regs->eax & 0xffff) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffffff00;
+ regs->ecx |= 0x00; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0003; /* eDP */
+ res = 0;
+ break;
+ case 0x5f70:
+ switch ((regs->ecx >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ ((regs->ecx >> 8) & 0xff));
+ return 0;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x00;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 3; /* eDP */
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ return 0;
+ }
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+ M.x86.R_AX);
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 * pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+
+}
+
+static void mainboard_init(device_t dev)
+{
+ /* Initialize the Embedded Controller */
+ parrot_ec_init();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+}
+
+static int parrot_smbios_type41(int *handle, unsigned long *current,
+ const char *name, u8 irq, u8 addr)
+{
+ struct smbios_type41 *t = (struct smbios_type41 *)*current;
+ int len = sizeof(struct smbios_type41);
+
+ memset(t, 0, sizeof(struct smbios_type41));
+ t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
+ t->handle = *handle;
+ t->length = len - 2;
+ t->reference_designation = smbios_add_string(t->eos, name);
+ t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
+ t->device_status = 1;
+ t->device_type_instance = irq;
+ t->segment_group_number = 0;
+ t->bus_number = addr;
+ t->function_number = 0;
+ t->device_number = 0;
+
+ len = t->length + smbios_string_table_len(t->eos);
+ *current += len;
+ *handle += 1;
+ return len;
+}
+
+static int parrot_onboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+ u8 hardware_version = parrot_rev();
+ if (hardware_version < 0x2) { /* DVT vs PVT */
+ len += parrot_smbios_type41(handle, current,
+ PARROT_TRACKPAD_NAME,
+ PARROT_TRACKPAD_IRQ_DVT,
+ PARROT_TRACKPAD_I2C_ADDR);
+ } else {
+ len += parrot_smbios_type41(handle, current,
+ PARROT_TRACKPAD_NAME,
+ PARROT_TRACKPAD_IRQ_PVT,
+ PARROT_TRACKPAD_I2C_ADDR);
+ }
+
+
+ return len;
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Google Parrot ChromeBook")
+ .enable_dev = mainboard_enable,
+ .get_smbios_data = parrot_onboard_smbios_data,
+};
diff --git a/src/mainboard/google/parrot/mainboard_smi.c b/src/mainboard/google/parrot/mainboard_smi.c
new file mode 100644
index 0000000..9caa4d7
--- /dev/null
+++ b/src/mainboard/google/parrot/mainboard_smi.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <ec/compal/ene932/ec.h>
+#include "ec.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ printk(BIOS_DEBUG, "mainboard_io_trap_handler: %x\n", smif);
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+
+static u8 mainboard_smi_ec(void)
+{
+ u8 src;
+ extern u16 pmbase; /* Set in southbridge SMI handler */
+ u32 pm1_cnt;
+
+ ec_kbc_write_cmd(0x56);
+ src = ec_kbc_read_ob();
+ printk(BIOS_DEBUG, "mainboard_smi_ec src: %x\n", src);
+
+ switch (src) {
+ case EC_LID_CLOSE:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+ /* Go to S5 */
+ pm1_cnt = inl(pmbase + PM1_CNT);
+ pm1_cnt |= (0xf << 10);
+ outl(pm1_cnt, pmbase + PM1_CNT);
+ break;
+ }
+
+ return src;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ printk(BIOS_DEBUG, "mainboard_smi_gpi: %x\n", gpi_sts);
+ if (gpi_sts & (1 << EC_SMI_GPI)) {
+ /* Process all pending events */
+ while (mainboard_smi_ec() != EC_NO_EVENT);
+ }
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ printk(BIOS_DEBUG, "mainboard_smi_sleep: %x\n", slp_typ);
+ /* Disable SCI and SMI events */
+
+
+ /* Clear pending events that may trigger immediate wake */
+
+
+ /* Enable wake events */
+
+}
+
+#define APMC_FINALIZE 0xcb
+#define APMC_ACPI_EN 0xe1
+#define APMC_ACPI_DIS 0x1e
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ printk(BIOS_DEBUG, "mainboard_smi_apmc: %x\n", apmc);
+ switch (apmc) {
+ case APMC_FINALIZE:
+ printk(BIOS_DEBUG, "APMC: FINALIZE\n");
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "APMC#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ case APMC_ACPI_EN:
+ printk(BIOS_DEBUG, "APMC: ACPI_EN\n");
+ /* Clear all pending events */
+ /* EC cmd:59 data:E8 */
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE8);
+ break;
+ case APMC_ACPI_DIS:
+ printk(BIOS_DEBUG, "APMC: ACPI_DIS\n");
+ /* Clear all pending events */
+ /* EC cmd:59 data:e9 */
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE9);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/parrot/onboard.h
similarity index 68%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/parrot/onboard.h
index 3ae8657..f3d200d 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/parrot/onboard.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,13 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+#ifndef PARROT_ONBOARD_H
+#define PARROT_ONBOARD_H
-struct mainboard_config {};
+#include <arch/smp/mpspec.h>
+
+#define PARROT_TRACKPAD_NAME "trackpad"
+#define PARROT_TRACKPAD_I2C_ADDR 0x67
+#define PARROT_TRACKPAD_IRQ_DVT 16
+#define PARROT_TRACKPAD_IRQ_PVT 20
+#endif
diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c
new file mode 100644
index 0000000..19ea057
--- /dev/null
+++ b/src/mainboard/google/parrot/romstage.c
@@ -0,0 +1,307 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+#include "ec/compal/ene932/ec.h"
+
+static void pch_enable_lpc(void)
+{
+ /* Parrot EC Decode Range Port60/64, Port62/66 */
+ /* Enable EC, PS/2 Keyboard/Mouse */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN);
+
+ /* Map EC_IO decode to the LPC bus */
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (EC_IO & ~3) | 0x00040001);
+
+ /* Map EC registers 68/6C decode to the LPC bus */
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, (68 & ~3) | 0x00040001);
+}
+
+static void rcba_config(void)
+{
+ u32 reg32;
+
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D28IP_P2IP WLAN INTA -> PIRQB
+ * D28IP_P3IP ETH0 INTC -> PIRQD
+ * D29IP_E1P EHCI1 INTA -> PIRQE
+ * D26IP_E2P EHCI2 INTA -> PIRQE
+ * D31IP_SIP SATA INTA -> PIRQF (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQG
+ * D31IP_TTIP THRT INTC -> PIRQH
+ * D27IP_ZIP HDA INTA -> PIRQG (MSI)
+ *
+ * Trackpad DVT PIRQA (16)
+ * Trackpad DVT PIRQE (20)
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+ (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+ (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
+ (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+ DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
+ DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+
+ /* Disable unused devices (board specific) */
+ reg32 = RCBA32(FD);
+ reg32 |= PCH_DISABLE_ALWAYS;
+ /* Disable PCI bridge so MRC does not probe this bus */
+ reg32 |= PCH_DISABLE_P2P;
+ RCBA32(FD) = reg32;
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ tsc_t start_romstage_time;
+ tsc_t before_dram_time;
+ tsc_t after_dram_time;
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+#endif
+ struct pei_data pei_data = {
+ pei_version: PEI_VERSION,
+ mchbar: DEFAULT_MCHBAR,
+ dmibar: DEFAULT_DMIBAR,
+ epbar: DEFAULT_EPBAR,
+ pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+ smbusbar: SMBUS_IO_BASE,
+ wdbbar: 0x4000000,
+ wdbsize: 0x1000,
+ hpet_address: HPET_ADDR,
+ rcba: DEFAULT_RCBABASE,
+ pmbase: DEFAULT_PMBASE,
+ gpiobase: DEFAULT_GPIOBASE,
+ thermalbase: 0xfed08000,
+ system_type: 0, // 0 Mobile, 1 Desktop/Server
+ tseg_size: CONFIG_SMM_TSEG_SIZE,
+ spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
+ ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+ ec_present: 1,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ dimm_channel0_disabled: 2,
+ dimm_channel1_disabled: 2,
+ max_ddr3_freq: 1600,
+ usb_port_config: {
+ /* Empty and onboard Ports 0-7, set to un-used pin OC3 */
+ { 0, 3, 0x0000 }, /* P0: Empty */
+ { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */
+ { 1, 1, 0x0040 }, /* P2: Left USB 2 (OC1) */
+ { 1, 1, 0x0040 }, /* P3: Left USB 3 (OC1) */
+ { 0, 3, 0x0000 }, /* P4: Empty */
+ { 0, 3, 0x0000 }, /* P5: Empty */
+ { 0, 3, 0x0000 }, /* P6: Empty */
+ { 0, 3, 0x0000 }, /* P7: Empty */
+ /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
+ { 1, 4, 0x0040 }, /* P8: MiniPCIe (WLAN) (no OC) */
+ { 0, 4, 0x0000 }, /* P9: Empty */
+ { 1, 4, 0x0040 }, /* P10: Camera (no OC) */
+ { 0, 4, 0x0000 }, /* P11: Empty */
+ { 0, 4, 0x0000 }, /* P12: Empty */
+ { 0, 4, 0x0000 }, /* P13: Empty */
+ },
+ };
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ start_romstage_time = rdtsc();
+#endif
+
+ if (bist == 0)
+ enable_lapic();
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+ setup_pch_gpios(&parrot_gpio_map);
+
+ /* Initialize console device(s) */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected\n");
+ boot_mode = 1;
+
+ /* System is not happy after keyboard reset... */
+ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+ outb(0x6, 0xcf9);
+ hlt();
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ post_code(0x3a);
+ pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_dram_time = rdtsc();
+#endif
+ sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_dram_time = rdtsc();
+#endif
+ post_code(0x3c);
+
+ rcba_config();
+ post_code(0x3d);
+
+ quick_ram_check();
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+ cbmem_was_initted = !cbmem_initialize();
+#else
+ cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+ - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+#if CONFIG_CHROMEOS
+ init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(base_time);
+ timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+ timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+ timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+ /* Keep this the last thing this function does. */
+ cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/parrot/thermal.h
similarity index 67%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/parrot/thermal.h
index 3ae8657..9154d0a 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/parrot/thermal.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 - 2012 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+#ifndef PARROT_THERMAL_H
+#define PARROT_THERMAL_H
-struct mainboard_config {};
+/* Active Thermal and fans are controlled by the EC. */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 90
+
+#endif
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig
new file mode 100644
index 0000000..2b676d1
--- /dev/null
+++ b/src/mainboard/google/stout/Kconfig
@@ -0,0 +1,54 @@
+if BOARD_GOOGLE_STOUT
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_RPGA989
+ select NORTHBRIDGE_INTEL_IVYBRIDGE
+ select SOUTHBRIDGE_INTEL_C216
+ select EC_QUANTA_IT8518
+ select BOARD_HAS_FADT
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select HAVE_MAINBOARD_RESOURCES
+ select MMCONF_SUPPORT
+ select HAVE_SMI_HANDLER
+ select GFXUMA
+ select CHROMEOS
+ select EXTERNAL_MRC_BLOB
+
+config MAINBOARD_DIR
+ string
+ default google/stout
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Stout"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 8
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+ hex
+ default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+ hex
+ default 0xc000
+
+endif # BOARD_GOOGLE_STOUT
diff --git a/src/mainboard/google/stout/Makefile.inc b/src/mainboard/google/stout/Makefile.inc
new file mode 100644
index 0000000..f351bf4
--- /dev/null
+++ b/src/mainboard/google/stout/Makefile.inc
@@ -0,0 +1,27 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
+SRC_ROOT = $(src)/mainboard/google/stout
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/stout/acpi/chromeos.asl
similarity index 79%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/stout/acpi/chromeos.asl
index 3ae8657..f3c212a 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/stout/acpi/chromeos.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+Name(OIPG, Package() {
+ // No GPIO for recovery mode, developer mode, or firmware write protect
+ // on stout
+})
-struct mainboard_config {};
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/stout/acpi/ec.asl
similarity index 78%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/stout/acpi/ec.asl
index 3ae8657..b807894 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/stout/acpi/ec.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+/* mainboard configuration */
+#include "../ec.h"
-struct mainboard_config {};
+/* ACPI code for EC functions */
+#include <ec/quanta/it8518/acpi/ec.asl>
diff --git a/src/mainboard/getac/p470/chip.h b/src/mainboard/google/stout/acpi/mainboard.asl
similarity index 74%
rename from src/mainboard/getac/p470/chip.h
rename to src/mainboard/google/stout/acpi/mainboard.asl
index b75c381..92702c8 100644
--- a/src/mainboard/getac/p470/chip.h
+++ b/src/mainboard/google/stout/acpi/mainboard.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
@@ -19,5 +19,19 @@
* MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+Scope (\_SB) {
+ Device (LID0)
+ {
+ Name (_HID, EisaId("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.HPLD, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId("PNP0C0C"))
+ }
+}
diff --git a/src/mainboard/google/stout/acpi/platform.asl b/src/mainboard/google/stout/acpi/platform.asl
new file mode 100644
index 0000000..a90a16e
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/platform.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+ APMC, 8, // APM command
+ APMS, 8 // APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+ DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+ Store (Arg0, SMIF) // SMI Function
+ Store (0, TRP0) // Generate trap
+ Return (SMIF) // Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+ // Remember the OS' IRQ routing choice.
+ Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Notify EC to enter S3
+ Store(0x01, \_SB.PCI0.LPCB.EC0.S3FG)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ /* Update AC status */
+ Store (\_SB.PCI0.LPCB.EC0.ACPW, Local0)
+ if (LNotEqual (Local0, \PWRS)) {
+ Store (Local0, \PWRS)
+ Notify (\_SB.PCI0.LPCB.EC0.AC, 0x80)
+ }
+
+ /* Update LID status */
+ Store (NOT(\_SB.PCI0.LPCB.EC0.HPLD), Local0)
+ if (LNotEqual (Local0, \LIDS)) {
+ Store (Local0, \LIDS)
+ Notify (\_SB.LID0, 0x80)
+ }
+
+ Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..ee4221a
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 19 },
+ Package() { 0x001cffff, 1, 0, 20 },
+ Package() { 0x001cffff, 2, 0, 17 },
+ Package() { 0x001cffff, 3, 0, 18 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, 0, 19 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, 0, 21 },
+ // LPC devices 0:1f.0
+ Package() { 0x001fffff, 0, 0, 17 },
+ Package() { 0x001fffff, 1, 0, 23 },
+ Package() { 0x001fffff, 2, 0, 16 },
+ Package() { 0x001fffff, 3, 0, 18 },
+ })
+ } Else {
+ Return (Package() {
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ // EHCI #1 0:1d.0
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+ // EHCI #2 0:1a.0
+ Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 },
+ })
+ }
+}
+
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/stout/acpi/superio.asl
similarity index 69%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/stout/acpi/superio.asl
index 3ae8657..feb4210 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/stout/acpi/superio.asl
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+/* mainboard configuration */
+#include "../ec.h"
-struct mainboard_config {};
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M // Enable PS/2 Mouse
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/quanta/it8518/acpi/superio.asl>
diff --git a/src/mainboard/google/stout/acpi/thermal.asl b/src/mainboard/google/stout/acpi/thermal.asl
new file mode 100644
index 0000000..0befd44
--- /dev/null
+++ b/src/mainboard/google/stout/acpi/thermal.asl
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+ ThermalZone (THRM)
+ {
+ Name (_TC1, 0x02)
+ Name (_TC2, 0x05)
+
+ // Thermal zone polling frequency: 10 seconds
+ Name (_TZP, 100)
+
+ // Thermal sampling period for passive cooling: 2 seconds
+ Name (_TSP, 20)
+
+ // Convert from Degrees C to 1/10 Kelvin for ACPI
+ Method (CTOK, 1) {
+ // 10th of Degrees C
+ Multiply (Arg0, 10, Local0)
+
+ // Convert to Kelvin
+ Add (Local0, 2732, Local0)
+
+ Return (Local0)
+ }
+
+ // Threshold for OS to shutdown
+ Method (_CRT, 0, Serialized)
+ {
+ Return (CTOK (\TCRT))
+ }
+
+ // Threshold for passive cooling
+ Method (_PSV, 0, Serialized)
+ {
+ Return (CTOK (\TPSV))
+ }
+
+ // Processors used for passive cooling
+ Method (_PSL, 0, Serialized)
+ {
+ Return (\PPKG ())
+ }
+
+ Method (_TMP, 0, Serialized)
+ {
+ // Get CPU Temperature from (TODO: Which Temperature reading?) via EC
+ Store (\_SB.PCI0.LPCB.EC0.TMP0, Local0)
+
+ // TODO Handle "bad" readings?
+ Return (Local0)
+ }
+ }
+}
+
diff --git a/src/mainboard/roda/rk886ex/chip.h b/src/mainboard/google/stout/acpi/video.asl
similarity index 71%
copy from src/mainboard/roda/rk886ex/chip.h
copy to src/mainboard/google/stout/acpi/video.asl
index 6f24f71..3ececa9 100644
--- a/src/mainboard/roda/rk886ex/chip.h
+++ b/src/mainboard/google/stout/acpi/video.asl
@@ -17,5 +17,27 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c
new file mode 100644
index 0000000..00dbfca
--- /dev/null
+++ b/src/mainboard/google/stout/acpi_tables.c
@@ -0,0 +1,303 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+#include <ec/quanta/it8518/ec.h>
+#include "ec.h"
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+ /* EC handles all thermal and fan control on Stout. */
+ gnvs->tcrt = CRITICAL_TEMPERATURE;
+ gnvs->tpsv = PASSIVE_TEMPERATURE;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ gnvs_ = gnvs;
+ memset((void *)gnvs, 0, sizeof(*gnvs));
+ gnvs->apic = 1;
+ gnvs->mpen = 1; /* Enable Multi Processing */
+ gnvs->pcnt = dev_count_cpu();
+
+ /* Disable USB ports in S3 by default */
+ gnvs->s3u0 = 0;
+ gnvs->s3u1 = 0;
+
+ /* Disable USB ports in S5 by default */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* CBMEM TOC */
+ gnvs->cmem = (u32)get_cbmem_toc();
+
+ /* IGD Displays */
+ gnvs->ndid = 3;
+ gnvs->did[0] = 0x80000100;
+ gnvs->did[1] = 0x80000240;
+ gnvs->did[2] = 0x80000410;
+ gnvs->did[3] = 0x80000410;
+ gnvs->did[4] = 0x00000005;
+
+#if CONFIG_CHROMEOS
+ // TODO(reinauer) this could move elsewhere?
+ chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+ acpi_update_thermal_table(gnvs);
+
+ gnvs->chromeos.vbt2 = stout_ec_running_ro() ?
+ ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+
+ // the lid is open by default.
+ gnvs->lids = 1;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfed00000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, "HPET", 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x8086a201; /* Intel */
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0080;
+
+ header->checksum =
+ acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ /* INT_SRC_OVR */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 0);
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+ current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+ return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+ const char *oem_table_id)
+{
+ generate_cpu_entries();
+ return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_xsdt_t *xsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+ acpi_header_t *slic;
+#endif
+ acpi_header_t *ssdt;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+ xsdt = (acpi_xsdt_t *) current;
+ current += sizeof(acpi_xsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt, xsdt);
+ acpi_write_rsdt(rsdt);
+ acpi_write_xsdt(xsdt);
+
+ printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *) current;
+ memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+ current += dsdt->length;
+ memcpy(dsdt, &AmlCode, dsdt->length);
+
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdp, fadt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk(BIOS_DEBUG, "ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_intel_hpet(hpet);
+ acpi_add_table(rsdp, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk(BIOS_DEBUG, "ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, madt);
+
+ printk(BIOS_DEBUG, "ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, mcfg);
+
+ /* Pack GNVS into the ACPI table area */
+ for (i=0; i < dsdt->length; i++) {
+ if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+ printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+ "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+ *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
+ break;
+ }
+ }
+
+ /* And fill it */
+ acpi_create_gnvs((global_nvs_t *)current);
+
+ /* And tell SMI about it */
+ smm_setup_structures((void *)current, NULL, NULL);
+
+ current += sizeof(global_nvs_t);
+ ALIGN_CURRENT;
+
+ /* We patched up the DSDT, so we need to recalculate the checksum */
+ dsdt->checksum = 0;
+ dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+ printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+ printk(BIOS_DEBUG, "ACPI: * SLIC\n");
+ slic = (acpi_header_t *)current;
+ current += acpi_create_slic(current);
+ ALIGN_CURRENT;
+ acpi_add_table(rsdp, slic);
+#endif
+
+ printk(BIOS_DEBUG, "ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ acpi_create_ssdt_generator(ssdt, "COREBOOT");
+ current += ssdt->length;
+ acpi_add_table(rsdp, ssdt);
+ ALIGN_CURRENT;
+
+ printk(BIOS_DEBUG, "current = %lx\n", current);
+ printk(BIOS_INFO, "ACPI: done.\n");
+ return current;
+}
diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c
new file mode 100644
index 0000000..70985f7
--- /dev/null
+++ b/src/mainboard/google/stout/chromeos.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011-2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "ec.h"
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+#include <ec/quanta/it8518/ec.h>
+
+#define GPIO_COUNT 6
+#define ACTIVE_LOW 0
+#define ACTIVE_HIGH 1
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+ gpios->count = GPIO_COUNT;
+
+ /*
+ * TODO(kimarie) - Finish recovery mode/developer mode support.
+ *
+ * Write protect, recovery, developer mode, lid switch and power button are
+ * all virtualized by EC. Hard-code read/write mode, and power button not
+ * asserted.
+ */
+ /* Write Protect: Virtual switch */
+ gpios->gpios[0].port = -1;
+ gpios->gpios[0].polarity = ACTIVE_HIGH;
+ gpios->gpios[0].value = 0; /* Hard-code to read/write mode */
+ strncpy((char *)gpios->gpios[0].name,"write protect",
+ GPIO_MAX_NAME_LENGTH);
+
+ /* Recovery: Virtual switch */
+ gpios->gpios[1].port = -1;
+ gpios->gpios[1].polarity = ACTIVE_HIGH;
+ gpios->gpios[1].value = get_recovery_mode_switch();
+ strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+ /* Developer: Virtual switch */
+ gpios->gpios[2].port = -1;
+ gpios->gpios[2].polarity = ACTIVE_HIGH;
+ gpios->gpios[2].value = get_developer_mode_switch();
+ strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+ /* Lid Switch: Virtual switch */
+ gpios->gpios[3].port = -1;
+ gpios->gpios[3].polarity = ACTIVE_HIGH;
+ gpios->gpios[3].value = 1; /* Hard-code to open */
+ strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+ /* Power Button: Virtual switch */
+ gpios->gpios[4].port = -1;
+ gpios->gpios[4].polarity = ACTIVE_HIGH;
+ gpios->gpios[4].value = 0; /* Hard-code to de-asserted */
+ strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+
+ /* Was VGA Option ROM loaded? */
+ gpios->gpios[5].port = -1; /* Indicate that this is a pseudo GPIO */
+ gpios->gpios[5].polarity = ACTIVE_HIGH;
+ gpios->gpios[5].value = oprom_is_loaded;
+ strncpy((char *)gpios->gpios[5].name,"oprom", GPIO_MAX_NAME_LENGTH);
+}
+#endif
+
+/* The dev-switch is virtual on Stout (and so handled elsewhere). */
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+/* The recovery-switch is virtual on Stout and is handled via the EC */
+int get_recovery_mode_switch(void)
+{
+ int rec_mode = 0;
+
+#ifndef __PRE_RAM__
+ rec_mode |= ((ec_read(EC_STATUS_REG) & 3) == EC_IN_RECOVERY_MODE);
+#endif
+
+ return rec_mode;
+}
diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout
new file mode 100644
index 0000000..afdd3c6
--- /dev/null
+++ b/src/mainboard/google/stout/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb
new file mode 100644
index 0000000..6c9c6b3
--- /dev/null
+++ b/src/mainboard/google/stout/devicetree.cb
@@ -0,0 +1,107 @@
+chip northbridge/intel/sandybridge
+
+ # Enable DisplayPort Hotplug with 6ms pulse
+ register "gpu_dp_d_hotplug" = "0x06"
+
+ # Enable Panel as LVDS and configure power delays
+ register "gpu_panel_port_select" = "0" # LVDS
+ register "gpu_panel_power_cycle_delay" = "5" # T4: 400ms
+ register "gpu_panel_power_up_delay" = "400" # T1+T2: 40ms
+ register "gpu_panel_power_down_delay" = "150" # T3: 15ms
+ register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms
+ register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
+
+ device lapic_cluster 0 on
+ chip cpu/intel/socket_rPGA989
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_206ax
+ # Magic APIC ID to locate this chip
+ device lapic 0xACAC off end
+
+ # Coordinate with HW_ALL
+ register "pstate_coord_type" = "0xfe"
+
+ register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
+
+ register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
+ register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
+ register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
+ end
+ end
+
+ device pci_domain 0 on
+ subsystemid 0x1ae0 0xc000 inherit
+ device pci 00.0 on end # host bridge
+ device pci 02.0 on end # vga controller
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "pirqa_routing" = "0x8b"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x8b"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x80"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ #
+ # TODO(kimarie): SMI handler for EC must be implemented before
+ # enabling the EC SMI source. Set bit 1 in
+ # alt_gp_smi_en to enable the EC SMI source.
+ #
+ register "alt_gp_smi_en" = "0x0000"
+ register "gpi1_routing" = "1"
+ register "gpi6_routing" = "2"
+
+ register "ide_legacy_combined" = "0x0"
+ register "sata_ahci" = "0x1"
+ register "sata_port_map" = "0x3"
+
+ # Enable EC Port 0x68/0x6C
+ register "gen1_dec" = "0x00040069"
+
+ # EC range is 0x800-0x9ff
+ register "gen2_dec" = "0x00fc0901"
+
+ # Enable zero-based linear PCIe root port functions
+ register "pcie_port_coalesce" = "1"
+
+ device pci 14.0 on end # USB 3.0 Controller
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT
+ device pci 19.0 off end # Intel Gigabit Ethernet
+ device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth)
+ device pci 1b.0 on end # High Definition Audio
+ device pci 1c.0 on end # PCIe Port #1
+ device pci 1c.1 on end # PCIe Port #2 (WLAN)
+ device pci 1c.2 on end # PCIe Port #3 (Card Reader)
+ device pci 1c.3 off end # PCIe Port #4
+ device pci 1c.4 off end # PCIe Port #5
+ device pci 1c.5 on end # PCIe Port #6 (LAN)
+ device pci 1c.6 off end # PCIe Port #7
+ device pci 1c.7 off end # PCIe Port #8
+ device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN)
+ device pci 1e.0 off end # PCI bridge
+ device pci 1f.0 on
+ chip ec/quanta/it8518
+ # 60h/64h KBC
+ device pnp ff.1 on #dummy address
+ end
+ end
+ end # LPC bridge
+ device pci 1f.2 on end # SATA Controller 1 (HDD/SSD)
+ device pci 1f.3 on end # SMBus Controller
+ device pci 1f.5 off end # SATA Controller 2 (MSATA)
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl
new file mode 100644
index 0000000..925dfd1
--- /dev/null
+++ b/src/mainboard/google/stout/dsdt.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+ #include "acpi/mainboard.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ #include "acpi/thermal.asl"
+
+ #include <cpu/intel/model_206ax/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+ }
+
+ #include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/google/stout/ec.c b/src/mainboard/google/stout/ec.c
new file mode 100644
index 0000000..df57aa1
--- /dev/null
+++ b/src/mainboard/google/stout/ec.c
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/quanta/it8518/ec.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include "ec.h"
+
+void stout_ec_init(void)
+{
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ u8 reg8 = pci_read_config8(dev, GEN_PMCON_3);
+
+ printk(BIOS_DEBUG, "stout_ec_init\n");
+
+ if ((reg8 & RTC_BATTERY_DEAD) != 0)
+ {
+ printk(BIOS_DEBUG, " EC Cold Boot Detected\n");
+ if ((ec_read(EC_STATUS_REG) & 0x3) != EC_IN_RECOVERY_MODE)
+ {
+ /*
+ * Make sure that RTC_BATTERY_DEAD is cleared before next reset
+ */
+ reg8 &= ~RTC_BATTERY_DEAD;
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+
+ /*
+ * Tell EC to exit RO mode
+ */
+ printk(BIOS_DEBUG, " EC will exit RO mode and boot normally\n");
+ ec_write_cmd(EC_CMD_EXIT_BOOT_BLOCK);
+ }
+ }
+
+ /*
+ * TODO(kimarie) Configure EC for S3 resume, ensure wake events are
+ * disabled, etc.
+ */
+
+ /* Report EC info */
+ /* EC FW version: 2 bytes */
+ printk(BIOS_DEBUG," EC FW version %x%x\n",
+ ec_read(EC_FW_VER),
+ ec_read(EC_FW_VER + 1));
+
+ /* Unmute */
+ ec_kbc_write_cmd(EC_KBD_CMD_UNMUTE);
+
+ // TODO If warm reset reset EC
+ //ec_cmd_write(EC_CMD_WARM_RESET);
+ // TODO Fan Error Check, Thermal Error Check, Critical Low Battery Check,
+ // First Use Day Check, Power Limit Setting
+}
+
+int stout_ec_running_ro(void)
+{
+ return ((ec_read(EC_STATUS_REG) & 1) == EC_IN_RO_MODE);
+}
diff --git a/src/mainboard/intel/emeraldlake2/chip.h b/src/mainboard/google/stout/ec.h
similarity index 67%
copy from src/mainboard/intel/emeraldlake2/chip.h
copy to src/mainboard/google/stout/ec.h
index fbe2477..5756e6e 100644
--- a/src/mainboard/intel/emeraldlake2/chip.h
+++ b/src/mainboard/google/stout/ec.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,5 +17,17 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+#ifndef STOUT_EC_H
+#define STOUT_EC_H
+
+#define EC_SCI_GPI 6 /* GPIO6 is EC_SCI# */
+#define EC_SMI_GPI 1 /* GPIO1 is EC_SMI# */
+
+#define EC_EVENT_LID_CLOSED 0x2B
+
+#ifndef __ACPI__
+extern void stout_ec_init(void);
+extern int stout_ec_running_ro(void);
+#endif
+
+#endif // STOUT_EC_H
diff --git a/src/mainboard/google/stout/fadt.c b/src/mainboard/google/stout/fadt.c
new file mode 100644
index 0000000..06d3231
--- /dev/null
+++ b/src/mainboard/google/stout/fadt.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT 0xb2
+#define CST_CONTROL 0x85
+#define PST_CONTROL 0x80
+#define ACPI_DISABLE 0x1e
+#define ACPI_ENABLE 0xe1
+#define GNVS_UPDATE 0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+ 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_DESKTOP;
+
+ fadt->sci_int = 0x9;
+ fadt->smi_cmd = APM_CNT;
+ fadt->acpi_enable = ACPI_ENABLE;
+ fadt->acpi_disable = ACPI_DISABLE;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = pmbase + 0x50;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x20;
+ fadt->gpe1_blk = 0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 1;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 16;
+ fadt->gpe1_blk_len = 0;
+ fadt->gpe1_base = 0;
+ fadt->cst_cnt = 0;
+ fadt->p_lvl2_lat = 1;
+ fadt->p_lvl3_lat = 87;
+ fadt->flush_size = 1024;
+ fadt->flush_stride = 16;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 0;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+ fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+ ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+ ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+ ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 0;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 8;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 0;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/stout/gpio.h b/src/mainboard/google/stout/gpio.h
new file mode 100644
index 0000000..277b5bf
--- /dev/null
+++ b/src/mainboard/google/stout/gpio.h
@@ -0,0 +1,285 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef STOUT_GPIO_H
+#define STOUT_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO, /* GPIO0 */
+ .gpio1 = GPIO_MODE_GPIO, /* SIO_EXT_SMI# */
+ .gpio2 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio3 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio4 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio5 = GPIO_MODE_GPIO, /* INTH# */
+ .gpio6 = GPIO_MODE_GPIO, /* SIO_EXT_SCI# */
+ .gpio7 = GPIO_MODE_GPIO, /* EXPRCRD_PWREN# */
+ .gpio8 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio9 = GPIO_MODE_NATIVE, /* USB_OC5# */
+ .gpio10 = GPIO_MODE_NATIVE, /* USB_OC6# */
+ .gpio11 = GPIO_MODE_NATIVE, /* SMBALERT# */
+ .gpio12 = GPIO_MODE_GPIO, /* GPIO12 */
+ .gpio13 = GPIO_MODE_GPIO, /* GPIO13 */
+ .gpio14 = GPIO_MODE_NATIVE, /* USB_OC7# */
+ .gpio15 = GPIO_MODE_GPIO, /* GPIO15 */
+ .gpio16 = GPIO_MODE_GPIO, /* WWAN_LED_ON */
+ .gpio17 = GPIO_MODE_GPIO, /* WLAN_LED_ON */
+ .gpio18 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_WLAN# */
+ .gpio19 = GPIO_MODE_GPIO, /* BBS_BIT0 */
+ .gpio20 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_CARD# */
+ .gpio21 = GPIO_MODE_GPIO, /* BT_DET# / TP29 */
+ .gpio22 = GPIO_MODE_GPIO, /* MODEL_ID0 */
+ .gpio23 = GPIO_MODE_GPIO, /* LCD_BK_OFF */
+ .gpio24 = GPIO_MODE_NATIVE, /* GPIO24 */
+ .gpio25 = GPIO_MODE_NATIVE, /* PCIE_REQ_WWAN# / TP89 */
+ .gpio26 = GPIO_MODE_NATIVE, /* CLK_PCIE_REQ4# / TP59 */
+ .gpio27 = GPIO_MODE_GPIO, /* MSATA_DTCT# */
+ .gpio28 = GPIO_MODE_GPIO, /* PLL_ODVR_EN */
+ .gpio29 = GPIO_MODE_GPIO, /* WLAN_AOAC_ON */
+ .gpio30 = GPIO_MODE_NATIVE, /* SUS_PWR_ACK */
+ .gpio31 = GPIO_MODE_NATIVE, /* AC_PRESENT */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ /*
+ * Note: Only gpio configured as "gpio" or "none" need to have the
+ * direction configured.
+ */
+ .gpio0 = GPIO_DIR_OUTPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_OUTPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_OUTPUT,
+
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+
+ .gpio19 = GPIO_DIR_OUTPUT,
+
+ .gpio21 = GPIO_DIR_OUTPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+ /*
+ * Note: Only gpio configured as "gpio" or "none" need to have the
+ * level set.
+ */
+ .gpio0 = GPIO_LEVEL_HIGH,
+ .gpio1 = GPIO_LEVEL_LOW,
+ .gpio2 = GPIO_LEVEL_LOW,
+ .gpio3 = GPIO_LEVEL_LOW,
+ .gpio4 = GPIO_LEVEL_LOW,
+ .gpio5 = GPIO_LEVEL_HIGH,
+ .gpio6 = GPIO_LEVEL_LOW,
+ .gpio7 = GPIO_LEVEL_HIGH,
+ .gpio8 = GPIO_LEVEL_LOW,
+
+ .gpio12 = GPIO_LEVEL_LOW,
+ .gpio13 = GPIO_LEVEL_LOW,
+
+ .gpio15 = GPIO_LEVEL_LOW,
+ .gpio16 = GPIO_LEVEL_HIGH,
+ .gpio17 = GPIO_LEVEL_HIGH,
+
+ .gpio19 = GPIO_LEVEL_LOW,
+
+ .gpio21 = GPIO_LEVEL_LOW,
+ .gpio22 = GPIO_LEVEL_LOW,
+ .gpio23 = GPIO_LEVEL_LOW,
+
+ .gpio27 = GPIO_LEVEL_LOW,
+ .gpio28 = GPIO_LEVEL_HIGH,
+ .gpio29 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE, /* PCI_CLKRUN# */
+ .gpio33 = GPIO_MODE_GPIO, /* GPIO33 */
+ .gpio34 = GPIO_MODE_GPIO, /* CCD_ON */
+ .gpio35 = GPIO_MODE_GPIO, /* BT_ON */
+ .gpio36 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio37 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio38 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio39 = GPIO_MODE_NONE, /* NOT USED */
+ .gpio40 = GPIO_MODE_GPIO, /* USB_OC1# */
+ .gpio41 = GPIO_MODE_GPIO, /* USB_OC2# */
+ .gpio42 = GPIO_MODE_NATIVE, /* USB_OC3# */
+ .gpio43 = GPIO_MODE_NATIVE, /* USB_OC4_AUO4# */
+ .gpio44 = GPIO_MODE_NATIVE, /* PCIE_CLKREQ_LAN# */
+ .gpio45 = GPIO_MODE_NATIVE, /* PCIECLKRQ6# / TP48 */
+ .gpio46 = GPIO_MODE_NATIVE, /* PCIECLKRQ7# / TP57 */
+ .gpio47 = GPIO_MODE_NATIVE, /* CLK_PEGA_REQ# */
+ .gpio48 = GPIO_MODE_GPIO, /* DIS_BT_ON# */
+ .gpio49 = GPIO_MODE_GPIO, /* GPIO49 */
+ .gpio50 = GPIO_MODE_NATIVE, /* PCI_REQ1# */
+ .gpio51 = GPIO_MODE_GPIO, /* BBS_BIT1 */
+ .gpio52 = GPIO_MODE_NATIVE, /* PCI_REQ2# */
+ .gpio53 = GPIO_MODE_GPIO, /* PWM_SELECT# / TP44 */
+ .gpio54 = GPIO_MODE_GPIO, /* PCI_REQ3# */
+ .gpio55 = GPIO_MODE_NATIVE, /* PCI_GNT3# */
+ .gpio56 = GPIO_MODE_NATIVE, /* CLK_PEGB_REQ# / TP60 */
+ .gpio57 = GPIO_MODE_GPIO, /* PCH_GPIO57 */
+ .gpio58 = GPIO_MODE_NATIVE, /* SMB_ME1_CLK */
+ .gpio59 = GPIO_MODE_GPIO, /* USB_OC0_1# */
+ .gpio60 = GPIO_MODE_GPIO, /* DRAMRST_CNTRL_PCH */
+ .gpio61 = GPIO_MODE_GPIO, /* LPCPD# */
+ .gpio62 = GPIO_MODE_NATIVE, /* PCH_SUSCLK_L / TP54 */
+ .gpio63 = GPIO_MODE_NATIVE, /* TP51 */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ /*
+ * Note: Only gpio configured as "gpio" or "none" need to have the
+ * direction configured.
+ */
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio40 = GPIO_DIR_INPUT,
+ .gpio41 = GPIO_DIR_INPUT,
+
+ .gpio48 = GPIO_DIR_OUTPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+
+ .gpio51 = GPIO_DIR_OUTPUT,
+
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+
+ .gpio57 = GPIO_DIR_INPUT,
+
+ .gpio59 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+ .gpio61 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+ /*
+ * Note: Only gpio configured as "gpio" or "none" need to have the
+ * level set.
+ */
+ .gpio33 = GPIO_LEVEL_LOW,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio35 = GPIO_LEVEL_HIGH,
+ .gpio36 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio38 = GPIO_LEVEL_LOW,
+ .gpio39 = GPIO_LEVEL_LOW,
+ .gpio40 = GPIO_LEVEL_HIGH,
+ .gpio41 = GPIO_LEVEL_LOW,
+
+ .gpio48 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+
+ .gpio51 = GPIO_LEVEL_HIGH,
+
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_LOW,
+
+ .gpio57 = GPIO_LEVEL_LOW,
+
+ .gpio59 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+ .gpio61 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO, /* CLK_FLEX0 / TP38 */
+ .gpio65 = GPIO_MODE_GPIO, /* CLK_FLEX1 / TP45 */
+ .gpio66 = GPIO_MODE_GPIO, /* CLK_FLEX2 / TP83 */
+ .gpio67 = GPIO_MODE_GPIO, /* CLK_FLEX3 / TP82 */
+ .gpio68 = GPIO_MODE_GPIO, /* WWAN_DTCT# */
+ .gpio69 = GPIO_MODE_GPIO, /* GPIO69 */
+ .gpio70 = GPIO_MODE_GPIO, /* WLAN_OFF# */
+ .gpio71 = GPIO_MODE_GPIO, /* WWAN_OFF# */
+ .gpio72 = GPIO_MODE_GPIO, /* PM_BATLOW# */
+ .gpio73 = GPIO_MODE_NATIVE, /* PCIECLKRQ0# / TP39 */
+ .gpio74 = GPIO_MODE_NATIVE, /* SML1ALERT#_R / TP56 */
+ .gpio75 = GPIO_MODE_NATIVE, /* SMB_ME1_DAT */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ /*
+ * Note: Only gpio configured as "gpio" or "none" need to have the
+ * direction configured.
+ */
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio65 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio67 = GPIO_DIR_INPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_OUTPUT,
+ .gpio70 = GPIO_DIR_OUTPUT,
+ .gpio71 = GPIO_DIR_OUTPUT,
+ .gpio72 = GPIO_DIR_OUTPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+ /*
+ * Note: Only gpio configured as "gpio" or "none" need to have the
+ * level set.
+ */
+ .gpio64 = GPIO_LEVEL_HIGH,
+ .gpio65 = GPIO_LEVEL_LOW,
+ .gpio66 = GPIO_LEVEL_HIGH,
+ .gpio67 = GPIO_LEVEL_LOW,
+ .gpio68 = GPIO_LEVEL_HIGH,
+ .gpio69 = GPIO_LEVEL_LOW,
+ .gpio70 = GPIO_LEVEL_HIGH,
+ .gpio71 = GPIO_LEVEL_HIGH,
+ .gpio72 = GPIO_LEVEL_HIGH,
+};
+
+const struct pch_gpio_map stout_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
+#endif
diff --git a/src/mainboard/google/stout/hda_verb.h b/src/mainboard/google/stout/hda_verb.h
new file mode 100644
index 0000000..13ce01f
--- /dev/null
+++ b/src/mainboard/google/stout/hda_verb.h
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0269, // Codec Vendor / Device ID: Realtek
+ 0x17aa21fe, // Subsystem ID
+ 0x0000000b, // Number of jacks
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21fe */
+ 0x001720fe,
+ 0x00172121,
+ 0x001722aa,
+ 0x00172317,
+
+ /* Pin Widget Verb Table */
+
+ /* Pin Complex (NID 0x12): 0x90a60930 DMIC */
+ 0x01271c30,
+ 0x01271d09,
+ 0x01271ea6,
+ 0x01271f90,
+
+ /* Pin Complex (NID 0x14): 0x90170110 SPEAKER-OUT (Port-D) */
+ 0x01471c10,
+ 0x01471d01,
+ 0x01471e17,
+ 0x01471f90,
+
+ /* Pin Complex (NID 0x15): 0x0321101f HP-OUT (Port-A) */
+ 0x01571c1f,
+ 0x01571d10,
+ 0x01571e21,
+ 0x01571f03,
+
+ /* Pin Complex (NID 0x17): 0x411111f0 MONO-OUT (Port-H) */
+ 0x01771cf0,
+ 0x01771d11,
+ 0x01771e11,
+ 0x01771f41,
+
+ /* Pin Complex (NID 0x18): 0x03a11820 MIC1 (Port-B) */
+ 0x01871c20,
+ 0x01871d18,
+ 0x01871ea1,
+ 0x01871f03,
+
+ /* Pin Complex (NID 0x19): 0x411111f0 MIC2 (Port-F) */
+ 0x01971cf0,
+ 0x01971d11,
+ 0x01971e11,
+ 0x01971f41,
+
+ /* Pin Complex (NID 0x1a): 0x411111f0 LINE1 (Port-C) */
+ 0x01a71cf0,
+ 0x01a71d11,
+ 0x01a71e11,
+ 0x01a71f41,
+
+ /* Pin Complex (NID 0x1b): 0x411111f0 LINE2 (Port-E) */
+ 0x01b71cf0,
+ 0x01b71d11,
+ 0x01b71e11,
+ 0x01b71f41,
+
+ /* Pin Complex (NID 0x1d): 0x4016862d PC-BEEP */
+ 0x01d71c2d,
+ 0x01d71d86,
+ 0x01d71e16,
+ 0x01d71f40,
+
+ /* Pin Complex (NID 0x1e): 0x411111f0 S/PDIF-OUT */
+ 0x01e71cf0,
+ 0x01e71d11,
+ 0x01e71e11,
+ 0x01e71f41,
+
+ /* coreboot specific header */
+ 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
+ 0x80860101, // Subsystem ID
+ 0x00000004, // Number of jacks
+
+ /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+ 0x30172001,
+ 0x30172101,
+ 0x30172286,
+ 0x30172380,
+
+ /* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+ 0x30571c10,
+ 0x30571d00,
+ 0x30571e56,
+ 0x30571f18,
+
+ /* Pin Complex (NID 0x06) Not Connected */
+ 0x30671c20,
+ 0x30671d00,
+ 0x30671e56,
+ 0x30671f58,
+
+ /* Pin Complex (NID 0x07) Not Connected */
+ 0x30771c30,
+ 0x30771d00,
+ 0x30771e56,
+ 0x30771f58
+};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x00170500, /* power up everything (codec, dac, adc, mixers) */
+ 0x01470740, /* enable speaker out */
+ 0x01470c02, /* set speaker EAPD pin */
+ 0x0143b01f, /* unmute speaker */
+ 0x00c37100, /* unmute mixer nid 0xc input 1 */
+ 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */
+};
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/google/stout/mainboard.c b/src/mainboard/google/stout/mainboard.c
new file mode 100644
index 0000000..7d62078
--- /dev/null
+++ b/src/mainboard/google/stout/mainboard.c
@@ -0,0 +1,283 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "onboard.h"
+#include "ec.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/quanta/it8518/ec.h>
+
+void mainboard_suspend_resume(void)
+{
+ /* Call SMM finalize() handlers before resume */
+ outb(0xcb, 0xb2);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+ int res=-1;
+
+ printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+ __func__, regs->eax & 0xffff);
+
+ switch(regs->eax & 0xffff) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffffff00;
+ regs->ecx |= 0x00; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000; /* Use video bios default */
+ res = 0;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0001;
+ res = 0;
+ break;
+ case 0x5f70:
+ switch ((regs->ecx >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ regs->eax &= 0xffff0000;
+ regs->eax |= 0x005f;
+ regs->ecx &= 0xffff0000;
+ regs->ecx |= 0x0000;
+ res = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ ((regs->ecx >> 8) & 0xff));
+ return 0;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+ regs->eax & 0xffff);
+ break;
+ }
+ return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+ switch (M.x86.R_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0x00;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV (eDP)
+ * bit 2 = EFP
+ * bit 3 = LFP
+ * bit 4 = CRT2
+ * bit 5 = TV2 (eDP)
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0x0000; /* Use video bios default */
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 1;
+ break;
+ case 0x5f70:
+ switch (M.x86.R_CH) {
+ case 0:
+ /* Get Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CL = 0;
+ break;
+ case 1:
+ /* Set Mux */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ M.x86.R_AX = 0x005f;
+ M.x86.R_CX = 0;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+ M.x86.R_CH);
+ return 0;
+ }
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+ M.x86.R_AX);
+ return 0;
+ }
+
+ /* Interrupt handled */
+ return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+ typedef int (* yabel_handleIntFunc)(void);
+ extern yabel_handleIntFunc yabel_intFuncArray[256];
+ yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+extern const u32 * pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
+
+static void verb_setup(void)
+{
+ cim_verb_data = mainboard_cim_verb_data;
+ cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
+}
+
+static void mainboard_init(device_t dev)
+{
+ /* Initialize the Embedded Controller */
+ stout_ec_init();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+ /* Install custom int15 handler for VGA OPROM */
+ int15_install();
+#endif
+ verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Google Stout ChromeBook")
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/stout/mainboard_smi.c b/src/mainboard/google/stout/mainboard_smi.c
new file mode 100644
index 0000000..f77c499
--- /dev/null
+++ b/src/mainboard/google/stout/mainboard_smi.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Include romstage serial for SIO helper functions */
+#include <superio/ite/it8772f/early_serial.c>
+
+/* Include EC functions */
+#include <ec/quanta/it8518/ec.h>
+#include "ec.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ gnvs->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ //gnvs->smif = 0;
+ return 1;
+}
+
+static u8 mainboard_smi_ec(void)
+{
+ u8 cmd = ec_it8518_get_event();
+ extern u16 pmbase; /* Set in southbridge SMI handler */
+ u32 pm1_cnt;
+
+ switch (cmd) {
+ case EC_EVENT_LID_CLOSED:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+ /* Go to S5 */
+ pm1_cnt = inl(pmbase + PM1_CNT);
+ pm1_cnt |= (0xf << 10);
+ outl(pm1_cnt, pmbase + PM1_CNT);
+ break;
+ }
+
+ return cmd;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+ if (gpi_sts & (1 << EC_SMI_GPI)) {
+ /* Process all pending events */
+ while (mainboard_smi_ec() != 0);
+ }
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ /*
+ * TODO(kimarie) Disable SCI and SMI events, clear pending events that
+ * would trigger an immediate wake event. Finally, enable
+ * wake events before entering the sleep state.
+ */
+}
+
+#define APMC_FINALIZE 0xcb
+#define APMC_ACPI_EN 0xe1
+#define APMC_ACPI_DIS 0x1e
+
+static int mainboard_finalized = 0;
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ switch (apmc) {
+ case APMC_FINALIZE:
+ if (mainboard_finalized) {
+ printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+ return 0;
+ }
+
+ intel_me_finalize_smm();
+ intel_pch_finalize_smm();
+ intel_sandybridge_finalize_smm();
+ intel_model_206ax_finalize_smm();
+
+ mainboard_finalized = 1;
+ break;
+ case APMC_ACPI_EN:
+ /*
+ * TODO(kimarie) Clear all pending events and enable SCI.
+ */
+ ec_write_cmd(EC_CMD_NOTIFY_ACPI_ENTER);
+ break;
+ case APMC_ACPI_DIS:
+ /*
+ * TODO(kimarie) Clear all pending events and enable SMI.
+ */
+ ec_write_cmd(EC_CMD_NOTIFY_ACPI_EXIT);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/intel/emeraldlake2/chip.h b/src/mainboard/google/stout/onboard.h
similarity index 82%
rename from src/mainboard/intel/emeraldlake2/chip.h
rename to src/mainboard/google/stout/onboard.h
index fbe2477..a42a92a 100644
--- a/src/mainboard/intel/emeraldlake2/chip.h
+++ b/src/mainboard/google/stout/onboard.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,5 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
+#ifndef STOUT_ONBOARD_H
+#define STOUT_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+
+#endif
diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c
new file mode 100644
index 0000000..de3c617
--- /dev/null
+++ b/src/mainboard/google/stout/romstage.c
@@ -0,0 +1,315 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <cbfs.h>
+
+static void pch_enable_lpc(void)
+{
+ /*
+ * Enable:
+ * EC Decode Range Port62/66
+ * SuperIO Port2E/2F
+ * PS/2 Keyboard/Mouse Port60/64
+ * FDD Port3F0h-3F5h and Port3F7h
+ */
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN |
+ CNF1_LPC_EN | FDD_LPC_EN);
+
+ /* Stout EC Decode Range Port68/6C */
+ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, (0x68 | 0x40001));
+}
+
+static void rcba_config(void)
+{
+ u32 reg32;
+
+ /*
+ * GFX INTA -> PIRQA (MSI)
+ * D26IP_E2P EHCI #2 INTA -> PIRQF
+ * D27IP_ZIP HDA INTA -> PIRQA (MSI)
+ * D28IP_P2IP WLAN INTA -> PIRQD
+ * D28IP_P3IP Card Reader INTB -> PIRQE
+ * D28IP_P6IP LAN INTC -> PIRQB
+ * D29IP_E1P EHCI #1 INTA -> PIRQD
+ * D31IP_SIP SATA INTA -> PIRQB (MSI)
+ * D31IP_SMIP SMBUS INTB -> PIRQG
+ */
+
+ /* Device interrupt pin register (board specific) */
+ RCBA32(D31IP) = (NOINT << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+ (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+ RCBA32(D30IP) = (NOINT << D30IP_PIP);
+ RCBA32(D29IP) = (INTA << D29IP_E1P);
+ RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
+ (INTB << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
+ (NOINT << D28IP_P5IP) | (INTC << D28IP_P6IP) |
+ (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
+ RCBA32(D27IP) = (INTA << D27IP_ZIP);
+ RCBA32(D26IP) = (INTA << D26IP_E2P);
+ RCBA32(D25IP) = (NOINT << D25IP_LIP);
+ RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+ /* Device interrupt route registers */
+ DIR_ROUTE(D31IR, PIRQB, PIRQG, PIRQA, PIRQC);
+ DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+ DIR_ROUTE(D28IR, PIRQD, PIRQE, PIRQB, PIRQC);
+ DIR_ROUTE(D27IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D26IR, PIRQF, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+ DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+ /* Enable IOAPIC (generic) */
+ RCBA16(OIC) = 0x0100;
+ /* PCH BWG says to read back the IOAPIC enable register */
+ (void) RCBA16(OIC);
+
+ /* Disable unused devices (board specific) */
+ reg32 = RCBA32(FD);
+ reg32 |= PCH_DISABLE_ALWAYS;
+ /* Disable PCI bridge so MRC does not probe this bus */
+ reg32 |= PCH_DISABLE_P2P;
+ RCBA32(FD) = reg32;
+}
+
+// FIXME, this function is generic code that should go to sb/... or
+// nb/../early_init.c
+static void early_pch_init(void)
+{
+ // Nothing to do for stout
+}
+
+void main(unsigned long bist)
+{
+ int boot_mode = 0;
+ int cbmem_was_initted;
+ u32 pm1_cnt;
+ u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ tsc_t start_romstage_time;
+ tsc_t before_dram_time;
+ tsc_t after_dram_time;
+ tsc_t base_time = {
+ .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+ .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+ };
+#endif
+ struct pei_data pei_data = {
+ pei_version: PEI_VERSION,
+ mchbar: DEFAULT_MCHBAR,
+ dmibar: DEFAULT_DMIBAR,
+ epbar: DEFAULT_EPBAR,
+ pciexbar: CONFIG_MMCONF_BASE_ADDRESS,
+ smbusbar: SMBUS_IO_BASE,
+ wdbbar: 0x4000000,
+ wdbsize: 0x1000,
+ hpet_address: HPET_ADDR,
+ rcba: DEFAULT_RCBABASE,
+ pmbase: DEFAULT_PMBASE,
+ gpiobase: DEFAULT_GPIOBASE,
+ thermalbase: 0xfed08000,
+ system_type: 0, // 0 Mobile, 1 Desktop/Server
+ tseg_size: CONFIG_SMM_TSEG_SIZE,
+ spd_addresses: { 0xA0, 0x00,0xA4,0x00 },
+ ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+ ec_present: 1,
+ // 0 = leave channel enabled
+ // 1 = disable dimm 0 on channel
+ // 2 = disable dimm 1 on channel
+ // 3 = disable dimm 0+1 on channel
+ dimm_channel0_disabled: 2,
+ dimm_channel1_disabled: 2,
+ max_ddr3_freq: 1600,
+ usb_port_config: {
+ /* enabled usb oc pin length */
+ { 1, 0, 0x0040 }, /* P0: USB 3.0 1 (OC0) */
+ { 1, 0, 0x0040 }, /* P1: USB 3.0 2 (OC0) */
+ { 0, 1, 0x0000 }, /* P2: Empty */
+ { 1, 1, 0x0040 }, /* P3: Camera (no OC) */
+ { 1, 1, 0x0040 }, /* P4: WLAN (no OC) */
+ { 1, 1, 0x0040 }, /* P5: WWAN (no OC) */
+ { 0, 1, 0x0000 }, /* P6: Empty */
+ { 0, 1, 0x0000 }, /* P7: Empty */
+ { 0, 5, 0x0000 }, /* P8: Empty */
+ { 1, 4, 0x0040 }, /* P9: USB 2.0 (AUO4) (OC4) */
+ { 0, 5, 0x0000 }, /* P10: Empty */
+ { 0, 5, 0x0000 }, /* P11: Empty */
+ { 0, 5, 0x0000 }, /* P12: Empty */
+ { 1, 5, 0x0040 }, /* P13: Bluetooth (no OC) */
+ },
+ };
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ start_romstage_time = rdtsc();
+#endif
+
+ if (bist == 0)
+ enable_lapic();
+
+ pch_enable_lpc();
+
+ /* Enable GPIOs */
+ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+ pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+ setup_pch_gpios(&stout_gpio_map);
+
+ /* Initialize console device(s) */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected\n");
+ boot_mode = 1;
+
+ /* System is not happy after keyboard reset... */
+ printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+ outb(0x6, 0xcf9);
+ hlt();
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+ printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+ /* Check PM1_STS[15] to see if we are waking from Sx */
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+ /* Read PM1_CNT[12:10] to determine which Sx state */
+ pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+ if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+ }
+
+ post_code(0x38);
+ /* Enable SPD ROMs and DDR-III DRAM */
+ enable_smbus();
+
+ /* Prepare USB controller early in S3 resume */
+ if (boot_mode == 2)
+ enable_usb_bar();
+
+ post_code(0x39);
+
+ post_code(0x3a);
+ pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+ before_dram_time = rdtsc();
+#endif
+ sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+ after_dram_time = rdtsc();
+#endif
+ post_code(0x3b);
+ /* Perform some initialization that must run before stage2 */
+ early_pch_init();
+ post_code(0x3c);
+
+ rcba_config();
+ post_code(0x3d);
+
+ quick_ram_check();
+ post_code(0x3e);
+
+ MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+ cbmem_was_initted = !cbmem_initialize();
+#else
+ cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+ - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+ /* If there is no high memory area, we didn't boot before, so
+ * this is not a resume. In that case we just create the cbmem toc.
+ */
+
+ *(u32 *)CBMEM_BOOT_MODE = 0;
+ *(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+ if ((boot_mode == 2) && cbmem_was_initted) {
+ void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+ if (resume_backup_memory) {
+ *(u32 *)CBMEM_BOOT_MODE = boot_mode;
+ *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+ }
+ /* Magic for S3 resume */
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+ } else if (boot_mode == 2) {
+ /* Failed S3 resume, reset to come up cleanly */
+ outb(0x6, 0xcf9);
+ hlt();
+ } else {
+ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+ }
+#endif
+ post_code(0x3f);
+#if CONFIG_CHROMEOS
+ init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+ timestamp_init(base_time);
+ timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+ timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+ timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+ timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+ /* Keep this the last thing this function does. */
+ cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/intel/eagleheights/chip.h b/src/mainboard/google/stout/thermal.h
similarity index 66%
copy from src/mainboard/intel/eagleheights/chip.h
copy to src/mainboard/google/stout/thermal.h
index 3ae8657..885d395 100644
--- a/src/mainboard/intel/eagleheights/chip.h
+++ b/src/mainboard/google/stout/thermal.h
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -17,6 +17,15 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern struct chip_operations mainboard_ops;
+#ifndef STOUT_THERMAL_H
+#define STOUT_THERMAL_H
-struct mainboard_config {};
+/* Active Thermal and fans are controlled by the EC. */
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE 100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE 90
+
+#endif /* STOUT_THERMAL_H */
diff --git a/src/mainboard/hp/dl145_g1/chip.h b/src/mainboard/hp/dl145_g1/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/hp/dl145_g1/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/hp/dl145_g1/mainboard.c b/src/mainboard/hp/dl145_g1/mainboard.c
index d68e720..fde9d22 100644
--- a/src/mainboard/hp/dl145_g1/mainboard.c
+++ b/src/mainboard/hp/dl145_g1/mainboard.c
@@ -22,7 +22,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("HP ProLiant DL145 G1 Mainboard")
diff --git a/src/mainboard/hp/dl145_g3/chip.h b/src/mainboard/hp/dl145_g3/chip.h
deleted file mode 100644
index 04039f1..0000000
--- a/src/mainboard/hp/dl145_g3/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/hp/dl145_g3/mainboard.c b/src/mainboard/hp/dl145_g3/mainboard.c
index 7799c16..81f074e 100644
--- a/src/mainboard/hp/dl145_g3/mainboard.c
+++ b/src/mainboard/hp/dl145_g3/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("HP ProLiant DL145 G3 Mainboard")
diff --git a/src/mainboard/hp/dl165_g6_fam10/chip.h b/src/mainboard/hp/dl165_g6_fam10/chip.h
deleted file mode 100644
index 6c54f71..0000000
--- a/src/mainboard/hp/dl165_g6_fam10/chip.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 University of Mannheim
- * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {
-};
-
diff --git a/src/mainboard/hp/dl165_g6_fam10/mainboard.c b/src/mainboard/hp/dl165_g6_fam10/mainboard.c
index d84ba47..97f2fb7 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mainboard.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("HP ProLiant DL165 G6 Mainboard (Fam10h)")
diff --git a/src/mainboard/hp/e_vectra_p2706t/chip.h b/src/mainboard/hp/e_vectra_p2706t/chip.h
deleted file mode 100644
index f354ee8..0000000
--- a/src/mainboard/hp/e_vectra_p2706t/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/hp/e_vectra_p2706t/mainboard.c b/src/mainboard/hp/e_vectra_p2706t/mainboard.c
index 74339e9..0f9b75e 100644
--- a/src/mainboard/hp/e_vectra_p2706t/mainboard.c
+++ b/src/mainboard/hp/e_vectra_p2706t/mainboard.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/ibase/mb899/chip.h b/src/mainboard/ibase/mb899/chip.h
deleted file mode 100644
index 831a973..0000000
--- a/src/mainboard/ibase/mb899/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c
index 5989685..4e3d606 100644
--- a/src/mainboard/ibase/mb899/mainboard.c
+++ b/src/mainboard/ibase/mb899/mainboard.c
@@ -27,7 +27,6 @@
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
#include <arch/coreboot_tables.h>
-#include "chip.h"
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
diff --git a/src/mainboard/ibm/e325/chip.h b/src/mainboard/ibm/e325/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/ibm/e325/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/ibm/e325/mainboard.c b/src/mainboard/ibm/e325/mainboard.c
index 49a8c41..136ffaf 100644
--- a/src/mainboard/ibm/e325/mainboard.c
+++ b/src/mainboard/ibm/e325/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("IBM eServer 325 Mainboard")
diff --git a/src/mainboard/ibm/e326/chip.h b/src/mainboard/ibm/e326/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/ibm/e326/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/ibm/e326/mainboard.c b/src/mainboard/ibm/e326/mainboard.c
index 70b59a9..bd5ebc5 100644
--- a/src/mainboard/ibm/e326/mainboard.c
+++ b/src/mainboard/ibm/e326/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("IBM eServer 326 Mainboard")
diff --git a/src/mainboard/iei/juki-511p/chip.h b/src/mainboard/iei/juki-511p/chip.h
deleted file mode 100644
index f5f5b7a..0000000
--- a/src/mainboard/iei/juki-511p/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/iei/juki-511p/mainboard.c b/src/mainboard/iei/juki-511p/mainboard.c
index e44a07c..e5714cf 100644
--- a/src/mainboard/iei/juki-511p/mainboard.c
+++ b/src/mainboard/iei/juki-511p/mainboard.c
@@ -24,7 +24,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("IEI JUKI-511P Mainboard")
diff --git a/src/mainboard/iei/kino-780am2-fam10/chip.h b/src/mainboard/iei/kino-780am2-fam10/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/iei/kino-780am2-fam10/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/iei/kino-780am2-fam10/mainboard.c b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
index ef02c89..42e7b5e 100644
--- a/src/mainboard/iei/kino-780am2-fam10/mainboard.c
+++ b/src/mainboard/iei/kino-780am2-fam10/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/iei/nova4899r/chip.h b/src/mainboard/iei/nova4899r/chip.h
deleted file mode 100644
index 271b02c..0000000
--- a/src/mainboard/iei/nova4899r/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Luis Correia <luis.f.correia@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/iei/nova4899r/mainboard.c b/src/mainboard/iei/nova4899r/mainboard.c
index 7ca0a14..85c6521 100644
--- a/src/mainboard/iei/nova4899r/mainboard.c
+++ b/src/mainboard/iei/nova4899r/mainboard.c
@@ -24,7 +24,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("IEI NOVA-4899R Mainboard")
diff --git a/src/mainboard/iei/pcisa-lx-800-r10/chip.h b/src/mainboard/iei/pcisa-lx-800-r10/chip.h
deleted file mode 100644
index f5f5b7a..0000000
--- a/src/mainboard/iei/pcisa-lx-800-r10/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/intel/d810e2cb/chip.h b/src/mainboard/intel/d810e2cb/chip.h
deleted file mode 100644
index 1f9a793..0000000
--- a/src/mainboard/intel/d810e2cb/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/intel/d810e2cb/mainboard.c b/src/mainboard/intel/d810e2cb/mainboard.c
index c55a680..7589d6e 100644
--- a/src/mainboard/intel/d810e2cb/mainboard.c
+++ b/src/mainboard/intel/d810e2cb/mainboard.c
@@ -19,7 +19,6 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/intel/d945gclf/chip.h b/src/mainboard/intel/d945gclf/chip.h
deleted file mode 100644
index 491eebd..0000000
--- a/src/mainboard/intel/d945gclf/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/intel/d945gclf/mainboard.c b/src/mainboard/intel/d945gclf/mainboard.c
index ff08b8a..ca920bc 100644
--- a/src/mainboard/intel/d945gclf/mainboard.c
+++ b/src/mainboard/intel/d945gclf/mainboard.c
@@ -21,7 +21,6 @@
#include <console/console.h>
#include <boot/tables.h>
#include <arch/coreboot_tables.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel D945GCLF Mainboard")
diff --git a/src/mainboard/intel/eagleheights/mainboard.c b/src/mainboard/intel/eagleheights/mainboard.c
index 7974dbc..d6bc10f 100644
--- a/src/mainboard/intel/eagleheights/mainboard.c
+++ b/src/mainboard/intel/eagleheights/mainboard.c
@@ -23,7 +23,6 @@
#include <device/device.h>
#include <boot/tables.h>
#include <arch/coreboot_tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig
index 9e4f347..873d273 100644
--- a/src/mainboard/intel/emeraldlake2/Kconfig
+++ b/src/mainboard/intel/emeraldlake2/Kconfig
@@ -43,12 +43,4 @@
string
default "pci8086,0166.rom"
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
- hex
- default 0x1ae0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
- hex
- default 0xc000
-
endif # BOARD_INTEL_EMERALDLAKE2
diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
index 6a61b0d..307e2e2 100644
--- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
+++ b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
@@ -17,98 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-Device (CRHW)
-{
- Name(_HID, EISAID("GGL0001"))
-
- Method(_STA, 0, Serialized)
- {
- Return (0xb)
- }
-
- Method(CHSW, 0, Serialized)
- {
- Name (WSHC, Package() { VBT3 })
- Return (WSHC)
- }
-
- Method(FWID, 0, Serialized)
- {
- Name (DIW1, "")
- ToString(VBT5, 63, DIW1)
- Name (DIWF, Package() { DIW1 })
- Return(DIWF)
- }
-
- Method(FRID, 0, Serialized)
- {
- Name (DIR1, "")
- ToString(VBT6, 63, DIR1)
- Name (DIRF, Package() { DIR1 })
- Return (DIRF)
- }
-
- Method(HWID, 0, Serialized)
- {
- Name (DIW0, "")
- ToString(VBT4, 255, DIW0)
- Name (DIWH, Package() { DIW0 })
- Return (DIWH)
- }
-
- Method(BINF, 0, Serialized)
- {
- Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
- Return (FNIB)
- }
-
- Method(GPIO, 0, Serialized)
- {
- Name(OIPG, Package() {
- Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
- Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
- Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
- })
- Return (OIPG)
-
- }
-
- Method(VBNV, 0, Serialized)
- {
- Name(VNBV, Package() {
- // See src/vendorcode/google/chromeos/Kconfig
- // for the definition of these:
- CONFIG_VBNV_OFFSET,
- CONFIG_VBNV_SIZE
- })
- Return(VNBV)
- }
-
- Method(VDAT, 0, Serialized)
- {
- Name(TAD0,"")
- ToBuffer(CHVD, TAD0)
- Name (TADV, Package() { TAD0 })
- Return (TADV)
- }
-
- Method(FMAP, 0, Serialized)
- {
- Name(PAMF, Package() { VBT9 })
- Return(PAMF)
- }
-
- Method(MECK, 0, Serialized)
- {
- Name(HASH, Package() { MEHH })
- Return(HASH)
- }
-
- Method(MLST, 0, Serialized)
- {
- Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
- "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
- })
- Return (TSLM)
- }
-}
+Name(OIPG, Package() {
+ Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
+ Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
+ Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
+})
diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c
index 01d4b54..b6ff40d 100644
--- a/src/mainboard/intel/emeraldlake2/acpi_tables.c
+++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c
@@ -279,6 +279,7 @@
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
"DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
break;
}
}
@@ -318,11 +319,3 @@
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
-
-#if CONFIG_CHROMEOS
-void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size)
-{
- *vdat_addr = &gnvs_->chromeos.vdat;
- *vdat_size = sizeof(gnvs_->chromeos.vdat);
-}
-#endif
diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl
index 9af312a..b67082e72 100644
--- a/src/mainboard/intel/emeraldlake2/dsdt.asl
+++ b/src/mainboard/intel/emeraldlake2/dsdt.asl
@@ -49,6 +49,7 @@
}
#include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
diff --git a/src/mainboard/intel/emeraldlake2/fadt.c b/src/mainboard/intel/emeraldlake2/fadt.c
index ff840c09..315cb58 100644
--- a/src/mainboard/intel/emeraldlake2/fadt.c
+++ b/src/mainboard/intel/emeraldlake2/fadt.c
@@ -47,7 +47,7 @@
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+ fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
@@ -65,7 +65,7 @@
fadt->gpe0_blk_len = 16;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
- fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c
index 0bf33fc..5717edf 100644
--- a/src/mainboard/intel/emeraldlake2/mainboard.c
+++ b/src/mainboard/intel/emeraldlake2/mainboard.c
@@ -34,7 +34,6 @@
#include <arch/interrupt.h>
#include <arch/coreboot_tables.h>
#include "hda_verb.h"
-#include "chip.h"
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_suspend_resume(void)
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index aba89d4..7a31242 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -113,9 +113,6 @@
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
- /* Enable upper 128bytes of CMOS (generic) */
- RCBA32(RC) = (1 << 2);
-
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
reg32 |= PCH_DISABLE_ALWAYS;
@@ -312,11 +309,8 @@
rcba_config();
post_code(0x3d);
- /* Initialize the internal PCIe links before we go into stage2 */
- sandybridge_late_initialization();
-
- post_code(0x3e);
quick_ram_check();
+ post_code(0x3e);
MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_EARLY_CBMEM_INIT
diff --git a/src/mainboard/intel/jarrell/chip.h b/src/mainboard/intel/jarrell/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/intel/jarrell/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/intel/jarrell/mainboard.c b/src/mainboard/intel/jarrell/mainboard.c
index ba2bfc5..f66431d 100644
--- a/src/mainboard/intel/jarrell/mainboard.c
+++ b/src/mainboard/intel/jarrell/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel Jarell Mainboard")
diff --git a/src/mainboard/intel/mtarvon/chip.h b/src/mainboard/intel/mtarvon/chip.h
deleted file mode 100644
index 9c9114d..0000000
--- a/src/mainboard/intel/mtarvon/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/intel/mtarvon/mainboard.c b/src/mainboard/intel/mtarvon/mainboard.c
index 26111f5..b69df9b 100644
--- a/src/mainboard/intel/mtarvon/mainboard.c
+++ b/src/mainboard/intel/mtarvon/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel Mt. Arvon Mainboard")
diff --git a/src/mainboard/intel/truxton/chip.h b/src/mainboard/intel/truxton/chip.h
deleted file mode 100644
index 9c9114d..0000000
--- a/src/mainboard/intel/truxton/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Arastra, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/intel/truxton/mainboard.c b/src/mainboard/intel/truxton/mainboard.c
index 78a16a9..754ba0d 100644
--- a/src/mainboard/intel/truxton/mainboard.c
+++ b/src/mainboard/intel/truxton/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel Truxton Mainboard")
diff --git a/src/mainboard/intel/xe7501devkit/chip.h b/src/mainboard/intel/xe7501devkit/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/intel/xe7501devkit/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/intel/xe7501devkit/mainboard.c b/src/mainboard/intel/xe7501devkit/mainboard.c
index 3b757d6..c605624 100644
--- a/src/mainboard/intel/xe7501devkit/mainboard.c
+++ b/src/mainboard/intel/xe7501devkit/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Intel Xeon E7501 DevKit Mainboard")
diff --git a/src/mainboard/iwave/iWRainbowG6/chip.h b/src/mainboard/iwave/iWRainbowG6/chip.h
deleted file mode 100644
index 831a973..0000000
--- a/src/mainboard/iwave/iWRainbowG6/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/iwave/iWRainbowG6/mainboard.c b/src/mainboard/iwave/iWRainbowG6/mainboard.c
index 7d0c61d..f3fc20f 100644
--- a/src/mainboard/iwave/iWRainbowG6/mainboard.c
+++ b/src/mainboard/iwave/iWRainbowG6/mainboard.c
@@ -21,7 +21,6 @@
#include <device/device.h>
#include <console/console.h>
#include <boot/tables.h>
-#include "chip.h"
#include "hda_verb.h"
static void verb_setup(void)
diff --git a/src/mainboard/iwill/dk8_htx/chip.h b/src/mainboard/iwill/dk8_htx/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/iwill/dk8_htx/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/iwill/dk8_htx/mainboard.c b/src/mainboard/iwill/dk8_htx/mainboard.c
index cbbd3f2..251852f 100644
--- a/src/mainboard/iwill/dk8_htx/mainboard.c
+++ b/src/mainboard/iwill/dk8_htx/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("IWILL DK8-HTX Mainboard")
diff --git a/src/mainboard/iwill/dk8s2/chip.h b/src/mainboard/iwill/dk8s2/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/iwill/dk8s2/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/iwill/dk8s2/mainboard.c b/src/mainboard/iwill/dk8s2/mainboard.c
index 7559da6..18ab152 100644
--- a/src/mainboard/iwill/dk8s2/mainboard.c
+++ b/src/mainboard/iwill/dk8s2/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("IWILL DK8S2 Mainboard")
diff --git a/src/mainboard/iwill/dk8x/chip.h b/src/mainboard/iwill/dk8x/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/iwill/dk8x/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/iwill/dk8x/mainboard.c b/src/mainboard/iwill/dk8x/mainboard.c
index a936f40..3e062de 100644
--- a/src/mainboard/iwill/dk8x/mainboard.c
+++ b/src/mainboard/iwill/dk8x/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("IWILL DK8X Mainboard")
diff --git a/src/mainboard/jetway/j7f24/chip.h b/src/mainboard/jetway/j7f24/chip.h
deleted file mode 100644
index 0a2badb..0000000
--- a/src/mainboard/jetway/j7f24/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/jetway/j7f24/mainboard.c b/src/mainboard/jetway/j7f24/mainboard.c
index 6693747..4b1ee39 100644
--- a/src/mainboard/jetway/j7f24/mainboard.c
+++ b/src/mainboard/jetway/j7f24/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Jetway J7F[24]* Mainboard")
diff --git a/src/mainboard/jetway/pa78vm5/chip.h b/src/mainboard/jetway/pa78vm5/chip.h
deleted file mode 100644
index d081720..0000000
--- a/src/mainboard/jetway/pa78vm5/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Wang Qing Pei <wangqingpei@gmail.com>
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/jetway/pa78vm5/mainboard.c b/src/mainboard/jetway/pa78vm5/mainboard.c
index e992f74..ce18ba9 100644
--- a/src/mainboard/jetway/pa78vm5/mainboard.c
+++ b/src/mainboard/jetway/pa78vm5/mainboard.c
@@ -28,7 +28,6 @@
#include <device/pci_def.h>
#include "southbridge/amd/sb700/sb700.h"
#include "southbridge/amd/sb700/smbus.h"
-#include "chip.h"
uint64_t uma_memory_base, uma_memory_size;
diff --git a/src/mainboard/kontron/986lcd-m/chip.h b/src/mainboard/kontron/986lcd-m/chip.h
deleted file mode 100644
index 831a973..0000000
--- a/src/mainboard/kontron/986lcd-m/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
index d7b1f13..b9686bd 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard.c
@@ -26,7 +26,6 @@
#include <pc80/mc146818rtc.h>
#include <arch/io.h>
#include <arch/interrupt.h>
-#include "chip.h"
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
static int int15_handler(void)
diff --git a/src/mainboard/kontron/kt690/chip.h b/src/mainboard/kontron/kt690/chip.h
deleted file mode 100644
index 05e1582..0000000
--- a/src/mainboard/kontron/kt690/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
diff --git a/src/mainboard/kontron/kt690/mainboard.c b/src/mainboard/kontron/kt690/mainboard.c
index c2a401e..ecba347 100644
--- a/src/mainboard/kontron/kt690/mainboard.c
+++ b/src/mainboard/kontron/kt690/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb600/sb600.h>
-#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
diff --git a/src/mainboard/lanner/em8510/chip.h b/src/mainboard/lanner/em8510/chip.h
deleted file mode 100644
index 96d8705..0000000
--- a/src/mainboard/lanner/em8510/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Travelping GmbH <info@travelping.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/lanner/em8510/mainboard.c b/src/mainboard/lanner/em8510/mainboard.c
index 4a20d25..9317944 100644
--- a/src/mainboard/lanner/em8510/mainboard.c
+++ b/src/mainboard/lanner/em8510/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("LANNER EM-8510 Mainboard")
diff --git a/src/mainboard/lenovo/t60/chip.h b/src/mainboard/lenovo/t60/chip.h
deleted file mode 100644
index 70f9bb4..0000000
--- a/src/mainboard/lenovo/t60/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c
index a9f4117..bd4c4a7 100644
--- a/src/mainboard/lenovo/t60/mainboard.c
+++ b/src/mainboard/lenovo/t60/mainboard.c
@@ -26,7 +26,6 @@
#include <boot/tables.h>
#include <delay.h>
#include <arch/coreboot_tables.h>
-#include "chip.h"
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <arch/io.h>
diff --git a/src/mainboard/lenovo/x60/chip.h b/src/mainboard/lenovo/x60/chip.h
deleted file mode 100644
index 70f9bb4..0000000
--- a/src/mainboard/lenovo/x60/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c
index b45342a..c37ae66 100644
--- a/src/mainboard/lenovo/x60/mainboard.c
+++ b/src/mainboard/lenovo/x60/mainboard.c
@@ -26,7 +26,6 @@
#include <boot/tables.h>
#include <delay.h>
#include <arch/coreboot_tables.h>
-#include "chip.h"
#include <device/pci_def.h>
#include <device/pci_ops.h>
#include <arch/io.h>
diff --git a/src/mainboard/lippert/frontrunner/chip.h b/src/mainboard/lippert/frontrunner/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/lippert/frontrunner/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/lippert/frontrunner/mainboard.c b/src/mainboard/lippert/frontrunner/mainboard.c
index 7cd9f1d..ec1503e 100644
--- a/src/mainboard/lippert/frontrunner/mainboard.c
+++ b/src/mainboard/lippert/frontrunner/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Lippert Cool Frontrunner Mainboard")
diff --git a/src/mainboard/lippert/hurricane-lx/chip.h b/src/mainboard/lippert/hurricane-lx/chip.h
deleted file mode 100644
index 0c70fcd..0000000
--- a/src/mainboard/lippert/hurricane-lx/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/lippert/hurricane-lx/mainboard.c b/src/mainboard/lippert/hurricane-lx/mainboard.c
index 959966c..9b7ad98 100644
--- a/src/mainboard/lippert/hurricane-lx/mainboard.c
+++ b/src/mainboard/lippert/hurricane-lx/mainboard.c
@@ -27,7 +27,6 @@
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "chip.h"
/* Bit1 switches Com1 to RS485, bit2 same for Com2. */
#if CONFIG_ONBOARD_UARTS_RS485
diff --git a/src/mainboard/lippert/literunner-lx/chip.h b/src/mainboard/lippert/literunner-lx/chip.h
deleted file mode 100644
index 0c70fcd..0000000
--- a/src/mainboard/lippert/literunner-lx/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/lippert/literunner-lx/mainboard.c b/src/mainboard/lippert/literunner-lx/mainboard.c
index 65ea12a..cfec2a8 100644
--- a/src/mainboard/lippert/literunner-lx/mainboard.c
+++ b/src/mainboard/lippert/literunner-lx/mainboard.c
@@ -27,7 +27,6 @@
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "chip.h"
/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
#if CONFIG_ONBOARD_UARTS_RS485
diff --git a/src/mainboard/lippert/roadrunner-lx/chip.h b/src/mainboard/lippert/roadrunner-lx/chip.h
deleted file mode 100644
index 398d424..0000000
--- a/src/mainboard/lippert/roadrunner-lx/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/lippert/roadrunner-lx/mainboard.c b/src/mainboard/lippert/roadrunner-lx/mainboard.c
index 31fdd46..26adb2f 100644
--- a/src/mainboard/lippert/roadrunner-lx/mainboard.c
+++ b/src/mainboard/lippert/roadrunner-lx/mainboard.c
@@ -27,7 +27,6 @@
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "chip.h"
/* Bit1 switches Com1 to RS485, bit2 same for Com2, bit5 turns off the Live LED. */
#if CONFIG_ONBOARD_UARTS_RS485
diff --git a/src/mainboard/lippert/spacerunner-lx/chip.h b/src/mainboard/lippert/spacerunner-lx/chip.h
deleted file mode 100644
index 398d424..0000000
--- a/src/mainboard/lippert/spacerunner-lx/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 LiPPERT Embedded Computers GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/lippert/spacerunner-lx/mainboard.c b/src/mainboard/lippert/spacerunner-lx/mainboard.c
index 34cd8c4..f2aeb10 100644
--- a/src/mainboard/lippert/spacerunner-lx/mainboard.c
+++ b/src/mainboard/lippert/spacerunner-lx/mainboard.c
@@ -27,7 +27,6 @@
#include <arch/io.h>
#include <device/pci.h>
#include <device/pci_ids.h>
-#include "chip.h"
/* Bit0 turns off the Live LED, bit1 switches Com1 to RS485, bit2 same for Com2. */
#if CONFIG_ONBOARD_UARTS_RS485
diff --git a/src/mainboard/mitac/6513wu/chip.h b/src/mainboard/mitac/6513wu/chip.h
deleted file mode 100644
index 0421977..0000000
--- a/src/mainboard/mitac/6513wu/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Michael Gold <mgold@ncf.ca>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/mitac/6513wu/mainboard.c b/src/mainboard/mitac/6513wu/mainboard.c
index 9e4ec8d..968b9e9 100644
--- a/src/mainboard/mitac/6513wu/mainboard.c
+++ b/src/mainboard/mitac/6513wu/mainboard.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/msi/ms6119/chip.h b/src/mainboard/msi/ms6119/chip.h
deleted file mode 100644
index 56e17ca..0000000
--- a/src/mainboard/msi/ms6119/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms6119/mainboard.c b/src/mainboard/msi/ms6119/mainboard.c
index 9c4ef29..7ef3d4b 100644
--- a/src/mainboard/msi/ms6119/mainboard.c
+++ b/src/mainboard/msi/ms6119/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-6119 Mainboard")
diff --git a/src/mainboard/msi/ms6147/chip.h b/src/mainboard/msi/ms6147/chip.h
deleted file mode 100644
index fbf5d32..0000000
--- a/src/mainboard/msi/ms6147/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Mats Erik Andersson <mats.andersson@gisladisker.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms6147/mainboard.c b/src/mainboard/msi/ms6147/mainboard.c
index b7c7386d..091de54 100644
--- a/src/mainboard/msi/ms6147/mainboard.c
+++ b/src/mainboard/msi/ms6147/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-6147 Mainboard")
diff --git a/src/mainboard/msi/ms6156/chip.h b/src/mainboard/msi/ms6156/chip.h
deleted file mode 100644
index 1c3876d..0000000
--- a/src/mainboard/msi/ms6156/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms6156/mainboard.c b/src/mainboard/msi/ms6156/mainboard.c
index 1864f0b..28b5e81 100644
--- a/src/mainboard/msi/ms6156/mainboard.c
+++ b/src/mainboard/msi/ms6156/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-6156 Mainboard")
diff --git a/src/mainboard/msi/ms6178/chip.h b/src/mainboard/msi/ms6178/chip.h
deleted file mode 100644
index 982cfb3..0000000
--- a/src/mainboard/msi/ms6178/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms6178/mainboard.c b/src/mainboard/msi/ms6178/mainboard.c
index e4ba148..0aeedb8 100644
--- a/src/mainboard/msi/ms6178/mainboard.c
+++ b/src/mainboard/msi/ms6178/mainboard.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/msi/ms7135/chip.h b/src/mainboard/msi/ms7135/chip.h
deleted file mode 100644
index 063d25b..0000000
--- a/src/mainboard/msi/ms7135/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Jonathan A. Kollasch <jakllsch@kollasch.net>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms7135/mainboard.c b/src/mainboard/msi/ms7135/mainboard.c
index 586f9c5..3ed0c6b 100644
--- a/src/mainboard/msi/ms7135/mainboard.c
+++ b/src/mainboard/msi/ms7135/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS7135 Mainboard")
diff --git a/src/mainboard/msi/ms7260/chip.h b/src/mainboard/msi/ms7260/chip.h
deleted file mode 100644
index 982cfb3..0000000
--- a/src/mainboard/msi/ms7260/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms7260/mainboard.c b/src/mainboard/msi/ms7260/mainboard.c
index 2b61736..06d606f 100644
--- a/src/mainboard/msi/ms7260/mainboard.c
+++ b/src/mainboard/msi/ms7260/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
#if 0
#include "hda_verb.h"
diff --git a/src/mainboard/msi/ms9185/chip.h b/src/mainboard/msi/ms9185/chip.h
deleted file mode 100644
index 6638ef1..0000000
--- a/src/mainboard/msi/ms9185/chip.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 MSI
- * Written by bxshi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
diff --git a/src/mainboard/msi/ms9185/mainboard.c b/src/mainboard/msi/ms9185/mainboard.c
index 873a490..f3e28d4 100644
--- a/src/mainboard/msi/ms9185/mainboard.c
+++ b/src/mainboard/msi/ms9185/mainboard.c
@@ -24,7 +24,6 @@
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("MSI MS-9185 Mainboard")
diff --git a/src/mainboard/msi/ms9282/chip.h b/src/mainboard/msi/ms9282/chip.h
deleted file mode 100644
index 0831119..0000000
--- a/src/mainboard/msi/ms9282/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2006 MSI
- * Written by Bingxun Shi <bingxunshi@gmail.com> for MSI.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms9282/mainboard.c b/src/mainboard/msi/ms9282/mainboard.c
index 99f7e22..800fd25 100644
--- a/src/mainboard/msi/ms9282/mainboard.c
+++ b/src/mainboard/msi/ms9282/mainboard.c
@@ -25,7 +25,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
// #include "hda_verb.h"
-#include "chip.h"
static void verb_setup(void)
{
diff --git a/src/mainboard/msi/ms9652_fam10/chip.h b/src/mainboard/msi/ms9652_fam10/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/msi/ms9652_fam10/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/msi/ms9652_fam10/mainboard.c b/src/mainboard/msi/ms9652_fam10/mainboard.c
index 255b22d7..e570607 100644
--- a/src/mainboard/msi/ms9652_fam10/mainboard.c
+++ b/src/mainboard/msi/ms9652_fam10/mainboard.c
@@ -25,7 +25,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
// #include "hda_verb.h"
-#include "chip.h"
static void verb_setup(void)
{
diff --git a/src/mainboard/nec/powermate2000/chip.h b/src/mainboard/nec/powermate2000/chip.h
deleted file mode 100644
index 41784c9..0000000
--- a/src/mainboard/nec/powermate2000/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/nec/powermate2000/mainboard.c b/src/mainboard/nec/powermate2000/mainboard.c
index a26e8df..3b29c7c 100644
--- a/src/mainboard/nec/powermate2000/mainboard.c
+++ b/src/mainboard/nec/powermate2000/mainboard.c
@@ -20,7 +20,6 @@
#include <device/device.h>
#include <boot/tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/newisys/khepri/chip.h b/src/mainboard/newisys/khepri/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/newisys/khepri/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/newisys/khepri/mainboard.c b/src/mainboard/newisys/khepri/mainboard.c
index d278fd2..11e7032 100644
--- a/src/mainboard/newisys/khepri/mainboard.c
+++ b/src/mainboard/newisys/khepri/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Newisys 2100 Mainboard")
diff --git a/src/mainboard/nokia/ip530/chip.h b/src/mainboard/nokia/ip530/chip.h
deleted file mode 100644
index 1046412..0000000
--- a/src/mainboard/nokia/ip530/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/nokia/ip530/mainboard.c b/src/mainboard/nokia/ip530/mainboard.c
index b0dd27b..8b934ff 100644
--- a/src/mainboard/nokia/ip530/mainboard.c
+++ b/src/mainboard/nokia/ip530/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Nokia IP530 Mainboard")
diff --git a/src/mainboard/nvidia/l1_2pvv/chip.h b/src/mainboard/nvidia/l1_2pvv/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/nvidia/l1_2pvv/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/nvidia/l1_2pvv/mainboard.c b/src/mainboard/nvidia/l1_2pvv/mainboard.c
index b425c3d..5836571 100644
--- a/src/mainboard/nvidia/l1_2pvv/mainboard.c
+++ b/src/mainboard/nvidia/l1_2pvv/mainboard.c
@@ -25,7 +25,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "hda_verb.h"
-#include "chip.h"
static void verb_setup(void)
{
diff --git a/src/mainboard/pcengines/alix1c/chip.h b/src/mainboard/pcengines/alix1c/chip.h
deleted file mode 100644
index fb321d5..0000000
--- a/src/mainboard/pcengines/alix1c/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/pcengines/alix1c/mainboard.c b/src/mainboard/pcengines/alix1c/mainboard.c
index a32cb14..74c1cc4 100644
--- a/src/mainboard/pcengines/alix1c/mainboard.c
+++ b/src/mainboard/pcengines/alix1c/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/pcengines/alix2d/chip.h b/src/mainboard/pcengines/alix2d/chip.h
deleted file mode 100644
index fb321d5..0000000
--- a/src/mainboard/pcengines/alix2d/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/pcengines/alix2d/mainboard.c b/src/mainboard/pcengines/alix2d/mainboard.c
index b227d66..1b526c9 100644
--- a/src/mainboard/pcengines/alix2d/mainboard.c
+++ b/src/mainboard/pcengines/alix2d/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/rca/rm4100/chip.h b/src/mainboard/rca/rm4100/chip.h
deleted file mode 100644
index 4aec17f..0000000
--- a/src/mainboard/rca/rm4100/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/rca/rm4100/mainboard.c b/src/mainboard/rca/rm4100/mainboard.c
index 653b22a..613c1d7 100644
--- a/src/mainboard/rca/rm4100/mainboard.c
+++ b/src/mainboard/rca/rm4100/mainboard.c
@@ -21,7 +21,6 @@
#include <device/device.h>
#include <boot/tables.h>
#include <arch/coreboot_tables.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c
index d87d712..1f4ebc7 100644
--- a/src/mainboard/roda/rk886ex/mainboard.c
+++ b/src/mainboard/roda/rk886ex/mainboard.c
@@ -29,7 +29,6 @@
#include <x86emu/x86emu.h>
#endif
#include <arch/coreboot_tables.h>
-#include "chip.h"
#include <ec/acpi/ec.h>
#include "m3885.h"
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
index 200edac..0835012 100644
--- a/src/mainboard/samsung/lumpy/Kconfig
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -44,14 +44,6 @@
string
default "pci8086,0106.rom"
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
- hex
- default 0x1ae0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
- hex
- default 0xc000
-
config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
bool
default n
diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
index fc7be20..fbe98c9 100644
--- a/src/mainboard/samsung/lumpy/acpi/chromeos.asl
+++ b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
@@ -17,98 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-Device (CRHW)
-{
- Name(_HID, EISAID("GGL0001"))
+Name(OIPG, Package() {
+ Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
+ Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
+ Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect
+})
- Method(_STA, 0, Serialized)
- {
- Return (0xb)
- }
-
- Method(CHSW, 0, Serialized)
- {
- Name (WSHC, Package() { VBT3 })
- Return (WSHC)
- }
-
- Method(FWID, 0, Serialized)
- {
- Name (DIW1, "")
- ToString(VBT5, 63, DIW1)
- Name (DIWF, Package() { DIW1 })
- Return(DIWF)
- }
-
- Method(FRID, 0, Serialized)
- {
- Name (DIR1, "")
- ToString(VBT6, 63, DIR1)
- Name (DIRF, Package() { DIR1 })
- Return (DIRF)
- }
-
- Method(HWID, 0, Serialized)
- {
- Name (DIW0, "")
- ToString(VBT4, 255, DIW0)
- Name (DIWH, Package() { DIW0 })
- Return (DIWH)
- }
-
- Method(BINF, 0, Serialized)
- {
- Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
- Return (FNIB)
- }
-
- Method(GPIO, 0, Serialized)
- {
- Name(OIPG, Package() {
- Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
- Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
- Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect
- })
- Return (OIPG)
-
- }
-
- Method(VBNV, 0, Serialized)
- {
- Name(VNBV, Package() {
- // See src/vendorcode/google/chromeos/Kconfig
- // for the definition of these:
- CONFIG_VBNV_OFFSET,
- CONFIG_VBNV_SIZE
- })
- Return(VNBV)
- }
-
- Method(VDAT, 0, Serialized)
- {
- Name(TAD0,"")
- ToBuffer(CHVD, TAD0)
- Name (TADV, Package() { TAD0 })
- Return (TADV)
- }
-
- Method(FMAP, 0, Serialized)
- {
- Name(PAMF, Package() { VBT9 })
- Return(PAMF)
- }
-
- Method(MECK, 0, Serialized)
- {
- Name(HASH, Package() { MEHH })
- Return(HASH)
- }
-
- Method(MLST, 0, Serialized)
- {
- Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
- "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
- })
- Return (TSLM)
- }
-}
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
index 46fdf31..5272cac 100644
--- a/src/mainboard/samsung/lumpy/acpi_tables.c
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -276,6 +276,7 @@
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
"DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
break;
}
}
@@ -315,9 +316,3 @@
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
-
-void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size)
-{
- *vdat_addr = &gnvs_->chromeos.vdat;
- *vdat_size = sizeof(gnvs_->chromeos.vdat);
-}
diff --git a/src/mainboard/samsung/lumpy/chip.h b/src/mainboard/samsung/lumpy/chip.h
deleted file mode 100644
index 831a973..0000000
--- a/src/mainboard/samsung/lumpy/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
index 36af1ca..3e93df4 100644
--- a/src/mainboard/samsung/lumpy/devicetree.cb
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -33,6 +33,7 @@
end
device pci_domain 0 on
+ subsystemid 0x1ae0 0xc000 inherit
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
index 94adfda..c1c9685 100644
--- a/src/mainboard/samsung/lumpy/dsdt.asl
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -52,6 +52,7 @@
}
#include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
diff --git a/src/mainboard/samsung/lumpy/fadt.c b/src/mainboard/samsung/lumpy/fadt.c
index 6d78233..510b765 100644
--- a/src/mainboard/samsung/lumpy/fadt.c
+++ b/src/mainboard/samsung/lumpy/fadt.c
@@ -47,7 +47,7 @@
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+ fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
@@ -65,7 +65,7 @@
fadt->gpe0_blk_len = 16;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
- fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
diff --git a/src/mainboard/samsung/lumpy/hda_verb.h b/src/mainboard/samsung/lumpy/hda_verb.h
index 732f0aa..3871aa1 100644
--- a/src/mainboard/samsung/lumpy/hda_verb.h
+++ b/src/mainboard/samsung/lumpy/hda_verb.h
@@ -69,3 +69,13 @@
0x00a71e45,
0x00a71f43
};
+
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x00170500, /* power up codec */
+ 0x00270500, /* power up DAC */
+ 0x00670500, /* power up speaker */
+ 0x00670740, /* enable speaker output */
+ 0x0023B04B, /* set DAC gain */
+};
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
index c5db0d3..75bc184 100644
--- a/src/mainboard/samsung/lumpy/mainboard.c
+++ b/src/mainboard/samsung/lumpy/mainboard.c
@@ -34,7 +34,6 @@
#include <arch/coreboot_tables.h>
#include <ec/smsc/mec1308/ec.h>
#include "hda_verb.h"
-#include "chip.h"
#include "ec.h"
#include "onboard.h"
#include <southbridge/intel/bd82x6x/pch.h>
@@ -254,11 +253,15 @@
extern const u32 * cim_verb_data;
extern u32 cim_verb_data_size;
+extern const u32 * pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
static void verb_setup(void)
{
cim_verb_data = mainboard_cim_verb_data;
cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
}
static void mainboard_init(device_t dev)
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
index 82856f6..4bba76e 100644
--- a/src/mainboard/samsung/lumpy/romstage.c
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -114,9 +114,6 @@
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
- /* Enable upper 128bytes of CMOS (generic) */
- RCBA32(RC) = (1 << 2);
-
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
reg32 |= PCH_DISABLE_ALWAYS;
@@ -330,11 +327,8 @@
rcba_config();
post_code(0x3c);
- /* Initialize the internal PCIe links before we go into stage2 */
- sandybridge_late_initialization();
-
- post_code(0x3e);
quick_ram_check();
+ post_code(0x3e);
MCHBAR16(SSKPD) = 0xCAFE;
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
index dda3002..18094cf 100644
--- a/src/mainboard/samsung/stumpy/Kconfig
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -43,14 +43,6 @@
string
default "pci8086,0106.rom"
-config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
- hex
- default 0x1ae0
-
-config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
- hex
- default 0xc000
-
config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
bool
default n
diff --git a/src/mainboard/samsung/stumpy/acpi/chromeos.asl b/src/mainboard/samsung/stumpy/acpi/chromeos.asl
index f517b16..739e0d4 100644
--- a/src/mainboard/samsung/stumpy/acpi/chromeos.asl
+++ b/src/mainboard/samsung/stumpy/acpi/chromeos.asl
@@ -17,98 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-Device (CRHW)
-{
- Name(_HID, EISAID("GGL0001"))
-
- Method(_STA, 0, Serialized)
- {
- Return (0xb)
- }
-
- Method(CHSW, 0, Serialized)
- {
- Name (WSHC, Package() { VBT3 })
- Return (WSHC)
- }
-
- Method(FWID, 0, Serialized)
- {
- Name (DIW1, "")
- ToString(VBT5, 63, DIW1)
- Name (DIWF, Package() { DIW1 })
- Return(DIWF)
- }
-
- Method(FRID, 0, Serialized)
- {
- Name (DIR1, "")
- ToString(VBT6, 63, DIR1)
- Name (DIRF, Package() { DIR1 })
- Return (DIRF)
- }
-
- Method(HWID, 0, Serialized)
- {
- Name (DIW0, "")
- ToString(VBT4, 255, DIW0)
- Name (DIWH, Package() { DIW0 })
- Return (DIWH)
- }
-
- Method(BINF, 0, Serialized)
- {
- Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
- Return (FNIB)
- }
-
- Method(GPIO, 0, Serialized)
- {
- Name(OIPG, Package() {
- Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
- Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
- Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect
- })
- Return (OIPG)
-
- }
-
- Method(VBNV, 0, Serialized)
- {
- Name(VNBV, Package() {
- // See src/vendorcode/google/chromeos/Kconfig
- // for the definition of these:
- CONFIG_VBNV_OFFSET,
- CONFIG_VBNV_SIZE
- })
- Return(VNBV)
- }
-
- Method(VDAT, 0, Serialized)
- {
- Name(TAD0,"")
- ToBuffer(CHVD, TAD0)
- Name (TADV, Package() { TAD0 })
- Return (TADV)
- }
-
- Method(FMAP, 0, Serialized)
- {
- Name(PAMF, Package() { VBT9 })
- Return(PAMF)
- }
-
- Method(MECK, 0, Serialized)
- {
- Name(HASH, Package() { MEHH })
- Return(HASH)
- }
-
- Method(MLST, 0, Serialized)
- {
- Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
- "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
- })
- Return (TSLM)
- }
-}
+Name(OIPG, Package() {
+ Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
+ Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
+ Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect
+})
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c
index 68da59d..47d77c0 100644
--- a/src/mainboard/samsung/stumpy/acpi_tables.c
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -280,6 +280,7 @@
printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
"DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+ acpi_save_gnvs(current);
break;
}
}
@@ -319,12 +320,3 @@
printk(BIOS_INFO, "ACPI: done.\n");
return current;
}
-
-#if CONFIG_CHROMEOS
-void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size)
-{
- *vdat_addr = &gnvs_->chromeos.vdat;
- *vdat_size = sizeof(gnvs_->chromeos.vdat);
-}
-#endif
-
diff --git a/src/mainboard/samsung/stumpy/chip.h b/src/mainboard/samsung/stumpy/chip.h
deleted file mode 100644
index 831a973..0000000
--- a/src/mainboard/samsung/stumpy/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
index f10b283..b59dcb2 100644
--- a/src/mainboard/samsung/stumpy/devicetree.cb
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -28,6 +28,7 @@
end
device pci_domain 0 on
+ subsystemid 0x1ae0 0xc000 inherit
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
index 63aa47e..608827a 100644
--- a/src/mainboard/samsung/stumpy/dsdt.asl
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -50,6 +50,7 @@
}
#include "acpi/chromeos.asl"
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
diff --git a/src/mainboard/samsung/stumpy/fadt.c b/src/mainboard/samsung/stumpy/fadt.c
index ff840c09..315cb58 100644
--- a/src/mainboard/samsung/stumpy/fadt.c
+++ b/src/mainboard/samsung/stumpy/fadt.c
@@ -47,7 +47,7 @@
fadt->acpi_enable = APM_CNT_ACPI_ENABLE;
fadt->acpi_disable = APM_CNT_ACPI_DISABLE;
fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = APM_CNT_PST_CONTROL;
+ fadt->pstate_cnt = 0;
fadt->pm1a_evt_blk = pmbase;
fadt->pm1b_evt_blk = 0x0;
@@ -65,7 +65,7 @@
fadt->gpe0_blk_len = 16;
fadt->gpe1_blk_len = 0;
fadt->gpe1_base = 0;
- fadt->cst_cnt = APM_CNT_CST_CONTROL;
+ fadt->cst_cnt = 0;
fadt->p_lvl2_lat = 1;
fadt->p_lvl3_lat = 87;
fadt->flush_size = 1024;
diff --git a/src/mainboard/samsung/stumpy/hda_verb.h b/src/mainboard/samsung/stumpy/hda_verb.h
index 9a4a740..c9a49c5 100644
--- a/src/mainboard/samsung/stumpy/hda_verb.h
+++ b/src/mainboard/samsung/stumpy/hda_verb.h
@@ -97,3 +97,12 @@
0x30771f18
};
+static const u32 mainboard_pc_beep_verbs[] = {
+ 0x00170500, /* power up codec */
+ 0x00270500, /* power up DAC */
+ 0x00670500, /* power up speaker */
+ 0x00670740, /* enable speaker output */
+ 0x0023B04B, /* set DAC gain */
+};
+static const u32 mainboard_pc_beep_verbs_size =
+ sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]);
diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c
index 9152a3b..3daa9fb 100644
--- a/src/mainboard/samsung/stumpy/mainboard.c
+++ b/src/mainboard/samsung/stumpy/mainboard.c
@@ -34,7 +34,6 @@
#include <arch/interrupt.h>
#include <arch/coreboot_tables.h>
#include "hda_verb.h"
-#include "chip.h"
#include <southbridge/intel/bd82x6x/pch.h>
void mainboard_suspend_resume(void)
@@ -224,11 +223,15 @@
extern const u32 * cim_verb_data;
extern u32 cim_verb_data_size;
+extern const u32 * pc_beep_verbs;
+extern u32 pc_beep_verbs_size;
static void verb_setup(void)
{
cim_verb_data = mainboard_cim_verb_data;
cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+ pc_beep_verbs = mainboard_pc_beep_verbs;
+ pc_beep_verbs_size = mainboard_pc_beep_verbs_size;
}
// mainboard_enable is executed as first thing after
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 10a9d7b..58305c8 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -119,9 +119,6 @@
/* PCH BWG says to read back the IOAPIC enable register */
(void) RCBA16(OIC);
- /* Enable upper 128bytes of CMOS (generic) */
- RCBA32(RC) = (1 << 2);
-
/* Disable unused devices (board specific) */
reg32 = RCBA32(FD);
reg32 |= PCH_DISABLE_ALWAYS;
@@ -335,11 +332,8 @@
rcba_config();
post_code(0x3c);
- /* Initialize the internal PCIe links before we go into stage2 */
- sandybridge_late_initialization();
-
- post_code(0x3e);
quick_ram_check();
+ post_code(0x3e);
MCHBAR16(SSKPD) = 0xCAFE;
#if CONFIG_EARLY_CBMEM_INIT
diff --git a/src/mainboard/siemens/sitemp_g1p1/chip.h b/src/mainboard/siemens/sitemp_g1p1/chip.h
deleted file mode 100644
index ff426e0..0000000
--- a/src/mainboard/siemens/sitemp_g1p1/chip.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- * Copyright (C) 2010 Siemens AG, Inc.
- * (Written by Josef Kellermann <joseph.kellermann@heitec.de> for Siemens AG, Inc.)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config
-{
- u32 uma_size; /* How many UMA should be used in memory for TOP. */
- unsigned int plx_present : 1;
-};
-
diff --git a/src/mainboard/siemens/sitemp_g1p1/mainboard.c b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
index 0d7b8da..0ed61eb 100644
--- a/src/mainboard/siemens/sitemp_g1p1/mainboard.c
+++ b/src/mainboard/siemens/sitemp_g1p1/mainboard.c
@@ -34,7 +34,6 @@
#include <southbridge/amd/rs690/chip.h>
#include <southbridge/amd/rs690/rs690.h>
#include <superio/ite/it8712f/it8712f.h>
-#include "chip.h"
#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
#include <x86emu/x86emu.h>
#endif
@@ -674,13 +673,14 @@
};
-static void update_subsystemid( device_t dev ) {
+unsigned int plx_present = 0;
+static void update_subsystemid( device_t dev )
+{
int i;
- struct mainboard_config *mb = dev->chip_info;
dev->subsystem_vendor = 0x110a;
- if( mb->plx_present ){
+ if( plx_present ){
dev->subsystem_device = 0x4076; // U1P1 = 0x4076, U1P0 = 0x4077
} else {
dev->subsystem_device = 0x4077; // U1P0 = 0x4077
@@ -702,12 +702,12 @@
* @param
*/
-static void detect_hw_variant( device_t dev ) {
+static void detect_hw_variant( device_t dev )
+{
device_t nb_dev =0, dev2 = 0;
struct southbridge_amd_rs690_config *cfg;
u32 lc_state, id = 0;
- struct mainboard_config *mb = dev->chip_info;
printk(BIOS_INFO, "Scan for PLX device ...\n");
nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
@@ -783,10 +783,10 @@
break;
}
- mb->plx_present = 0;
+ plx_present = 0;
if( id == PLX_VIDDID ){
printk(BIOS_INFO, "found PLX device\n");
- mb->plx_present = 1;
+ plx_present = 1;
cfg = (struct southbridge_amd_rs690_config *)dev2->chip_info;
if( cfg->gfx_tmds ) {
printk(BIOS_INFO, "Disable 'gfx_tmds' support\n");
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/chip.h b/src/mainboard/soyo/sy-6ba-plus-iii/chip.h
deleted file mode 100644
index 1c3876d..0000000
--- a/src/mainboard/soyo/sy-6ba-plus-iii/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c b/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c
index 4cead76..9e7b1f2 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Soyo SY-6BA+ III Mainboard")
diff --git a/src/mainboard/sunw/ultra40/chip.h b/src/mainboard/sunw/ultra40/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/sunw/ultra40/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/sunw/ultra40/mainboard.c b/src/mainboard/sunw/ultra40/mainboard.c
index b5e865d..d46ea38 100644
--- a/src/mainboard/sunw/ultra40/mainboard.c
+++ b/src/mainboard/sunw/ultra40/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Sun Ultra 40 Mainboard")
diff --git a/src/mainboard/supermicro/h8dme/chip.h b/src/mainboard/supermicro/h8dme/chip.h
deleted file mode 100644
index 2076c6f..0000000
--- a/src/mainboard/supermicro/h8dme/chip.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8dme/mainboard.c b/src/mainboard/supermicro/h8dme/mainboard.c
index c1b9635..c092c71 100644
--- a/src/mainboard/supermicro/h8dme/mainboard.c
+++ b/src/mainboard/supermicro/h8dme/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8DME Mainboard")
diff --git a/src/mainboard/supermicro/h8dmr/chip.h b/src/mainboard/supermicro/h8dmr/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/supermicro/h8dmr/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8dmr/mainboard.c b/src/mainboard/supermicro/h8dmr/mainboard.c
index a00d9e8..45536af 100644
--- a/src/mainboard/supermicro/h8dmr/mainboard.c
+++ b/src/mainboard/supermicro/h8dmr/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8DMR Mainboard")
diff --git a/src/mainboard/supermicro/h8dmr_fam10/chip.h b/src/mainboard/supermicro/h8dmr_fam10/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/supermicro/h8dmr_fam10/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8dmr_fam10/mainboard.c b/src/mainboard/supermicro/h8dmr_fam10/mainboard.c
index e59a980..24736a9 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8DMR Mainboard (Family 10)")
diff --git a/src/mainboard/supermicro/h8qgi/chip.h b/src/mainboard/supermicro/h8qgi/chip.h
deleted file mode 100644
index a252705..0000000
--- a/src/mainboard/supermicro/h8qgi/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8qgi/mainboard.c b/src/mainboard/supermicro/h8qgi/mainboard.c
index f6d437e..1f02c73 100644
--- a/src/mainboard/supermicro/h8qgi/mainboard.c
+++ b/src/mainboard/supermicro/h8qgi/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <NbPlatform.h>
-#include "chip.h"
void set_pcie_dereset(void *nbconfig);
void set_pcie_reset(void *nbconfig);
diff --git a/src/mainboard/supermicro/h8qme_fam10/chip.h b/src/mainboard/supermicro/h8qme_fam10/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/supermicro/h8qme_fam10/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8qme_fam10/mainboard.c b/src/mainboard/supermicro/h8qme_fam10/mainboard.c
index 45b0920..647f623 100644
--- a/src/mainboard/supermicro/h8qme_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8qme_fam10/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro H8QME-2+ Mainboard (Family 10)")
diff --git a/src/mainboard/supermicro/h8scm_fam10/chip.h b/src/mainboard/supermicro/h8scm_fam10/chip.h
deleted file mode 100644
index a98b97e..0000000
--- a/src/mainboard/supermicro/h8scm_fam10/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/h8scm_fam10/mainboard.c b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
index d0fb541..e5a58fe 100644
--- a/src/mainboard/supermicro/h8scm_fam10/mainboard.c
+++ b/src/mainboard/supermicro/h8scm_fam10/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sr5650/cmn.h>
-#include "chip.h"
void set_pcie_reset(void);
@@ -73,10 +72,6 @@
*************************************************/
static void h8scm_enable(device_t dev)
{
- /* Leave it for furture use. */
- /* struct mainboard_config *mainboard =
- (struct mainboard_config *)dev->chip_info; */
-
printk(BIOS_INFO, "Mainboard H8SCM Enable. dev=0x%p\n", dev);
msr_t msr, msr2;
diff --git a/src/mainboard/supermicro/x6dai_g/chip.h b/src/mainboard/supermicro/x6dai_g/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/supermicro/x6dai_g/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x6dai_g/mainboard.c b/src/mainboard/supermicro/x6dai_g/mainboard.c
index 1db8cd4..d9b4bc4 100644
--- a/src/mainboard/supermicro/x6dai_g/mainboard.c
+++ b/src/mainboard/supermicro/x6dai_g/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro X6DAi-G Mainboard")
diff --git a/src/mainboard/supermicro/x6dhe_g/chip.h b/src/mainboard/supermicro/x6dhe_g/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/supermicro/x6dhe_g/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x6dhe_g/mainboard.c b/src/mainboard/supermicro/x6dhe_g/mainboard.c
index a242ddd..c09c95a 100644
--- a/src/mainboard/supermicro/x6dhe_g/mainboard.c
+++ b/src/mainboard/supermicro/x6dhe_g/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro X6DHE-G Mainboard")
diff --git a/src/mainboard/supermicro/x6dhe_g2/chip.h b/src/mainboard/supermicro/x6dhe_g2/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/supermicro/x6dhe_g2/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x6dhe_g2/mainboard.c b/src/mainboard/supermicro/x6dhe_g2/mainboard.c
index fdb67cc..c20a842 100644
--- a/src/mainboard/supermicro/x6dhe_g2/mainboard.c
+++ b/src/mainboard/supermicro/x6dhe_g2/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro X6DHE-G2 Mainboard")
diff --git a/src/mainboard/supermicro/x6dhr_ig/chip.h b/src/mainboard/supermicro/x6dhr_ig/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/supermicro/x6dhr_ig/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x6dhr_ig/mainboard.c b/src/mainboard/supermicro/x6dhr_ig/mainboard.c
index 51acb86..3875fe0 100644
--- a/src/mainboard/supermicro/x6dhr_ig/mainboard.c
+++ b/src/mainboard/supermicro/x6dhr_ig/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro X6DHR-iG Mainboard")
diff --git a/src/mainboard/supermicro/x6dhr_ig2/chip.h b/src/mainboard/supermicro/x6dhr_ig2/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/supermicro/x6dhr_ig2/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/supermicro/x6dhr_ig2/mainboard.c b/src/mainboard/supermicro/x6dhr_ig2/mainboard.c
index 6b6c64f..981aee8 100644
--- a/src/mainboard/supermicro/x6dhr_ig2/mainboard.c
+++ b/src/mainboard/supermicro/x6dhr_ig2/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Supermicro X6DHR-iG2 Mainboard")
diff --git a/src/mainboard/technexion/tim5690/chip.h b/src/mainboard/technexion/tim5690/chip.h
deleted file mode 100644
index 05e1582..0000000
--- a/src/mainboard/technexion/tim5690/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
diff --git a/src/mainboard/technexion/tim5690/mainboard.c b/src/mainboard/technexion/tim5690/mainboard.c
index 6350230..783e985 100644
--- a/src/mainboard/technexion/tim5690/mainboard.c
+++ b/src/mainboard/technexion/tim5690/mainboard.c
@@ -27,7 +27,6 @@
#include <device/pci_def.h>
#include <southbridge/amd/sb600/sb600.h>
#include <superio/ite/it8712f/it8712f.h>
-#include "chip.h"
#include "tn_post_code.h"
#include "vgabios.h"
diff --git a/src/mainboard/technexion/tim8690/chip.h b/src/mainboard/technexion/tim8690/chip.h
deleted file mode 100644
index 05e1582..0000000
--- a/src/mainboard/technexion/tim8690/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
-
diff --git a/src/mainboard/technexion/tim8690/mainboard.c b/src/mainboard/technexion/tim8690/mainboard.c
index 18abbc9..c3ba1ef 100644
--- a/src/mainboard/technexion/tim8690/mainboard.c
+++ b/src/mainboard/technexion/tim8690/mainboard.c
@@ -26,7 +26,6 @@
#include <cpu/amd/mtrr.h>
#include <device/pci_def.h>
#include <southbridge/amd/sb600/sb600.h>
-#include "chip.h"
#define ADT7461_ADDRESS 0x4C
#define ARA_ADDRESS 0x0C /* Alert Response Address */
diff --git a/src/mainboard/technologic/ts5300/chip.h b/src/mainboard/technologic/ts5300/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/technologic/ts5300/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/technologic/ts5300/mainboard.c b/src/mainboard/technologic/ts5300/mainboard.c
index 58333b8..164b7e8 100644
--- a/src/mainboard/technologic/ts5300/mainboard.c
+++ b/src/mainboard/technologic/ts5300/mainboard.c
@@ -4,7 +4,6 @@
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <cpu/amd/sc520.h>
-#include "chip.h"
#if 0
diff --git a/src/mainboard/televideo/tc7020/chip.h b/src/mainboard/televideo/tc7020/chip.h
deleted file mode 100644
index 6b6d455..0000000
--- a/src/mainboard/televideo/tc7020/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/televideo/tc7020/mainboard.c b/src/mainboard/televideo/tc7020/mainboard.c
index a0919dc..ee41109 100644
--- a/src/mainboard/televideo/tc7020/mainboard.c
+++ b/src/mainboard/televideo/tc7020/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("TeleVideo TC7020 Mainboard")
diff --git a/src/mainboard/thomson/ip1000/chip.h b/src/mainboard/thomson/ip1000/chip.h
deleted file mode 100644
index 4aec17f..0000000
--- a/src/mainboard/thomson/ip1000/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/thomson/ip1000/mainboard.c b/src/mainboard/thomson/ip1000/mainboard.c
index f6eee68..e5c3ea1 100644
--- a/src/mainboard/thomson/ip1000/mainboard.c
+++ b/src/mainboard/thomson/ip1000/mainboard.c
@@ -27,7 +27,6 @@
#endif
#include <arch/coreboot_tables.h>
#include <arch/io.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/traverse/geos/chip.h b/src/mainboard/traverse/geos/chip.h
deleted file mode 100644
index ae69536..0000000
--- a/src/mainboard/traverse/geos/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/traverse/geos/mainboard.c b/src/mainboard/traverse/geos/mainboard.c
index b578959..c299bc8 100644
--- a/src/mainboard/traverse/geos/mainboard.c
+++ b/src/mainboard/traverse/geos/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/tyan/s1846/chip.h b/src/mainboard/tyan/s1846/chip.h
deleted file mode 100644
index dc9bed3..0000000
--- a/src/mainboard/tyan/s1846/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s1846/mainboard.c b/src/mainboard/tyan/s1846/mainboard.c
index e5ab1c90..fb2034c 100644
--- a/src/mainboard/tyan/s1846/mainboard.c
+++ b/src/mainboard/tyan/s1846/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S1846 Mainboard")
diff --git a/src/mainboard/tyan/s2735/chip.h b/src/mainboard/tyan/s2735/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2735/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c
index 267755c..5456b9e 100644
--- a/src/mainboard/tyan/s2735/mainboard.c
+++ b/src/mainboard/tyan/s2735/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2735 Mainboard")
diff --git a/src/mainboard/tyan/s2850/chip.h b/src/mainboard/tyan/s2850/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2850/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2850/mainboard.c b/src/mainboard/tyan/s2850/mainboard.c
index 8afa8f0..137aa57 100644
--- a/src/mainboard/tyan/s2850/mainboard.c
+++ b/src/mainboard/tyan/s2850/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2850 Mainboard")
diff --git a/src/mainboard/tyan/s2875/chip.h b/src/mainboard/tyan/s2875/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2875/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2875/mainboard.c b/src/mainboard/tyan/s2875/mainboard.c
index 49e1092..cbc4c6c 100644
--- a/src/mainboard/tyan/s2875/mainboard.c
+++ b/src/mainboard/tyan/s2875/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2875 Mainboard")
diff --git a/src/mainboard/tyan/s2880/chip.h b/src/mainboard/tyan/s2880/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2880/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2880/mainboard.c b/src/mainboard/tyan/s2880/mainboard.c
index 7fc8615..96e3cf2 100644
--- a/src/mainboard/tyan/s2880/mainboard.c
+++ b/src/mainboard/tyan/s2880/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2880 Mainboard")
diff --git a/src/mainboard/tyan/s2881/chip.h b/src/mainboard/tyan/s2881/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2881/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2881/mainboard.c b/src/mainboard/tyan/s2881/mainboard.c
index 9da5fe8..5034c5d 100644
--- a/src/mainboard/tyan/s2881/mainboard.c
+++ b/src/mainboard/tyan/s2881/mainboard.c
@@ -21,7 +21,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2881 Mainboard")
diff --git a/src/mainboard/tyan/s2882/chip.h b/src/mainboard/tyan/s2882/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2882/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2882/mainboard.c b/src/mainboard/tyan/s2882/mainboard.c
index 0779df1..771d8b6 100644
--- a/src/mainboard/tyan/s2882/mainboard.c
+++ b/src/mainboard/tyan/s2882/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2882 Mainboard")
diff --git a/src/mainboard/tyan/s2885/chip.h b/src/mainboard/tyan/s2885/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2885/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2885/mainboard.c b/src/mainboard/tyan/s2885/mainboard.c
index 27da722..446460d 100644
--- a/src/mainboard/tyan/s2885/mainboard.c
+++ b/src/mainboard/tyan/s2885/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2885 Mainboard")
diff --git a/src/mainboard/tyan/s2891/chip.h b/src/mainboard/tyan/s2891/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2891/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2891/mainboard.c b/src/mainboard/tyan/s2891/mainboard.c
index c529c0a..155f084 100644
--- a/src/mainboard/tyan/s2891/mainboard.c
+++ b/src/mainboard/tyan/s2891/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2891 Mainboard")
diff --git a/src/mainboard/tyan/s2892/chip.h b/src/mainboard/tyan/s2892/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2892/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2892/mainboard.c b/src/mainboard/tyan/s2892/mainboard.c
index 299f836..10fd0c0 100644
--- a/src/mainboard/tyan/s2892/mainboard.c
+++ b/src/mainboard/tyan/s2892/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2892 Mainboard")
diff --git a/src/mainboard/tyan/s2895/chip.h b/src/mainboard/tyan/s2895/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s2895/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2895/mainboard.c b/src/mainboard/tyan/s2895/mainboard.c
index f152eae..4de60af 100644
--- a/src/mainboard/tyan/s2895/mainboard.c
+++ b/src/mainboard/tyan/s2895/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2895 Mainboard")
diff --git a/src/mainboard/tyan/s2912/chip.h b/src/mainboard/tyan/s2912/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/tyan/s2912/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2912/mainboard.c b/src/mainboard/tyan/s2912/mainboard.c
index 6084b3d..bfdb75e 100644
--- a/src/mainboard/tyan/s2912/mainboard.c
+++ b/src/mainboard/tyan/s2912/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2912 Mainboard")
diff --git a/src/mainboard/tyan/s2912_fam10/chip.h b/src/mainboard/tyan/s2912_fam10/chip.h
deleted file mode 100644
index ebd990b..0000000
--- a/src/mainboard/tyan/s2912_fam10/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 AMD
- * Written by Yinghai Lu <yinghailu@amd.com> for AMD.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s2912_fam10/mainboard.c b/src/mainboard/tyan/s2912_fam10/mainboard.c
index f976b14..3fed2f8 100644
--- a/src/mainboard/tyan/s2912_fam10/mainboard.c
+++ b/src/mainboard/tyan/s2912_fam10/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S2912 Mainboard (Family 10)")
diff --git a/src/mainboard/tyan/s4880/chip.h b/src/mainboard/tyan/s4880/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s4880/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s4880/mainboard.c b/src/mainboard/tyan/s4880/mainboard.c
index f2f865b..ad9adab 100644
--- a/src/mainboard/tyan/s4880/mainboard.c
+++ b/src/mainboard/tyan/s4880/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S4880 Mainboard")
diff --git a/src/mainboard/tyan/s4882/chip.h b/src/mainboard/tyan/s4882/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/tyan/s4882/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/tyan/s4882/mainboard.c b/src/mainboard/tyan/s4882/mainboard.c
index 8d626c7..0595d59 100644
--- a/src/mainboard/tyan/s4882/mainboard.c
+++ b/src/mainboard/tyan/s4882/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("Tyan S4882 Mainboard")
diff --git a/src/mainboard/via/epia-cn/chip.h b/src/mainboard/via/epia-cn/chip.h
deleted file mode 100644
index 0a2badb..0000000
--- a/src/mainboard/via/epia-cn/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/via/epia-cn/mainboard.c b/src/mainboard/via/epia-cn/mainboard.c
index 1a7210e..702b5b0 100644
--- a/src/mainboard/via/epia-cn/mainboard.c
+++ b/src/mainboard/via/epia-cn/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("VIA EPIA-CN Mainboard")
diff --git a/src/mainboard/via/epia-m/chip.h b/src/mainboard/via/epia-m/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/via/epia-m/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/via/epia-m/mainboard.c b/src/mainboard/via/epia-m/mainboard.c
index 2e517a3..49f18df 100644
--- a/src/mainboard/via/epia-m/mainboard.c
+++ b/src/mainboard/via/epia-m/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("VIA EPIA-M Mainboard")
diff --git a/src/mainboard/via/epia-m700/chip.h b/src/mainboard/via/epia-m700/chip.h
deleted file mode 100644
index c44330b..0000000
--- a/src/mainboard/via/epia-m700/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 One Laptop per Child, Association, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/via/epia-m700/mainboard.c b/src/mainboard/via/epia-m700/mainboard.c
index 5a21b86..53537e0 100644
--- a/src/mainboard/via/epia-m700/mainboard.c
+++ b/src/mainboard/via/epia-m700/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("VIA EPIA-M700 Mainboard")
diff --git a/src/mainboard/via/epia-n/chip.h b/src/mainboard/via/epia-n/chip.h
deleted file mode 100644
index 0a2badb..0000000
--- a/src/mainboard/via/epia-n/chip.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 VIA Technologies, Inc.
- * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/via/epia-n/mainboard.c b/src/mainboard/via/epia-n/mainboard.c
index cf5ae96..0dfbd3c9 100644
--- a/src/mainboard/via/epia-n/mainboard.c
+++ b/src/mainboard/via/epia-n/mainboard.c
@@ -26,7 +26,6 @@
#include <arch/ioapic.h>
#include <southbridge/via/vt8237r/vt8237r.h>
#include <cpu/x86/lapic_def.h>
-#include "chip.h"
int add_mainboard_resources(struct lb_memory *mem)
{
diff --git a/src/mainboard/via/epia/chip.h b/src/mainboard/via/epia/chip.h
deleted file mode 100644
index d138e51..0000000
--- a/src/mainboard/via/epia/chip.h
+++ /dev/null
@@ -1,3 +0,0 @@
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/via/epia/mainboard.c b/src/mainboard/via/epia/mainboard.c
index 25d72a5..95edf46 100644
--- a/src/mainboard/via/epia/mainboard.c
+++ b/src/mainboard/via/epia/mainboard.c
@@ -1,5 +1,4 @@
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("VIA EPIA Mainboard")
diff --git a/src/mainboard/via/pc2500e/chip.h b/src/mainboard/via/pc2500e/chip.h
deleted file mode 100644
index 41784c9..0000000
--- a/src/mainboard/via/pc2500e/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/via/pc2500e/mainboard.c b/src/mainboard/via/pc2500e/mainboard.c
index 9fcee55..65aed56 100644
--- a/src/mainboard/via/pc2500e/mainboard.c
+++ b/src/mainboard/via/pc2500e/mainboard.c
@@ -19,7 +19,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("VIA pc2500e Mainboard")
diff --git a/src/mainboard/via/vt8454c/chip.h b/src/mainboard/via/vt8454c/chip.h
deleted file mode 100644
index 5101c16..0000000
--- a/src/mainboard/via/vt8454c/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/via/vt8454c/mainboard.c b/src/mainboard/via/vt8454c/mainboard.c
index e931ccd..c6e1b92 100644
--- a/src/mainboard/via/vt8454c/mainboard.c
+++ b/src/mainboard/via/vt8454c/mainboard.c
@@ -20,7 +20,6 @@
*/
#include <device/device.h>
-#include "chip.h"
struct chip_operations mainboard_ops = {
CHIP_NAME("VIA VT8454c Mainboard")
diff --git a/src/mainboard/winent/pl6064/chip.h b/src/mainboard/winent/pl6064/chip.h
deleted file mode 100644
index ae69536..0000000
--- a/src/mainboard/winent/pl6064/chip.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/winent/pl6064/mainboard.c b/src/mainboard/winent/pl6064/mainboard.c
index cd664f6..0293c7a 100644
--- a/src/mainboard/winent/pl6064/mainboard.c
+++ b/src/mainboard/winent/pl6064/mainboard.c
@@ -19,7 +19,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/mainboard/wyse/s50/chip.h b/src/mainboard/wyse/s50/chip.h
deleted file mode 100644
index e0e9727..0000000
--- a/src/mainboard/wyse/s50/chip.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Nils Jacobs
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-extern struct chip_operations mainboard_ops;
-
-struct mainboard_config {};
diff --git a/src/mainboard/wyse/s50/mainboard.c b/src/mainboard/wyse/s50/mainboard.c
index 8497b24..99dfb42 100644
--- a/src/mainboard/wyse/s50/mainboard.c
+++ b/src/mainboard/wyse/s50/mainboard.c
@@ -21,7 +21,6 @@
#include <console/console.h>
#include <device/device.h>
-#include "chip.h"
static void init(struct device *dev)
{
diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index d226085..191c077 100644
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -1334,5 +1334,5 @@
pci_write_config16(PCI_DEV(0, 0x00, 0), MCHSCRB, data16);
/* The memory is now setup, use it */
- cache_lbmem(MTRR_TYPE_WRBACK);
+ cache_ramstage();
}
diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index b5895bc..c491a7e 100644
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -1307,5 +1307,5 @@
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
- cache_lbmem(MTRR_TYPE_WRBACK);
+ cache_ramstage();
}
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 050df95..b453e8b 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1198,6 +1198,6 @@
/* The memory is now setup, use it */
#if !CONFIG_CACHE_AS_RAM
- cache_lbmem(MTRR_TYPE_WRBACK);
+ cache_ramstage();
#endif
}
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 79fc5f7..5fe206f 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -772,7 +772,7 @@
pci_write_config32(ctrl->f0, DRC, drc);
/* The memory is now set up--use it */
- cache_lbmem(MTRR_TYPE_WRBACK);
+ cache_ramstage();
}
static inline int memory_initialized(void)
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 67b3def..676bc01 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -21,11 +21,13 @@
bool
select CACHE_MRC_BIN
select CPU_INTEL_MODEL_206AX
+ select REQUIRES_BLOB
config NORTHBRIDGE_INTEL_IVYBRIDGE
bool
select CACHE_MRC_BIN
select CPU_INTEL_MODEL_306AX
+ select REQUIRES_BLOB
if NORTHBRIDGE_INTEL_SANDYBRIDGE
@@ -44,16 +46,14 @@
config MRC_CACHE_LOCATION
hex
+ depends on !CHROMEOS
default 0x1ec000
config MRC_CACHE_SIZE
hex
+ depends on !CHROMEOS
default 0x10000
-config MRC_CACHE_ALIGNMENT
- hex
- default 0x1000
-
config DCACHE_RAM_BASE
hex
default 0xff7f0000
@@ -78,6 +78,21 @@
int
default 512
+# FIXME: build from rom size
+config MRC_CACHE_BASE
+ hex
+ default 0xff800000
+
+config MRC_CACHE_LOCATION
+ hex
+ depends on !CHROMEOS
+ default 0x370000
+
+config MRC_CACHE_SIZE
+ hex
+ depends on !CHROMEOS
+ default 0x10000
+
config DCACHE_RAM_BASE
hex
default 0xff7e0000
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
index d1174d6..10b1a68 100644
--- a/src/northbridge/intel/sandybridge/acpi.c
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -36,7 +36,9 @@
u32 pciexbar_reg;
int max_buses;
- dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NB, 0);
+ dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_SB, 0);
+ if (!dev)
+ dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_IB, 0);
if (!dev)
return current;
diff --git a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
index 592c4c6..93db98d 100644
--- a/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/hostbridge.asl
@@ -101,8 +101,143 @@
TLUD, 32,
}
-}
+ Mutex (CTCM, 1) /* CTDP Switch Mutex (sync level 1) */
+ Name (CTCC, 0) /* CTDP Current Selection */
+ Name (CTCN, 0) /* CTDP Nominal Select */
+ Name (CTCD, 1) /* CTDP Down Select */
+ Name (CTCU, 2) /* CTDP Up Select */
+ OperationRegion (MCHB, SystemMemory, DEFAULT_MCHBAR, 0x8000)
+ Field (MCHB, DWordAcc, Lock, Preserve)
+ {
+ Offset (0x5930),
+ CTDN, 15, /* CTDP Nominal PL1 */
+ Offset (0x59a0),
+ PL1V, 15, /* Power Limit 1 Value */
+ PL1E, 1, /* Power Limit 1 Enable */
+ PL1C, 1, /* Power Limit 1 Clamp */
+ PL1T, 7, /* Power Limit 1 Time */
+ Offset (0x59a4),
+ PL2V, 15, /* Power Limit 2 Value */
+ PL2E, 1, /* Power Limit 2 Enable */
+ PL2C, 1, /* Power Limit 2 Clamp */
+ PL2T, 7, /* Power Limit 2 Time */
+ Offset (0x5f3c),
+ TARN, 8, /* CTDP Nominal Turbo Activation Ratio */
+ Offset (0x5f40),
+ CTDD, 15, /* CTDP Down PL1 */
+ , 1,
+ TARD, 8, /* CTDP Down Turbo Activation Ratio */
+ Offset (0x5f48),
+ CTDU, 15, /* CTDP Up PL1 */
+ , 1,
+ TARU, 8, /* CTDP Up Turbo Activation Ratio */
+ Offset (0x5f50),
+ CTCS, 2, /* CTDP Select */
+ Offset (0x5f54),
+ TARS, 8, /* Turbo Activation Ratio Select */
+ }
+
+ /*
+ * Search CPU0 _PSS looking for control=arg0 and then
+ * return previous P-state entry number for new _PPC
+ *
+ * Format of _PSS:
+ * Name (_PSS, Package () {
+ * Package (6) { freq, power, tlat, blat, control, status }
+ * }
+ */
+ External (\_PR.CPU0._PSS)
+ Method (PSSS, 1, NotSerialized)
+ {
+ Store (One, Local0) /* Start at P1 */
+ Store (SizeOf (\_PR.CPU0._PSS), Local1)
+
+ While (LLess (Local0, Local1)) {
+ /* Store _PSS entry Control value to Local2 */
+ ShiftRight (DeRefOf (Index (DeRefOf (Index
+ (\_PR.CPU0._PSS, Local0)), 4)), 8, Local2)
+ If (LEqual (Local2, Arg0)) {
+ Return (Subtract (Local0, 1))
+ }
+ Increment (Local0)
+ }
+
+ Return (0)
+ }
+
+ /* Set TDP Down */
+ Method (STND, 0, Serialized)
+ {
+ If (Acquire (CTCM, 100)) {
+ Return (0)
+ }
+ If (LEqual (CTCD, CTCC)) {
+ Release (CTCM)
+ Return (0)
+ }
+
+ Store ("Set TDP Down", Debug)
+
+ /* Set CTC */
+ Store (CTCD, CTCS)
+
+ /* Set TAR */
+ Store (TARD, TARS)
+
+ /* Set PPC limit and notify OS */
+ Store (PSSS (TARD), PPCM)
+ PPCN ()
+
+ /* Set PL2 to 1.25 * PL1 */
+ Divide (Multiply (CTDD, 125), 100, Local0, PL2V)
+
+ /* Set PL1 */
+ Store (CTDD, PL1V)
+
+ /* Store the new TDP Down setting */
+ Store (CTCD, CTCC)
+
+ Release (CTCM)
+ Return (1)
+ }
+
+ /* Set TDP Nominal from Down */
+ Method (STDN, 0, Serialized)
+ {
+ If (Acquire (CTCM, 100)) {
+ Return (0)
+ }
+ If (LEqual (CTCN, CTCC)) {
+ Release (CTCM)
+ Return (0)
+ }
+
+ Store ("Set TDP Nominal", Debug)
+
+ /* Set PL1 */
+ Store (CTDN, PL1V)
+
+ /* Set PL2 to 1.25 * PL1 */
+ Divide (Multiply (CTDN, 125), 100, Local0, PL2V)
+
+ /* Set PPC limit and notify OS */
+ Store (PSSS (TARN), PPCM)
+ PPCN ()
+
+ /* Set TAR */
+ Store (TARN, TARS)
+
+ /* Set CTC */
+ Store (CTCN, CTCS)
+
+ /* Store the new TDP Nominal setting */
+ Store (CTCN, CTCC)
+
+ Release (CTCM)
+ Return (1)
+ }
+}
// Current Resource Settings
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 64b5d8f..6708e27 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -19,8 +19,8 @@
* MA 02110-1301 USA
*/
-#include "hostbridge.asl"
#include "../sandybridge.h"
+#include "hostbridge.asl"
/* PCI Device Resource Consumption */
Device (PDRC)
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
index f052fbc..2954bf1 100644
--- a/src/northbridge/intel/sandybridge/early_init.c
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -24,6 +24,7 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
+#include <elog.h>
#include "sandybridge.h"
#include "pcie_config.c"
@@ -64,6 +65,14 @@
pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
printk(BIOS_DEBUG, " done.\n");
+
+#if CONFIG_ELOG_BOOT_COUNT
+ /* Increment Boot Counter except when resuming from S3 */
+ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) &&
+ ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3)
+ return;
+ boot_count_increment();
+#endif
}
static void sandybridge_setup_graphics(void)
@@ -108,8 +117,6 @@
pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8);
/* Erratum workarounds */
- MCHBAR8(0x5f10) = 0x20;
-
reg32 = MCHBAR32(0x5f00);
reg32 |= (1 << 9)|(1 << 10);
MCHBAR32(0x5f00) = reg32;
@@ -158,8 +165,3 @@
sandybridge_setup_graphics();
}
-
-void sandybridge_late_initialization(void)
-{
-}
-
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index 499f347..9a8b631 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -374,19 +374,11 @@
if (bridge_silicon_revision() < IVB_STEP_C0) {
/* 1: Enable force wake */
gtt_write(0xa18c, 0x00000001);
- if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
- return;
+ gtt_poll(0x130090, (1 << 0), (1 << 0));
} else {
gtt_write(0xa180, 1 << 5);
gtt_write(0xa188, 0xffff0001);
- if (!gtt_poll(0x130040, (1 << 0), (1 << 0)))
- return;
- /*
- * HACK: also poll on 0x130090, for some reason graphics does
- * not work on all SKUs unless this register is polled at boot.
- */
- if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
- return;
+ gtt_poll(0x130040, (1 << 0), (1 << 0));
}
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) {
@@ -432,7 +424,7 @@
gtt_write_powermeter(ivb_pm_gt2_17w);
} else if ((tdp >= 25) && (tdp <= 35)) {
/* 25W-35W */
- printk(BIOS_DEBUG, "IVB GT2 35W "
+ printk(BIOS_DEBUG, "IVB GT2 25W-35W "
"Power Meter Weights\n");
gtt_write_powermeter(ivb_pm_gt2_35w);
} else {
@@ -472,8 +464,7 @@
reg32 &= 0xf;
reg32 |= (1 << 1);
gtt_write(0x941c, reg32);
- if (!gtt_poll(0x941c, (1 << 1), (0 << 1)))
- return;
+ gtt_poll(0x941c, (1 << 1), (0 << 1));
}
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
@@ -489,15 +480,13 @@
}
/* 7 */
- if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
- return;
- gtt_write(0x138128, 0x00000029); /* Mailbox Data */
- gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
- if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
- return;
- gtt_write(0x138124, 0x8000000a); /* Mailbox Cmd to clear RC6 count */
- if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
- return;
+ if (gtt_poll(0x138124, (1 << 31), (0 << 31))) {
+ gtt_write(0x138128, 0x00000029); /* Mailbox Data */
+ gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
+ if (gtt_poll(0x138124, (1 << 31), (0 << 31)))
+ gtt_write(0x138124, 0x8000000a);
+ gtt_poll(0x138124, (1 << 31), (0 << 31));
+ }
/* 8 */
gtt_write(0xa090, 0x00000000); /* RC Control */
@@ -530,8 +519,13 @@
/* 11a: Enable Render Standby (RC6) */
if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
- /* on IVB: also enable DeepRenderStandby */
- gtt_write(0xa090, 0x88060000); /* HW RC Control */
+ /*
+ * IvyBridge should also support DeepRenderStandby.
+ *
+ * Unfortunately it does not work reliably on all SKUs so
+ * disable it here and it can be enabled by the kernel.
+ */
+ gtt_write(0xa090, 0x88040000); /* HW RC Control */
} else {
gtt_write(0xa090, 0x88040000); /* HW RC Control */
}
@@ -566,22 +560,11 @@
/* 15: Deassert Force Wake */
if (bridge_silicon_revision() < IVB_STEP_C0) {
gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
- if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) {
- return;
- }
+ gtt_poll(0x130090, (1 << 0), (0 << 0));
} else {
gtt_write(0xa188, 0x1fffe);
- if (!gtt_poll(0x130040, (1 << 0), (0 << 0))) {
- return;
- }
- /*
- * HACK: also poll on 0x130090, for some reason graphics does
- * not work on all SKUs unless this register is polled at boot.
- */
- if (!gtt_poll(0x130090, (1 << 0), (0 << 0))) {
- return;
- }
- gtt_write(0xa188, gtt_read(0xa188) | 1);
+ if (gtt_poll(0x130040, (1 << 0), (0 << 0)))
+ gtt_write(0xa188, gtt_read(0xa188) | 1);
}
/* 16: SW RC Control */
diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c
index 5c4c382..2a7727c 100644
--- a/src/northbridge/intel/sandybridge/mrccache.c
+++ b/src/northbridge/intel/sandybridge/mrccache.c
@@ -28,18 +28,8 @@
#include "sandybridge.h"
#include <spi.h>
#include <spi_flash.h>
-/* Using the FDT FMAP for finding the MRC cache area requires including FDT
- * support in coreboot, which we would like to avoid. There are a number of
- * options:
- * - Have each mainboard Kconfig supply a hard-coded offset
- * - For ChromeOS devices: implement native FMAP
- * - For non-ChromeOS devices: use CBFS
- * For now let's leave this code in here until the issue is sorted out in
- * a way that works for everyone.
- */
-#undef USE_FDT_FMAP_FOR_MRC_CACHE
-#ifdef USE_FDT_FMAP_FOR_MRC_CACHE
-#include <fdt/libfdt.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/fmap.h>
#endif
struct mrc_data_container *next_mrc_block(struct mrc_data_container *mrc_cache)
@@ -61,67 +51,23 @@
return (!!mrc_cache) && (mrc_cache->mrc_signature == MRC_DATA_SIGNATURE);
}
+/* Right now, the offsets for the MRC cache area are hard-coded in the
+ * northbridge Kconfig if CONFIG_CHROMEOS is not set. In order to make
+ * this more flexible, there are two of options:
+ * - Have each mainboard Kconfig supply a hard-coded offset
+ * - Use CBFS
+ */
u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
- u8 *mrc_region;
u32 region_size;
- u32 *data;
-#ifdef USE_FDT_FMAP_FOR_MRC_CACHE
- const struct fdt_header *fdt_header;
- const struct fdt_property *fdtp;
- int offset, len;
- const char *compatible = "chromeos,flashmap";
- const char *subnode = "rw-mrc-cache";
- const char *property = "reg";
- u64 flashrom_base = 0;
-
- fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT);
-
- if (!fdt_header) {
- printk(BIOS_ERR, "%s: no FDT found!\n", __func__);
- return 0;
- }
-
- offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible);
- if (offset < 0) {
- printk(BIOS_ERR, "%s: no %s node found!\n",
- __func__, compatible);
- return 0;
- }
-
- if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) {
- printk(BIOS_ERR, "%s: no base address in node name!\n",
- __func__);
- return 0;
- }
-
- offset = fdt_subnode_offset(fdt_header, offset, subnode);
- if (offset < 0) {
- printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode);
- return 0;
- }
-
- fdtp = fdt_get_property(fdt_header, offset, property, &len);
- if (!fdtp || (len != 8)) {
- printk(BIOS_ERR, "%s: property %s at %p, len %d!\n",
- __func__, property, fdtp, len);
- return 0;
- }
-
- data = (u32 *)fdtp->data;
-
- // Calculate actual address of the MRC cache in memory
- region_size = fdt32_to_cpu(data[1]);
- mrc_region = (u8*)((unsigned long)flashrom_base + fdt32_to_cpu(data[0]));
+#if CONFIG_CHROMEOS
+ region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr);
#else
- data = (u32 *)((void *)(CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION + 12));
-
region_size = CONFIG_MRC_CACHE_SIZE;
- mrc_region = (u8*)(CONFIG_MRC_CACHE_BASE + be32_to_cpu(data[0]));
+ *mrc_region_ptr = (struct mrc_data_container *)
+ (CONFIG_MRC_CACHE_BASE + CONFIG_MRC_CACHE_LOCATION);
#endif
- *mrc_region_ptr = (struct mrc_data_container *)mrc_region;
-
return region_size;
}
@@ -178,17 +124,22 @@
* from having no cache area at all
*/
return mrc_cache;
- } else {
- /* Search for the last filled entry in the region */
- while (is_mrc_cache(mrc_next)) {
- entry_id++;
- mrc_cache = mrc_next;
- mrc_next = next_mrc_block(mrc_cache);
- /* Stay in the mrcdata region defined in fdt */
- if ((void*)mrc_next >= (void*)(mrc_region + region_size))
- break;
- }
- entry_id--;
+ }
+
+ /* Search for the last filled entry in the region */
+ while (is_mrc_cache(mrc_next)) {
+ entry_id++;
+ mrc_cache = mrc_next;
+ mrc_next = next_mrc_block(mrc_cache);
+ /* Stay in the mrc data region */
+ if ((void*)mrc_next >= (void*)(mrc_region + region_size))
+ break;
+ }
+ entry_id--;
+
+ if (entry_id == -1) {
+ printk(BIOS_ERR, "%s: No valid MRC cache found.\n", __func__);
+ return NULL;
}
/* Verify checksum */
@@ -210,6 +161,7 @@
#if !defined(__PRE_RAM__)
void update_mrc_cache(void)
{
+ printk(BIOS_DEBUG, "Updating MRC cache data.\n");
struct mrc_data_container *current = cbmem_find(CBMEM_ID_MRCDATA);
if (!current) {
printk(BIOS_ERR, "No MRC cache in cbmem. Can't update flash.\n");
@@ -226,12 +178,14 @@
// 0. compare MRC data to last mrc-cache block (exit if same)
struct mrc_data_container *cache;
if ((cache = find_current_mrc_cache()) == NULL) {
- printk(BIOS_DEBUG, "Failure looking for current last block\n");
+ printk(BIOS_DEBUG, "Failure looking for current last block.\n");
return;
}
- if ((cache->mrc_data_size == current->mrc_data_size) && (memcmp(cache, current, cache->mrc_data_size) == 0)) {
- printk(BIOS_DEBUG, "MRC data in flash is up to date. No update.\n");
+ if ((cache->mrc_data_size == current->mrc_data_size) &&
+ (memcmp(cache, current, cache->mrc_data_size) == 0)) {
+ printk(BIOS_DEBUG,
+ "MRC data in flash is up to date. No update.\n");
return;
}
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
index 6419f8c..6f83743 100644
--- a/src/northbridge/intel/sandybridge/northbridge.c
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -24,6 +24,7 @@
#include <stdint.h>
#include <delay.h>
#include <cpu/intel/model_206ax/model_206ax.h>
+#include <cpu/x86/msr.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@@ -390,9 +391,28 @@
static void northbridge_init(struct device *dev)
{
u8 bios_reset_cpl;
+ u32 bridge_type;
northbridge_dmi_init(dev);
+ bridge_type = MCHBAR32(0x5f10);
+ bridge_type &= ~0xff;
+
+ if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_IVB) {
+ /* Enable Power Aware Interrupt Routing */
+ u8 pair = MCHBAR8(0x5418);
+ pair &= ~0xf; /* Clear 3:0 */
+ pair |= 0x4; /* Fixed Priority */
+ MCHBAR8(0x5418) = pair;
+
+ /* 30h for IvyBridge */
+ bridge_type |= 0x30;
+ } else {
+ /* 20h for Sandybridge */
+ bridge_type |= 0x20;
+ }
+ MCHBAR32(0x5f10) = bridge_type;
+
/*
* Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
* that BIOS has initialized memory and power management
@@ -406,6 +426,16 @@
mdelay(1);
set_power_limits(28);
+ /*
+ * CPUs with configurable TDP also need power limits set
+ * in MCHBAR. Use same values from MSR_PKG_POWER_LIMIT.
+ */
+ if (cpu_config_tdp_levels()) {
+ msr_t msr = rdmsr(MSR_PKG_POWER_LIMIT);
+ MCHBAR32(0x59A0) = msr.lo;
+ MCHBAR32(0x59A4) = msr.hi;
+ }
+
/* Set here before graphics PM init */
MCHBAR32(0x5500) = 0x00100001;
}
@@ -444,6 +474,12 @@
.ops_pci = &intel_pci_ops,
};
+static const struct pci_driver mc_driver_0100 __pci_driver = {
+ .ops = &mc_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x0100,
+};
+
static const struct pci_driver mc_driver __pci_driver = {
.ops = &mc_ops,
.vendor = PCI_VENDOR_ID_INTEL,
@@ -484,6 +520,6 @@
}
struct chip_operations northbridge_intel_sandybridge_ops = {
- CHIP_NAME("Intel i7 (Sandybridge) integrated Northbridge")
+ CHIP_NAME("Intel i7 (SandyBridge/IvyBridge) integrated Northbridge")
.enable_dev = enable_dev,
};
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
index cda08b2..8c907c1 100644
--- a/src/northbridge/intel/sandybridge/pei_data.h
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -30,7 +30,8 @@
#ifndef PEI_DATA_H
#define PEI_DATA_H
-#define PEI_VERSION 1
+typedef void (*tx_byte_func)(unsigned char byte);
+#define PEI_VERSION 4
struct pei_data
{
uint32_t pei_version;
@@ -78,6 +79,9 @@
* [1] = overcurrent pin
* [2] = length
*
+ * Ports 0-7 can be mapped to OC0-OC3
+ * Ports 8-13 can be mapped to OC4-OC7
+ *
* Port Length
* MOBILE:
* < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
@@ -93,6 +97,19 @@
* spd_address for a given "DIMM".
*/
uint8_t spd_data[4][256];
+ tx_byte_func tx_byte;
+ int ddr3lv_support;
+ /* pcie_init needs to be set to 1 to have the system agent initialize
+ * PCIe. Note: This should only be required if your system has Gen3 devices
+ * and it will increase your boot time by at least 100ms.
+ */
+ int pcie_init;
+ /* N mode functionality. Leave this setting at 0.
+ * 0 Auto
+ * 1 1N
+ * 2 2N
+ */
+ int nmode;
} __attribute__((packed));
#endif
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 0df86d6..713953e 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -50,9 +50,9 @@
#define CMOS_OFFSET_MRC_SEED_S3 (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3)
#else
-#define CMOS_OFFSET_MRC_SEED 112
-#define CMOS_OFFSET_MRC_SEED_S3 116
-#define CMOS_OFFSET_MRC_SEED_CHK 120
+#define CMOS_OFFSET_MRC_SEED 152
+#define CMOS_OFFSET_MRC_SEED_S3 156
+#define CMOS_OFFSET_MRC_SEED_CHK 160
#endif
static void save_mrc_data(struct pei_data *pei_data)
@@ -205,6 +205,13 @@
}
}
+static void post_system_agent_init(struct pei_data *pei_data)
+{
+ /* If PCIe init is skipped, set the PEG clock gating */
+ if (!pei_data->pcie_init)
+ MCHBAR32(0x7010) = MCHBAR32(0x7010) | 0x01;
+}
+
/**
* Find PEI executable in coreboot filesystem and execute it.
*
@@ -241,6 +248,9 @@
hlt();
}
+ /* Pass console handler in pei_data */
+ pei_data->tx_byte = console_tx_byte;
+
/* Locate and call UEFI System Agent binary. */
entry = (unsigned long)cbfs_find_file("mrc.bin", 0xab);
if (entry) {
@@ -249,8 +259,17 @@
"call *%%ecx\n\t"
:"=a" (rv) : "c" (entry), "a" (pei_data));
if (rv) {
- printk(BIOS_ERR, "MRC returned %x\n", rv);
- die("Nonzero MRC return value\n");
+ switch (rv) {
+ case -1:
+ printk(BIOS_ERR, "PEI version mismatch.\n");
+ break;
+ case -2:
+ printk(BIOS_ERR, "Invalid memory frequency.\n");
+ break;
+ default:
+ printk(BIOS_ERR, "MRC returned %x.\n", rv);
+ }
+ die("Nonzero MRC return value.\n");
}
} else {
die("UEFI PEI System Agent not found.\n");
@@ -272,6 +291,7 @@
else
intel_early_me_status();
+ post_system_agent_init(pei_data);
report_memory_config();
/* S3 resume: don't save scrambler seed or MRC data */
diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c
index d59cfe9..ecd8f18 100644
--- a/src/northbridge/intel/sandybridge/report_platform.c
+++ b/src/northbridge/intel/sandybridge/report_platform.c
@@ -29,7 +29,7 @@
{
struct cpuid_result cpuidr;
u32 i, index;
- char cpu_string[50]; /* 48 bytes are reported */
+ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
int vt, txt, aes;
const char *mode[] = {"NOT ", ""};
@@ -47,8 +47,12 @@
*p++ = cpuidr.edx;
}
}
+ /* Skip leading spaces in CPU name string */
+ while (cpu_name[0] == ' ')
+ cpu_name++;
+
cpuidr = cpuid(1);
- printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_string);
+ printk(BIOS_DEBUG, "CPU id(%x): %s\n", cpuidr.eax, cpu_name);
aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
@@ -62,21 +66,24 @@
const char *dev_name;
} pch_table [] = {
{0x1E41, "Desktop Sample"},
+ {0x1E42, "Mobile Sample"},
+ {0x1E43, "SFF Sample"},
+ {0x1E44, "Z77"},
+ {0x1E45, "H71"},
+ {0x1E46, "Z75"},
{0x1E47, "Q77"},
{0x1E48, "Q75"},
{0x1E49, "B75"},
- {0x1E44, "Z77"},
- {0x1E46, "Z75"},
{0x1E4A, "H77"},
{0x1E53, "C216"},
- {0x1E42, "Mobile Sample"},
{0x1E55, "QM77"},
+ {0x1E56, "QS77"},
{0x1E58, "UM77"},
{0x1E57, "HM77"},
{0x1E59, "HM76"},
- {0x1E5d, "HM75"},
- {0x1E43, "SFF Sample"},
- {0x1E56, "QS77"},
+ {0x1E5D, "HM75"},
+ {0x1E5E, "HM70"},
+ {0x1E5F, "NM70"},
};
static void report_pch_info(void)
@@ -92,8 +99,8 @@
break;
}
}
- printk (BIOS_DEBUG, "PCH type: %s rev id %x\n",
- pch_type, pci_read_config8(PCH_LPC_DEV, 8));
+ printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",
+ pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8));
}
void report_platform_info(void)
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
index 7e12416..f8617de 100644
--- a/src/northbridge/intel/sandybridge/sandybridge.h
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -199,12 +199,8 @@
u8 reserved[34];
} __attribute__ ((packed));
-#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
-#define PCI_DEVICE_ID_NB 0x0104
-#endif
-#if CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE
-#define PCI_DEVICE_ID_NB 0x0154
-#endif
+#define PCI_DEVICE_ID_SB 0x0104
+#define PCI_DEVICE_ID_IB 0x0154
#ifdef __SMM__
void intel_sandybridge_finalize_smm(void);
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
index 3d8ba96..2e795c7 100644
--- a/src/northbridge/intel/sandybridge/udelay.c
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -23,9 +23,20 @@
#include <cpu/x86/msr.h>
/**
- * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
*/
+/* Simple 32- to 64-bit multiplication. Uses 16-bit words to avoid overflow. */
+static inline void multiply_to_tsc(tsc_t *const tsc, const u32 a, const u32 b)
+{
+ tsc->lo = (a & 0xffff) * (b & 0xffff);
+ tsc->hi = ((tsc->lo >> 16)
+ + ((a & 0xffff) * (b >> 16))
+ + ((b & 0xffff) * (a >> 16)));
+ tsc->lo = ((tsc->hi & 0xffff) << 16) | (tsc->lo & 0xffff);
+ tsc->hi = ((a >> 16) * (b >> 16)) + (tsc->hi >> 16);
+}
+
void udelay(u32 us)
{
u32 dword;
@@ -33,15 +44,12 @@
msr_t msr;
u32 fsb = 100, divisor;
u32 d; /* ticks per us */
- u32 dn = 0x1000000 / 2; /* how many us before we need to use hi */
msr = rdmsr(0xce);
divisor = (msr.lo >> 8) & 0xff;
- d = fsb * divisor;
-
- tscd.hi = us / dn;
- tscd.lo = (us - tscd.hi * dn) * d;
+ d = fsb * divisor; /* On Core/Core2 this is divided by 4 */
+ multiply_to_tsc(&tscd, us, d);
tsc1 = rdtsc();
dword = tsc1.lo + tscd.lo;
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index 33dfe9d..0a7d38b 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -34,7 +34,6 @@
select PCIEXP_ASPM
select PCIEXP_COMMON_CLOCK
select SPI_FLASH
- select SPI_FLASH_NO_FAST_READ
config EHCI_BAR
hex
@@ -56,15 +55,3 @@
operated in continuous mode.
endif
-
-if SOUTHBRIDGE_INTEL_BD82X6X
-config PCH_CHIP_NAME
- string
- default "Cougar Point"
-endif
-
-if SOUTHBRIDGE_INTEL_C216
-config PCH_CHIP_NAME
- string
- default "Panther Point"
-endif
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
index f086426..f9aade8 100644
--- a/src/southbridge/intel/bd82x6x/Makefile.inc
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -17,9 +17,6 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-me-src-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += me.c
-me-src-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += me_8.x.c
-
driver-y += pch.c
driver-y += azalia.c
driver-y += lpc.c
@@ -27,17 +24,20 @@
driver-y += pcie.c
driver-y += sata.c
driver-y += usb_ehci.c
-driver-y += $(me-src-y)
+driver-y += me.c
+driver-y += me_8.x.c
driver-y += smbus.c
ramstage-y += me_status.c
ramstage-y += reset.c
ramstage-y += watchdog.c
+ramstage-$(CONFIG_ELOG) += elog.c
ramstage-y += spi.c
+smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c
romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
index df450e3..7aeb32b 100644
--- a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -71,6 +71,7 @@
F4OF, 8, // 0x22 - FAN 4 OFF Threshold
F4ON, 8, // 0x23 - FAN 4 ON Threshold
F4PW, 8, // 0x24 - FAN 4 PWM value
+ TMPS, 8, // 0x25 - Temperature Sensor ID
/* Processor Identification */
Offset (0x28),
APIC, 8, // 0x28 - APIC Enabled by coreboot
@@ -82,8 +83,8 @@
/* Super I/O & CMOS config */
Offset (0x32),
NATP, 8, // 0x32 -
- S5U0, 8, // 0x32 - Enable USB0 in S5
- S5U1, 8, // 0x33 - Enable USB1 in S5
+ S5U0, 8, // 0x33 - Enable USB0 in S5
+ S5U1, 8, // 0x34 - Enable USB1 in S5
S3U0, 8, // 0x35 - Enable USB0 in S3
S3U1, 8, // 0x36 - Enable USB1 in S3
S33G, 8, // 0x37 - Enable 3G in S3
@@ -208,11 +209,28 @@
Store (Zero, \S33G)
}
+External (\_TZ.THRM)
+External (\_TZ.SKIN)
+
+Method (TZUP)
+{
+ /* Update Primary Thermal Zone */
+ If (CondRefOf (\_TZ.THRM, Local0)) {
+ Notify (\_TZ.THRM, 0x81)
+ }
+
+ /* Update Secondary Thermal Zone */
+ If (CondRefOf (\_TZ.SKIN, Local0)) {
+ Notify (\_TZ.SKIN, 0x81)
+ }
+}
+
/* Update Fan 0 thresholds */
Method (F0UT, 2)
{
Store (Arg0, \F0OF)
Store (Arg1, \F0ON)
+ TZUP ()
}
/* Update Fan 1 thresholds */
@@ -220,6 +238,7 @@
{
Store (Arg0, \F1OF)
Store (Arg1, \F1ON)
+ TZUP ()
}
/* Update Fan 2 thresholds */
@@ -227,6 +246,7 @@
{
Store (Arg0, \F2OF)
Store (Arg1, \F2ON)
+ TZUP ()
}
/* Update Fan 3 thresholds */
@@ -234,6 +254,7 @@
{
Store (Arg0, \F3OF)
Store (Arg1, \F3ON)
+ TZUP ()
}
/* Update Fan 4 thresholds */
@@ -241,4 +262,12 @@
{
Store (Arg0, \F4OF)
Store (Arg1, \F4ON)
+ TZUP ()
+}
+
+/* Update Temperature Sensor ID */
+Method (TMPU, 1)
+{
+ Store (Arg0, \TMPS)
+ TZUP ()
}
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
index 5a83e38..a257daf 100644
--- a/src/southbridge/intel/bd82x6x/azalia.c
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -92,6 +92,8 @@
const u32 * cim_verb_data = NULL;
u32 cim_verb_data_size = 0;
+const u32 * pc_beep_verbs = NULL;
+u32 pc_beep_verbs_size = 0;
static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
{
@@ -218,6 +220,16 @@
if (codec_mask & (1 << i))
codec_init(dev, base, i);
}
+
+ for (i = 0; i < pc_beep_verbs_size; i++) {
+ if (wait_for_ready(base) == -1)
+ return;
+
+ write32(base + 0x60, pc_beep_verbs[i]);
+
+ if (wait_for_valid(base) == -1)
+ return;
+ }
}
static void azalia_init(struct device *dev)
@@ -353,15 +365,11 @@
.ops_pci = &azalia_pci_ops,
};
-static const struct pci_driver azalia_0 __pci_driver = {
- .ops = &azalia_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c20,
-};
+static const unsigned short pci_device_ids[] = { 0x1c20, 0x1e20, 0 };
-static const struct pci_driver azalia_1 __pci_driver = {
- .ops = &azalia_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e20,
+static const struct pci_driver pch_azalia __pci_driver = {
+ .ops = &azalia_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
};
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
index d6cba5f..7d0db7f 100644
--- a/src/southbridge/intel/bd82x6x/bootblock.c
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -65,6 +65,26 @@
#endif
}
+static void set_spi_speed(void)
+{
+ u32 fdod;
+ u8 ssfc;
+
+ /* Observe SPI Descriptor Component Section 0 */
+ RCBA32(0x38b0) = 0x1000;
+
+ /* Extract the Write/Erase SPI Frequency from descriptor */
+ fdod = RCBA32(0x38b4);
+ fdod >>= 24;
+ fdod &= 7;
+
+ /* Set Software Sequence frequency to match */
+ ssfc = RCBA8(0x3893);
+ ssfc &= ~7;
+ ssfc |= fdod;
+ RCBA8(0x3893) = ssfc;
+}
+
static void bootblock_southbridge_init(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
@@ -72,4 +92,8 @@
#endif
enable_spi_prefetch();
enable_port80_on_lpc();
+ set_spi_speed();
+
+ /* Enable upper 128bytes of CMOS */
+ RCBA32(RC) = (1 << 2);
}
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 880244b..6073eb8 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -67,6 +67,8 @@
uint32_t ide_legacy_combined;
uint32_t sata_ahci;
uint8_t sata_port_map;
+ uint32_t sata_port0_gen3_tx;
+ uint32_t sata_port1_gen3_tx;
uint32_t gen1_dec;
uint32_t gen2_dec;
@@ -75,6 +77,16 @@
/* Enable linear PCIe Root Port function numbers starting at zero */
uint8_t pcie_port_coalesce;
+
+ /* Override PCIe ASPM */
+ uint8_t pcie_aspm_f0;
+ uint8_t pcie_aspm_f1;
+ uint8_t pcie_aspm_f2;
+ uint8_t pcie_aspm_f3;
+ uint8_t pcie_aspm_f4;
+ uint8_t pcie_aspm_f5;
+ uint8_t pcie_aspm_f6;
+ uint8_t pcie_aspm_f7;
};
extern struct chip_operations southbridge_intel_bd82x6x_ops;
diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c
new file mode 100644
index 0000000..09dfcdb
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/elog.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#include <stdint.h>
+#include <string.h>
+#include <elog.h>
+#include "pch.h"
+
+void pch_log_state(void)
+{
+ u16 pm1_sts, gen_pmcon_3, tco2_sts;
+ u32 gpe0_sts, gpe0_en;
+ u8 gen_pmcon_2;
+ int i;
+ struct device *lpc = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+ if (!lpc)
+ return;
+
+ pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+ gpe0_sts = inl(DEFAULT_PMBASE + GPE0_STS);
+ gpe0_en = inl(DEFAULT_PMBASE + GPE0_EN);
+ tco2_sts = inw(DEFAULT_PMBASE + TCO2_STS);
+ gen_pmcon_2 = pci_read_config8(lpc, GEN_PMCON_2);
+ gen_pmcon_3 = pci_read_config16(lpc, GEN_PMCON_3);
+
+ /* PWR_FLR Power Failure */
+ if (gen_pmcon_2 & (1 << 0))
+ elog_add_event(ELOG_TYPE_POWER_FAIL);
+
+ /* SUS Well Power Failure */
+ if (gen_pmcon_3 & (1 << 14))
+ elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
+
+ /* SYS_PWROK Failure */
+ if (gen_pmcon_2 & (1 << 1))
+ elog_add_event(ELOG_TYPE_SYS_PWROK_FAIL);
+
+ /* PWROK Failure */
+ if (gen_pmcon_2 & (1 << 0))
+ elog_add_event(ELOG_TYPE_PWROK_FAIL);
+
+ /* Second TCO Timeout */
+ if (tco2_sts & (1 << 1))
+ elog_add_event(ELOG_TYPE_TCO_RESET);
+
+ /* Power Button Override */
+ if (pm1_sts & (1 << 11))
+ elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
+
+ /* System Reset Status (reset button pushed) */
+ if (gen_pmcon_2 & (1 << 4))
+ elog_add_event(ELOG_TYPE_RESET_BUTTON);
+
+ /* General Reset Status */
+ if (gen_pmcon_3 & (1 << 9))
+ elog_add_event(ELOG_TYPE_SYSTEM_RESET);
+
+ /* ACPI Wake */
+ if (pm1_sts & (1 << 15))
+ elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
+ acpi_slp_type == 3 ? 3 : 5);
+
+ /*
+ * Wake sources
+ */
+
+ /* RTC */
+ if (pm1_sts & (1 << 10))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0);
+
+ /* PCI Express (TODO: determine wake device) */
+ if (pm1_sts & (1 << 14))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0);
+
+ /* PME (TODO: determine wake device) */
+ if (gpe0_sts & (1 << 13))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME, 0);
+
+ /* Internal PME (TODO: determine wake device) */
+ if (gpe0_sts & (1 << 13))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
+
+ /* GPIO 0-15 */
+ for (i = 0; i < 16; i++) {
+ if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i))))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i);
+ }
+
+ /* SMBUS Wake */
+ if (gpe0_sts & (1 << 7))
+ elog_add_event_wake(ELOG_WAKE_SOURCE_SMBUS, 0);
+}
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
index ed1ebf7..228258d 100644
--- a/src/southbridge/intel/bd82x6x/finalize.c
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -20,8 +20,10 @@
#include <arch/io.h>
#include <arch/romcc_io.h>
+#include <console/post_codes.h>
#include <northbridge/intel/sandybridge/pcie_config.c>
#include "pch.h"
+#include "spi.h"
void intel_pch_finalize_smm(void)
{
@@ -31,8 +33,14 @@
RCBA32(0x3898) = SPI_OPMENU_LOWER;
RCBA32(0x389c) = SPI_OPMENU_UPPER;
+/* Need to fix SMI driver use of opcode menu */
+#if !CONFIG_ELOG_GSMI
/* Lock SPIBAR */
RCBA32_OR(0x3804, (1 << 15));
+#endif
+
+ /* Re-init SPI driver to handle locked BAR */
+ spi_init();
/* TCLOCKDN: TC Lockdown */
RCBA32_OR(0x0050, (1 << 31));
@@ -53,4 +61,7 @@
RCBA32(0x21a4) = RCBA32(0x21a4);
pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+
+ /* Indicate finalize step with post code */
+ outb(POST_OS_BOOT, 0x80);
}
diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c
index 598726a..25eda9a 100644
--- a/src/southbridge/intel/bd82x6x/gpio.c
+++ b/src/southbridge/intel/bd82x6x/gpio.c
@@ -25,6 +25,8 @@
#include "pch.h"
#include "gpio.h"
+#define MAX_GPIO_NUMBER 75 /* zero based */
+
void setup_pch_gpios(const struct pch_gpio_map *gpio)
{
u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
@@ -63,3 +65,37 @@
if (gpio->set3.reset)
outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);
}
+
+int get_gpio(int gpio_num)
+{
+ static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48};
+ u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+ int index, bit;
+
+ if (gpio_num > MAX_GPIO_NUMBER)
+ return 0; /* Just ignore wrong gpio numbers. */
+
+ index = gpio_num / 32;
+ bit = gpio_num % 32;
+
+ return (inl(gpio_base + gpio_reg_offsets[index]) >> bit) & 1;
+}
+
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array)
+{
+ int gpio;
+ unsigned bitmask = 1;
+ unsigned vector = 0;
+
+ while (bitmask &&
+ ((gpio = *gpio_num_array++) != -1)) {
+ if (get_gpio(gpio))
+ vector |= bitmask;
+ bitmask <<= 1;
+ }
+ return vector;
+}
diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h
index 214947f..44e808a 100644
--- a/src/southbridge/intel/bd82x6x/gpio.h
+++ b/src/southbridge/intel/bd82x6x/gpio.h
@@ -150,4 +150,12 @@
/* Configure GPIOs with mainboard provided settings */
void setup_pch_gpios(const struct pch_gpio_map *gpio);
+/* get GPIO pin value */
+int get_gpio(int gpio_num);
+/*
+ * get a number comprised of multiple GPIO values. gpio_num_array points to
+ * the array of gpio pin numbers to scan, terminated by -1.
+ */
+unsigned get_gpios(const int *gpio_num_array);
+
#endif
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index dddab6a..592f5de 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -29,6 +29,7 @@
#include <arch/ioapic.h>
#include <arch/acpi.h>
#include <cpu/cpu.h>
+#include <elog.h>
#include "pch.h"
#define NMI_OFF 0
@@ -296,14 +297,19 @@
if (rtc_failed) {
reg8 &= ~RTC_BATTERY_DEAD;
pci_write_config8(dev, GEN_PMCON_3, reg8);
+#if CONFIG_ELOG
+ elog_add_event(ELOG_TYPE_RTC_RESET);
+#endif
}
printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
rtc_init(rtc_failed);
}
-static void pch_pm_init(struct device *dev)
+/* CougarPoint PCH Power Management init */
+static void cpt_pm_init(struct device *dev)
{
+ printk(BIOS_DEBUG, "CougarPoint PM init\n");
pci_write_config8(dev, 0xa9, 0x47);
RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
@@ -342,6 +348,49 @@
RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
}
+/* PantherPoint PCH Power Management init */
+static void ppt_pm_init(struct device *dev)
+{
+ printk(BIOS_DEBUG, "PantherPoint PM init\n");
+ pci_write_config8(dev, 0xa9, 0x47);
+ RCBA32_AND_OR(0x2238, ~0UL, (1 << 0));
+ RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
+ RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
+ RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
+ RCBA32(0x2304) = 0xc03b8400;
+ RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
+ RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
+ RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
+ RCBA32(0x3318) = 0x054f0000;
+ RCBA32(0x3324) = 0x04000000;
+ RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
+ RCBA32_AND_OR(0x3344, ~0UL, (1 << 1)|(1 << 0));
+ RCBA32(0x3360) = 0x0001c000;
+ RCBA32(0x3368) = 0x00061100;
+ RCBA32(0x3378) = 0x7f8fdfff;
+ RCBA32(0x337c) = 0x000003fd;
+ RCBA32(0x3388) = 0x00001000;
+ RCBA32(0x3390) = 0x0001c000;
+ RCBA32(0x33a0) = 0x00000800;
+ RCBA32(0x33b0) = 0x00001000;
+ RCBA32(0x33c0) = 0x00093900;
+ RCBA32(0x33cc) = 0x24653002;
+ RCBA32(0x33d0) = 0x067388fe;
+ RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
+ RCBA32(0x3a28) = 0x01010000;
+ RCBA32(0x3a2c) = 0x01010404;
+ RCBA32(0x3a80) = 0x01040000;
+ RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
+ RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
+ RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0)); /* SATA 4/5 disabled */
+ RCBA32(0x3a6c) = 0x00000001;
+ RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
+ RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
+ RCBA32_AND_OR(0x33a4, ~0UL, (1 << 0));
+ RCBA32(0x33c8) = 0;
+ RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
+}
+
static void enable_hpet(void)
{
u32 reg32;
@@ -500,7 +549,16 @@
pch_power_options(dev);
/* Initialize power management */
- pch_pm_init(dev);
+ switch (pch_silicon_type()) {
+ case PCH_TYPE_CPT: /* CougarPoint */
+ cpt_pm_init(dev);
+ break;
+ case PCH_TYPE_PPT: /* PantherPoint */
+ ppt_pm_init(dev);
+ break;
+ default:
+ printk(BIOS_ERR, "Unknown Chipset: 0x%04x\n", dev->device);
+ }
/* Set the state of the GPIO lines. */
//gpio_init(dev);
@@ -535,18 +593,20 @@
static void pch_lpc_read_resources(device_t dev)
{
struct resource *res;
+ config_t *config = dev->chip_info;
+ u8 io_index = 0;
/* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O. */
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
- res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
@@ -556,6 +616,39 @@
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+ /* Set PCH IO decode ranges if required.*/
+ if ((config->gen1_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen1_dec & 0xFFFC;
+ res->size = (config->gen1_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+
+ if ((config->gen2_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen2_dec & 0xFFFC;
+ res->size = (config->gen2_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+
+ if ((config->gen3_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen3_dec & 0xFFFC;
+ res->size = (config->gen3_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
+
+ if ((config->gen4_dec & 0xFFFC) > 0x1000) {
+ res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
+ res->base = config->gen4_dec & 0xFFFC;
+ res->size = (config->gen4_dec >> 16) & 0xFC;
+ res->flags = IORESOURCE_IO| IORESOURCE_SUBTRACTIVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+ }
}
static void pch_lpc_enable_resources(device_t dev)
@@ -599,88 +692,21 @@
};
-/* IDs for LPC device of Intel 6 series Chipset and
- * Intel C200 Series Chipset according to specification
- * update from August 2011
+/* IDs for LPC device of Intel 6 Series Chipset, Intel 7 Series Chipset, and
+ * Intel C200 Series Chipset
*/
-static const struct pci_driver q67_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c4e,
+static const unsigned short pci_device_ids[] = { 0x1c46, 0x1c47, 0x1c49, 0x1c4a,
+ 0x1c4b, 0x1c4c, 0x1c4d, 0x1c4e,
+ 0x1c4f, 0x1c50, 0x1c52, 0x1c54,
+ 0x1e55, 0x1c56, 0x1e57, 0x1c5c,
+ 0x1e5d, 0x1e5e, 0x1e5f,
+ 0 };
+
+static const struct pci_driver pch_lpc __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
};
-static const struct pci_driver q65_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c4c,
-};
-static const struct pci_driver b65_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c50,
-};
-static const struct pci_driver h67_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c4a,
-};
-static const struct pci_driver z68_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c46,
-};
-static const struct pci_driver h61_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c5c,
-};
-static const struct pci_driver c202_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c52,
-};
-static const struct pci_driver c204_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c54,
-};
-static const struct pci_driver c206_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c56,
-};
-static const struct pci_driver qm67_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c4f,
-};
-static const struct pci_driver um67_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c47,
-};
-static const struct pci_driver hm67_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c4b,
-};
-static const struct pci_driver hm65_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c49,
-};
-static const struct pci_driver qs67_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c4d,
-};
-static const struct pci_driver c216_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e55,
-};
-static const struct pci_driver hm75_lpc __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e5d,
-};
+
+
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
index a1ae06d..b9aff37 100644
--- a/src/southbridge/intel/bd82x6x/me.c
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -35,6 +35,7 @@
#include <device/pci_def.h>
#include <string.h>
#include <delay.h>
+#include <elog.h>
#ifdef __SMM__
# include <arch/romcc_io.h>
@@ -353,8 +354,9 @@
return 0;
}
+#ifdef __SMM__
/* Send END OF POST message to the ME */
-int mkhi_end_of_post(void)
+static int mkhi_end_of_post(void)
{
struct mkhi_header mkhi = {
.group_id = MKHI_GROUP_ID_GEN,
@@ -376,6 +378,7 @@
printk(BIOS_INFO, "ME: END OF POST message successful\n");
return 0;
}
+#endif
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__)
/* Get ME firmware version */
@@ -460,6 +463,7 @@
}
#endif
+#if CONFIG_CHROMEOS && 0 /* DISABLED */
/* Tell ME to issue a global reset */
int mkhi_global_reset(void)
{
@@ -490,10 +494,10 @@
printk(BIOS_ERR, "ME: Global Reset failed\n");
return -1;
}
+#endif
#ifdef __SMM__
-
-void intel_me_finalize_smm(void)
+static void intel_me7_finalize_smm(void)
{
struct me_hfs hfs;
u32 reg32;
@@ -528,6 +532,20 @@
RCBA32_OR(FD2, PCH_DISABLE_MEI1);
}
+void intel_me_finalize_smm(void)
+{
+ u32 did = pcie_read_config32(PCH_ME_DEV, PCI_VENDOR_ID);
+ switch (did) {
+ case 0x1c3a8086:
+ intel_me7_finalize_smm();
+ break;
+ case 0x1e3a8086:
+ intel_me8_finalize_smm();
+ break;
+ default:
+ printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did);
+ }
+}
#else /* !__SMM__ */
/* Determine the path that we should take based on ME status */
@@ -550,10 +568,6 @@
/* Check and dump status */
intel_me_status(&hfs, &gmes);
- /* Check for valid firmware */
- if (hfs.fpt_bad)
- return ME_ERROR_BIOS_PATH;
-
/* Check Current Working State */
switch (hfs.working_state) {
case ME_HFS_CWS_NORMAL:
@@ -580,10 +594,27 @@
break;
}
- /* Check for any error code */
- if (hfs.error_code)
+ /* Check for any error code and valid firmware */
+ if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
+#if CONFIG_ELOG
+ if (path != ME_NORMAL_BIOS_PATH) {
+ struct elog_event_data_me_extended data = {
+ .current_working_state = hfs.working_state,
+ .operation_state = hfs.operation_state,
+ .operation_mode = hfs.operation_mode,
+ .error_code = hfs.error_code,
+ .progress_code = gmes.progress_code,
+ .current_pmevent = gmes.current_pmevent,
+ .current_state = gmes.current_state,
+ };
+ elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path);
+ elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT,
+ &data, sizeof(data));
+ }
+#endif
+
return path;
}
@@ -621,7 +652,7 @@
static int intel_me_extend_valid(device_t dev)
{
struct me_heres status;
- u32 extend[] = {0};
+ u32 extend[8] = {0};
int i, count = 0;
pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
@@ -710,9 +741,6 @@
case ME_RECOVERY_BIOS_PATH:
case ME_DISABLE_BIOS_PATH:
case ME_FIRMWARE_UPDATE_BIOS_PATH:
- /*
- * TODO(dlaurie) Force recovery mode if ME is unhappy?
- */
break;
}
}
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
index 53964a2..aaeb24d 100644
--- a/src/southbridge/intel/bd82x6x/me.h
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -248,14 +248,11 @@
int intel_early_me_init(void);
int intel_early_me_uma_size(void);
int intel_early_me_init_done(u8 status);
-#else
-/* ME Kernel Host Interface Messages */
-int mkhi_end_of_post(void);
-int mkhi_global_reset(void);
#endif
#ifdef __SMM__
void intel_me_finalize_smm(void);
+void intel_me8_finalize_smm(void);
#endif
typedef struct {
u32 major_version : 16;
diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c
index 1bb2ce3..b71f7ea 100644
--- a/src/southbridge/intel/bd82x6x/me_8.x.c
+++ b/src/southbridge/intel/bd82x6x/me_8.x.c
@@ -35,6 +35,7 @@
#include <device/pci_def.h>
#include <string.h>
#include <delay.h>
+#include <elog.h>
#ifdef __SMM__
# include <arch/romcc_io.h>
@@ -49,6 +50,7 @@
#if CONFIG_CHROMEOS
#include <vendorcode/google/chromeos/chromeos.h>
+#include <vendorcode/google/chromeos/gnvs.h>
#endif
#ifndef __SMM__
@@ -355,33 +357,6 @@
return 0;
}
-/* Send END OF POST message to the ME */
-int mkhi_end_of_post(void)
-{
- struct mkhi_header mkhi = {
- .group_id = MKHI_GROUP_ID_GEN,
- .command = MKHI_END_OF_POST,
- };
- struct mei_header mei = {
- .is_complete = 1,
- .host_address = MEI_HOST_ADDRESS,
- .client_address = MEI_ADDRESS_MKHI,
- .length = sizeof(mkhi),
- };
-
- u32 eop_ack;
-
- /* Send request and wait for response */
- printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
- if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) {
- printk(BIOS_ERR, "ME: END OF POST message failed\n");
- return -1;
- }
-
- printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack);
- return 0;
-}
-
#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__)
static inline void print_cap(const char *name, int state)
{
@@ -456,8 +431,9 @@
}
#endif
+#if CONFIG_CHROMEOS && 0 /* DISABLED */
/* Tell ME to issue a global reset */
-int mkhi_global_reset(void)
+static int mkhi_global_reset(void)
{
struct me_global_reset reset = {
.request_origin = GLOBAL_RESET_BIOS_POST,
@@ -485,10 +461,38 @@
printk(BIOS_ERR, "ME: Global Reset failed\n");
return -1;
}
+#endif
#ifdef __SMM__
-void intel_me_finalize_smm(void)
+/* Send END OF POST message to the ME */
+static int mkhi_end_of_post(void)
+{
+ struct mkhi_header mkhi = {
+ .group_id = MKHI_GROUP_ID_GEN,
+ .command = MKHI_END_OF_POST,
+ };
+ struct mei_header mei = {
+ .is_complete = 1,
+ .host_address = MEI_HOST_ADDRESS,
+ .client_address = MEI_ADDRESS_MKHI,
+ .length = sizeof(mkhi),
+ };
+
+ u32 eop_ack;
+
+ /* Send request and wait for response */
+ printk(BIOS_NOTICE, "ME: %s\n", __FUNCTION__);
+ if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) {
+ printk(BIOS_ERR, "ME: END OF POST message failed\n");
+ return -1;
+ }
+
+ printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack);
+ return 0;
+}
+
+void intel_me8_finalize_smm(void)
{
struct me_hfs hfs;
u32 reg32;
@@ -545,20 +549,10 @@
/* Check and dump status */
intel_me_status(&hfs, &gmes);
- /* Check for valid firmware */
- if (hfs.fpt_bad)
- return ME_ERROR_BIOS_PATH;
-
/* Check Current Working State */
switch (hfs.working_state) {
case ME_HFS_CWS_NORMAL:
path = ME_NORMAL_BIOS_PATH;
- /* check if the MBP is ready */
- if (!gmes.mbp_rdy) {
- printk(BIOS_CRIT, "%s: mbp is not ready!\n",
- __FUNCTION__);
- return ME_ERROR_BIOS_PATH;
- }
break;
case ME_HFS_CWS_REC:
path = ME_RECOVERY_BIOS_PATH;
@@ -581,10 +575,34 @@
break;
}
- /* Check for any error code */
- if (hfs.error_code)
+ /* Check for any error code and valid firmware and MBP */
+ if (hfs.error_code || hfs.fpt_bad)
path = ME_ERROR_BIOS_PATH;
+ /* Check if the MBP is ready */
+ if (!gmes.mbp_rdy) {
+ printk(BIOS_CRIT, "%s: mbp is not ready!\n",
+ __FUNCTION__);
+ path = ME_ERROR_BIOS_PATH;
+ }
+
+#if CONFIG_ELOG
+ if (path != ME_NORMAL_BIOS_PATH) {
+ struct elog_event_data_me_extended data = {
+ .current_working_state = hfs.working_state,
+ .operation_state = hfs.operation_state,
+ .operation_mode = hfs.operation_mode,
+ .error_code = hfs.error_code,
+ .progress_code = gmes.progress_code,
+ .current_pmevent = gmes.current_pmevent,
+ .current_state = gmes.current_state,
+ };
+ elog_add_event_byte(ELOG_TYPE_MANAGEMENT_ENGINE, path);
+ elog_add_event_raw(ELOG_TYPE_MANAGEMENT_ENGINE_EXT,
+ &data, sizeof(data));
+ }
+#endif
+
return path;
}
@@ -622,7 +640,7 @@
static int intel_me_extend_valid(device_t dev)
{
struct me_heres status;
- u32 extend;
+ u32 extend[8] = {0};
int i, count = 0;
pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
@@ -651,16 +669,17 @@
return -1;
}
- /*
- * TODO(dlaurie) Verify the hash against a saved good value.
- */
-
for (i = 0; i < count; ++i) {
- extend = pci_read_config32(dev, PCI_ME_HER(i));
- printk(BIOS_DEBUG, "%08x", extend);
+ extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
+ printk(BIOS_DEBUG, "%08x", extend[i]);
}
printk(BIOS_DEBUG, "\n");
+#if CONFIG_CHROMEOS
+ /* Save hash in NVS for the OS to verify */
+ chromeos_set_me_hash(extend, count);
+#endif
+
return 0;
}
@@ -715,19 +734,17 @@
me_print_fw_version(&mbp_data.fw_version_name);
me_print_fwcaps(&mbp_data.fw_caps_sku);
#endif
- /* Tell ME that BIOS is done */
- mkhi_end_of_post();
- /* Hide the virtual PCI device */
- intel_me_hide(dev);
+
+ /*
+ * Leave the ME unlocked in this path.
+ * It will be locked via SMI command later.
+ */
break;
case ME_ERROR_BIOS_PATH:
case ME_RECOVERY_BIOS_PATH:
case ME_DISABLE_BIOS_PATH:
case ME_FIRMWARE_UPDATE_BIOS_PATH:
- /*
- * TODO(dlaurie) Force recovery mode if ME is unhappy?
- */
break;
}
}
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
index 3928804..385dc64 100644
--- a/src/southbridge/intel/bd82x6x/nvs.h
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -55,7 +55,8 @@
u8 f4of; /* 0x22 - FAN 4 OFF Threshold */
u8 f4on; /* 0x23 - FAN 4 ON Threshold */
u8 f4pw; /* 0x24 - FAN 4 PWM value */
- u8 rsvd3[3];
+ u8 tmps; /* 0x25 - Temperature Sensor ID */
+ u8 rsvd3[2];
/* Processor Identification */
u8 apic; /* 0x28 - APIC enabled */
u8 mpen; /* 0x29 - MP capable/enabled */
@@ -137,3 +138,7 @@
chromeos_acpi_t chromeos;
} __attribute__((packed)) global_nvs_t;
+#ifdef __SMM__
+/* Used in SMM to find the ACPI GNVS address */
+global_nvs_t *smm_get_gnvs(void);
+#endif
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
index 5f440e6..d8a919d 100644
--- a/src/southbridge/intel/bd82x6x/pch.c
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -297,6 +297,8 @@
}
if (!dev->enabled) {
+ printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
+
/*
* PCIE Power Savings for PantherPoint and CougarPoint/B1+
*
@@ -403,6 +405,6 @@
}
struct chip_operations southbridge_intel_bd82x6x_ops = {
- CHIP_NAME("Intel Series 6 (" CONFIG_PCH_CHIP_NAME ") Southbridge")
+ CHIP_NAME("Intel Series 6/7 (Cougar Point/Panther Point) Southbridge")
.enable_dev = pch_enable,
};
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
index 7b646f3..00c0703 100644
--- a/src/southbridge/intel/bd82x6x/pch.h
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -65,6 +65,9 @@
int pch_silicon_supported(int type, int rev);
void pch_enable(device_t dev);
void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+#if CONFIG_ELOG
+void pch_log_state(void);
+#endif
#else
void enable_smbus(void);
void enable_usb_bar(void);
@@ -193,8 +196,14 @@
#define PCB1 (1 << 1)
#define PCB0 (1 << 0)
+#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
+#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
#define SATA_SP 0xd0 /* Scratchpad */
+/* SATA IOBP Registers */
+#define SATA_IOBP_SP0G3IR 0xea000151
+#define SATA_IOBP_SP1G3IR 0xea000051
+
/* PCI Configuration Space (D31:F3): SMBus */
#define PCH_SMBUS_DEV PCI_DEV(0, 0x1f, 3)
#define SMB_BASE 0x20
@@ -365,6 +374,8 @@
#define D25IR 0x3150 /* 16bit */
#define D22IR 0x315c /* 16bit */
#define OIC 0x31fe /* 16bit */
+#define SOFT_RESET_CTRL 0x38f4
+#define SOFT_RESET_DATA 0x38f8
#define DIR_ROUTE(x,a,b,c,d) \
RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
@@ -483,6 +494,8 @@
#define DEVACT_STS 0x44
#define SS_CNT 0x50
#define C3_RES 0x54
+#define TCO1_STS 0x64
+#define TCO2_STS 0x66
/*
* SPI Opcode Menu setup for SPIBAR lockdown
@@ -510,8 +523,8 @@
#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
#define SPI_OPTYPE_6 0x03 /* Write, address required */
-#define SPI_OPMENU_7 0x52 /* BE52: Block Erase 0x52 */
-#define SPI_OPTYPE_7 0x03 /* Write, address required */
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
(SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
index 5ab18f6..6ae197a 100644
--- a/src/southbridge/intel/bd82x6x/pcie.c
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -134,7 +134,8 @@
static void pch_pcie_pm_late(struct device *dev)
{
- enum aspm_type apmc;
+ struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
+ enum aspm_type apmc = 0;
u32 reg32;
/* Set 0x314 = 0x743a361b */
@@ -168,8 +169,42 @@
reg32 |= (1 << 1);
pci_write_config32(dev, 0xd4, reg32);
- /* Get configured ASPM state */
- apmc = pci_read_config32(dev, 0x50) & 3;
+ /* Check for a rootport ASPM override */
+ switch (PCI_FUNC(dev->path.pci.devfn)) {
+ case 0:
+ apmc = config->pcie_aspm_f0;
+ break;
+ case 1:
+ apmc = config->pcie_aspm_f1;
+ break;
+ case 2:
+ apmc = config->pcie_aspm_f2;
+ break;
+ case 3:
+ apmc = config->pcie_aspm_f3;
+ break;
+ case 4:
+ apmc = config->pcie_aspm_f4;
+ break;
+ case 5:
+ apmc = config->pcie_aspm_f5;
+ break;
+ case 6:
+ apmc = config->pcie_aspm_f6;
+ break;
+ case 7:
+ apmc = config->pcie_aspm_f7;
+ break;
+ }
+
+ /* Setup the override or get the real ASPM setting */
+ if (apmc) {
+ reg32 = pci_read_config32(dev, 0xd4);
+ reg32 |= (apmc << 2) | (1 << 4);
+ pci_write_config32(dev, 0xd4, reg32);
+ } else {
+ apmc = pci_read_config32(dev, 0x50) & 3;
+ }
/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
if (apmc == PCIE_ASPM_BOTH) {
@@ -220,9 +255,6 @@
reg16 = pci_read_config16(dev, 0x1e);
//reg16 |= 0xf900;
pci_write_config16(dev, 0x1e, reg16);
-
- /* Power Management init after enumeration */
- pch_pcie_pm_late(dev);
}
static void pch_pcie_enable(device_t dev)
@@ -231,6 +263,19 @@
pch_pcie_pm_early(dev);
}
+static unsigned int pch_pciexp_scan_bridge(device_t dev, unsigned int max)
+{
+ unsigned int ret;
+
+ /* Normal PCIe Scan */
+ ret = pciexp_scan_bridge(dev, max);
+
+ /* Late Power Management init after bridge device enumeration */
+ pch_pcie_pm_late(dev);
+
+ return ret;
+}
+
static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
{
/* NOTE: This is not the default position! */
@@ -253,72 +298,18 @@
.enable_resources = pci_bus_enable_resources,
.init = pci_init,
.enable = pch_pcie_enable,
- .scan_bus = pciexp_scan_bridge,
+ .scan_bus = pch_pciexp_scan_bridge,
.ops_pci = &pci_ops,
};
-static const struct pci_driver pch_pcie_port1 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c10, /* D28:F0 */
-};
+static const unsigned short pci_device_ids[] = { 0x1c10, 0x1c12, 0x1c14, 0x1c16,
+ 0x1c18, 0x1c1a, 0x1c1c, 0x1c1e,
+ 0x1e10, 0x1e12, 0x1e14, 0x1e16,
+ 0x1e18, 0x1e1a, 0x1e1c, 0x1e1e,
+ 0 };
-static const struct pci_driver pch_pcie_port1_a __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e10, /* D28:F0 */
-};
-
-static const struct pci_driver pch_pcie_port2 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c12, /* D28:F1 */
-};
-
-static const struct pci_driver pch_pcie_port3 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c14, /* D28:F2 */
-};
-
-static const struct pci_driver pch_pcie_port3_a __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e14, /* D28:F2 */
-};
-
-static const struct pci_driver pch_pcie_port4 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c16, /* D28:F3 */
-};
-
-static const struct pci_driver pch_pcie_port4_a __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e16, /* D28:F3 */
-};
-
-static const struct pci_driver pch_pcie_port5 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c18, /* D28:F4 */
-};
-
-static const struct pci_driver pch_pcie_port6 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c1a, /* D28:F5 */
-};
-
-static const struct pci_driver pch_pcie_port7 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c1c, /* D28:F6 */
-};
-
-static const struct pci_driver pch_pcie_port8 __pci_driver = {
- .ops = &device_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c1e, /* D28:F7 */
+static const struct pci_driver pch_pcie __pci_driver = {
+ .ops = &device_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
};
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
index 29b69ff..5324142 100644
--- a/src/southbridge/intel/bd82x6x/reset.c
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -26,16 +26,7 @@
outb(0x04, 0xcf9);
}
-#if 0
void hard_reset(void)
{
- /* Try rebooting through port 0xcf9. */
- outb((1 << 2) | (1 << 1), 0xcf9);
-}
-#endif
-
-void hard_reset(void)
-{
- outb(0x02, 0xcf9);
outb(0x06, 0xcf9);
}
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
index 431a29b..fb29d73 100644
--- a/src/southbridge/intel/bd82x6x/sata.c
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -27,6 +27,18 @@
typedef struct southbridge_intel_bd82x6x_config config_t;
+static inline u32 sir_read(struct device *dev, int idx)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ return pci_read_config32(dev, SATA_SIRD);
+}
+
+static inline void sir_write(struct device *dev, int idx, u32 value)
+{
+ pci_write_config32(dev, SATA_SIRI, idx);
+ pci_write_config32(dev, SATA_SIRD, value);
+}
+
static void sata_init(struct device *dev)
{
u32 reg32;
@@ -34,10 +46,10 @@
/* Get the chip configuration */
config_t *config = dev->chip_info;
- printk(BIOS_DEBUG, "pch_sata: initializing...\n");
+ printk(BIOS_DEBUG, "SATA: Initializing...\n");
if (config == NULL) {
- printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n");
+ printk(BIOS_ERR, "SATA: ERROR: Device not in devicetree.cb!\n");
return;
}
@@ -47,7 +59,7 @@
pci_write_config16(dev, PCI_COMMAND, 0x0007);
if (config->ide_legacy_combined) {
- printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
+ printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n");
/* No AHCI: clear AHCI base */
pci_write_config32(dev, 0x24, 0x00000000);
@@ -85,7 +97,7 @@
} else if(config->sata_ahci) {
u32 abar;
- printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
+ printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n");
/* Set Interrupt Line */
/* Interrupt Pin is set by D31IP.PIP */
@@ -137,7 +149,7 @@
reg32 &= ~0x00000005;
write32(abar + 0xa0, reg32);
} else {
- printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
+ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n");
/* No AHCI: clear AHCI base */
pci_write_config32(dev, 0x24, 0x00000000);
@@ -182,6 +194,42 @@
pci_write_config32(dev, 0x94,
((config->sata_port_map ^ 0x3f) << 24) | 0x183);
}
+
+ /* Set Gen3 Transmitter settings if needed */
+ if (config->sata_port0_gen3_tx)
+ pch_iobp_update(SATA_IOBP_SP0G3IR, 0,
+ config->sata_port0_gen3_tx);
+
+ if (config->sata_port1_gen3_tx)
+ pch_iobp_update(SATA_IOBP_SP1G3IR, 0,
+ config->sata_port1_gen3_tx);
+
+ /* Additional Programming Requirements */
+ sir_write(dev, 0x04, 0x00001600);
+ sir_write(dev, 0x28, 0xa0000033);
+ reg32 = sir_read(dev, 0x54);
+ reg32 &= 0xff000000;
+ reg32 |= 0x5555aa;
+ sir_write(dev, 0x54, reg32);
+ sir_write(dev, 0x64, 0xcccc8484);
+ reg32 = sir_read(dev, 0x68);
+ reg32 &= 0xffff0000;
+ reg32 |= 0xcccc;
+ sir_write(dev, 0x68, reg32);
+ reg32 = sir_read(dev, 0x78);
+ reg32 &= 0x0000ffff;
+ reg32 |= 0x88880000;
+ sir_write(dev, 0x78, reg32);
+ sir_write(dev, 0x84, 0x001c7000);
+ sir_write(dev, 0x88, 0x88338822);
+ sir_write(dev, 0xa0, 0x001c7000);
+ // a4
+ sir_write(dev, 0xc4, 0x0c0c0c0c);
+ sir_write(dev, 0xc8, 0x0c0c0c0c);
+ sir_write(dev, 0xd4, 0x10000000);
+
+ pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
+ pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
}
static void sata_enable(device_t dev)
@@ -230,13 +278,13 @@
.ops_pci = &sata_pci_ops,
};
-static const unsigned short all_dev_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
- 0x1e00, 0x1e01, 0x1e02, 0x1e03,
- 0 };
-/* Non-AHCI and Non-RAID Mode */
-static const struct pci_driver pch_sata_normal_driver __pci_driver = {
- .ops = &sata_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .devices = all_dev_ids,
+static const unsigned short pci_device_ids[] = { 0x1c00, 0x1c01, 0x1c02, 0x1c03,
+ 0x1e00, 0x1e01, 0x1e02, 0x1e03,
+ 0 };
+
+static const struct pci_driver pch_sata __pci_driver = {
+ .ops = &sata_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
};
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index baa3cfb..4930685 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -100,14 +100,10 @@
.ops_pci = &smbus_pci_ops,
};
-static const struct pci_driver pch_smbus __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c22,
-};
+static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0 };
-static const struct pci_driver pch_smbus_a __pci_driver = {
- .ops = &smbus_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e22,
+static const struct pci_driver pch_smbus __pci_driver = {
+ .ops = &smbus_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
};
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
index da10840..c89ae18 100644
--- a/src/southbridge/intel/bd82x6x/smi.c
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -269,6 +269,11 @@
gpe0_en &= ~PME_B0_EN;
outl(gpe0_en, pmbase + GPE0_EN);
+ pm1_en = 0;
+ pm1_en |= PWRBTN_EN;
+ pm1_en |= GBL_EN;
+ outw(pm1_en, pmbase + PM1_EN);
+
/* Enable SMI generation:
* - on TCO events
* - on APMC writes (io 0xb2)
@@ -301,11 +306,6 @@
outl(smi_en, pmbase + SMI_EN);
- pm1_en = 0;
- pm1_en |= PWRBTN_EN;
- pm1_en |= GBL_EN;
- outw(pm1_en, pmbase + PM1_EN);
-
/**
* There are several methods of raising a controlled SMI# via
* software, among them:
@@ -370,6 +370,11 @@
void smm_init(void)
{
+#if CONFIG_ELOG
+ /* Log events from chipset before clearing */
+ pch_log_state();
+#endif
+
/* Put SMM code to 0xa0000 */
smm_install();
@@ -393,11 +398,19 @@
void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
{
- /* The GDT or coreboot table is going to live here. But a long time
- * after we relocated the GNVS, so this is not troublesome.
+ /*
+ * Issue SMI to set the gnvs pointer in SMM.
+ * tcg and smi1 are unused.
+ *
+ * EAX = APM_CNT_GNVS_UPDATE
+ * EBX = gnvs pointer
+ * EDX = APM_CNT
*/
- *(u32 *)0x500 = (u32)gnvs;
- *(u32 *)0x504 = (u32)tcg;
- *(u32 *)0x508 = (u32)smi1;
- outb(0xea, 0xb2);
+ asm volatile (
+ "outb %%al, %%dx\n\t"
+ : /* ignore result */
+ : "a" (APM_CNT_GNVS_UPDATE),
+ "b" ((u32)gnvs),
+ "d" (APM_CNT)
+ );
}
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
index d7690ba..804607c 100644
--- a/src/southbridge/intel/bd82x6x/smihandler.c
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -25,36 +25,55 @@
#include <arch/romcc_io.h>
#include <console/console.h>
#include <cpu/x86/cache.h>
-#include <cpu/x86/smm.h>
#include <device/pci_def.h>
#include <cpu/x86/smm.h>
+#include <elog.h>
+#include <pc80/mc146818rtc.h>
#include "pch.h"
#include "nvs.h"
+/* We are using PCIe accesses for now
+ * 1. the chipset can do it
+ * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
+ */
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/pcie_config.c>
+
/* While we read PMBASE dynamically in case it changed, let's
* initialize it with a sane value
*/
-u16 pmbase = DEFAULT_PMBASE;
-u8 smm_initialized = 0;
+static u16 pmbase = DEFAULT_PMBASE;
+u16 smm_get_pmbase(void)
+{
+ return pmbase;
+}
+
+static u8 smm_initialized = 0;
/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
* by coreboot.
*/
-global_nvs_t *gnvs = (global_nvs_t *)0x0;
-void *tcg = (void *)0x0;
-void *smi1 = (void *)0x0;
+static global_nvs_t *gnvs = (global_nvs_t *)0x0;
+global_nvs_t *smm_get_gnvs(void)
+{
+ return gnvs;
+}
#if CONFIG_SMM_TSEG
static u32 tseg_base = 0;
-static inline void tseg_fixup(void **ptr)
+u32 smi_get_tseg_base(void)
+{
+ if (!tseg_base)
+ tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
+ return tseg_base;
+}
+void tseg_relocate(void **ptr)
{
/* Adjust pointer with TSEG base */
- if (*ptr)
- *ptr = (void *)(((u8*)*ptr) + tseg_base);
+ if (*ptr && *ptr < (void*)smi_get_tseg_base())
+ *ptr = (void *)(((u8*)*ptr) + smi_get_tseg_base());
}
-#else
-#define tseg_fixup(x) do {} while(0)
#endif
/**
@@ -208,13 +227,6 @@
printk(BIOS_DEBUG, "\n");
}
-/* We are using PCIe accesses for now
- * 1. the chipset can do it
- * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind
- */
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/pcie_config.c>
-
int southbridge_io_trap_handler(int smif)
{
switch (smif) {
@@ -319,11 +331,16 @@
u8 reg8;
u32 reg32;
u8 slp_typ;
- /* FIXME: the power state on boot should be read from
- * CMOS or even better from GNVS. Right now it's hard
- * coded at compile time.
- */
u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+
+ // save and recover RTC port values
+ u8 tmp70, tmp72;
+ tmp70 = inb(0x70);
+ tmp72 = inb(0x72);
+ get_option(&s5pwr, "power_on_after_fail");
+ outb(tmp70, 0x70);
+ outb(tmp72, 0x72);
+
void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
/* First, disable further SMIs */
@@ -337,9 +354,15 @@
slp_typ = (reg32 >> 10) & 7;
/* Do any mainboard sleep handling */
- tseg_fixup((void **)&mainboard_sleep);
+ tseg_relocate((void **)&mainboard_sleep);
if (mainboard_sleep)
- mainboard_sleep(slp_typ);
+ mainboard_sleep(slp_typ-2);
+
+#if CONFIG_ELOG_GSMI
+ /* Log S3, S4, and S5 entry */
+ if (slp_typ >= 5)
+ elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ-2);
+#endif
/* Next, do the deed.
*/
@@ -362,16 +385,16 @@
outl(0, pmbase + GPE0_EN);
- /* Should we keep the power state after a power loss?
- * In case the setting is "ON" or "OFF" we don't have
- * to do anything. But if it's "KEEP" we have to switch
- * to "OFF" before entering S5.
+ /* Always set the flag in case CMOS was changed on runtime. For
+ * "KEEP", switch to "OFF" - KEEP is software emulated
*/
- if (s5pwr == MAINBOARD_POWER_KEEP) {
- reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ if (s5pwr == MAINBOARD_POWER_ON) {
+ reg8 &= ~1;
+ } else {
reg8 |= 1;
- pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
}
+ pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
/* also iterates over all bridges on bus 0 */
busmaster_disable_on_bus(0);
@@ -401,11 +424,73 @@
}
}
+/*
+ * Look for Synchronous IO SMI and use save state from that
+ * core in case we are not running on the same core that
+ * initiated the IO transaction.
+ */
+static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd)
+{
+ em64t101_smm_state_save_area_t *state;
+ u32 base = smi_get_tseg_base() + 0x8000 + 0x7d00;
+ int node;
+
+ /* Check all nodes looking for the one that issued the IO */
+ for (node = 0; node < CONFIG_MAX_CPUS; node++) {
+ state = (em64t101_smm_state_save_area_t *)
+ (base - (node * 0x400));
+
+ /* Check for Synchronous IO (bit0==1) */
+ if (!(state->io_misc_info & (1 << 0)))
+ continue;
+
+ /* Make sure it was a write (bit4==0) */
+ if (state->io_misc_info & (1 << 4))
+ continue;
+
+ /* Check for APMC IO port */
+ if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
+ continue;
+
+ /* Check AX against the requested command */
+ if ((state->rax & 0xff) != cmd)
+ continue;
+
+ return state;
+ }
+
+ return NULL;
+}
+
+#if CONFIG_ELOG_GSMI
+static void southbridge_smi_gsmi(void)
+{
+ u32 *ret, *param;
+ u8 sub_command;
+ em64t101_smm_state_save_area_t *io_smi =
+ smi_apmc_find_state_save(ELOG_GSMI_APM_CNT);
+
+ if (!io_smi)
+ return;
+
+ /* Command and return value in EAX */
+ ret = (u32*)&io_smi->rax;
+ sub_command = (u8)(*ret >> 8);
+
+ /* Parameter buffer in EBX */
+ param = (u32*)&io_smi->rbx;
+
+ /* drivers/elog/gsmi.c */
+ *ret = gsmi_exec(sub_command, param);
+}
+#endif
+
static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
{
u32 pmctrl;
u8 reg8;
int (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
+ em64t101_smm_state_save_area_t *state;
/* Emulate B2 register as the FADT / Linux expects it */
@@ -442,15 +527,22 @@
printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
return;
}
- gnvs = *(global_nvs_t **)0x500;
- tcg = *(void **)0x504;
- smi1 = *(void **)0x508;
- smm_initialized = 1;
- printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
+ state = smi_apmc_find_state_save(reg8);
+ if (state) {
+ /* EBX in the state save contains the GNVS pointer */
+ gnvs = (global_nvs_t *)((u32)state->rbx);
+ smm_initialized = 1;
+ printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs);
+ }
break;
+#if CONFIG_ELOG_GSMI
+ case ELOG_GSMI_APM_CNT:
+ southbridge_smi_gsmi();
+ break;
+#endif
}
- tseg_fixup((void **)&mainboard_apmc);
+ tseg_relocate((void **)&mainboard_apmc);
if (mainboard_apmc)
mainboard_apmc(reg8);
}
@@ -469,6 +561,9 @@
// power button pressed
u32 reg32;
reg32 = (7 << 10) | (1 << 13);
+#if CONFIG_ELOG_GSMI
+ elog_add_event(ELOG_TYPE_POWER_BUTTON);
+#endif
outl(reg32, pmbase + PM1_CNT);
}
}
@@ -490,7 +585,7 @@
reg16 &= inw(pmbase + ALT_GP_SMI_EN);
- tseg_fixup((void **)&mainboard_gpi);
+ tseg_relocate((void **)&mainboard_gpi);
if (mainboard_gpi) {
mainboard_gpi(reg16);
} else {
@@ -672,11 +767,6 @@
/* Update global variable pmbase */
pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
-#if CONFIG_SMM_TSEG
- /* Update global variable TSEG base */
- tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
-#endif
-
/* We need to clear the SMI status registers, or we won't see what's
* happening in the following calls.
*/
@@ -688,7 +778,8 @@
if (southbridge_smi[i]) {
#if CONFIG_SMM_TSEG
smi_handler_t handler = (smi_handler_t)
- ((u8*)southbridge_smi[i] + tseg_base);
+ ((u8*)southbridge_smi[i] +
+ smi_get_tseg_base());
if (handler)
handler(node, state_save);
#else
diff --git a/src/southbridge/intel/bd82x6x/spi.c b/src/southbridge/intel/bd82x6x/spi.c
index 2508a96..05649fc 100644
--- a/src/southbridge/intel/bd82x6x/spi.c
+++ b/src/southbridge/intel/bd82x6x/spi.c
@@ -27,20 +27,43 @@
#include <delay.h>
#include <arch/io.h>
#include <console/console.h>
-#include <device/pci.h>
#include <device/pci_ids.h>
#include <spi.h>
#define min(a, b) ((a)<(b)?(a):(b))
-typedef device_t pci_dev_t;
-#define pci_read_config_byte(dev, reg, targ) *(targ) = pci_read_config8(dev, reg)
-#define pci_read_config_word(dev, reg, targ) *(targ) = pci_read_config16(dev, reg)
-#define pci_read_config_dword(dev, reg, targ) *(targ) = pci_read_config32(dev, reg)
-#define pci_write_config_byte(dev, reg, val) pci_write_config8(dev, reg, val)
-#define pci_write_config_word(dev, reg, val) pci_write_config16(dev, reg, val)
-#define pci_write_config_dword(dev, reg, val) pci_write_config32(dev, reg, val)
+#ifdef __SMM__
+#include <arch/romcc_io.h>
+#include <northbridge/intel/sandybridge/pcie_config.c>
+#define pci_read_config_byte(dev, reg, targ)\
+ *(targ) = pcie_read_config8(dev, reg)
+#define pci_read_config_word(dev, reg, targ)\
+ *(targ) = pcie_read_config16(dev, reg)
+#define pci_read_config_dword(dev, reg, targ)\
+ *(targ) = pcie_read_config32(dev, reg)
+#define pci_write_config_byte(dev, reg, val)\
+ pcie_write_config8(dev, reg, val)
+#define pci_write_config_word(dev, reg, val)\
+ pcie_write_config16(dev, reg, val)
+#define pci_write_config_dword(dev, reg, val)\
+ pcie_write_config32(dev, reg, val)
+#else /* !__SMM__ */
+#include <device/device.h>
+#include <device/pci.h>
+#define pci_read_config_byte(dev, reg, targ)\
+ *(targ) = pci_read_config8(dev, reg)
+#define pci_read_config_word(dev, reg, targ)\
+ *(targ) = pci_read_config16(dev, reg)
+#define pci_read_config_dword(dev, reg, targ)\
+ *(targ) = pci_read_config32(dev, reg)
+#define pci_write_config_byte(dev, reg, val)\
+ pci_write_config8(dev, reg, val)
+#define pci_write_config_word(dev, reg, val)\
+ pci_write_config16(dev, reg, val)
+#define pci_write_config_dword(dev, reg, val)\
+ pci_write_config32(dev, reg, val)
+#endif /* !__SMM__ */
typedef struct spi_slave ich_spi_slave;
@@ -162,7 +185,7 @@
static u8 readb_(const void *addr)
{
- u8 v = readb(addr);
+ u8 v = read8((unsigned long)addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -170,7 +193,7 @@
static u16 readw_(const void *addr)
{
- u16 v = readw(addr);
+ u16 v = read16((unsigned long)addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -178,7 +201,7 @@
static u32 readl_(const void *addr)
{
- u32 v = readl(addr);
+ u32 v = read32((unsigned long)addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -186,21 +209,21 @@
static void writeb_(u8 b, const void *addr)
{
- writeb(b, addr);
+ write8((unsigned long)addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
- writew(b, addr);
+ write16((unsigned long)addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
- writel(b, addr);
+ write32((unsigned long)addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
@@ -280,17 +303,24 @@
return slave;
}
-void spi_free_slave(struct spi_slave *_slave)
+/*
+ * Check if this device ID matches one of supported Intel PCH devices.
+ *
+ * Return the ICH version if there is a match, or zero otherwise.
+ */
+static inline int get_ich_version(uint16_t device_id)
{
- ich_spi_slave *slave = (ich_spi_slave *)_slave;
- free(slave);
-}
+ if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC)
+ return 7;
-static inline int spi_is_cougarpoint_lpc(uint16_t device_id)
-{
- return device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
- device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX;
-};
+ if ((device_id >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
+ device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) ||
+ (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
+ device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX))
+ return 9;
+
+ return 0;
+}
void spi_init(void)
{
@@ -299,11 +329,15 @@
uint8_t *rcrb; /* Root Complex Register Block */
uint32_t rcba; /* Root Complex Base Address */
uint8_t bios_cntl;
- pci_dev_t dev;
+ device_t dev;
uint32_t ids;
uint16_t vendor_id, device_id;
+#ifdef __SMM__
+ dev = PCI_DEV(0, 31, 0);
+#else
dev = dev_find_slot(0, PCI_DEVFN(31, 0));
+#endif
pci_read_config_dword(dev, 0, &ids);
vendor_id = ids;
device_id = (ids >> 16);
@@ -313,11 +347,9 @@
return;
}
- if (device_id == PCI_DEVICE_ID_INTEL_TGP_LPC) {
- ich_version = 7;
- } else if (spi_is_cougarpoint_lpc(device_id)) {
- ich_version = 9;
- } else {
+ ich_version = get_ich_version(device_id);
+
+ if (!ich_version) {
printk(BIOS_DEBUG, "ICH SPI: No known ICH found.\n");
return;
}
@@ -452,6 +484,12 @@
if (trans->bytesout == 4) { /* and bytesin is > 0 */
trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
}
+
+ /* Fast read command is called with 5 bytes instead of 4 */
+ if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
+ trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
+ --trans->bytesout;
+ }
}
static int spi_setup_opcode(spi_transaction *trans)
@@ -473,6 +511,10 @@
uint8_t optype;
uint16_t opcode_index;
+ /* Write Enable is handled as atomic prefix */
+ if (trans->opcode == SPI_OPCODE_WREN)
+ return 0;
+
read_reg(cntlr.opmenu, opmenu, sizeof(opmenu));
for (opcode_index = 0; opcode_index < cntlr.menubytes;
opcode_index++) {
@@ -591,13 +633,14 @@
if ((with_address = spi_setup_offset(&trans)) < 0)
return -1;
- if (!ichspi_lock && trans.opcode == 0x06) {
+ if (trans.opcode == SPI_OPCODE_WREN) {
/*
* Treat Write Enable as Atomic Pre-Op if possible
* in order to prevent the Management Engine from
* issuing a transaction between WREN and DATA.
*/
- writew_(trans.opcode, cntlr.preop);
+ if (!ichspi_lock)
+ writew_(trans.opcode, cntlr.preop);
return 0;
}
@@ -609,6 +652,10 @@
control |= SPIC_ACS;
if (!trans.bytesout && !trans.bytesin) {
+ /* SPI addresses are 24 bit only */
+ if (with_address)
+ writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
+
/*
* This is a 'no data' command (like Write Enable), its
* bitesout size was 1, decremented to zero while executing
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
index c299535..76e8338 100644
--- a/src/southbridge/intel/bd82x6x/usb_ehci.c
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -102,23 +102,11 @@
.ops_pci = &lops_pci,
};
-static const struct pci_driver pch_usb_ehci1 __pci_driver = {
- .ops = &usb_ehci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c26,
-};
-static const struct pci_driver pch_usb_ehci2 __pci_driver = {
- .ops = &usb_ehci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1c2d,
-};
-static const struct pci_driver pch_usb_ehci3 __pci_driver = {
- .ops = &usb_ehci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e26,
-};
-static const struct pci_driver pch_usb_ehci4 __pci_driver = {
- .ops = &usb_ehci_ops,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x1e2d,
+static const unsigned short pci_device_ids[] = { 0x1c26, 0x1c2d, 0x1e26, 0x1e2d,
+ 0 };
+
+static const struct pci_driver pch_usb_ehci __pci_driver = {
+ .ops = &usb_ehci_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
};
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 179bbb1..24f4c11 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -57,4 +57,11 @@
default 0x00100000
depends on CHROMEOS_RAMOOPS
+config FLASHMAP_OFFSET
+ hex "Flash Map Offset"
+ default 0x00670000 if NORTHBRIDGE_INTEL_SANDYBRIDGE
+ default 0x00610000 if NORTHBRIDGE_INTEL_IVYBRIDGE
+ help
+ Offset of flash map in firmware image
+
endmenu
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
index c1b1cce..b2f3d35 100644
--- a/src/vendorcode/google/chromeos/Makefile.inc
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -23,3 +23,6 @@
ramstage-y += vbnv.c
romstage-y += vboot.c
ramstage-y += gnvs.c
+romstage-y += fmap.c
+ramstage-y += fmap.c
+smm-y += fmap.c
diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl
new file mode 100644
index 0000000..278296c
--- /dev/null
+++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (CRHW)
+{
+ Name(_HID, EISAID("GGL0001"))
+
+ Method(_STA, 0, Serialized)
+ {
+ Return (0xb)
+ }
+
+ Method(CHSW, 0, Serialized)
+ {
+ Name (WSHC, Package() { VBT3 })
+ Return (WSHC)
+ }
+
+ Method(FWID, 0, Serialized)
+ {
+ Name (DIW1, "")
+ ToString(VBT5, 63, DIW1)
+ Name (DIWF, Package() { DIW1 })
+ Return(DIWF)
+ }
+
+ Method(FRID, 0, Serialized)
+ {
+ Name (DIR1, "")
+ ToString(VBT6, 63, DIR1)
+ Name (DIRF, Package() { DIR1 })
+ Return (DIRF)
+ }
+
+ Method(HWID, 0, Serialized)
+ {
+ Name (DIW0, "")
+ ToString(VBT4, 255, DIW0)
+ Name (DIWH, Package() { DIW0 })
+ Return (DIWH)
+ }
+
+ Method(BINF, 0, Serialized)
+ {
+ Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+ Return (FNIB)
+ }
+
+ Method(GPIO, 0, Serialized)
+ {
+ Return (OIPG)
+
+ }
+
+ Method(VBNV, 0, Serialized)
+ {
+ Name(VNBV, Package() {
+ // See src/vendorcode/google/chromeos/Kconfig
+ // for the definition of these:
+ CONFIG_VBNV_OFFSET,
+ CONFIG_VBNV_SIZE
+ })
+ Return(VNBV)
+ }
+
+ Method(VDAT, 0, Serialized)
+ {
+ Name(TAD0,"")
+ ToBuffer(CHVD, TAD0)
+ Name (TADV, Package() { TAD0 })
+ Return (TADV)
+ }
+
+ Method(FMAP, 0, Serialized)
+ {
+ Name(PAMF, Package() { VBT9 })
+ Return(PAMF)
+ }
+
+ Method(MECK, 0, Serialized)
+ {
+ Name(HASH, Package() { MEHH })
+ Return(HASH)
+ }
+
+ Method(MLST, 0, Serialized)
+ {
+ Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+ "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+ })
+ Return (TSLM)
+ }
+}
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
index ec0f3b7..37630a6 100644
--- a/src/vendorcode/google/chromeos/chromeos.h
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -29,6 +29,8 @@
/* functions implemented in vbnv.c: */
int get_recovery_mode_from_vbnv(void);
+int vboot_wants_oprom(void);
+extern int oprom_is_loaded;
/* functions implemented in chromeos.c: */
int developer_mode_enabled(void);
diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c
new file mode 100644
index 0000000..0871529
--- /dev/null
+++ b/src/vendorcode/google/chromeos/fmap.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+#include <console/console.h>
+#include "fmap.h"
+
+static int fmap_try_find(void *fmap)
+{
+ if (!memcmp(fmap, FMAP_SIGNATURE,
+ sizeof(FMAP_SIGNATURE)-1))
+ return 1;
+ return 0;
+}
+
+/* Find FMAP data structure in ROM.
+ * See http://code.google.com/p/flashmap/ for more information on FMAP.
+ */
+const struct fmap *fmap_find(void)
+{
+ const struct fmap *fmap = NULL;
+
+ /* FIXME: Get rid of the hard codes. The "easy" way would be to
+ * do a binary search, but since ROM accesses are slow, we don't
+ * want to spend a lot of time looking for the FMAP. An elegant
+ * solution would be to store a pointer to the FMAP in the CBFS
+ * master header; that would require some more changes to cbfstool
+ * and possibly cros_bundle_firmware.
+ * FIXME: Use CONFIG_ROMSIZE instead of CONFIG_MRC_CACHE_BASE
+ * (and get rid of CONFIG_MRC_CACHE_BASE), once we are building
+ * coreboot images with ME firmware etc built in instead of just
+ * the CBFS part.
+ */
+ if (fmap_try_find((void *)CONFIG_MRC_CACHE_BASE +
+ CONFIG_FLASHMAP_OFFSET))
+ fmap = (const struct fmap *)(CONFIG_MRC_CACHE_BASE +
+ CONFIG_FLASHMAP_OFFSET);
+ if (fmap) {
+ printk(BIOS_DEBUG, "FMAP: Found \"%s\" version %d.%d at %p.\n",
+ fmap->name, fmap->ver_major, fmap->ver_minor, fmap);
+ printk(BIOS_DEBUG, "FMAP: base = %llx size = %x #areas = %d\n",
+ (unsigned long long)fmap->base, fmap->size,
+ fmap->nareas);
+ } else
+ printk(BIOS_DEBUG, "No FMAP found.\n");
+
+ return fmap;
+}
+
+const struct fmap_area *find_fmap_area(const struct fmap *fmap,
+ const char name[])
+{
+ const struct fmap_area *area = NULL;
+
+ if (fmap) {
+ int i;
+ for (i = 0; i < fmap->nareas; i++) {
+ if (!strcmp((const char *)fmap->areas[i].name, name)) {
+ area = &fmap->areas[i];
+ break;
+ }
+ }
+ }
+
+ if (area) {
+ printk(BIOS_DEBUG, "FMAP: area %s found\n", name);
+ printk(BIOS_DEBUG, "FMAP: offset: %x\n", area->offset);
+ printk(BIOS_DEBUG, "FMAP: size: %d bytes\n", area->size);
+ } else {
+ printk(BIOS_DEBUG, "FMAP: area %s not found\n", name);
+ }
+
+ return area;
+}
+
+int find_fmap_entry(const char name[], void **pointer)
+{
+#ifndef __PRE_RAM__
+ static
+#endif
+ const struct fmap *fmap = NULL;
+ const struct fmap_area *area;
+ void *base = NULL;
+
+ if (!fmap)
+ fmap = fmap_find();
+
+ area = find_fmap_area(fmap, name);
+
+ if (!area)
+ return -1;
+
+ /* Right now cros_bundle_firmware does not write a valid
+ * base address into the FMAP. Hence, if base is 0, assume
+ * 4GB-8MB as base address.
+ */
+ if (fmap->base) {
+ base = (void *)(unsigned long)fmap->base;
+ } else {
+ printk(BIOS_WARNING, "FMAP: No valid base address, using"
+ " 0x%08x\n", CONFIG_MRC_CACHE_BASE);
+ base = (void *)CONFIG_MRC_CACHE_BASE;
+ }
+
+ *pointer = base + area->offset;
+
+ return area->size;
+}
diff --git a/src/vendorcode/google/chromeos/fmap.h b/src/vendorcode/google/chromeos/fmap.h
new file mode 100644
index 0000000..a3d2abd
--- /dev/null
+++ b/src/vendorcode/google/chromeos/fmap.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2010, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following disclaimer
+ * in the documentation and/or other materials provided with the
+ * distribution.
+ * * Neither the name of Google Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Alternatively, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") version 2 as published by the Free
+ * Software Foundation.
+ */
+
+#ifndef FLASHMAP_LIB_FMAP_H__
+#define FLASHMAP_LIB_FMAP_H__
+
+#include <stdint.h>
+
+#define FMAP_SIGNATURE "__FMAP__"
+#define FMAP_VER_MAJOR 1 /* this header's FMAP minor version */
+#define FMAP_VER_MINOR 1 /* this header's FMAP minor version */
+#define FMAP_STRLEN 32 /* maximum length for strings, */
+ /* including null-terminator */
+
+enum fmap_flags {
+ FMAP_AREA_STATIC = 1 << 0,
+ FMAP_AREA_COMPRESSED = 1 << 1,
+ FMAP_AREA_RO = 1 << 2,
+};
+
+/* Mapping of volatile and static regions in firmware binary */
+struct fmap_area {
+ uint32_t offset; /* offset relative to base */
+ uint32_t size; /* size in bytes */
+ uint8_t name[FMAP_STRLEN]; /* descriptive name */
+ uint16_t flags; /* flags for this area */
+} __attribute__((packed));
+
+struct fmap {
+ uint8_t signature[8]; /* "__FMAP__" (0x5F5F464D41505F5F) */
+ uint8_t ver_major; /* major version */
+ uint8_t ver_minor; /* minor version */
+ uint64_t base; /* address of the firmware binary */
+ uint32_t size; /* size of firmware binary in bytes */
+ uint8_t name[FMAP_STRLEN]; /* name of this firmware binary */
+ uint16_t nareas; /* number of areas described by
+ fmap_areas[] below */
+ struct fmap_area areas[];
+} __attribute__((packed));
+
+
+/* coreboot specific function prototypes */
+const struct fmap *fmap_find(void);
+const struct fmap_area *find_fmap_area(const struct fmap *fmap,
+ const char name[]);
+int find_fmap_entry(const char name[], void **pointer);
+#endif /* FLASHMAP_LIB_FMAP_H__*/
diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c
index 6b545f4..2e9975c 100644
--- a/src/vendorcode/google/chromeos/gnvs.c
+++ b/src/vendorcode/google/chromeos/gnvs.c
@@ -21,9 +21,12 @@
#include <string.h>
#include <cbfs.h>
#include <console/console.h>
+#include <elog.h>
+
+#include "chromeos.h"
#include "gnvs.h"
-chromeos_acpi_t *vboot_data;
+chromeos_acpi_t *vboot_data = NULL;
static u32 me_hash_saved[8];
void chromeos_init_vboot(chromeos_acpi_t *chromeos)
@@ -32,47 +35,16 @@
/* Copy saved ME hash into NVS */
memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh));
-}
-void chromeos_set_vboot_data_ptr(void *blob)
-{
- /* This code has to be rewritten to pass the vboot table
- * pointer through the coreboot table instead of the
- * FDT, since FDT support was rejected upstream. For now
- * just make the code available for reference.
- */
-#if 0 // CONFIG_ADD_FDT
- int node_offset, addr_cell_len;
- const u32 *cell;
- uintptr_t table_addr = (uintptr_t)vboot_data;
- u32 table_addr32;
- u64 table_addr64;
- void *table_ptr;
-
- cell = fdt_getprop(blob, 0, "#address-cells", NULL);
- if (cell && *cell == 2) {
- addr_cell_len = 8;
- table_addr64 = cpu_to_fdt64(table_addr);
- table_ptr = &table_addr64;
- } else {
- addr_cell_len = 4;
- table_addr32 = cpu_to_fdt32(table_addr);
- table_ptr = &table_addr32;
+#if CONFIG_ELOG
+ if (developer_mode_enabled() ||
+ (vboot_wants_oprom() && !recovery_mode_enabled()))
+ elog_add_event(ELOG_TYPE_CROS_DEVELOPER_MODE);
+ if (recovery_mode_enabled()) {
+ int reason = get_recovery_mode_from_vbnv();
+ elog_add_event_byte(ELOG_TYPE_CROS_RECOVERY_MODE,
+ reason ? reason : ELOG_CROS_RECOVERY_MODE_BUTTON);
}
-
- node_offset = fdt_path_offset(blob, "/chromeos-config");
- if (node_offset < 0) {
- printk(BIOS_ERR,
- "Couldn't find /chromeos-config in the fdt.\n");
- return;
- }
-
- if (fdt_setprop(blob, node_offset, "gnvs-vboot-table",
- table_ptr, addr_cell_len) < 0) {
- printk(BIOS_ERR, "Couldn't set gnvs-vboot-table.\n");
- }
-#else
- printk(BIOS_ERR, "Can't set gnvs-vboot-table.\n");
#endif
}
@@ -83,7 +55,14 @@
/* Copy to NVS or save until it is ready */
if (vboot_data)
+ /* This does never happen! */
memcpy(vboot_data->mehh, hash, len*sizeof(u32));
else
memcpy(me_hash_saved, hash, len*sizeof(u32));
}
+
+void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size)
+{
+ *vdat_addr = vboot_data;
+ *vdat_size = sizeof(*vboot_data);
+}
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
index 36922ba..4067494 100644
--- a/src/vendorcode/google/chromeos/gnvs.h
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -63,7 +63,7 @@
extern chromeos_acpi_t *vboot_data;
void chromeos_init_vboot(chromeos_acpi_t *chromeos);
-void chromeos_set_vboot_data_ptr(void *);
void chromeos_set_me_hash(u32*, int);
+void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size);
#endif
diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c
index 2129461..da65c0e 100644
--- a/src/vendorcode/google/chromeos/vbnv.c
+++ b/src/vendorcode/google/chromeos/vbnv.c
@@ -38,6 +38,8 @@
#define BOOT_OFFSET 1
#define BOOT_DEBUG_RESET_MODE 0x80
+#define BOOT_DISABLE_DEV_REQUEST 0x40
+#define BOOT_OPROM_NEEDED 0x20
#define BOOT_TRY_B_COUNT_MASK 0x0F
#define RECOVERY_OFFSET 2
@@ -45,11 +47,7 @@
#define DEV_FLAGS_OFFSET 4
#define DEV_BOOT_USB_MASK 0x01
-
-#define FIRMWARE_FLAGS_OFFSET 5
-#define FIRMWARE_TEST_ERR_FUNC_MASK 0x38
-#define FIRMWARE_TEST_ERR_FUNC_SHIFT 3
-#define FIRMWARE_TEST_ERR_NUM_MASK 0x07
+#define DEV_BOOT_SIGNED_ONLY_MASK 0x02
#define KERNEL_FIELD_OFFSET 11
#define CRC_OFFSET 15
@@ -107,3 +105,11 @@
vbnv_setup();
return vbnv[RECOVERY_OFFSET];
}
+
+int vboot_wants_oprom(void)
+{
+ if (!vbnv_initialized)
+ vbnv_setup();
+
+ return (vbnv[BOOT_OFFSET] & BOOT_OPROM_NEEDED) ? 1 : 0;
+}
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index 0b61342..813ba1b 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -3,7 +3,7 @@
HOSTCXX ?= g++
HOSTCC ?= gcc
CFLAGS ?= -g -Wall
-CXXFLAGS ?=-DCOMPACT $(CFLAGS)
+CXXFLAGS +=-DCOMPACT $(CFLAGS)
LDFLAGS ?= -g
BINARY:=$(obj)/cbfstool
@@ -16,6 +16,8 @@
COMMON:=$(addprefix $(obj)/,$(COMMON))
+all: dep $(BINARY)
+
$(obj)/%.o: %.c
$(HOSTCC) $(CFLAGS) -c -o $@ $<
@@ -37,8 +39,6 @@
$(obj)/%.o: lzma/C/Common/%.cpp
$(HOSTCXX) $(CXXFLAGS) -c -o $@ $<
-all: $(BINARY)
-
clean:
rm -f $(COMMON) $(BINARY)
@@ -47,3 +47,13 @@
$(obj)/cbfstool:$(COMMON)
$(HOSTCXX) $(LDFLAGS) -o $@ $^
+
+dep:
+ @$(HOSTCC) $(CFLAGS) -MM *.c > .dependencies
+ @$(HOSTCC) $(CFLAGS) -MM lzma/C/7zip/Decompress/*.c >> .dependencies
+ @$(HOSTCXX) $(CXXFLAGS) -MM lzma/C/7zip/Compress/*/*.cpp >> .dependencies
+ @$(HOSTCXX) $(CXXFLAGS) -MM lzma/C/7zip/Common/*.cpp >> .dependencies
+ @$(HOSTCXX) $(CXXFLAGS) -MM lzma/C/Common/*.cpp >> .dependencies
+ @$(HOSTCXX) $(CXXFLAGS) -MM lzma/*.cc >> .dependencies
+
+-include .dependencies
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 9dbdc1c..b344a35 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -245,7 +245,11 @@
if (argc > 5)
align = strtoul(argv[5], NULL, 0);
- return create_cbfs_image(romname, size, bootblock, align);
+ uint32_t offs = 0;
+ if (argc > 6)
+ offs = strtoul(argv[6], NULL, 0);
+
+ return create_cbfs_image(romname, size, bootblock, align, offs);
}
static int cbfs_locate(int argc, char **argv)
@@ -318,14 +322,14 @@
" cbfstool FILE COMMAND [PARAMETERS]...\n\n" "OPTIONs:\n"
" -h Display this help message\n\n"
"COMMANDs:\n"
- " add FILE NAME TYPE [base address] Add a component\n"
- " add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n"
- " add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n"
- " remove FILE NAME Remove a component\n"
- " create SIZE BOOTBLOCK [ALIGN] Create a ROM file\n"
- " locate FILE NAME ALIGN Find a place for a file of that size\n"
- " print Show the contents of the ROM\n"
- " extract NAME FILE Extracts a raw payload from ROM\n"
+ " add FILE NAME TYPE [base address] Add a component\n"
+ " add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n"
+ " add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n"
+ " remove FILE NAME Remove a component\n"
+ " create SIZE BOOTBLOCK [ALIGN] [offset] Create a ROM file\n"
+ " locate FILE NAME ALIGN Find a place for a file of that size\n"
+ " print Show the contents of the ROM\n"
+ " extract NAME FILE Extracts a raw payload from ROM\n"
"\n"
"TYPEs:\n"
);
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index 7a6e2c2..ac7195b 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -446,7 +446,7 @@
}
int create_cbfs_image(const char *romfile, uint32_t _romsize,
- const char *bootblock, uint32_t align)
+ const char *bootblock, uint32_t align, uint32_t offs)
{
romsize = _romsize;
unsigned char *romarea = malloc(romsize);
@@ -473,14 +473,14 @@
master_header->romsize = htonl(romsize);
master_header->bootblocksize = htonl(bootblocksize);
master_header->align = htonl(align);
- master_header->offset = htonl(0);
+ master_header->offset = htonl(offs);
((uint32_t *) phys_to_virt(0xfffffffc))[0] =
virt_to_phys(master_header);
recalculate_rom_geometry(romarea);
- cbfs_create_empty_file((0 - romsize) & 0xffffffff,
- romsize - bootblocksize -
+ cbfs_create_empty_file((0 - romsize + offs) & 0xffffffff,
+ romsize - offs - bootblocksize -
sizeof(struct cbfs_header) -
sizeof(struct cbfs_file) - 16);
diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h
index 7034e0c..3bcfae8 100644
--- a/util/cbfstool/common.h
+++ b/util/cbfstool/common.h
@@ -64,9 +64,10 @@
uint32_t type, uint32_t * location);
int create_cbfs_image(const char *romfile, uint32_t romsize,
- const char *bootblock, uint32_t align);
+ const char *bootblock, uint32_t align, uint32_t offs);
int add_file_to_cbfs(void *content, uint32_t contentsize, uint32_t location);
+int remove_file_from_cbfs(const char *filename);
void print_cbfs_directory(const char *filename);
int extract_file_from_cbfs(const char *filename, const char *payloadname, const char *outpath);
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 8c1077c..1b418d1 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -152,16 +152,52 @@
}
}
+static void decode_component_density(unsigned int density)
+{
+ switch (density) {
+ case COMPONENT_DENSITY_512KB:
+ printf("512KB");
+ break;
+ case COMPONENT_DENSITY_1MB:
+ printf("1MB");
+ break;
+ case COMPONENT_DENSITY_2MB:
+ printf("2MB");
+ break;
+ case COMPONENT_DENSITY_4MB:
+ printf("4MB");
+ break;
+ case COMPONENT_DENSITY_8MB:
+ printf("8MB");
+ break;
+ case COMPONENT_DENSITY_16MB:
+ printf("16MB");
+ break;
+ default:
+ printf("unknown<%x>MB", density);
+ }
+}
+
static void dump_fcba(fcba_t * fcba)
{
printf("\nFound Component Section\n");
printf("FLCOMP 0x%08x\n", fcba->flcomp);
+ printf(" Dual Output Fast Read Support: %ssupported\n",
+ (fcba->flcomp & (1 << 30))?"":"not ");
printf(" Read ID/Read Status Clock Frequency: ");
decode_spi_frequency((fcba->flcomp >> 27) & 7);
printf("\n Write/Erase Clock Frequency: ");
decode_spi_frequency((fcba->flcomp >> 24) & 7);
printf("\n Fast Read Clock Frequency: ");
decode_spi_frequency((fcba->flcomp >> 21) & 7);
+ printf("\n Fast Read Support: %ssupported",
+ (fcba->flcomp & (1 << 20))?"":"not ");
+ printf("\n Read Clock Frequency: ");
+ decode_spi_frequency((fcba->flcomp >> 17) & 7);
+ printf("\n Component 2 Density: ");
+ decode_component_density((fcba->flcomp >> 3) & 7);
+ printf("\n Component 1 Density: ");
+ decode_component_density(fcba->flcomp & 7);
printf("\n");
printf("FLILL 0x%08x\n", fcba->flill);
printf("FLPB 0x%08x\n", fcba->flpb);
@@ -260,7 +296,7 @@
O_WRONLY | O_CREAT | O_TRUNC,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if (write(region_fd, image + region.base, region.size) != region.size)
- printf("Error while writing.");
+ perror("Error while writing");
close(region_fd);
}
}
@@ -281,7 +317,7 @@
O_WRONLY | O_CREAT | O_TRUNC,
S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
if (write(new_fd, image, size) != size)
- printf("Error while writing.");
+ perror("Error while writing");
close(new_fd);
}
@@ -303,6 +339,15 @@
write_image(filename, image, size);
}
+static void set_em100_mode(char *filename, char *image, int size)
+{
+ fdbar_t *fdb = find_fd(image, size);
+ fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4));
+
+ fcba->flcomp &= ~(1 << 30);
+ set_spi_frequency(filename, image, size, SPI_FREQUENCY_20MHZ);
+}
+
void inject_region(char *filename, char *image, int size, int region_type,
char *region_fname)
{
@@ -389,6 +434,8 @@
" -x | --extract: extract intel fd modules\n"
" -i | --inject <region>:<module> inject file <module> into region <region>\n"
" -s | --spifreq <20|33|50> set the SPI frequency\n"
+ " -e | --em100 set SPI frequency to 20MHz and disable\n"
+ " Dual Output Fast Read Support\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
"<region> is one of Descriptor, BIOS, ME, GbE, Platform\n"
@@ -399,6 +446,7 @@
{
int opt, option_index = 0;
int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0;
+ int mode_em100 = 0;
char *region_type_string = NULL, *region_fname = NULL;
int region_type = -1, inputfreq = 0;
enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
@@ -408,12 +456,13 @@
{"extract", 0, NULL, 'x'},
{"inject", 1, NULL, 'i'},
{"spifreq", 1, NULL, 's'},
+ {"em100", 0, NULL, 'e'},
{"version", 0, NULL, 'v'},
{"help", 0, NULL, 'h'},
{0, 0, 0, 0}
};
- while ((opt = getopt_long(argc, argv, "dxi:s:vh?",
+ while ((opt = getopt_long(argc, argv, "dxi:s:evh?",
long_options, &option_index)) != EOF) {
switch (opt) {
case 'd':
@@ -473,6 +522,9 @@
}
mode_spifreq = 1;
break;
+ case 'e':
+ mode_em100 = 1;
+ break;
case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -492,7 +544,8 @@
exit(EXIT_FAILURE);
}
- if ((mode_dump + mode_extract + mode_inject + mode_spifreq) == 0) {
+ if ((mode_dump + mode_extract + mode_inject + mode_spifreq +
+ mode_em100) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
print_usage(argv[0]);
exit(EXIT_FAILURE);
@@ -545,6 +598,9 @@
if (mode_spifreq)
set_spi_frequency(filename, image, size, spifreq);
+ if (mode_em100)
+ set_em100_mode(filename, image, size);
+
free(image);
return 0;
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index 0571534..31361df 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -26,6 +26,15 @@
SPI_FREQUENCY_50MHZ = 4,
};
+enum component_density {
+ COMPONENT_DENSITY_512KB = 0,
+ COMPONENT_DENSITY_1MB = 1,
+ COMPONENT_DENSITY_2MB = 2,
+ COMPONENT_DENSITY_4MB = 3,
+ COMPONENT_DENSITY_8MB = 4,
+ COMPONENT_DENSITY_16MB = 5,
+};
+
// flash descriptor
typedef struct {
uint32_t flvalsig;
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index 181be38..479c79a 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -44,7 +44,11 @@
.id = 0,
.chip = &mainboard,
.type = chip,
+#ifdef MAINBOARDS_HAVE_CHIP_H
.chiph_exists = 1,
+#else
+ .chiph_exists = 0,
+#endif
.children = &root
};
@@ -323,22 +327,26 @@
static void pass0(FILE *fil, struct device *ptr) {
if (ptr->type == device && ptr->id == 0)
- fprintf(fil, "struct bus %s_links[];\n", ptr->name);
+ fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n", ptr->name);
+
if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) {
- fprintf(fil, "static struct device %s;\n", ptr->name);
+ fprintf(fil, "ROMSTAGE_CONST static struct device %s;\n", ptr->name);
if (ptr->rescnt > 0)
- fprintf(fil, "struct resource %s_res[];\n", ptr->name);
+ fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[];\n", ptr->name);
if (ptr->children || ptr->multidev)
- fprintf(fil, "struct bus %s_links[];\n", ptr->name);
+ fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[];\n",
+ ptr->name);
}
}
static void pass1(FILE *fil, struct device *ptr) {
if (!ptr->used && (ptr->type == device)) {
if (ptr->id != 0)
- fprintf(fil, "static ", ptr->name);
- fprintf(fil, "struct device %s = {\n", ptr->name);
+ fprintf(fil, "static ");
+ fprintf(fil, "ROMSTAGE_CONST struct device %s = {\n", ptr->name);
+ fprintf(fil, "#ifndef __PRE_RAM__\n");
fprintf(fil, "\t.ops = %s,\n", (ptr->ops)?(ptr->ops):"0");
+ fprintf(fil, "#endif\n");
fprintf(fil, "\t.bus = &%s_links[%d],\n", ptr->bus->name, ptr->bus->link);
fprintf(fil, "\t.path = {");
fprintf(fil, ptr->path, ptr->path_a, ptr->path_b);
@@ -362,8 +370,14 @@
if (ptr->sibling)
fprintf(fil, "\t.sibling = &%s,\n", ptr->sibling->name);
if (ptr->chip->chiph_exists) {
+ fprintf(fil, "#ifndef __PRE_RAM__\n");
fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore);
+ fprintf(fil, "#endif\n");
fprintf(fil, "\t.chip_info = &%s_info_%d,\n", ptr->chip->name_underscore, ptr->chip->id);
+ } else if (ptr->chip->chip == &mainboard) {
+ fprintf(fil, "#ifndef __PRE_RAM__\n");
+ fprintf(fil, "\t.chip_ops = &%s_ops,\n", ptr->chip->name_underscore);
+ fprintf(fil, "#endif\n");
}
if (ptr->nextdev)
fprintf(fil, "\t.next=&%s\n", ptr->nextdev->name);
@@ -371,7 +385,8 @@
}
if (ptr->rescnt > 0) {
int i=1;
- fprintf(fil, "struct resource %s_res[] = {\n", ptr->name);
+ fprintf(fil, "ROMSTAGE_CONST struct resource %s_res[] = {\n",
+ ptr->name);
struct resource *r = ptr->res;
while (r) {
fprintf(fil, "\t\t{ .flags=IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_");
@@ -388,7 +403,7 @@
fprintf(fil, "\t };\n");
}
if (!ptr->used && ptr->type == device && (ptr->children || ptr->multidev)) {
- fprintf(fil, "struct bus %s_links[] = {\n", ptr->name);
+ fprintf(fil, "ROMSTAGE_CONST struct bus %s_links[] = {\n", ptr->name);
if (ptr->multidev) {
struct device *d = ptr;
while (d) {
@@ -420,8 +435,9 @@
}
if ((ptr->type == chip) && (ptr->chiph_exists)) {
if (ptr->reg) {
- fprintf(fil, "struct %s_config %s_info_%d\t= {\n",
- ptr->name_underscore, ptr->name_underscore, ptr->id);
+ fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = {\n",
+ ptr->name_underscore, ptr->name_underscore,
+ ptr->id);
struct reg *r = ptr->reg;
while (r) {
fprintf(fil, "\t.%s = %s,\n", r->key, r->value);
@@ -429,7 +445,7 @@
}
fprintf(fil, "};\n\n");
} else {
- fprintf(fil, "struct %s_config %s_info_%d;\n",
+ fprintf(fil, "ROMSTAGE_CONST struct %s_config ROMSTAGE_CONST %s_info_%d = { };\n",
ptr->name_underscore, ptr->name_underscore, ptr->id);
}
}
@@ -512,12 +528,14 @@
}
headers.next = 0;
+#ifdef MAINBOARDS_HAVE_CHIP_H
if (scan_mode == STATIC_MODE) {
headers.next = malloc(sizeof(struct header));
headers.next->name = malloc(strlen(mainboard)+12);
headers.next->next = 0;
sprintf(headers.next->name, "mainboard/%s", mainboard);
}
+#endif
FILE *filec = fopen(devtree, "r");
if (!filec) {
@@ -561,8 +579,13 @@
walk_device_tree(autogen, &root, inherit_subsystem_ids, NULL);
fprintf(autogen, "\n/* pass 0 */\n");
walk_device_tree(autogen, &root, pass0, NULL);
- fprintf(autogen, "\n/* pass 1 */\nstruct mainboard_config mainboard_info_0;\n"
- "struct device *last_dev = &%s;\n", lastdev->name);
+ fprintf(autogen, "\n/* pass 1 */\n"
+ "ROMSTAGE_CONST struct device * ROMSTAGE_CONST last_dev = &%s;\n", lastdev->name);
+#ifdef MAINBOARDS_HAVE_CHIP_H
+ fprintf(autogen, "static ROMSTAGE_CONST struct mainboard_config ROMSTAGE_CONST mainboard_info_0;\n");
+#else
+ fprintf(autogen, "extern struct chip_operations mainboard_ops;\n");
+#endif
walk_device_tree(autogen, &root, pass1, NULL);
} else if (scan_mode == BOOTBLOCK_MODE) {
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 3930460..c292f70 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -44,7 +44,7 @@
TARCH=('i386' 'x86_64')
TWIDTH=32
for search_for in "${TARCH[@]}"; do
- TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf-)
+ TARCH_SEARCH=("${TARCH_SEARCH[@]}" ${XGCCPATH}${search_for}-elf- ${search_for}-elf- ${CROSS_COMPILE})
done
echo '# TARCH_SEARCH='${TARCH_SEARCH[@]}
@@ -89,6 +89,8 @@
# now:
testcc "$CC" "$CFLAGS-Wno-unused-but-set-variable " && \
CFLAGS="$CFLAGS-Wno-unused-but-set-variable "
+# Use bfd linker instead of gold if available:
+testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd'
if which gcc 2>/dev/null >/dev/null; then
HOSTCC=gcc
