publish lumpy/stumpy firmware

This is a snapshot from:
	https://chrome-internal.googlesource.com/chromeos/third_party/coreboot
at git sha1:
	2a5362c5bf2e070f1b312317666404fac2c12117

All files in the 3rdparty/ subdir have been stripped.

Further, swap the internal base from:
	1f0b0d9ffb318b7869abb06b9213f5c231ac0e57
to the public base:
	8eee19d0eafd3a34742df4d26c810424097211fe

They contain the same source, but the svn-to-git trees diverged at commit:
	7272fcb2a466d2554b29e082c8e57038bfc4ebe6
The differences are limited to metadata in git itself and not the files
the commits contain.

BUG=None
TEST=compiled internal repo & public repo and compared disassembled files

Change-Id: Ic63d6647474c7a527d41886b03a66ce1316e1a65
Reviewed-on: https://chromium-review.googlesource.com/194379
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Mike Frysinger <vapier@chromium.org>
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..305ef4f
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+build
+coreboot-builds
+.config
+.config.old
+.xcompile
diff --git a/Makefile b/Makefile
index ac7115d..04fbb02 100644
--- a/Makefile
+++ b/Makefile
@@ -109,7 +109,7 @@
 endif
 
 ifeq ($(CONFIG_CCACHE),y)
-CCACHE:=$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH))))
+CCACHE:=$(word 1,$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH)))))
 ifeq ($(CCACHE),)
 $(error ccache selected, but not found in PATH)
 endif
@@ -176,7 +176,7 @@
 	$(foreach class,$(classes), \
 		$(eval $(class)-srcs+= \
 			$$(subst $(top)/,, \
-			$$(abspath $$(addprefix $(dir $(1)),$$($(class)-y)))))) \
+			$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y))))))) \
 	$(foreach special,$(special-classes), \
 		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
 	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
diff --git a/Makefile.inc b/Makefile.inc
index 6267539..94edd81 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -19,8 +19,8 @@
 
 #######################################################################
 # misleadingly named, this is the coreboot version
-REV=-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)
-export KERNELVERSION      := 4.0$(REV)
+KERNELREVISION?=-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)
+export KERNELVERSION      := 4.0$(KERNELREVISION)
 
 #######################################################################
 # Basic component discovery
@@ -43,6 +43,7 @@
 subdirs-y += util/cbfstool util/sconfig
 subdirs-y += src/arch/$(ARCHDIR-y)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
+subdirs-y += src/vendorcode
 
 subdirs-$(CONFIG_ARCH_X86) += src/pc80
 
@@ -55,6 +56,11 @@
 smm-c-ccopts:=-D__SMM__
 smm-S-ccopts:=-D__SMM__
 
+# SMM TSEG base is dynamic
+ifeq ($(CONFIG_SMM_TSEG),y)
+smm-c-ccopts += -fpic
+endif
+
 ramstage-c-deps:=$$(OPTION_TABLE_H)
 romstage-c-deps:=$$(OPTION_TABLE_H)
 
@@ -64,7 +70,8 @@
 $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h
 	@printf "    IASL       $$(subst $(top)/,,$$(@))\n"
 	$(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
-	iasl -p $$(obj)/$(1) -tc $$(basename $$@).asl
+	cd $$(dir $$@); iasl -p $$(notdir $$(basename $$(obj)/$(1))) \
+				-tc $$(notdir $$(basename $$@)).asl
 	mv $$(obj)/$(1).hex $$(basename $$@).c
 	$(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c
 	# keep %.o: %.c rule from catching the temporary .c file after a make clean
@@ -102,7 +109,7 @@
 endif
 
 INCLUDES := -Isrc -Isrc/include -I$(obj) -Isrc/arch/$(ARCHDIR-y)/include
-INCLUDES += -Isrc/devices/oprom/include
+INCLUDES += -Isrc/devices/oprom/include -Isrc/include/fdt
 # abspath is a workaround for romcc
 INCLUDES += -include $(abspath $(obj)/config.h)
 
@@ -131,6 +138,7 @@
 	printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht
+	printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht
 	printf "\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht
@@ -182,7 +190,7 @@
 	@printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"
 	$(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $<
 
-$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
+$(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) -c -o $@ $<
 
diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg
new file mode 100644
index 0000000..b9a7fca
--- /dev/null
+++ b/PRESUBMIT.cfg
@@ -0,0 +1,10 @@
+# This config file disables some of the ChromiumOS source style checks for
+# coreboot as they are directly conflicting with the coreboot coding
+# guidelines.
+
+[Hook Overrides]
+#stray_whitespace_check: false
+#long_line_check: false
+cros_license_check: false
+tab_check: false
+
diff --git a/README b/README
index d879695..16a805f 100644
--- a/README
+++ b/README
@@ -42,6 +42,7 @@
  * gdb (for better debugging facilities on some targets)
  * ncurses (for 'make menuconfig')
  * flex and bison (for regenerating parsers)
+ * git (for internal SeaBIOS payload)
 
 
 Building coreboot
diff --git a/config.lumpy b/config.lumpy
new file mode 100644
index 0000000..95756bd
--- /dev/null
+++ b/config.lumpy
@@ -0,0 +1,353 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version: 4.0-r6552
+# Sat Mar  3 00:42:46 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_ADD_FDT=y
+CONFIG_FDT_FILE_NAME="u-boot.dtb"
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTEC_GROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_DIGITAL_LOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EVOC is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PC_ENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+CONFIG_VENDOR_SAMSUNG=y
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="samsung/lumpy"
+CONFIG_MAINBOARD_PART_NUMBER="Lumpy"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="SAMSUNG"
+CONFIG_MAX_CPUS=8
+CONFIG_MAX_PHYSICAL_CPUS=1
+CONFIG_DCACHE_RAM_BASE=0xff7f0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_ID_SECTION_OFFSET=0x10
+CONFIG_STACK_SIZE=0x8000
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS_ID="8086,0106"
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_VGA_BIOS_FILE="3rdparty/intel/sandybridge/lumpy/snm_2130_coreboot.bin"
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1ae0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xc000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is not set
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_SAMSUNG_LUMPY=y
+# CONFIG_BOARD_SAMSUNG_STUMPY is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+CONFIG_AP_IN_SIPI_WAIT=y
+CONFIG_ROMBASE=0xffff0000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_TINY_BOOTBLOCK=y
+# CONFIG_BIG_BOOTBLOCK is not set
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_BASE=0xffff0000
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_DIMM_SUPPORT=0x0004
+# CONFIG_UDELAY_IO is not set
+CONFIG_UPDATE_CPU_MICROCODE=y
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_CPU_INTEL_MODEL_206AX=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_SIZE_KB=256
+CONFIG_DCACHE_MRC_BASE=0xfffd0000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_MMX=y
+CONFIG_SSE=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_SMSC_MEC1308=y
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_SMSC_MEC1308=y
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+CONFIG_VGA_BIOS=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x114
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_DEBUG_INTEL_ME is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_CHROMEOS=y
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
diff --git a/config.stumpy b/config.stumpy
new file mode 100644
index 0000000..9b92a36
--- /dev/null
+++ b/config.stumpy
@@ -0,0 +1,352 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version: 4.0-r6552
+# Sat Mar  3 01:00:42 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_ADD_FDT=y
+CONFIG_FDT_FILE_NAME="u-boot.dtb"
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTEC_GROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_DIGITAL_LOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EVOC is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PC_ENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+CONFIG_VENDOR_SAMSUNG=y
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="samsung/stumpy"
+CONFIG_MAINBOARD_PART_NUMBER="Stumpy"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="SAMSUNG"
+CONFIG_MAX_CPUS=8
+CONFIG_MAX_PHYSICAL_CPUS=1
+CONFIG_DCACHE_RAM_BASE=0xff7f0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_ID_SECTION_OFFSET=0x10
+CONFIG_STACK_SIZE=0x8000
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS_ID="8086,0106"
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_VGA_BIOS_FILE="3rdparty/intel/sandybridge/stumpy/snm_2124_coreboot.bin"
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1ae0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xc000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is not set
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+# CONFIG_BOARD_SAMSUNG_LUMPY is not set
+CONFIG_BOARD_SAMSUNG_STUMPY=y
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+CONFIG_AP_IN_SIPI_WAIT=y
+CONFIG_ROMBASE=0xffff0000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_TINY_BOOTBLOCK=y
+# CONFIG_BIG_BOOTBLOCK is not set
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_BASE=0xffff0000
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_DIMM_SUPPORT=0x0004
+# CONFIG_UDELAY_IO is not set
+CONFIG_UPDATE_CPU_MICROCODE=y
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_CPU_INTEL_MODEL_206AX=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_SIZE_KB=256
+CONFIG_DCACHE_MRC_BASE=0xfffd0000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_MMX=y
+CONFIG_SSE=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_ITE_IT8772F=y
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+CONFIG_VGA_BIOS=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x114
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_DEBUG_INTEL_ME is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_CHROMEOS=y
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
diff --git a/payloads/external/FILO/.gitignore b/payloads/external/FILO/.gitignore
new file mode 100644
index 0000000..dd2c4d2
--- /dev/null
+++ b/payloads/external/FILO/.gitignore
@@ -0,0 +1 @@
+filo
diff --git a/payloads/external/SeaBIOS/.gitignore b/payloads/external/SeaBIOS/.gitignore
new file mode 100644
index 0000000..41f077c
--- /dev/null
+++ b/payloads/external/SeaBIOS/.gitignore
@@ -0,0 +1 @@
+seabios
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 8441903..b5e722c 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -77,7 +77,9 @@
 static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_serial *ser = (struct cb_serial *)ptr;
-	info->ser_ioport = ser->ioport;
+	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
+		return;
+	info->ser_ioport = ser->baseaddr;
 }
 
 #ifdef CONFIG_NVRAM
diff --git a/payloads/libpayload/arch/powerpc/coreboot.c b/payloads/libpayload/arch/powerpc/coreboot.c
index 95d8f16..7d5dc02 100644
--- a/payloads/libpayload/arch/powerpc/coreboot.c
+++ b/payloads/libpayload/arch/powerpc/coreboot.c
@@ -77,7 +77,9 @@
 static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_serial *ser = (struct cb_serial *)ptr;
-	info->ser_ioport = ser->ioport;
+	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
+		return;
+	info->ser_ioport = ser->baseaddr;
 }
 
 #ifdef CONFIG_NVRAM
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index c4dc115..d342c99 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -60,9 +60,13 @@
 	u32 type;
 };
 
-#define CB_MEM_RAM      1
-#define CB_MEM_RESERVED 2
-#define CB_MEM_TABLE    16
+#define CB_MEM_RAM          1
+#define CB_MEM_RESERVED     2
+#define CB_MEM_ACPI         3
+#define CB_MEM_NVS          4
+#define CB_MEM_UNUSABLE     5
+#define CB_MEM_VENDOR_RSVD  6
+#define CB_MEM_TABLE       16
 
 struct cb_memory {
 	u32 tag;
@@ -110,7 +114,11 @@
 struct cb_serial {
 	u32 tag;
 	u32 size;
-	u16 ioport;
+#define CB_SERIAL_TYPE_IO_MAPPED     1
+#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
+	u32 type;
+	u32 baseaddr;
+	u32 baud;
 };
 
 #define CB_TAG_CONSOLE       0x00010
diff --git a/src/Kconfig b/src/Kconfig
index 9abbc21..06fd39e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -87,7 +87,7 @@
 	help
 	  Enable this option if you are working on the sconfig
 	  device tree parser and made changes to sconfig.l and
-	  sconfig.y. 
+	  sconfig.y.
 	  Otherwise, say N.
 
 config USE_OPTION_TABLE
@@ -106,6 +106,37 @@
 	  that decompression might slow down booting if the boot flash
 	  is connected through a slow Link (i.e. SPI)
 
+config ADD_FDT
+	bool "Add FDT to the coreboot table"
+	default n
+	help
+	  Make coreboot look for the Flat Device Tree (FDT) in CBFS and once
+	  found insert the device tree into the coreboot table (potentially
+	  modifying the tree as needed). The FDT is used by the payload.
+
+config FDT_FILE_NAME
+	depends on ADD_FDT
+	string "Name of the CBFS file containing the compiled FDT"
+	default "u-boot.dtb"
+	help
+	  Name of the CBFS file containing the binary representation of the
+	  device tree to be optionally modified and passed to the payload.
+
+config EARLY_CBMEM_INIT
+	bool "Initialize CBMEM while in ROM stage"
+	default n
+	help
+	  Make coreboot initialize the cbmem structures while running in rom
+	  stage. This could be useful when the rom stage wants to communicate
+	  some, for instance, execution timestamps.
+
+config COLLECT_TIMESTAMPS
+	bool "Create a table of timestamps collected during boot"
+	depends on EARLY_CBMEM_INIT
+	help
+	  Make coreboot create a table of timer id/timer value pairs to
+	  allow measuring time spent at different phases of the boot
+	  process.
 endmenu
 
 source src/mainboard/Kconfig
@@ -233,6 +264,10 @@
 	bool
 	default n
 
+config TPM
+	bool
+	default n
+
 # TODO: Can probably be removed once all chipsets have kconfig options for it.
 config VIDEO_MB
 	int
@@ -298,6 +333,10 @@
 	bool
 	default HAVE_PIRQ_TABLE
 
+config GENERATE_SMBIOS_TABLES
+	bool
+	default y
+
 menu "System tables"
 
 config WRITE_HIGH_TABLES
@@ -336,6 +375,15 @@
 
 	  If unsure, say Y.
 
+config GENERATE_SMBIOS_TABLES
+	depends on ARCH_X86
+	bool "Generate SMBIOS tables"
+	default y
+	help
+	  Generate SMBIOS tables for this board.
+
+	  If unsure, say Y.
+
 endmenu
 
 menu "Payload"
@@ -497,13 +545,42 @@
 
 endmenu
 
-menu "Bootsplash"
-	depends on PCI_OPTION_ROM_RUN_YABEL
+menu "Display"
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+
+config FRAMEBUFFER_SET_VESA_MODE
+	prompt "Set VESA framebuffer mode"
+	bool
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+	help
+	  Set VESA framebuffer mode (needed for bootsplash)
+
+# TODO: Turn this into a "choice".
+config FRAMEBUFFER_VESA_MODE
+	prompt "VESA framebuffer video mode"
+	hex
+	default 0x117
+	depends on FRAMEBUFFER_SET_VESA_MODE
+	help
+	  This option sets the resolution used for the coreboot framebuffer (and
+	  bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
+	  some day make this a "choice".
+
+config FRAMEBUFFER_KEEP_VESA_MODE
+	prompt "Keep VESA framebuffer"
+	bool
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+	help
+	  This option keeps the framebuffer mode set after coreboot finishes
+	  execution. If this option is enabled, coreboot will pass a
+	  framebuffer entry in its coreboot table and the payload will need a
+	  framebuffer driver. If this option is disabled, coreboot will switch
+	  back to text mode before handing control to a payload.
 
 config BOOTSPLASH
 	prompt "Show graphical bootsplash"
 	bool
-	depends on PCI_OPTION_ROM_RUN_YABEL
+	depends on FRAMEBUFFER_SET_VESA_MODE
 	help
 	  This option shows a graphical bootsplash screen. The grapics are
 	  loaded from the CBFS file bootsplash.jpg.
@@ -515,29 +592,6 @@
 	help
 	  The path and filename of the file to use as graphical bootsplash
 	  screen. The file format has to be jpg.
-
-# TODO: Turn this into a "choice".
-config FRAMEBUFFER_VESA_MODE
-	prompt "VESA framebuffer video mode"
-	hex
-	default 0x117
-	depends on BOOTSPLASH
-	help
-	  This option sets the resolution used for the coreboot framebuffer and
-	  bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
-	  some day make this a "choice".
-
-config COREBOOT_KEEP_FRAMEBUFFER
-	prompt "Keep VESA framebuffer"
-	bool
-	depends on BOOTSPLASH
-	help
-	  This option keeps the framebuffer mode set after coreboot finishes
-	  execution. If this option is enabled, coreboot will pass a
-	  framebuffer entry in its coreboot table and the payload will need a
-	  framebuffer driver. If this option is disabled, coreboot will switch
-	  back to text mode before handing control to a payload.
-
 endmenu
 
 menu "Debugging"
@@ -809,6 +863,23 @@
 	  Put llshell() in your (romstage) code to start the shell.
 	  See src/arch/x86/llshell/llshell.inc for details.
 
+if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible with the right southbridge and loglevel.
+config DEBUG_INTEL_ME
+	bool "Verbose logging for Intel Management Engine"
+	default n
+	help
+	  Enable verbose logging for Intel Management Engine driver that
+	  is present on Intel 6-series chipsets.
+endif
+
+config DEBUG_CBFS
+	bool "Output verbose CBFS debug messages"
+	default n
+	help
+	  This option enables additional CBFS related debug messages when
+	  enabling console loglevel SPEW.
+
 endmenu
 
 config LIFT_BSP_APIC_ID
@@ -876,3 +947,4 @@
 	  Internal option that controls ENABLE_POWER_BUTTON visibility.
 
 source src/Kconfig.deprecated_options
+source src/vendorcode/Kconfig
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index f98cf5b..c173938 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -91,6 +91,14 @@
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMSET
+	bool
+	default y
+
+config HAVE_ARCH_MEMCPY
+	bool
+	default y
+
 config BIG_ENDIAN
 	bool
 	default n
diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc
index f076238..5204ad1 100644
--- a/src/arch/x86/Makefile.bootblock.inc
+++ b/src/arch/x86/Makefile.bootblock.inc
@@ -3,9 +3,11 @@
 
 $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
-	rm -f $@
-	cp $(obj)/coreboot.pre1 $@
-	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	cp $(obj)/coreboot.pre1 $@.tmp
+	$(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \
+            $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	mv $@.tmp $@
+
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8c1a887..7abc34f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -58,13 +58,15 @@
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \
 	$(foreach file,$(cbfs-files), \
-		$(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); )
+	$(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \
+	$(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \
+	$(call extract_nth,4,$(file)) &&)
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
 $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL)
-	rm -f $@
-	$(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
-	$(prebuild-files)
+	$(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
+	$(prebuild-files) true
+	mv $@.tmp $@
 else
 $(obj)/coreboot.pre1: $(CBFSTOOL)
 	mv $(obj)/coreboot.rom $@
@@ -206,13 +208,6 @@
 
 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_disable.inc
-endif
-ifeq ($(CONFIG_MMX),y)
-crt0s += $(src)/cpu/x86/mmx_disable.inc
-endif
-
 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
 crt0s += $(chipset_bootblock_inc)
 ldscripts += $(chipset_bootblock_lds)
@@ -240,7 +235,8 @@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
 	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $^ > $@.tmp
+	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
+		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
 	mv $@.tmp $@
 endif
 
diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc
index d4a377f..3f11c01 100644
--- a/src/arch/x86/boot/Makefile.inc
+++ b/src/arch/x86/boot/Makefile.inc
@@ -6,8 +6,10 @@
 ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
 ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
 
 $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H)
+$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h
 
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 957ec45..7de6674 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -29,8 +29,12 @@
 #include <string.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
+#include <arch/io.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 
 u8 acpi_checksum(u8 *table, u32 length)
 {
@@ -472,8 +476,12 @@
 
 	/* If we happen to be resuming find wakeup vector and jump to OS. */
 	wake_vec = acpi_find_wakeup_vector();
-	if (wake_vec)
+	if (wake_vec) {
+		/* Call mainboard resume handler first, if defined. */
+		if (mainboard_suspend_resume)
+			mainboard_suspend_resume();
 		acpi_jump_to_wakeup(wake_vec);
+	}
 }
 
 /* This is to be filled by SB code - startup value what was found. */
@@ -598,6 +606,10 @@
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_ACPI_WAKE_JUMP);
+#endif
+
 	acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
 		       HIGH_MEMORY_SAVE);
 }
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index e8cd724..e62aa47 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -26,6 +26,7 @@
 #define ACPIGEN_MAXLEN 0xfff
 
 #include <string.h>
+#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -35,7 +36,7 @@
 char *len_stack[ACPIGEN_LENSTACK_SIZE];
 int ltop = 0;
 
-static int acpigen_write_len_f(void)
+int acpigen_write_len_f(void)
 {
 	ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1))
 	    len_stack[ltop++] = gencurrent;
@@ -71,6 +72,26 @@
 	return 1;
 }
 
+int acpigen_write_register(acpi_addr_t *addr)
+{
+	acpigen_emit_byte(0x82);		/* Register Descriptor */
+	acpigen_emit_byte(0x0c);		/* Register Length 7:0 */
+	acpigen_emit_byte(0x00);		/* Register Length 15:8 */
+	acpigen_emit_byte(addr->space_id);	/* Address Space ID */
+	acpigen_emit_byte(addr->bit_width);	/* Register Bit Width */
+	acpigen_emit_byte(addr->bit_offset);	/* Register Bit Offset */
+	acpigen_emit_byte(addr->resv);		/* Register Access Size */
+	acpigen_emit_byte(addr->addrl & 0xff);	/* Register Address Low */
+	acpigen_emit_byte((addr->addrl >> 8) & 0xff);
+	acpigen_emit_byte((addr->addrl >> 16) & 0xff);
+	acpigen_emit_byte((addr->addrl >> 24) & 0xff);
+	acpigen_emit_byte(addr->addrh & 0xff);	/* Register Address High */
+	acpigen_emit_byte((addr->addrh >> 8) & 0xff);
+	acpigen_emit_byte((addr->addrh >> 16) & 0xff);
+	acpigen_emit_byte((addr->addrh >> 24) & 0xff);
+	return 15;
+}
+
 int acpigen_write_package(int nr_el)
 {
 	int len;
@@ -89,6 +110,15 @@
 	return 2;
 }
 
+int acpigen_write_word(unsigned int data)
+{
+	/* word op */
+	acpigen_emit_byte(0xb);
+	acpigen_emit_byte(data & 0xff);
+	acpigen_emit_byte((data >> 8) & 0xff);
+	return 3;
+}
+
 int acpigen_write_dword(unsigned int data)
 {
 	/* dword op */
@@ -315,6 +345,59 @@
 	return acpigen_emit_stream(stream, ARRAY_SIZE(stream));
 }
 
+int acpigen_write_empty_PTC(void)
+{
+/*
+    Name (_PTC, Package (0x02)
+    {
+        ResourceTemplate ()
+        {
+            Register (FFixedHW,
+                0x00,               // Bit Width
+                0x00,               // Bit Offset
+                0x0000000000000000, // Address
+                ,)
+        },
+
+        ResourceTemplate ()
+        {
+            Register (FFixedHW,
+                0x00,               // Bit Width
+                0x00,               // Bit Offset
+                0x0000000000000000, // Address
+                ,)
+        }
+    })
+*/
+	int len, nlen, rlen;
+	acpi_addr_t addr = {
+		.space_id   = ACPI_ADDRESS_SPACE_FIXED,
+		.bit_width  = 0,
+		.bit_offset = 0,
+		.resv       = 0,
+		.addrl      = 0,
+		.addrh      = 0,
+	};
+
+	nlen = acpigen_write_name("_PTC");
+	len = acpigen_write_package(2);
+
+	/* ControlRegister */
+	rlen = acpigen_write_resourcetemplate_header();
+	rlen += acpigen_write_register(&addr);
+	len += acpigen_write_resourcetemplate_footer(rlen);
+	len += rlen;
+
+	/* StatusRegister */
+	rlen = acpigen_write_resourcetemplate_header();
+	rlen += acpigen_write_register(&addr);
+	len += acpigen_write_resourcetemplate_footer(rlen);
+	len += rlen;
+
+	acpigen_patch_len(len - 1);
+	return len + nlen;
+}
+
 /* generates a func with max supported P states */
 int acpigen_write_PPC(u8 nr)
 {
@@ -341,6 +424,91 @@
 	return len;
 }
 
+int acpigen_write_TPC(const char *gnvs_tpc_limit)
+{
+/*
+    // Sample _TPC method
+    Method (_TPC, 0, NotSerialized)
+    {
+        Return (\TLVL)
+    }
+ */
+	int len;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_TPC");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+	len += acpigen_emit_byte(0xa4);		/* ReturnOp */
+	len += acpigen_emit_namestring(gnvs_tpc_limit);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+int acpigen_write_CST_package(u8 level, acpi_cstate_t *cstate)
+{
+/*
+    // Sample C2 state _CST package
+    Package (0x04)
+    {
+        ResourceTemplate ()
+        {
+            Register (SystemIO,
+                0x08,               // Register Bit Width
+                0x00,               // Register Bit Offset
+                0x0000000000000514, // Register Address
+            )
+        },
+        0x02,
+        0x0002,
+        0x000001F4
+    }
+ */
+	int len, rlen;
+	len = acpigen_write_package(4);
+	rlen = acpigen_write_resourcetemplate_header();
+	rlen += acpigen_write_register(&cstate->resource);
+	len += acpigen_write_resourcetemplate_footer(rlen);
+	len += rlen;
+	len += acpigen_write_byte((level > 3) ? 3 : level);
+	len += acpigen_write_word(cstate->latency);
+	len += acpigen_write_dword(cstate->power);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list)
+{
+/*
+    // Sample _TSS package with 100% and 50% duty cycles
+    Name (_TSS, Package (0x02)
+    {
+        Package(){100, 1000, 0, 0x00, 0)
+        Package(){50, 520, 0, 0x18, 0)
+    })
+ */
+	int i, len, plen, nlen;
+	acpi_tstate_t *tstate = tstate_list;
+
+	nlen = acpigen_write_name("_TSS");
+	plen = acpigen_write_package(entries);
+
+	for (i = 0; i < entries; i++) {
+		len = acpigen_write_package(5);
+		len += acpigen_write_dword(tstate->percent);
+		len += acpigen_write_dword(tstate->power);
+		len += acpigen_write_dword(tstate->latency);
+		len += acpigen_write_dword(tstate->control);
+		len += acpigen_write_dword(tstate->status);
+		acpigen_patch_len(len - 1);
+		tstate++;
+		plen += len;
+	}
+
+	acpigen_patch_len(plen - 1);
+	return plen + nlen;
+}
+
 int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
 			      u32 busmLat, u32 control, u32 status)
 {
@@ -354,6 +522,10 @@
 	len += acpigen_write_dword(status);
 	//pkglen without the len opcode
 	acpigen_patch_len(len - 1);
+
+	printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n",
+	       coreFreq, power, control, status);
+
 	return len;
 }
 
@@ -374,6 +546,23 @@
 	return len + lenh;
 }
 
+int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
+{
+	int len, lenh, lenp;
+	lenh = acpigen_write_name("_TSD");
+	lenp = acpigen_write_package(1);
+	len = acpigen_write_package(5);
+	len += acpigen_write_byte(5);	// 5 values
+	len += acpigen_write_byte(0);	// revision 0
+	len += acpigen_write_dword(domain);
+	len += acpigen_write_dword(coordtype);
+	len += acpigen_write_dword(numprocs);
+	acpigen_patch_len(len - 1);
+	len += lenp;
+	acpigen_patch_len(len - 1);
+	return len + lenh;
+}
+
 int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
 {
 	/*
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index db3a8a9..524da6a 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -29,9 +29,21 @@
 #include <version.h>
 #include <device/device.h>
 #include <stdlib.h>
-#if (CONFIG_USE_OPTION_TABLE == 1)
-#include <option_table.h>
 #include <cbfs.h>
+#include <cbmem.h>
+#if CONFIG_USE_OPTION_TABLE
+#include <option_table.h>
+#endif
+#if CONFIG_CHROMEOS
+#include <arch/acpi.h>
+#endif
+#if CONFIG_ADD_FDT
+#include <fdt/fdt.h>
+#include <fdt/libfdt.h>
+#include <fdt/libfdt_env.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
 #endif
 
 static struct lb_header *lb_table_init(unsigned long addr)
@@ -91,7 +103,6 @@
 	return rec;
 }
 
-
 static struct lb_memory *lb_memory(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -112,14 +123,32 @@
 	serial = (struct lb_serial *)rec;
 	serial->tag = LB_TAG_SERIAL;
 	serial->size = sizeof(*serial);
-	serial->ioport = CONFIG_TTYS0_BASE;
+	serial->type = LB_SERIAL_TYPE_IO_MAPPED;
+	serial->baseaddr = CONFIG_TTYS0_BASE;
 	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
+#elif CONFIG_CONSOLE_SERIAL8250MEM
+	if (uartmem_getbaseaddr()) {
+		struct lb_record *rec;
+		struct lb_serial *serial;
+		rec = lb_new_record(header);
+		serial = (struct lb_serial *)rec;
+		serial->tag = LB_TAG_SERIAL;
+		serial->size = sizeof(*serial);
+		serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+		serial->baseaddr = uartmem_getbaseaddr();
+		serial->baud = CONFIG_TTYS0_BAUD;
+		return serial;
+	} else {
+		return NULL;
+	}
 #else
 	return NULL;
 #endif
 }
 
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \
+    CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG
 static void add_console(struct lb_header *header, u16 consoletype)
 {
 	struct lb_console *console;
@@ -129,6 +158,7 @@
 	console->size = sizeof(*console);
 	console->type = consoletype;
 }
+#endif
 
 static void lb_console(struct lb_header *header)
 {
@@ -148,7 +178,7 @@
 
 static void lb_framebuffer(struct lb_header *header)
 {
-#if CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER
+#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
 	void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
 
 	struct lb_framebuffer *framebuffer;
@@ -159,6 +189,187 @@
 #endif
 }
 
+#if CONFIG_CHROMEOS
+static void lb_gpios(struct lb_header *header)
+{
+	struct lb_gpios *gpios;
+	gpios = (struct lb_gpios *)lb_new_record(header);
+	gpios->tag = LB_TAG_GPIO;
+	gpios->size = sizeof(*gpios);
+	gpios->count = 0;
+	fill_lb_gpios(gpios);
+}
+
+static void lb_vdat(struct lb_header *header)
+{
+	struct lb_vdat* vdat;
+
+	vdat = (struct lb_vdat *)lb_new_record(header);
+	vdat->tag = LB_TAG_VDAT;
+	vdat->size = sizeof(*vdat);
+	acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size);
+}
+
+static void lb_vbnv(struct lb_header *header)
+{
+	struct lb_vbnv* vbnv;
+
+	vbnv = (struct lb_vbnv *)lb_new_record(header);
+	vbnv->tag = LB_TAG_VBNV;
+	vbnv->size = sizeof(*vbnv);
+	vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14;
+	vbnv->vbnv_size = CONFIG_VBNV_SIZE;
+
+}
+#endif
+
+#if CONFIG_ADD_FDT
+static void lb_map_lb_serial_to_fdt(struct fdt_header *fdt_header, struct lb_serial *serial)
+{
+	char serial_node_name[64];
+	const int name_len = ARRAY_SIZE(serial_node_name) - 1;
+	serial_node_name[name_len] = 0;
+	int root_offset = fdt_path_offset(fdt_header, "/");
+
+	/* Pick a name for the serial node. */
+	if (serial) {
+		sprintf(serial_node_name, "serial@%x", serial->baseaddr);
+	} else {
+		strncpy(serial_node_name, "null-serial@0", name_len);
+	}
+
+	/* Find or create the /aliases node. */
+	int alias_offset = fdt_path_offset(fdt_header, "/aliases");
+	if (alias_offset < 0) {
+		/* It wasn't found, so try to create it. */
+		alias_offset = fdt_add_subnode(fdt_header, root_offset,
+			"/aliases");
+	}
+	if (alias_offset < 0)
+		printk(BIOS_ERR, "Couldn't find/make fdt \"aliases\" node.\n");
+
+	/* Add a "console" property, and point it at the serial node. */
+	if (alias_offset >= 0) {
+		char alias[name_len + 2];
+		sprintf(alias, "/%s", serial_node_name);
+		fdt_setprop_string(fdt_header, alias_offset, "console", alias);
+	}
+
+	/* Add the serial node itself. */
+	int serial_offset =
+		fdt_add_subnode(fdt_header, root_offset, serial_node_name);
+	if (serial_offset < 0) {
+		printk(BIOS_ERR, "Couldn't create serial node \"%s\"\n",
+			serial_node_name);
+	}
+
+	/* If there's a serial node and device, populate the node. */
+	if (serial_offset >= 0 && serial) {
+		fdt_setprop_string(fdt_header, serial_offset,
+			"compatible", "ns16550");
+		uint32_t reg[2] = {
+			cpu_to_fdt32(serial->baseaddr),
+			cpu_to_fdt32(0x8)
+		};
+		fdt_setprop(fdt_header, serial_offset,
+			"reg", reg, sizeof(reg));
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"id", 1);
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"reg-shift", 1);
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"baudrate", serial->baud);
+#if CONFIG_DRIVERS_OXFORD_OXPCIE
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"clock-frequency", 4000000);
+#else
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"clock-frequency", 115200);
+#endif
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"multiplier", 1);
+		if (serial->type == LB_SERIAL_TYPE_IO_MAPPED) {
+			fdt_setprop_cell(fdt_header, serial_offset,
+				"io-mapped", 1);
+		}
+		fdt_setprop_string(fdt_header, serial_offset,
+			"status", "ok");
+	}
+}
+
+static void lb_fdt(struct lb_header *header, struct lb_serial *serial)
+{
+	struct lb_fdt *fdt_record;
+	struct fdt_header *fdt_header;
+	u32 magic, fdt_size;
+
+	fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT);
+	if (!fdt_header) {
+		printk(BIOS_ERR, "Can't find FDT (%s)\n", CONFIG_FDT_FILE_NAME);
+		return;
+	}
+
+	magic = fdt32_to_cpu(fdt_header->magic);
+	if (magic != FDT_MAGIC) {
+		printk(BIOS_ERR, "FDT header corrupted (0x%x)\n", magic);
+		return;
+	}
+
+	fdt_size = fdt32_to_cpu(fdt_header->totalsize);
+	fdt_record = (struct lb_fdt *) lb_new_record(header);
+	fdt_record->tag = LB_TAG_FDT;
+	fdt_record->size = sizeof(*fdt_record) + fdt_size;
+	memcpy(fdt_record + 1, fdt_header, fdt_size);
+	fdt_header = (struct fdt_header *)(fdt_record + 1);
+
+#if CONFIG_CHROMEOS
+	chromeos_set_vboot_data_ptr(fdt_header);
+#endif
+
+	lb_map_lb_serial_to_fdt(fdt_header, serial);
+
+	fdt_size = fdt32_to_cpu(fdt_header->totalsize);
+	fdt_record->size = sizeof(*fdt_record) + fdt_size;
+
+	printk(BIOS_SPEW, "FDT of %d bytes added\n", fdt_size);
+}
+#endif
+
+static void add_cbmem_pointers(struct lb_header *header)
+{
+	/*
+	 * These CBMEM sections' addresses are included in the coreboot table
+	 * with the appropriate tags.
+	 */
+	const struct section_id {
+		int cbmem_id;
+		int table_tag;
+	} section_ids[] = {
+		{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
+		{CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE},
+		{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
+		const struct section_id *sid = section_ids + i;
+		struct lb_cbmem_ref *cbmem_ref;
+		void *cbmem_addr = cbmem_find(sid->cbmem_id);
+
+		if (!cbmem_addr)
+			continue;  /* This section is not present */
+
+		cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
+		if (!cbmem_ref) {
+			printk(BIOS_ERR, "No more room in coreboot table!\n");
+			break;
+		}
+		cbmem_ref->tag = sid->table_tag;
+		cbmem_ref->size = sizeof(*cbmem_ref);
+		cbmem_ref->cbmem_addr = cbmem_addr;
+	}
+}
+
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -183,7 +394,7 @@
 	return mainboard;
 }
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -305,9 +516,10 @@
 	head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
 	head->header_checksum = 0;
 	head->header_checksum = compute_ip_checksum(head, sizeof(*head));
-	printk(BIOS_DEBUG, "Wrote coreboot table at: %p - %p  checksum %x\n",
-		head, rec, head->table_checksum);
-	return (unsigned long)rec;
+	printk(BIOS_DEBUG,
+	       "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n",
+	       head, head->table_bytes, head->table_checksum);
+	return (unsigned long)rec + rec->size;
 }
 
 static void lb_cleanup_memory_ranges(struct lb_memory *mem)
@@ -497,10 +709,6 @@
 		lb_add_rsvd_range, mem);
 }
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
-extern uint64_t high_tables_base, high_tables_size;
-#endif
-
 unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end)
@@ -508,7 +716,7 @@
 	struct lb_header *head;
 	struct lb_memory *mem;
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
@@ -544,7 +752,7 @@
 	rom_table_end &= ~0xffff;
 	printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 	{
 		struct cmos_option_table *option_table = cbfs_find_file("cmos_layout.bin", 0x1aa);
 		if (option_table) {
@@ -569,7 +777,7 @@
 	lb_add_memory_range(mem, LB_MEM_TABLE,
 		rom_table_start, rom_table_end-rom_table_start);
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Adding high table area\n");
 	// should this be LB_MEM_ACPI?
 	lb_add_memory_range(mem, LB_MEM_TABLE,
@@ -579,7 +787,7 @@
 	/* Add reserved regions */
 	add_lb_reserved(mem);
 
-#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
 	add_mainboard_resources(mem);
 #endif
 
@@ -595,7 +803,8 @@
 	/* Record our motherboard */
 	lb_mainboard(head);
 	/* Record the serial port, if present */
-	lb_serial(head);
+	struct lb_serial *serial;
+	serial = lb_serial(head);
 	/* Record our console setup */
 	lb_console(head);
 	/* Record our various random string information */
@@ -603,6 +812,25 @@
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+#if CONFIG_CHROMEOS
+	/* Record our GPIO settings (ChromeOS specific) */
+	lb_gpios(head);
+
+	/* pass along the VDAT buffer adress */
+	lb_vdat(head);
+
+	/* pass along VBNV offsets in CMOS */
+	lb_vbnv(head);
+#endif
+#if CONFIG_ADD_FDT
+	/*
+	 * Copy FDT from CBFS into the coreboot table possibly augmenting it
+	 * along the way.
+	 */
+	lb_fdt(head, serial);
+#endif
+	add_cbmem_pointers(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
new file mode 100644
index 0000000..dc0c53d
--- /dev/null
+++ b/src/arch/x86/boot/smbios.c
@@ -0,0 +1,308 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <smbios.h>
+#include <console/console.h>
+#include <build.h>
+#include <device/device.h>
+#include <arch/cpu.h>
+#include <cpu/x86/name.h>
+#include <cbfs.h>
+#include <arch/byteorder.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
+
+static u8 smbios_checksum(u8 *p, u32 length)
+{
+	u8 ret = 0;
+	while (length--)
+		ret += *p++;
+	return -ret;
+}
+
+
+int smbios_add_string(char *start, const char *str)
+{
+	int i = 1;
+	char *p = start;
+
+	for(;;) {
+		if (!*p) {
+			strcpy(p, str);
+			p += strlen(str);
+			*p++ = '\0';
+			*p++ = '\0';
+			return i;
+		}
+
+		if (!strcmp(p, str))
+			return i;
+
+		p += strlen(p)+1;
+		i++;
+	}
+}
+
+int smbios_string_table_len(char *start)
+{
+	char *p = start;
+	int i, len = 0;
+
+	while(*p) {
+		i = strlen(p) + 1;
+		p += i;
+		len += i;
+	}
+	return len + 1;
+}
+
+static int smbios_cpu_vendor(char *start)
+{
+	char tmp[13];
+	u32 *_tmp = (u32 *)tmp;
+	struct cpuid_result res = cpuid(0);
+
+	_tmp[0] = res.ebx;
+	_tmp[1] = res.edx;
+	_tmp[2] = res.ecx;
+	tmp[12] = '\0';
+	return smbios_add_string(start, tmp);
+
+}
+
+static int smbios_processor_name(char *start)
+{
+	char tmp[49];
+	u32  *_tmp = (u32 *)tmp;
+	struct cpuid_result res;
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		res = cpuid(0x80000002 + i);
+		_tmp[i * 4 + 0] = res.eax;
+		_tmp[i * 4 + 1] = res.ebx;
+		_tmp[i * 4 + 2] = res.ecx;
+		_tmp[i * 4 + 3] = res.edx;
+	}
+
+	tmp[48] = 0;
+	return smbios_add_string(start, tmp);
+}
+
+static int smbios_write_type0(unsigned long *current, int handle)
+{
+	struct cbfs_header *hdr;
+	struct smbios_type0 *t = (struct smbios_type0 *)*current;
+	int len = sizeof(struct smbios_type0);
+
+	memset(t, 0, sizeof(struct smbios_type0));
+	t->type = SMBIOS_BIOS_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+
+	t->vendor = smbios_add_string(t->eos, "coreboot");
+#if !CONFIG_CHROMEOS
+	t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
+	t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+#else
+#define SPACES \
+	"                                                                  "
+	t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
+	u32 version_offset = (u32)smbios_string_table_len(t->eos);
+	t->bios_version = smbios_add_string(t->eos, SPACES);
+	/* SMBIOS offsets start at 1 rather than 0 */
+	vboot_data->vbt10 = (u32)t->eos + (version_offset - 1);
+#endif
+
+	if ((hdr = get_cbfs_header()) != (struct cbfs_header *)0xffffffff)
+		t->bios_rom_size = (ntohl(hdr->romsize) / 65535) - 1;
+	t->system_bios_major_release = 4;
+	t->bios_characteristics =
+		BIOS_CHARACTERISTICS_PCI_SUPPORTED |
+#if CONFIG_CARDBUS_PLUGIN_SUPPORT
+		BIOS_CHARACTERISTICS_PC_CARD |
+#endif
+		BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
+		BIOS_CHARACTERISTICS_UPGRADEABLE;
+
+#if CONFIG_GENERATE_ACPI_TABLES
+	t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
+#endif
+	t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type1(unsigned long *current, int handle)
+{
+	struct smbios_type1 *t = (struct smbios_type1 *)*current;
+	int len = sizeof(struct smbios_type1);
+
+	memset(t, 0, sizeof(struct smbios_type1));
+	t->type = SMBIOS_SYSTEM_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR);
+	t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER);
+	t->serial_number = smbios_add_string(t->eos, "123456789");
+	t->version = smbios_add_string(t->eos, "1.0");
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type3(unsigned long *current, int handle)
+{
+	struct smbios_type3 *t = (struct smbios_type3 *)*current;
+	int len = sizeof(struct smbios_type3);
+
+	memset(t, 0, sizeof(struct smbios_type3));
+	t->type = SMBIOS_SYSTEM_ENCLOSURE;
+	t->handle = handle;
+	t->length = len - 2;
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR);
+	t->bootup_state = SMBIOS_STATE_SAFE;
+	t->power_supply_state = SMBIOS_STATE_SAFE;
+	t->thermal_state = SMBIOS_STATE_SAFE;
+	t->_type = 3;
+	t->security_status = SMBIOS_STATE_SAFE;
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type4(unsigned long *current, int handle)
+{
+	struct cpuid_result res;
+	struct smbios_type4 *t = (struct smbios_type4 *)*current;
+	int len = sizeof(struct smbios_type4);
+
+	res = cpuid(1);
+
+	memset(t, 0, sizeof(struct smbios_type4));
+	t->type = SMBIOS_PROCESSOR_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+	t->processor_id[0] = res.eax;
+	t->processor_id[1] = res.edx;
+	t->processor_manufacturer = smbios_cpu_vendor(t->eos);
+	t->processor_version = smbios_processor_name(t->eos);
+	t->processor_family = 0x0c;
+	t->processor_type = 3; /* System Processor */
+	t->processor_upgrade = 0x06;
+	t->core_count = (res.ebx >> 16) & 0xff;
+	t->l1_cache_handle = 0xffff;
+	t->l2_cache_handle = 0xffff;
+	t->l3_cache_handle = 0xffff;
+	t->processor_upgrade = 1;
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type32(unsigned long *current, int handle)
+{
+	struct smbios_type32 *t = (struct smbios_type32 *)*current;
+	int len = sizeof(struct smbios_type32);
+
+	memset(t, 0, sizeof(struct smbios_type32));
+	t->type = SMBIOS_SYSTEM_BOOT_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type127(unsigned long *current, int handle)
+{
+	struct smbios_type127 *t = (struct smbios_type127 *)*current;
+	int len = sizeof(struct smbios_type127);
+
+	memset(t, 0, sizeof(struct smbios_type127));
+	t->type = SMBIOS_END_OF_TABLE;
+	t->handle = handle;
+	t->length = len - 2;
+	*current += len;
+	return len;
+}
+
+static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current)
+{
+	device_t dev;
+	int len = 0;
+
+	for(dev = tree; dev; dev = dev->next) {
+		printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev->chip_ops ? dev->chip_ops->name : "");
+
+		if (dev->ops && dev->ops->get_smbios_data)
+			len += dev->ops->get_smbios_data(dev, handle, current);
+
+		if (dev->chip_ops && dev->chip_ops->get_smbios_data)
+			len += dev->chip_ops->get_smbios_data(dev, handle, current);
+	}
+	return len;
+}
+
+unsigned long smbios_write_tables(unsigned long current)
+{
+	struct smbios_entry *se;
+	unsigned long tables;
+	int len, handle = 0;
+
+	current = ALIGN(current, 16);
+	printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current);
+
+	se = (struct smbios_entry *)current;
+	current += sizeof(struct smbios_entry);
+	current = ALIGN(current, 16);
+
+	tables = current;
+	len = smbios_write_type0(&current, handle++);
+	len += smbios_write_type1(&current, handle++);
+	len += smbios_write_type3(&current, handle++);
+	len += smbios_write_type4(&current, handle++);
+	len += smbios_write_type32(&current, handle++);
+
+	len += smbios_walk_device_tree(all_devices, &handle, &current);
+
+	len += smbios_write_type127(&current, handle++);
+
+	memset(se, 0, sizeof(struct smbios_entry));
+	memcpy(se->anchor, "_SM_", 4);
+	se->length = sizeof(struct smbios_entry);
+	se->major_version = 2;
+	se->minor_version = 7;
+	se->max_struct_size = 24;
+	se->struct_count = handle;
+	memcpy(se->intermediate_anchor_string, "_DMI_", 5);
+
+	se->struct_table_address = (u32)tables;
+	se->struct_table_length = len;
+
+	se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10,
+						    sizeof(struct smbios_entry) - 0x10);
+	se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry));
+	return current;
+}
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index d816e76..b7dc4fe 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -31,6 +31,7 @@
 #include <cpu/x86/multiboot.h>
 #include <cbmem.h>
 #include <lib.h>
+#include <smbios.h>
 
 uint64_t high_tables_base = 0;
 uint64_t high_tables_size;
@@ -120,7 +121,7 @@
 #endif /* CONFIG_GENERATE_MP_TABLE */
 
 #if CONFIG_GENERATE_ACPI_TABLES == 1
-#define MAX_ACPI_SIZE (47 * 1024)
+#define MAX_ACPI_SIZE (45 * 1024)
 	post_code(0x9c);
 
 	/* Write ACPI tables to F segment and high tables area */
@@ -178,9 +179,30 @@
 	}
 
 #endif
+#define MAX_SMBIOS_SIZE 2048
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE);
+	if (high_table_pointer) {
+		unsigned long new_high_table_pointer;
 
+		new_high_table_pointer = smbios_write_tables(high_table_pointer);
+		rom_table_end = ALIGN(rom_table_end, 16);
+		memcpy((void *)rom_table_end, (void *)high_table_pointer, sizeof(struct smbios_entry));
+		rom_table_end += sizeof(struct smbios_entry);
 
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+		if (new_high_table_pointer > ( high_table_pointer + MAX_SMBIOS_SIZE)) {
+			printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n");
+		}
+                printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n",
+				new_high_table_pointer - high_table_pointer);
+	} else {
+		unsigned long new_rom_table_end = smbios_write_tables(rom_table_end);
+		printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - rom_table_end);
+		rom_table_end = ALIGN(new_rom_table_end, 16);
+	}
+#endif
+
+#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
 	post_code(0x9d);
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S
index a1df4d5..2f3f6eb 100644
--- a/src/arch/x86/boot/wakeup.S
+++ b/src/arch/x86/boot/wakeup.S
@@ -38,23 +38,11 @@
 	movw	%ax, (__wakeup_segment)
 
 	/* Then overwrite coreboot with our backed up memory */
-	movl 8(%esp), %esi
-	movl 12(%esp), %edi
-	movl 16(%esp), %ecx
-	shrl	$4, %ecx
-1:
-	movl	0(%esi),%eax
-	movl	4(%esi),%edx
-	movl	8(%esi),%ebx
-	movl	12(%esi),%ebp
-	addl	$16,%esi
-	subl	$1,%ecx
-	movl	%eax,0(%edi)
-	movl	%edx,4(%edi)
-	movl	%ebx,8(%edi)
-	movl	%ebp,12(%edi)
-	leal	16(%edi),%edi
-	jne	1b
+	movl	8(%esp), %esi
+	movl	12(%esp), %edi
+	movl	16(%esp), %ecx
+	shrl	$2, %ecx
+	rep	movsl
 
 	/* Activate the right segment descriptor real mode. */
 	ljmp	$0x28, $RELOCATED(1f)
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d..dc674d0 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -66,6 +66,12 @@
 #define ACPI_ADDRESS_SPACE_EC		   3	/* Embedded controller */
 #define ACPI_ADDRESS_SPACE_SMBUS	   4	/* SMBus */
 #define ACPI_ADDRESS_SPACE_FIXED	0x7f	/* Functional fixed hardware */
+#define  ACPI_FFIXEDHW_VENDOR_INTEL	   1	/* Intel */
+#define  ACPI_FFIXEDHW_CLASS_HLT	   0	/* C1 Halt */
+#define  ACPI_FFIXEDHW_CLASS_IO_HLT	   1	/* C1 I/O then Halt */
+#define  ACPI_FFIXEDHW_CLASS_MWAIT	   2    /* MWAIT Native C-state */
+#define  ACPI_FFIXEDHW_FLAG_HW_COORD	   1	/* Hardware Coordination bit */
+#define  ACPI_FFIXEDHW_FLAG_BM_STS  	   2	/* BM_STS avoidance bit */
 /* 0x80-0xbf: Reserved */
 /* 0xc0-0xff: OEM defined */
 
@@ -357,6 +363,20 @@
 	u8 ec_id[];				/* EC ID  */
 } __attribute__ ((packed)) acpi_ecdt_t;
 
+typedef struct acpi_cstate {
+	u16 latency;
+	u32 power;
+	acpi_addr_t resource;
+} __attribute__ ((packed)) acpi_cstate_t;
+
+typedef struct acpi_tstate {
+	u32 percent;
+	u32 power;
+	u32 latency;
+	u32 control;
+	u32 status;
+} __attribute__ ((packed)) acpi_tstate_t;
+
 /* These are implemented by the target port or north/southbridge. */
 unsigned long write_acpi_tables(unsigned long addr);
 unsigned long acpi_fill_madt(unsigned long current);
@@ -417,12 +437,14 @@
 extern u8 acpi_slp_type;
 
 void suspend_resume(void);
+void __attribute__((weak)) mainboard_suspend_resume(void);
 void *acpi_find_wakeup_vector(void);
 void *acpi_get_wakeup_rsdp(void);
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);
-
+#else
+#define acpi_slp_type 0
 #endif
 
 /* northbridge/amd/amdfam10/amdfam10_acpi.c */
@@ -434,7 +456,11 @@
 #else // CONFIG_GENERATE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
+#define acpi_slp_type 0
 
 #endif
 
+#if CONFIG_CHROMEOS
+void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size);
+#endif
 #endif
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index 6f13a7a..676ed6b 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -24,14 +24,19 @@
 #include <stdlib.h>
 #include <stdint.h>
 
+#include <arch/acpi.h>
+
 void acpigen_patch_len(int len);
 void acpigen_set_current(char *curr);
 char *acpigen_get_current(void);
+int acpigen_write_len_f(void);
 int acpigen_write_package(int nr_el);
+int acpigen_write_register(acpi_addr_t *addr);
 int acpigen_write_byte(unsigned int data);
 int acpigen_emit_byte(unsigned char data);
 int acpigen_emit_stream(const char *data, int size);
 int acpigen_emit_namestring(const char *namepath);
+int acpigen_write_word(unsigned int data);
 int acpigen_write_dword(unsigned int data);
 int acpigen_write_qword(uint64_t data);
 int acpigen_write_name(const char *name);
@@ -40,11 +45,16 @@
 int acpigen_write_name_byte(const char *name, uint8_t val);
 int acpigen_write_scope(const char *name);
 int acpigen_write_PPC(u8 nr);
+int acpigen_write_TPC(const char *gnvs_tpc_limit);
 int acpigen_write_empty_PCT(void);
+int acpigen_write_empty_PTC(void);
+int acpigen_write_CST_package(u8 level, acpi_cstate_t *cstate);
+int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list);
 int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat,
 			u32 control, u32 status);
 typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord;
 int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
+int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
 int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
 int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
 int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16);
diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h
index ab344e6..7ba6290 100644
--- a/src/arch/x86/include/arch/byteorder.h
+++ b/src/arch/x86/include/arch/byteorder.h
@@ -5,10 +5,14 @@
 
 #include <swab.h>
 
+#define cpu_to_le64(x) ((unsigned long)(x))
+#define le64_to_cpu(x) ((unsigned long)(x))
 #define cpu_to_le32(x) ((unsigned int)(x))
 #define le32_to_cpu(x) ((unsigned int)(x))
 #define cpu_to_le16(x) ((unsigned short)(x))
 #define le16_to_cpu(x) ((unsigned short)(x))
+#define cpu_to_be64(x) swab64(x)
+#define be64_to_cpu(x) swab64(x)
 #define cpu_to_be32(x) swab32((x))
 #define be32_to_cpu(x) swab32((x))
 #define cpu_to_be16(x) swab16((x))
diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h
index 773e053..b177949 100644
--- a/src/arch/x86/include/arch/coreboot_tables.h
+++ b/src/arch/x86/include/arch/coreboot_tables.h
@@ -20,4 +20,6 @@
 int add_mainboard_resources(struct lb_memory *mem);
 int add_northbridge_resources(struct lb_memory *mem);
 
+void fill_lb_gpios(struct lb_gpios *gpios);
+
 #endif /* COREBOOT_TABLE_H */
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..14acfdf 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -36,12 +36,36 @@
 {
 	struct cpuid_result result;
 	asm volatile(
-		"cpuid"
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
 		: "=a" (result.eax),
-		  "=b" (result.ebx),
+		  "=S" (result.ebx),
 		  "=c" (result.ecx),
 		  "=d" (result.edx)
-		: "0" (op));
+		: "0" (op)
+		: "edi");
+	return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+	struct cpuid_result result;
+	asm volatile(
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (result.eax),
+		  "=S" (result.ebx),
+		  "=c" (result.ecx),
+		  "=d" (result.edx)
+		: "0" (op), "2" (ecx)
+		: "edi");
 	return result;
 }
 
@@ -52,10 +76,12 @@
 {
 	unsigned int eax;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax)
 		: "0" (op)
-		: "ebx", "ecx", "edx");
+		: "ecx", "edx", "edi");
 	return eax;
 }
 
@@ -63,10 +89,13 @@
 {
 	unsigned int eax, ebx;
 
-	__asm__("cpuid"
-		: "=a" (eax), "=b" (ebx)
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		"mov %%edi, %%esi;"
+		: "=a" (eax), "=S" (ebx)
 		: "0" (op)
-		: "ecx", "edx" );
+		: "ecx", "edx", "edi");
 	return ebx;
 }
 
@@ -74,10 +103,12 @@
 {
 	unsigned int eax, ecx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=c" (ecx)
 		: "0" (op)
-		: "ebx", "edx" );
+		: "edx", "edi");
 	return ecx;
 }
 
@@ -85,10 +116,12 @@
 {
 	unsigned int eax, edx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=d" (edx)
 		: "0" (op)
-		: "ebx", "ecx");
+		: "ecx", "edi");
 	return edx;
 }
 
@@ -113,11 +146,16 @@
 	unsigned device;
 };
 
+struct acpi_cstate;
 struct cpu_driver {
 	struct device_operations *ops;
 	struct cpu_device_id *id_table;
+	struct acpi_cstate *cstates;
 };
 
+struct device;
+struct cpu_driver *find_cpu_driver(struct device *cpu);
+
 struct cpu_info {
 	device_t cpu;
 	unsigned long index;
diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h
new file mode 100644
index 0000000..1de6097
--- /dev/null
+++ b/src/arch/x86/include/arch/ebda.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_EBDA_H
+#define __ARCH_EBDA_H
+
+#define X86_BDA_SIZE		0x200
+#define X86_BDA_BASE		0x400
+#define X86_EBDA_SEGMENT	0x40e
+#define X86_EBDA_LOWMEM		0x413
+
+#define DEFAULT_EBDA_LOWMEM	(1024 << 10)
+#define DEFAULT_EBDA_SEGMENT	0xF600
+#define DEFAULT_EBDA_SIZE	0x400
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size);
+void setup_default_ebda(void);
+
+#endif
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index aad8408..544d6e2 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -6,9 +6,9 @@
 /*
  * This file contains the definitions for the x86 IO instructions
  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
+ * (insb/insw/insl/outsb/outsw/outsl).
  */
+
 #if defined(__ROMCC__)
 static inline void outb(uint8_t value, uint16_t port)
 {
diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h
index 00d2a93..3ddba51 100644
--- a/src/arch/x86/include/arch/stages.h
+++ b/src/arch/x86/include/arch/stages.h
@@ -19,7 +19,6 @@
 
 #ifndef __ARCH_STAGES_H
 #define __ARCH_STAGES_H
-void cbfs_and_run_core(const char *filename, unsigned int ebp);
 void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
 void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr);
 #endif
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index 4c4a092..c53b478 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -1,3 +1,14 @@
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/tsc.h>
+
+static void post_code(uint16_t value)
+{
+	outb(value, 0x80);
+	outb(value >> 8, 0x90);
+}
+
 #if CONFIG_LOGICAL_CPUS && \
  (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
 #include <cpu/x86/lapic/boot_cpu.c>
diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index eab64cf..45b752d 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -50,5 +50,12 @@
 		*(.note.*)
 	}
 
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		*(.car.global_data);
+		*(.car.cbmem_console);
+	}
+
+	_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
 	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");
 }
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3092388..8483b62 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -6,8 +6,15 @@
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memset.c
+ramstage-y += memcpy.c
+ramstage-y += ebda.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memset.c
+romstage-y += memcpy.c
+
+smm-y += memcpy.c
 
 $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h
diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index 5e3d8fe..67e21c3 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -20,16 +20,19 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include <arch/stages.h>
+#include <timestamp.h>
 
-void cbfs_and_run_core(const char *filename, unsigned ebp)
+static void cbfs_and_run_core(const char *filename, unsigned ebp)
 {
 	u8 *dst;
 
+        timestamp_add_now(TS_START_COPYRAM);
 	print_debug("Loading image.\n");
 	dst = cbfs_load_stage(filename);
 	if ((void *)dst == (void *) -1)
 		die("FATAL: Essential component is missing.\n");
 
+        timestamp_add_now(TS_END_COPYRAM);
 	print_debug("Jumping to image.\n");
 	__asm__ volatile (
 		"movl %%eax, %%ebp\n"
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..596a592 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -192,23 +192,27 @@
 	}
 }
 
-static void set_cpu_ops(struct device *cpu)
+struct cpu_driver *find_cpu_driver(struct device *cpu)
 {
 	struct cpu_driver *driver;
-	cpu->ops = 0;
 	for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
 		struct cpu_device_id *id;
-		for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) {
+		for (id = driver->id_table;
+		     id->vendor != X86_VENDOR_INVALID; id++) {
 			if ((cpu->vendor == id->vendor) &&
 				(cpu->device == id->device))
 			{
-				goto found;
+				return driver;
 			}
 		}
 	}
-	return;
- found:
-	cpu->ops = driver->ops;
+	return NULL;
+}
+
+static void set_cpu_ops(struct device *cpu)
+{
+	struct cpu_driver *driver = find_cpu_driver(cpu);
+	cpu->ops = driver ? driver->ops : NULL;
 }
 
 void cpu_initialize(void)
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
new file mode 100644
index 0000000..fb407b6
--- /dev/null
+++ b/src/arch/x86/lib/ebda.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/ebda.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Skip in S3 resume path */
+	if (acpi_slp_type == 3)
+		return;
+#endif
+
+	if (!low_memory_size || !ebda_segment || !ebda_size)
+		return;
+
+	/* clear BIOS DATA AREA */
+	memset((void *)X86_BDA_BASE, 0, X86_BDA_SIZE);
+
+	write16(X86_EBDA_LOWMEM, (low_memory_size >> 10));
+	write16(X86_EBDA_SEGMENT, ebda_segment);
+
+	/* Set up EBDA */
+	memset((void *)(ebda_segment << 4), 0, ebda_size);
+	write16((ebda_segment << 4), (ebda_size >> 10));
+}
+
+void setup_default_ebda(void)
+{
+	setup_ebda(DEFAULT_EBDA_LOWMEM,
+		   DEFAULT_EBDA_SEGMENT,
+		   DEFAULT_EBDA_SIZE);
+}
diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c
new file mode 100644
index 0000000..de21092
--- /dev/null
+++ b/src/arch/x86/lib/memcpy.c
@@ -0,0 +1,13 @@
+#include <string.h>
+
+void *memcpy(void *__restrict __dest,
+	     __const void *__restrict __src, size_t __n)
+{
+	asm("cld\n"
+	    "rep\n"
+	    "movsb"
+	    :	/* no input (?) */
+	    :"S"(__src), "D"(__dest), "c"(__n)
+	);
+	return __dest;
+}
diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c
new file mode 100644
index 0000000..e850726
--- /dev/null
+++ b/src/arch/x86/lib/memset.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* From glibc-2.14, sysdeps/i386/memset.c */
+
+#include <string.h>
+#include <stdint.h>
+
+typedef uint32_t op_t;
+
+void *memset(void *dstpp, int c, size_t len)
+{
+	int d0;
+	unsigned long int dstp = (unsigned long int) dstpp;
+
+	/* This explicit register allocation improves code very much indeed. */
+	register op_t x asm("ax");
+
+	x = (unsigned char) c;
+
+	/* Clear the direction flag, so filling will move forward.  */
+	asm volatile("cld");
+
+	/* This threshold value is optimal.  */
+	if (len >= 12) {
+		/* Fill X with four copies of the char we want to fill with. */
+		x |= (x << 8);
+		x |= (x << 16);
+
+		/* Adjust LEN for the bytes handled in the first loop.  */
+		len -= (-dstp) % sizeof(op_t);
+
+		/*
+		 * There are at least some bytes to set. No need to test for
+		 * LEN == 0 in this alignment loop.
+		 */
+
+		/* Fill bytes until DSTP is aligned on a longword boundary. */
+		asm volatile(
+			"rep\n"
+			"stosb" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
+			"memory");
+
+		/* Fill longwords.  */
+		asm volatile(
+			"rep\n"
+			"stosl" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
+			"memory");
+		len %= sizeof(op_t);
+	}
+
+	/* Write the last few bytes. */
+	asm volatile(
+		"rep\n"
+		"stosb" /* %0, %2, %3 */ :
+		"=D" (dstp), "=c" (d0) :
+		"0" (dstp), "1" (len), "a" (x) :
+		"memory");
+
+	return dstpp;
+}
diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c
index 13ee1f0..0e1f4e6 100644
--- a/src/arch/x86/lib/romcc_console.c
+++ b/src/arch/x86/lib/romcc_console.c
@@ -46,6 +46,9 @@
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void __console_tx_nibble(unsigned nibble)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index a5f2e2b..67e8122 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -35,7 +35,10 @@
 		console_tx_byte('\r');
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
-	uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	if (oxford_oxpcie_present) {
+		uart8250_mem_tx_byte(
+			CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	}
 #endif
 #if CONFIG_CONSOLE_SERIAL8250
 	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
@@ -46,6 +49,9 @@
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 int do_printk(int msg_level, const char *fmt, ...)
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 3d15b55..489caa3 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -41,6 +41,7 @@
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
+#include <timestamp.h>
 
 /**
  * @brief Main function of the RAM part of coreboot.
@@ -56,7 +57,9 @@
 void hardwaremain(int boot_complete)
 {
 	struct lb_memory *lb_mem;
+	tsc_t timestamps[6];
 
+	timestamps[0] = rdtsc();
 	post_code(POST_ENTRY_RAMSTAGE);
 
 	/* console_init() MUST PRECEDE ALL printk()! */
@@ -78,30 +81,51 @@
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
 
+	timestamps[1] = rdtsc();
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
 	post_code(POST_DEVICE_ENUMERATION_COMPLETE);
+
+	timestamps[2] = rdtsc();
 	/* Now compute and assign the bus resources. */
 	dev_configure();
 	post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
+
+	timestamps[3] = rdtsc();
 	/* Now actually enable devices on the bus */
 	dev_enable();
+
+	timestamps[4] = rdtsc();
 	/* And of course initialize devices on the bus */
 	dev_initialize();
 	post_code(POST_DEVICES_ENABLED);
 
+	timestamps[5] = rdtsc();
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 #endif
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	suspend_resume();
 	post_code(0x8a);
 #endif
 
+	timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
+	timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
+	timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]);
+	timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
+	timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
+	timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+	timestamp_add_now(TS_WRITE_TABLES);
+
 	/* Now that we have collected all of our information
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
+
+	timestamp_add_now(TS_LOAD_PAYLOAD);
 	cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
 	printk(BIOS_ERR, "Boot failed.\n");
 }
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index 5f7a8f1..75c9de5 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
 
+#include <arch/byteorder.h>
 #include <console/console.h>
 #include <fallback.h>
 #include <boot/elf.h>
@@ -29,12 +30,8 @@
 #include <string.h>
 #include <cbfs.h>
 #include <lib.h>
-
-#if !CONFIG_BIG_ENDIAN
-#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \
-		((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) )
-#else
-#define ntohl(x) (x)
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
 #endif
 
 /* Maximum physical address we can use for the coreboot bounce buffer.
@@ -49,8 +46,6 @@
 struct segment {
 	struct segment *next;
 	struct segment *prev;
-	struct segment *phdr_next;
-	struct segment *phdr_prev;
 	unsigned long s_dstaddr;
 	unsigned long s_srcaddr;
 	unsigned long s_memsz;
@@ -58,36 +53,6 @@
 	int compression;
 };
 
-struct verify_callback {
-	struct verify_callback *next;
-	int (*callback)(struct verify_callback *vcb,
-		Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head);
-	unsigned long desc_offset;
-	unsigned long desc_addr;
-};
-
-struct ip_checksum_vcb {
-	struct verify_callback data;
-	unsigned short ip_checksum;
-};
-
-static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload);
-
-void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name)
-{
-	struct cbfs_payload *payload;
-
-	payload = (struct cbfs_payload *)cbfs_find_file(name, CBFS_TYPE_PAYLOAD);
-	if (payload == NULL)
-		return (void *) -1;
-	printk(BIOS_DEBUG, "Got a payload\n");
-
-	selfboot(lb_mem, payload);
-	printk(BIOS_EMERG, "SELFBOOT RETURNED!\n");
-
-	return (void *) -1;
-}
-
 /* The problem:
  * Static executables all want to share the same addresses
  * in memory because only a few addresses are reliably present on
@@ -171,15 +136,20 @@
 		mtype = mem->map[i].type;
 		mstart = unpack_lb64(mem->map[i].start);
 		mend = mstart + unpack_lb64(mem->map[i].size);
-		if ((mtype == LB_MEM_RAM) && (start < mend) && (end > mstart)) {
+		if ((mtype == LB_MEM_RAM) && (start >= mstart) && (end < mend)) {
 			break;
 		}
-		if ((mtype == LB_MEM_TABLE) && (start < mend) && (end > mstart)) {
+		if ((mtype == LB_MEM_TABLE) && (start >= mstart) && (end < mend)) {
 			printk(BIOS_ERR, "Payload is overwriting coreboot tables.\n");
 			break;
 		}
 	}
 	if (i == mem_entries) {
+		if (start < (1024*1024) && end <=(1024*1024)) {
+			printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded"
+				" into a reserved area in the lower 1MB\n");
+			return 1;
+		}
 		printk(BIOS_ERR, "No matching ram area found for range:\n");
 		printk(BIOS_ERR, "  [0x%016lx, 0x%016lx)\n", start, end);
 		printk(BIOS_ERR, "Ram areas\n");
@@ -259,11 +229,6 @@
 			new->prev = seg->prev;
 			seg->prev->next = new;
 			seg->prev = new;
-			/* Order by original program header order */
-			new->phdr_next = seg;
-			new->phdr_prev = seg->phdr_prev;
-			seg->phdr_prev->phdr_next = new;
-			seg->phdr_prev = new;
 
 			/* compute the new value of start */
 			start = seg->s_dstaddr;
@@ -299,11 +264,6 @@
 			new->prev = seg;
 			seg->next->prev = new;
 			seg->next = new;
-			/* Order by original program header order */
-			new->phdr_next = seg->phdr_next;
-			new->phdr_prev = seg;
-			seg->phdr_next->phdr_prev = new;
-			seg->phdr_next = new;
 
 			printk(BIOS_SPEW, "   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 				new->s_dstaddr,
@@ -331,13 +291,14 @@
 static int build_self_segment_list(
 	struct segment *head,
 	struct lb_memory *mem,
-	struct cbfs_payload *payload, u32 *entry)
+	struct cbfs_payload *payload,
+	u32 payload_len,
+	u32 *entry)
 {
 	struct segment *new;
 	struct segment *ptr;
 	struct cbfs_payload_segment *segment, *first_segment;
 	memset(head, 0, sizeof(*head));
-	head->phdr_next = head->phdr_prev = head;
 	head->next = head->prev = head;
 	first_segment = segment = &payload->segments;
 
@@ -361,6 +322,13 @@
 
 			new->s_srcaddr = (u32) ((unsigned char *) first_segment) + ntohl(segment->offset);
 			new->s_filesz = ntohl(segment->len);
+
+			if ((new->s_srcaddr < (u32)payload) ||
+				((new->s_srcaddr + new->s_filesz) >
+				(payload_len + (u32)payload))) {
+				printk(BIOS_WARNING, "WARNING: source address not within payload file!\n");
+			}
+
 			printk(BIOS_DEBUG, "  New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n",
 				new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz);
 			/* Clean up the values */
@@ -398,9 +366,10 @@
 			return -1;
 		}
 
+		/* We have found another CODE, DATA or BSS segment */
 		segment++;
 
-		// FIXME: Explain what this is
+		/* Find place where to insert our segment */
 		for(ptr = head->next; ptr != head; ptr = ptr->next) {
 			if (new->s_srcaddr < ntohl((u32) segment->load_addr))
 				break;
@@ -411,12 +380,6 @@
 		new->prev = ptr->prev;
 		ptr->prev->next = new;
 		ptr->prev = new;
-
-		/* Order by original program header order */
-		new->phdr_next = head;
-		new->phdr_prev = head->phdr_prev;
-		head->phdr_prev->phdr_next  = new;
-		head->phdr_prev = new;
 	}
 
 	return 1;
@@ -431,7 +394,8 @@
 
 	unsigned long bounce_high = lb_end;
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
-		if (!overlaps_coreboot(ptr)) continue;
+		if (!overlaps_coreboot(ptr))
+			continue;
 		if (ptr->s_dstaddr + ptr->s_memsz > bounce_high)
 			bounce_high = ptr->s_dstaddr + ptr->s_memsz;
 	}
@@ -534,13 +498,13 @@
 	return 1;
 }
 
-static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
+static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload, u32 payload_len)
 {
 	u32 entry=0;
 	struct segment head;
 
 	/* Preprocess the self segments */
-	if (!build_self_segment_list(&head, mem, payload, &entry))
+	if (!build_self_segment_list(&head, mem, payload, payload_len, &entry))
 		goto out;
 
 	/* Load the segments */
@@ -555,6 +519,10 @@
 	printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry);
 	post_code(POST_ENTER_ELF_BOOT);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_SELFBOOT_JUMP);
+#endif
+
 	/* Jump to kernel */
 	jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size);
 	return 1;
@@ -563,3 +531,33 @@
 	return 0;
 }
 
+void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name)
+{
+	struct cbfs_payload *payload;
+	struct cbfs_file *file = cbfs_find(name);
+
+	if (file == NULL) {
+		printk(BIOS_INFO,  "CBFS: Could not find file %s\n",
+		       name);
+		return (void *) -1;
+	}
+
+	if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) {
+		printk(BIOS_INFO,  "CBFS: File %s is of type %x instead of "
+		       "type %x\n", name, file->type, CBFS_TYPE_PAYLOAD);
+
+		return (void *) -1;
+	}
+
+	payload = (struct cbfs_payload *)CBFS_SUBHEADER(file);
+	if (payload == NULL)
+		return (void *) -1;
+
+	printk(BIOS_DEBUG, "Got a payload\n");
+
+	selfboot(lb_mem, payload, ntohl(file->len));
+	printk(BIOS_EMERG, "SELFBOOT RETURNED!\n");
+
+	return (void *) -1;
+}
+
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 02244d7d..38f1023 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -190,6 +190,33 @@
 	  32 bytes of IO spaces will be used (and align on 32 bytes
 	  boundary, qemu needs broader align)
 
+config CONSOLE_CBMEM
+	depends on EARLY_CBMEM_INIT
+	bool "Send console output to a CBMEM buffer"
+	default n
+	help
+	  Enable this to save the console output in a CBMEM buffer. This would
+	  allow to see coreboot console output from Linux space.
+
+config CONSOLE_CBMEM_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in CBMEM"
+	default 0x10000
+	help
+	  Space allocated for console output storage in CBMEM. The default
+	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
+	  even the BIOS_SPEW level.
+
+config CONSOLE_CAR_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in Cache as RAM"
+	default 0xc00
+	help
+	  Console is used before RAM is initialized. This is the room reserved
+	  in the DCACHE based RAM to keep console output before it can be
+	  saved in a CBMEM buffer. 3K bytes should be enough even for the
+	  BIOS_SPEW level.
+
 
 choice
 	prompt "Maximum console log level"
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4a30918..f3b8758 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -18,6 +18,8 @@
 driver-$(CONFIG_USBDEBUG) += usbdebug_console.c
 driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c
+driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
+
 
 $(obj)/console/console.ramstage.o : $(obj)/build.h
 $(obj)/console/console.romstage.o : $(obj)/build.h
diff --git a/src/cpu/x86/mmx_disable.inc b/src/console/cbmem_console.c
similarity index 61%
copy from src/cpu/x86/mmx_disable.inc
copy to src/console/cbmem_console.c
index 1a4e70f..2c43f5c 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/console/cbmem_console.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,22 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#include <console/console.h>
 
+static void cbmemc_init_(void)
+{
+	cbmemc_init();
+}
+
+static void cbmemc_tx_byte_(unsigned char data)
+{
+	cbmemc_tx_byte(data);
+}
+
+static const struct console_driver cbmem_console __console = {
+	.init     = cbmemc_init_,
+	.tx_byte  = cbmemc_tx_byte_,
+};
diff --git a/src/console/console.c b/src/console/console.c
index a73616e..8f60f04 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -22,14 +22,6 @@
 #include <arch/hlt.h>
 #include <arch/io.h>
 
-#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
-#include <uart8250.h>
-#endif
-
-#if CONFIG_CONSOLE_NE2K
-#include <console/ne2k.h>
-#endif
-
 #ifndef __PRE_RAM__
 #include <string.h>
 #include <pc80/mc146818rtc.h>
@@ -48,14 +40,6 @@
 	}
 }
 
-static void __console_tx_byte(unsigned char byte)
-{
-	struct console_driver *driver;
-	for(driver = console_drivers; driver < econsole_drivers; driver++) {
-		driver->tx_byte(byte);
-	}
-}
-
 void console_tx_flush(void)
 {
 	struct console_driver *driver;
@@ -66,6 +50,14 @@
 	}
 }
 
+static void __console_tx_byte(unsigned char byte)
+{
+	struct console_driver *driver;
+	for(driver = console_drivers; driver < econsole_drivers; driver++) {
+		driver->tx_byte(byte);
+	}
+}
+
 void console_tx_byte(unsigned char byte)
 {
 	if (byte == '\n')
@@ -95,7 +87,7 @@
 	return 0;
 }
 
-#else
+#else // __PRE_RAM__   ^^^ NOT defined   vvv defined
 
 void console_init(void)
 {
@@ -112,6 +104,9 @@
 #if CONFIG_CONSOLE_NE2K
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_init();
+#endif
 	static const char console_test[] =
 		"\n\ncoreboot-"
 		COREBOOT_VERSION
diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c
index a6968dd..3c5cfc6 100644
--- a/src/console/uart8250mem_console.c
+++ b/src/console/uart8250mem_console.c
@@ -23,11 +23,16 @@
 
 static u32 uart_bar = 0;
 
-static void uartmem_init(void)
+void uartmem_init(void)
 {
 	uart_bar = uart_mem_init();
 }
 
+u32 uartmem_getbaseaddr(void)
+{
+	return uart_bar;
+}
+
 static void uartmem_tx_byte(unsigned char data)
 {
 	if (!uart_bar)
diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index 944fd5b..d2efc8d 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
@@ -6,6 +6,7 @@
 
 #include <string.h>
 #include <div64.h>
+#include <console/console.h>
 #include <console/vtxprintf.h>
 
 /* haha, don't need ctype.c */
@@ -115,6 +116,11 @@
 
 	int count;
 
+#if defined(__SMM__) && CONFIG_SMM_TSEG
+	/* Fix pointer in TSEG */
+	tx_byte = console_tx_byte;
+#endif
+
 	for (count=0; *fmt ; ++fmt) {
 		if (*fmt != '%') {
 			tx_byte(*fmt), count++;
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 8cf30c9..774b7fe 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -9,6 +9,7 @@
 source src/cpu/intel/model_6fx/Kconfig
 source src/cpu/intel/model_1067x/Kconfig
 source src/cpu/intel/model_106cx/Kconfig
+source src/cpu/intel/model_206ax/Kconfig
 source src/cpu/intel/model_f0x/Kconfig
 source src/cpu/intel/model_f1x/Kconfig
 source src/cpu/intel/model_f2x/Kconfig
@@ -28,3 +29,4 @@
 source src/cpu/intel/socket_mPGA604/Kconfig
 source src/cpu/intel/socket_PGA370/Kconfig
 source src/cpu/intel/socket_441/Kconfig
+source src/cpu/intel/socket_rPGA989/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 93ab7de..40d92f1 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -14,6 +14,7 @@
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 
diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh
index 7a234a8..46691c9 100755
--- a/src/cpu/intel/microcode/update-microcodes.sh
+++ b/src/cpu/intel/microcode/update-microcodes.sh
@@ -18,10 +18,10 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-MICROCODE_VERSION=20100914
+MICROCODE_VERSION=20110428
 MICROCODE_ARCHIVE=microcode-$MICROCODE_VERSION.tgz
-MICROCODE_FILE=microcode-$MICROCODE_VERSION.dat
-INTEL_MICROCODE=http://downloadmirror.intel.com/19342/eng/$MICROCODE_ARCHIVE
+MICROCODE_FILE=microcode.dat
+INTEL_MICROCODE=http://downloadmirror.intel.com/20050/eng/$MICROCODE_ARCHIVE
 
 #
 # Getting Intel(R) Microcode
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 09449cb..e640e6b 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -4,3 +4,20 @@
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_MODEL_106CX
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/model_106cx/bootblock.c"
+
+config CACHE_MRC_BIN
+	bool
+	default n
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+endif
+
diff --git a/src/cpu/intel/model_106cx/bootblock.c b/src/cpu/intel/model_106cx/bootblock.c
new file mode 100644
index 0000000..0e36bd2
--- /dev/null
+++ b/src/cpu/intel/model_106cx/bootblock.c
@@ -0,0 +1,136 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+//#include <arch/io.h>
+//#include <arch/romcc_io.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+static const uint32_t microcode_updates[] = {
+	//#include "microcode-2963-M01106C2217.h"
+	//#include "microcode-2964-M04106C2218.h"
+	//#include "microcode-2965-M08106C2219.h"
+	//#include "microcode-3098-M01106CA107.h"
+	#include "microcode-3101-M04106CA107.h"
+	//#include "microcode-3104-M08106CA107.h"
+	//#include "microcode-3107-M10106CA107.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+
+
+struct microcode {
+	u32 hdrver;	/* Header Version */
+	u32 rev;	/* Patch ID       */
+	u32 date;	/* DATE           */
+	u32 sig;	/* CPUID          */
+
+	u32 cksum;	/* Checksum       */
+	u32 ldrver;	/* Loader Version */
+	u32 pf;		/* Platform ID    */
+
+	u32 data_size;	/* Data size      */
+	u32 total_size;	/* Total size     */
+
+	u32 reserved[3];
+	u32 bits[1012];
+};
+
+static inline u32 read_microcode_rev(void)
+{
+	/* Some Intel Cpus can be very finicky about the
+	 * CPUID sequence used.  So this is implemented in
+	 * assembly so that it works reliably.
+	 */
+	msr_t msr;
+	__asm__ volatile (
+		"wrmsr\n\t"
+		"xorl %%eax, %%eax\n\t"
+		"xorl %%edx, %%edx\n\t"
+		"movl $0x8b, %%ecx\n\t"
+		"wrmsr\n\t"
+		"movl $0x01, %%eax\n\t"
+		"cpuid\n\t"
+		"movl $0x08b, %%ecx\n\t"
+		"rdmsr \n\t"
+		: /* outputs */
+		"=a" (msr.lo), "=d" (msr.hi)
+		: /* inputs */
+		: /* trashed */
+		 "ecx"
+	);
+	return msr.hi;
+}
+
+void intel_update_microcode(const void *microcode_updates)
+{
+	unsigned int eax;
+	unsigned int pf, rev, sig;
+	unsigned int x86_model, x86_family;
+	const struct microcode *m;
+	const char *c;
+	msr_t msr;
+
+	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(0x8B, msr);
+	eax = cpuid_eax(1);
+	msr = rdmsr(0x8B);
+	rev = msr.hi;
+	x86_model = (eax >>4) & 0x0f;
+	x86_family = (eax >>8) & 0x0f;
+	sig = eax;
+
+	pf = 0;
+	if ((x86_model >= 5)||(x86_family>6)) {
+		msr = rdmsr(0x17);
+		pf = 1 << ((msr.hi >> 18) & 7);
+	}
+
+	m = microcode_updates;
+	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
+		if ((m->sig == sig) && (m->pf & pf)) {
+			unsigned int new_rev;
+			msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
+			msr.hi = 0;
+			wrmsr(0x79, msr);
+
+			/* Read back the new microcode version */
+			new_rev = read_microcode_rev();
+			break;
+		}
+		if (m->total_size) {
+			c += m->total_size;
+		} else {
+			c += 2048;
+		}
+	}
+}
+
+static void bootblock_cpu_init(void)
+{
+	intel_update_microcode(microcode_updates);
+}
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index da14db2..de2848c 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -63,22 +63,27 @@
 
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
-	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
 	xorl	%edx, %edx
 	wrmsr
 
 	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
-	orl	$(1 << 11), %eax
+	orl	$MTRRdefTypeEn, %eax
 	wrmsr
 
 	/* Enable L2 cache. */
 	movl	$0x11e, %ecx
 	rdmsr
+	bt	$0, %eax
+	jnc	L2done
+	bt	$23, %eax
+	jc	L2done
 	orl	$(1 << 8), %eax
 	wrmsr
 
+L2done:
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
         movl	%cr0, %eax
 	andl	$(~((1 << 30) | (1 << 29))), %eax
@@ -98,7 +103,6 @@
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
@@ -113,14 +117,27 @@
 	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for the last 32k of memory for 
+	 * ram init code to run faster
+	 */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(0xffff0000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$((~((64*1024) - 1)) | MTRRphysMaskValid), %eax
+	xorl	%edx, %edx
+	wrmsr
+#endif
 
 	/* Enable cache. */
 	movl	%cr0, %eax
@@ -148,6 +165,15 @@
 
 	post_code(0x2f)
 
+#if CONFIG_USBDEBUG
+	/* Copy global variable space (for USBDEBUG) to memory */
+	cld
+	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	24, %ecx
+	rep	movsb
+#endif
+
 	post_code(0x30)
 
 	/* Disable cache. */
@@ -160,7 +186,7 @@
 	/* Disable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
-	andl	$(~(1 << 11)), %eax
+	andl	$(~MTRRdefTypeEn), %eax
 	wrmsr
 
 	post_code(0x31)
@@ -195,13 +221,27 @@
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for the first 1MB. */
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
 	xorl	%edx, %edx
 	wrmsr
 
@@ -217,7 +257,7 @@
 	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
-	orl	$(1 << 11), %eax
+	orl	$MTRRdefTypeEn, %eax
 	wrmsr
 
 	post_code(0x3b)
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..498fb07 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -31,6 +31,76 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 #include <usbdebug.h>
+#include <arch/acpi.h>
+
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* HLT */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_HLT,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C2 */
+		.latency = 2,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 4: C2E */
+		.latency = 2,
+		.power = 500,
+		.resource = {
+			.addrl = 0x11,	/* MWAIT State 1 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 5: C4 */
+		.latency = 57,
+		.power = 100,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 6: C4E */
+		.latency = 57,
+		.power = 100,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{ 0 }
+};
 
 static const uint32_t microcode_updates[] = {
 	#include "microcode-2963-M01106C2217.h"
@@ -84,23 +154,24 @@
 #define PMG_IO_BASE_ADDR	0xe3
 #define PMG_IO_CAPTURE_ADDR	0xe4
 
-#define HIGHEST_CLEVEL		3
+#define HIGHEST_CLEVEL		4 // Pineview-M only
 static void configure_c_states(void)
 {
 	msr_t msr;
 
 	msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 3);  // Enable Dynamic L2 shrinking
 	msr.lo |= (1 << 15); // Lock configuration
 	msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT
 	msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
-	msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
+	msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL;
 	wrmsr(PMG_CST_CONFIG_CONTROL, msr);
 
-	/* Set Processor MWAIT IO BASE (P_BLK) */
+	/* Set Processor MWAIT IO BASE (P_BLK)
+	 * PMB0 points to PBLK+4,
+	 * PMB1 points to IO address that will trap tp SMM (not used)
+	 */
 	msr.hi = 0;
-	// TODO Do we want PM1_BASE? Needs SMM?
-	//msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
 	msr.lo = ((PMB0_BASE + 4) & 0xffff);
 	wrmsr(PMG_IO_BASE_ADDR, msr);
 
@@ -116,6 +187,12 @@
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
+
+	msr.hi |= (1 << (32-32)); 	/* C4E enable */
+	msr.hi |= (1 << (33-32)); 	/* Hard C4E enable */
+	msr.lo |= (1 << 26); 	/* C2E enable */
+	msr.lo |= (1 << 25); 	/* C1E enable */
+
 	msr.lo |= (1 << 3); 	/* TM1 enable */
 	msr.lo |= (1 << 13);	/* TM2 enable */
 	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
@@ -124,8 +201,8 @@
 
 	// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
 	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	msr.lo |= (1 << 0);	/* Fast String Enable */
 
-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
@@ -189,11 +266,13 @@
 
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, 0x106c0 }, /* Intel Atom 230 */
+	{ X86_VENDOR_INTEL, 0x106ca }, /* Intel Pineview */
 	{ 0, 0 },
 };
 
 static const struct cpu_driver driver __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
+	.cstates  = cstate_map,
 };
 
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
new file mode 100644
index 0000000..55948a4
--- /dev/null
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -0,0 +1,24 @@
+config CPU_INTEL_MODEL_206AX
+	bool
+	select SMP
+	select SSE2
+	select UDELAY_LAPIC
+	select SMM_TSEG
+	#select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_MODEL_206AX
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/model_206ax/bootblock.c"
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	int
+	default 0x800000
+
+endif
+
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
new file mode 100644
index 0000000..e9b8e6d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -0,0 +1,8 @@
+driver-y += model_206ax_init.c
+subdirs-y += ../../x86/name
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
new file mode 100644
index 0000000..9a70bd4
--- /dev/null
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -0,0 +1,357 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/acpi.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "model_206ax.h"
+#include "chip.h"
+
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	switch (c.x86_model) {
+	case 0x2a: /* SandyBridge */
+		result = cpuid_ext(0xb, 1);
+		cores = result.ebx & 0xff;
+		break;
+	default:
+		cores = (cpuid_ebx(1) >> 16) & 0xff;
+		break;
+	}
+
+	return cores;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0)
+		length += acpigen_write_CST_package(1, &cstates[c1]);
+	if (c2 > 0)
+		length += acpigen_write_CST_package(2, &cstates[c2]);
+	if (c3 > 0)
+		length += acpigen_write_CST_package(3, &cstates[c3]);
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_C_state_entries(void)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+	device_t lapic;
+	struct cpu_intel_model_206ax_config *conf = NULL;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic)
+		return 0;
+	conf = lapic->chip_info;
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+static acpi_tstate_t tss_table_fine[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 94, 940, 0, 0x1f, 0 },
+	{ 88, 880, 0, 0x1e, 0 },
+	{ 82, 820, 0, 0x1d, 0 },
+	{ 75, 760, 0, 0x1c, 0 },
+	{ 69, 700, 0, 0x1b, 0 },
+	{ 63, 640, 0, 0x1a, 0 },
+	{ 57, 580, 0, 0x19, 0 },
+	{ 50, 520, 0, 0x18, 0 },
+	{ 44, 460, 0, 0x17, 0 },
+	{ 38, 400, 0, 0x16, 0 },
+	{ 32, 340, 0, 0x15, 0 },
+	{ 25, 280, 0, 0x14, 0 },
+	{ 19, 220, 0, 0x13, 0 },
+	{ 13, 160, 0, 0x12, 0 },
+};
+
+static acpi_tstate_t tss_table_coarse[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 88, 875, 0, 0x1f, 0 },
+	{ 75, 750, 0, 0x1e, 0 },
+	{ 63, 625, 0, 0x1d, 0 },
+	{ 50, 500, 0, 0x1c, 0 },
+	{ 38, 375, 0, 0x1b, 0 },
+	{ 25, 250, 0, 0x1a, 0 },
+	{ 13, 125, 0, 0x19, 0 },
+};
+
+static int generate_T_state_entries(int core, int cores_per_package)
+{
+	int len;
+
+	/* Indicate SW_ALL coordination for T-states */
+	len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+
+	/* Indicate FFixedHW so OS will use MSR */
+	len += acpigen_write_empty_PTC();
+
+	/* Set a T-state limit that can be modified in NVS */
+	len += acpigen_write_TPC("\\TLVL");
+
+	/*
+	 * CPUID.(EAX=6):EAX[5] indicates support
+	 * for extended throttle levels.
+	 */
+	if (cpuid_eax(6) & (1 << 5))
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_fine), tss_table_fine);
+	else
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
+
+	return len;
+}
+
+static int calculate_power(int tdp, int p1_ratio, int ratio)
+{
+	u32 m;
+	u32 power;
+
+	/*
+	 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
+	 *
+	 * Power = (ratio / p1_ratio) * m * tdp
+	 */
+
+	m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
+	m = (m * m) / 1000;
+
+	power = ((ratio * 100000 / p1_ratio) / 100);
+	power *= (m / 100) * (tdp / 1000);
+	power /= 1000;
+
+	return (int)power;
+}
+
+static int generate_P_state_entries(int core, int cores_per_package)
+{
+	int len, len_pss;
+	int ratio_min, ratio_max, ratio_turbo, ratio_step;
+	int coord_type, power_max, power_unit, num_entries;
+	int ratio, power, clock, clock_max;
+	msr_t msr;
+
+	/* Determine P-state coordination type from MISC_PWR_MGMT[0] */
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
+		coord_type = SW_ANY;
+	else
+		coord_type = HW_ALL;
+
+	/* Get bus ratio limits and calculate clock speeds */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
+	ratio_max = (msr.lo >> 8) & 0xff;       /* Max Non-Turbo Ratio */
+	clock_max = ratio_max * SANDYBRIDGE_BCLK;
+
+	/* Calculate CPU TDP in mW */
+	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+	msr = rdmsr(MSR_PKG_POWER_SKU);
+	power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
+
+	/* Write _PCT indicating use of FFixedHW */
+	len = acpigen_write_empty_PCT();
+
+	/* Write _PPC with no limit on supported P-state */
+	len += acpigen_write_PPC(0);
+
+	/* Write PSD indicating configured coordination type */
+	len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
+
+	/* Add P-state entries in _PSS table */
+	len += acpigen_write_name("_PSS");
+
+	/* Determine ratio points */
+	ratio_step = PSS_RATIO_STEP;
+	num_entries = (ratio_max - ratio_min) / ratio_step;
+	while (num_entries > PSS_MAX_ENTRIES-1) {
+		ratio_step <<= 1;
+		num_entries >>= 1;
+	}
+
+	/* P[T] is Turbo state if enabled */
+	if (get_turbo_state() == TURBO_ENABLED) {
+		/* _PSS package count including Turbo */
+		len_pss = acpigen_write_package(num_entries + 2);
+
+		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+		ratio_turbo = msr.lo & 0xff;
+
+		/* Add entry for Turbo ratio */
+		len_pss += acpigen_write_PSS_package(
+			clock_max + 1,		/*MHz*/
+			power_max,		/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio_turbo << 8,	/*control*/
+			ratio_turbo << 8);	/*status*/
+	} else {
+		/* _PSS package count without Turbo */
+		len_pss = acpigen_write_package(num_entries + 1);
+	}
+
+	/* First regular entry is max non-turbo ratio */
+	len_pss += acpigen_write_PSS_package(
+		clock_max,		/*MHz*/
+		power_max,		/*mW*/
+		PSS_LATENCY_TRANSITION,	/*lat1*/
+		PSS_LATENCY_BUSMASTER,	/*lat2*/
+		ratio_max << 8,		/*control*/
+		ratio_max << 8);	/*status*/
+
+	/* Generate the remaining entries */
+	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
+	     ratio >= ratio_min; ratio -= ratio_step) {
+
+		/* Calculate power at this ratio */
+		power = calculate_power(power_max, ratio_max, ratio);
+		clock = ratio * SANDYBRIDGE_BCLK;
+
+		len_pss += acpigen_write_PSS_package(
+			clock,			/*MHz*/
+			power,			/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio << 8,		/*control*/
+			ratio << 8);		/*status*/
+	}
+
+	/* Fix package length */
+	len_pss--;
+	acpigen_patch_len(len_pss);
+
+	return len + len_pss;
+}
+
+void generate_cpu_entries(void)
+{
+	int len_pr;
+	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+	int totalcores = dev_count_cpu();
+	int cores_per_package = get_cores_per_package();
+	int numcpus = totalcores/cores_per_package;
+
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+	       numcpus, cores_per_package);
+
+	for (cpuID=1; cpuID <=numcpus; cpuID++) {
+		for (coreID=1; coreID<=cores_per_package; coreID++) {
+			if (coreID>1) {
+				pcontrol_blk = 0;
+				plen = 0;
+			}
+
+			/* Generate processor \_PR.CPUx */
+			len_pr = acpigen_write_processor(
+				(cpuID-1)*cores_per_package+coreID-1,
+				pcontrol_blk, plen);
+
+			/* Generate P-state tables */
+			len_pr += generate_P_state_entries(
+				cpuID-1, cores_per_package);
+
+			/* Generate C-state tables */
+			len_pr += generate_C_state_entries();
+
+			/* Generate T-state tables */
+			len_pr += generate_T_state_entries(
+				cpuID-1, cores_per_package);
+
+			len_pr--;
+			acpigen_patch_len(len_pr);
+		}
+	}
+}
+
+struct chip_operations cpu_intel_model_206ax_ops = {
+	CHIP_NAME("Intel SandyBridge CPU")
+};
diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl
new file mode 100644
index 0000000..a9d5eeb
--- /dev/null
+++ b/src/cpu/intel/model_206ax/acpi/cpu.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CPU0, DeviceObj)
+External (\_PR.CPU1, DeviceObj)
+External (\_PR.CPU2, DeviceObj)
+External (\_PR.CPU3, DeviceObj)
+External (\_PR.CPU4, DeviceObj)
+External (\_PR.CPU5, DeviceObj)
+External (\_PR.CPU6, DeviceObj)
+External (\_PR.CPU7, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CPU0, 0x80)  // _PPC
+		Notify (\_PR.CPU0, 0x81)  // _CST
+		Notify (\_PR.CPU1, 0x80)  // _PPC
+		Notify (\_PR.CPU1, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CPU2, 0x80)  // _PPC
+		Notify (\_PR.CPU2, 0x81)  // _CST
+		Notify (\_PR.CPU3, 0x80)  // _PPC
+		Notify (\_PR.CPU3, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CPU4, 0x80)  // _PPC
+		Notify (\_PR.CPU4, 0x81)  // _CST
+		Notify (\_PR.CPU5, 0x80)  // _PPC
+		Notify (\_PR.CPU5, 0x81)  // _CST
+		Notify (\_PR.CPU6, 0x80)  // _PPC
+		Notify (\_PR.CPU6, 0x81)  // _CST
+		Notify (\_PR.CPU7, 0x80)  // _PPC
+		Notify (\_PR.CPU7, 0x81)  // _CST
+	}
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CPU0, 0x82)  // _TPC
+		Notify (\_PR.CPU1, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CPU2, 0x82)  // _TPC
+		Notify (\_PR.CPU3, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CPU4, 0x82)  // _TPC
+		Notify (\_PR.CPU5, 0x82)  // _TPC
+		Notify (\_PR.CPU6, 0x82)  // _TPC
+		Notify (\_PR.CPU7, 0x82)  // _TPC
+	}
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+	If (LGreaterEqual (\PCNT, 8)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3,
+				   \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7})
+	} ElseIf (LGreaterEqual (\PCNT, 4)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3})
+	} ElseIf (LGreaterEqual (\PCNT, 2)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1})
+	} Else {
+		Return (Package() {\_PR.CPU0})
+	}
+}
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
new file mode 100644
index 0000000..8d91126
--- /dev/null
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_00000025.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+struct microcode {
+	u32 hdrver;	/* Header Version */
+	u32 rev;	/* Patch ID       */
+	u32 date;	/* DATE           */
+	u32 sig;	/* CPUID          */
+
+	u32 cksum;	/* Checksum       */
+	u32 ldrver;	/* Loader Version */
+	u32 pf;		/* Platform ID    */
+
+	u32 data_size;	/* Data size      */
+	u32 total_size;	/* Total size     */
+
+	u32 reserved[3];
+	u32 bits[1012];
+};
+
+static inline u32 read_microcode_rev(void)
+{
+	/* Some Intel Cpus can be very finicky about the
+	 * CPUID sequence used.  So this is implemented in
+	 * assembly so that it works reliably.
+	 */
+	msr_t msr;
+	__asm__ volatile (
+		"wrmsr\n\t"
+		"xorl %%eax, %%eax\n\t"
+		"xorl %%edx, %%edx\n\t"
+		"movl $0x8b, %%ecx\n\t"
+		"wrmsr\n\t"
+		"movl $0x01, %%eax\n\t"
+		"cpuid\n\t"
+		"movl $0x08b, %%ecx\n\t"
+		"rdmsr \n\t"
+		: /* outputs */
+		"=a" (msr.lo), "=d" (msr.hi)
+		: /* inputs */
+		: /* trashed */
+		 "ecx"
+	);
+	return msr.hi;
+}
+
+void intel_update_microcode(const void *microcode_updates)
+{
+	unsigned int eax;
+	unsigned int pf, rev, sig;
+	unsigned int x86_model, x86_family;
+	const struct microcode *m;
+	const char *c;
+	msr_t msr;
+
+	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(0x8B, msr);
+	eax = cpuid_eax(1);
+	msr = rdmsr(0x8B);
+	rev = msr.hi;
+	x86_model = (eax >>4) & 0x0f;
+	x86_family = (eax >>8) & 0x0f;
+	sig = eax;
+
+	pf = 0;
+	if ((x86_model >= 5)||(x86_family>6)) {
+		msr = rdmsr(0x17);
+		pf = 1 << ((msr.hi >> 18) & 7);
+	}
+
+	m = microcode_updates;
+	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
+		if ((m->sig == sig) && (m->pf & pf)) {
+			unsigned int new_rev;
+			msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
+			msr.hi = 0;
+			wrmsr(0x79, msr);
+
+			/* Read back the new microcode version */
+			new_rev = read_microcode_rev();
+			break;
+		}
+		if (m->total_size) {
+			c += m->total_size;
+		} else {
+			c += 2048;
+		}
+	}
+}
+
+static void set_var_mtrr(
+	unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+	/* FIXME: It only support 4G less range */
+	msr_t basem, maskm;
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRRphysBase_MSR(reg), basem);
+	maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
+static void enable_rom_caching(void)
+{
+	msr_t msr;
+
+	disable_cache();
+	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	enable_cache();
+
+	/* Enable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000800;
+	wrmsr(MTRRdefType_MSR, msr);
+}
+
+static void bootblock_cpu_init(void)
+{
+	enable_rom_caching();
+	intel_update_microcode(microcode_updates);
+}
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
new file mode 100644
index 0000000..d5f1d7d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -0,0 +1,348 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <cpu/x86/stack.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
+
+cache_as_ram:
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
+
+	/* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+	movl	(%esi), %eax
+	bt	$12, %eax
+	jc	wait_for_sipi
+
+	post_code(0x21)
+	/* Zero out all fixed range and variable range MTRRs. */
+	movl	$mtrr_table, %esi
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+clear_mtrrs:
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	post_code(0x22)
+	/* Configure the default memory type to uncacheable. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	post_code(0x23)
+	/* Set Cache-as-RAM base address. */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	post_code(0x24)
+	/* Set Cache-as-RAM mask. */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x25)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+        movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* enable the 'no eviction' mode */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $1, %eax
+	andl    $~2, %eax
+	wrmsr
+
+       /* Clear the cache memory region. This will also fill up the cache */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	// movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+
+	/* enable the 'no eviction run' state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $3, %eax
+	wrmsr
+
+	post_code(0x26)
+	/* Enable Cache-as-RAM mode by disabling cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
+#if CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$0x0000000f, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	wrmsr
+
+	post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for ram init code to run faster */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+#endif
+
+	post_code(0x28)
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0
+
+	/* Set up the stack pointer below MRC variable space. */
+	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
+		  CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+before_romstage:
+	post_code(0x29)
+	/* Call romstage.c main function. */
+	call	main
+
+	post_code(0x2f)
+
+	/* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+	cld
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	$24, %ecx
+	rep	movsb
+#endif
+
+	post_code(0x30)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x31)
+
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~MTRRdefTypeEn), %eax
+	wrmsr
+
+	post_code(0x31)
+
+	/* Disable the no eviction run state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	andl    $~2, %eax
+	wrmsr
+
+	invd
+
+	/* Disable the no eviction mode */
+	rdmsr
+	andl    $~1, %eax
+	wrmsr
+
+#if CONFIG_CACHE_MRC_BIN
+	/* Clear MTRR that was used to cache MRC */
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	movl	$MTRRphysBase_MSR(2), %ecx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	wrmsr
+#endif
+
+	post_code(0x33)
+
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x36)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x38)
+
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
+	movl	$MTRRphysBase_MSR(0), %ecx
+	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(0), %ecx
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx	// 36bit address space
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+	post_code(0x3c)
+
+#if CONFIG_HAVE_ACPI_RESUME
+	movl	CBMEM_BOOT_MODE, %eax
+	cmpl	$0x2, %eax // Resume?
+	jne	__acpi_resume_backup_done
+
+	/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+	 * through stage 2. We could keep stuff like stack and heap in high
+	 * tables memory completely, but that's a wonderful clean up task for
+	 * another day.
+	 */
+	cld
+	movl	$CONFIG_RAMBASE, %esi
+	movl	CBMEM_RESUME_BACKUP, %edi
+	movl	$HIGH_MEMORY_SAVE / 4, %ecx
+	rep	movsl
+
+__acpi_resume_backup_done:
+#endif
+
+	post_code(0x3d)
+
+	/* Clear boot_complete flag. */
+	xorl	%ebp, %ebp
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+
+	movl	%ebp, %esi
+
+	movl	$ROMSTAGE_STACK, %esp
+	movl	%esp, %ebp
+	pushl	%esi
+	call	copy_and_run
+
+.Lhlt:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.Lhlt
+
+mtrr_table:
+	/* Fixed MTRRs */
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
+	/* Variable MTRRs */
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
+
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h
new file mode 100644
index 0000000..48e0c89
--- /dev/null
+++ b/src/cpu/intel/model_206ax/chip.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_model_206ax_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_model_206ax_config {
+	u8 disable_acpi;	/* Do not generate CPU ACPI tables */
+
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* ACPI C1 on Battery Power */
+	int c2_battery;		/* ACPI C2 on Battery Power */
+	int c3_battery;		/* ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* ACPI C1 on AC Power */
+	int c2_acpower;		/* ACPI C2 on AC Power */
+	int c3_acpower;		/* ACPI C3 on AC Power */
+};
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
new file mode 100644
index 0000000..9de94c4
--- /dev/null
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include "model_206ax.h"
+
+static void msr_set_bit(unsigned reg, unsigned bit)
+{
+	msr_t msr = rdmsr(reg);
+
+	if (bit < 32) {
+		if (msr.lo & (1 << bit))
+			return;
+		msr.lo |= 1 << bit;
+	} else {
+		if (msr.hi & (1 << (bit - 32)))
+			return;
+		msr.hi |= 1 << (bit - 32);
+	}
+
+	wrmsr(reg, msr);
+}
+
+void intel_model_206ax_finalize_smm(void)
+{
+	msr_set_bit(IA32_FEATURE_CONTROL, 0);
+	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+
+	/* Lock AES-NI only if supported */
+	if (cpuid_ecx(1) & (1 << 25))
+		msr_set_bit(MSR_FEATURE_CONFIG, 0);
+
+	msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
+	msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
+	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
+	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
+}
diff --git a/src/cpu/intel/model_206ax/microcode-M12206A7_00000025.h b/src/cpu/intel/model_206ax/microcode-M12206A7_00000025.h
new file mode 100644
index 0000000..2b9e59a
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12206A7_00000025.h
@@ -0,0 +1,578 @@
+/* Intel Copyrighted material. Do not distribute */
+
+0x00000001,	0x00000025,	0x10112011,	0x000206a7,
+0x6aa14554,	0x00000001,	0x00000012,	0x000023d0,
+0x00002400,	0x00000000,	0x00000000,	0x00000000,
+0x00000000,	0x000000a1,	0x00020001,	0x00000025,
+0x00000000,	0x00000000,	0x20111011,	0x000008d1,
+0x00000001,	0x000206a7,	0x00000000,	0x00000000,
+0x00000000,	0x00000000,	0x00000000,	0x00000000,
+0x00000000,	0x000008d1,	0x00000000,	0x00000000,
+0x00000000,	0x00000000,	0x00000000,	0x00000000,
+0x9d225b45,	0x6ab4c3b0,	0xebba1c32,	0x469a230a,
+0x8a7d6315,	0x2fc24d3e,	0x82506f79,	0x18dbb9d6,
+0x1a7bbeb1,	0x355a1d62,	0x2e7eb594,	0x09f8dea9,
+0x432a49e4,	0xbf520253,	0xdafa4010,	0x893a858a,
+0x766e0efb,	0xd91e196d,	0x838bd2ef,	0xe5146494,
+0xd515f413,	0x29704828,	0xe85598b6,	0xdcbe6c51,
+0x88eabbfa,	0xa1e8909f,	0xd8931721,	0x35386554,
+0x089a78a7,	0xd9914775,	0xd4644748,	0x1556a4dc,
+0xf44448f6,	0xd054d7db,	0xf30f2b7d,	0x5ae223d0,
+0xcbbb48b0,	0x5c8b0383,	0x177de157,	0x9c1e5f73,
+0x2ec28289,	0xd72a7b6c,	0x823b6eb2,	0x35e02171,
+0xba8deae4,	0x06f4d468,	0x13dbafaa,	0x72b419f1,
+0x033385b5,	0x05806920,	0x4c6034cf,	0x9bd117dc,
+0x976e2d04,	0x250330f0,	0x7250b5e1,	0x184980c2,
+0x12a9d7d6,	0x1bc808f9,	0xae79994f,	0xc6f87901,
+0xc0e3132f,	0x671491c5,	0x236cad39,	0x37889d9c,
+0x67f7c3f3,	0x964a6be5,	0xbcced7da,	0x57eeaa6e,
+0x7bca1522,	0x654fee4c,	0x2a1ca5d9,	0xa1803cf3,
+0x00000011,	0x3f96e33b,	0xbcc97e7d,	0xfecb5781,
+0x24a87ac3,	0x281fad3d,	0x6c5d0169,	0x406f3d4b,
+0x1bedf9bf,	0x514f3332,	0xb33e1926,	0x539139d4,
+0x0b5a03bb,	0x7948224c,	0x403919aa,	0xd30c64b2,
+0xb1df420a,	0xbc62cb65,	0x8b036cd8,	0x662064a0,
+0x7381ae61,	0xfb070274,	0x9a3978d9,	0x051c1cbd,
+0x7bcfb857,	0x2c94fcc0,	0x25f643f1,	0xda3d4463,
+0x8aad6318,	0xabd2966c,	0x663d015a,	0x9fe4c504,
+0x43786fce,	0xa1b3dfdc,	0x435783a4,	0x1e44e90a,
+0x85ae6018,	0x9402a6c9,	0x709f4d13,	0x1bdec841,
+0x4840a539,	0xaa446221,	0x27401d2d,	0x1e0d39c6,
+0x6ae8973f,	0xc8b603b8,	0x8044340d,	0x9a4846e1,
+0xf7e68ad9,	0xd2a0cbd1,	0xc64bf2bf,	0x51286697,
+0xf3110b6f,	0x1562e9dc,	0xc682712e,	0x5cfbda8f,
+0x0d575c4f,	0x929f8530,	0x69abd158,	0x41c783e1,
+0xbfe313de,	0x33cbec29,	0xbcbddb8a,	0xe0861b12,
+0x866f3884,	0xf3b79ad6,	0x3415ad37,	0x3a17893c,
+0xb29694df,	0xecd242ce,	0x5d8231ef,	0x5b208f8f,
+0xc781cb94,	0xeb8dc8b8,	0x9d04fd73,	0x4639b3f9,
+0x543fbc28,	0x3957879c,	0xc7f0d4a1,	0x29ac4965,
+0x10f47a96,	0xf7d5b5ce,	0x8ed0c39f,	0x5a36d20f,
+0xff5bd157,	0xf4a3152e,	0xfa9087b4,	0xe4021354,
+0x2b394395,	0x118d8abd,	0xa6ef26da,	0xe47688e5,
+0x15352ccd,	0xa2a1120c,	0xf86a3b13,	0x3453d233,
+0x74d464e9,	0x28cb0910,	0x1c0d9908,	0xf7a672c4,
+0xa725013d,	0xfd618f4a,	0x2035f826,	0x2544d00b,
+0xe6bd2f30,	0xd6e3992f,	0xf7f39f5e,	0x282a3593,
+0x00de27bf,	0x5d0470c2,	0x14473c88,	0xc763ad23,
+0x2ccd5c60,	0x71f0d333,	0x09e8b8cd,	0x716fd1e1,
+0x2dfd1003,	0x006b819f,	0x7b157ad2,	0xa6305470,
+0xcde50f1a,	0x955bc9c8,	0xbe464835,	0xf67f9b33,
+0x21ab56ea,	0xc133d4c6,	0x77d754bf,	0x130877e0,
+0xbd1b247a,	0x7840690d,	0xe6174dd0,	0x61d13bfd,
+0x675ae943,	0x9149e21b,	0xce8ddf65,	0xe06ca163,
+0x33ee3750,	0xa89318e4,	0xa5476a0f,	0x72d15429,
+0x1442d6e5,	0x13f70d65,	0x81923d22,	0x4eefbbc5,
+0x1af2cbf1,	0x052ae881,	0x2fcb621a,	0x44e6c1f6,
+0x10c0c127,	0x6132dbfc,	0x0b3e5d38,	0x18379c7c,
+0x24848ccf,	0xb929cddf,	0xbd0c9549,	0x68d44ac1,
+0xf1a4967b,	0x60d466f9,	0x60a12700,	0x6bdf875f,
+0x2d8255a9,	0x464c149d,	0x32c047ee,	0x5d744d6c,
+0xdf44c2b2,	0xda41f152,	0xb83bd853,	0x3f612ed9,
+0xcecd3f95,	0xde938fc5,	0x2120712d,	0x6e895650,
+0xa5d34947,	0xb5d7459d,	0x13df64d9,	0xf8d40e55,
+0x7f590e01,	0x1724e7cf,	0x5843ee08,	0xdce43dd9,
+0x574cae1c,	0x5ec349e6,	0x56ab1066,	0x7d518ee9,
+0x1f83b1fe,	0xac633b58,	0xcef8a5fd,	0xacf35357,
+0xa93932b1,	0x64e73ca0,	0xb824e2b0,	0xb6c68da4,
+0x287ee847,	0xec1dbf97,	0xd313d2fa,	0x9fe37eec,
+0x281d8559,	0x2fd0c6c7,	0x15e9a89a,	0x273e9932,
+0xf081dec8,	0xa04d5e16,	0x8a3ac66a,	0xe5b25b5c,
+0x4138b7b3,	0xace013c4,	0xe5bee1c8,	0xd9daafd4,
+0x952af837,	0xf28c36bf,	0xcdff2a71,	0xa1cf3b94,
+0x8821440c,	0x3693fab8,	0xd6d2d0d0,	0xa2ccd66d,
+0xe8736467,	0x8a8952f8,	0xe32db4d9,	0x47b71bdf,
+0x620f3c22,	0xdb2922a7,	0x98e5cc6b,	0x905be886,
+0x822feb82,	0xf722cf0c,	0x7a356d80,	0x9c6b3ab6,
+0x19a3cc17,	0x08dfaf09,	0x4c99a23d,	0x0926d99e,
+0xa81577e5,	0xc684495a,	0x359aa743,	0xbc7aa166,
+0xaac2e24d,	0x16110785,	0x8ccc6fbc,	0xfd90cf70,
+0xb34be19c,	0xf57fef0d,	0x9c29c8a7,	0x022c249d,
+0x946cef68,	0xe07b7779,	0x4f6ea6b4,	0xe3a4eef4,
+0xfed31061,	0x96e78ae9,	0x220c0f91,	0x30aca707,
+0xa081c7b9,	0x159dc936,	0x4cbaa290,	0x447910e2,
+0x6ec95f93,	0x3cc3fde8,	0xce2c17a1,	0x4f18c4cb,
+0x025605b1,	0xbce02471,	0x21656693,	0x9368f6cd,
+0x0c19760f,	0xcc35da81,	0x4c5edab1,	0x85a0890e,
+0xbc5b861e,	0x203a23a6,	0xddc7d7ed,	0x0b585825,
+0xec9e7ab2,	0x1f1ad49a,	0xa7444b1f,	0xe77976b4,
+0x99e8c05e,	0x8b04c7c2,	0xb1aeb88b,	0x416d07ac,
+0x5a5689be,	0xe4094686,	0xe048c8e6,	0x2e0259dd,
+0xd2fe1113,	0x6190504b,	0xa0352318,	0x6f0cae7c,
+0x040da641,	0x29fab483,	0x2e354a07,	0xab62c485,
+0xbd787e0a,	0xc345308c,	0xc8ab8568,	0xf75adc1d,
+0x82b55654,	0x6cf29bbf,	0x8786a46e,	0x433c20d2,
+0x9229c1ee,	0x5e8eedf5,	0xab9bb981,	0x1a1a5419,
+0x97994816,	0x010eef10,	0x0172fd65,	0x975b8297,
+0xff6c4377,	0x6fca39f8,	0x13accf88,	0x94f05a02,
+0x5a772f20,	0xfbf97bca,	0x60801139,	0x64cbd0a6,
+0x72512821,	0x0830cb9a,	0x402f033c,	0xd0e2a50d,
+0x7ac45ee3,	0xbae23515,	0xd213695d,	0x72016572,
+0x20651143,	0x3552bc4d,	0xf014ebb1,	0x9aeebedf,
+0xee65d90f,	0x53abd424,	0x841f5383,	0xa43a2e44,
+0xee379480,	0x1638e568,	0x2573aad0,	0x2e935090,
+0xb9dcbe13,	0x9cdc4e30,	0xce8d170c,	0xbc546d14,
+0x18b77a7b,	0x3b652642,	0x79ae26c2,	0x5ab240c2,
+0xf74cfe35,	0x30be64cf,	0x3b5e7456,	0x81be84d1,
+0x12bb10db,	0x573da6b3,	0x83e28efe,	0x395c1512,
+0xf11928ee,	0xe64d50b5,	0x6f714c8b,	0xb3393f61,
+0x13b6b2f4,	0x0ab3b2aa,	0x5cada4c7,	0x19dfb423,
+0xe7b1c195,	0x47ee32d7,	0x03ab86bd,	0x08b8a8c6,
+0xdc7a6cdf,	0x3e5b4f68,	0x9ea0e297,	0x13193f7e,
+0x8fe31f30,	0x6118a11c,	0xc0762196,	0x9fd26fc0,
+0x9f515662,	0x5a1abb55,	0x5e434855,	0x4c6af26a,
+0x163cf95d,	0xa54ee076,	0xb41a0c1a,	0xf8a8affb,
+0x69db8391,	0xa7204db3,	0x86dc9909,	0x25ba82c5,
+0x04154f7a,	0xa191c23a,	0x6f3ee8ed,	0x55162d2b,
+0x14f9478d,	0xc717fb1c,	0x91408cdd,	0x7a87a50d,
+0x44d10ceb,	0xd04b5347,	0x82a3b3ce,	0x07e3998e,
+0x1dafee6f,	0x77c24219,	0x4ff885ef,	0xd994194a,
+0xfeff078a,	0x20f4b18a,	0x529676bd,	0x17738de7,
+0x01f8491b,	0xe31d2728,	0x34e5155b,	0x87120d79,
+0xb96f615c,	0xd6d15cd2,	0x4a1f66a8,	0xa0b37474,
+0x0713a36e,	0x70df574c,	0xe6015de6,	0x5f50f282,
+0xbd828397,	0xda75bb9f,	0x13e35581,	0x5bb84a7f,
+0xf66216ca,	0xac35d098,	0xff3a8f78,	0xb43a2d55,
+0xcb820994,	0x74f97ab1,	0x0ebb37aa,	0x5457d670,
+0xc7617908,	0x5f0ad21e,	0xeb8a4b9f,	0x0c678bc7,
+0x705cb6ce,	0xc2b3ef2a,	0x89c0c723,	0xab4399a9,
+0xc2216b3e,	0x9adda9ee,	0x82c7bfa0,	0x9d56f661,
+0x0f715ee5,	0x627d8182,	0x306a00b9,	0x2d9c259c,
+0x251b933c,	0x67fbe9e7,	0x103e2322,	0x29d1c68a,
+0x8f019d2f,	0x077e80b4,	0xbbbd9c2a,	0x266f4f74,
+0x96b32213,	0x5019c61d,	0x4a59782c,	0x8810efb7,
+0xfa55eaae,	0xbabe0b82,	0x956cae7f,	0xf016453c,
+0x255e2b2a,	0x1b805b17,	0x9c9b51cb,	0x0eaafa33,
+0x45fb3835,	0x2c2070d2,	0x70005da8,	0xf39c43b4,
+0x78c372ac,	0xa6fe8b80,	0x473ab824,	0x758cf1c0,
+0x8d012210,	0x8e26dc51,	0xf8f88450,	0xd1ffe2b8,
+0xa36a40ff,	0xbed11609,	0xaaa32039,	0xbc6ee3b5,
+0x36f84b62,	0xbacf3880,	0x26af8917,	0x9c6cb47f,
+0xa2a70b0b,	0x4b003af3,	0x83d9d354,	0x7aa355ce,
+0x75ec5db9,	0xa4384855,	0x0e8ac979,	0xa55a370e,
+0xbb3af0dd,	0x42153802,	0x32531de8,	0xe57570a8,
+0xe490a98c,	0xa9a910ee,	0x453953a6,	0x1348535e,
+0xb73595c5,	0x89bcd5dd,	0x0c68cc61,	0x5e880831,
+0x65cf0e50,	0xa4ccd3ac,	0xe61f9f5f,	0x01b610b0,
+0x7387c5aa,	0x6458654f,	0x35bbb16c,	0x90e9e91c,
+0xc56957f2,	0xaadb7f70,	0x07732d08,	0xce4ad932,
+0x7fa3e135,	0x31a83cad,	0x43271bcf,	0xa74b4eab,
+0x4f483674,	0x9cc84d3c,	0x7562feb5,	0x0b445b18,
+0xc1b1b769,	0xcfd31f23,	0xdf6f0843,	0x56789e7b,
+0x0ed7daf8,	0xe28e3610,	0x0b516cac,	0x5d805128,
+0xe430861d,	0x993bc596,	0xd85434cb,	0x740f7d13,
+0xe91e0d47,	0xe518a80f,	0xf729e13a,	0xd7fde910,
+0x838697c0,	0xf25c49b6,	0x7b9a6956,	0x70c8cb88,
+0xe5befc43,	0x84e0cd72,	0x2799a866,	0x62f8241e,
+0xa13dd267,	0x675404c0,	0x107995e6,	0xd5a44abb,
+0xe8b14bc2,	0x299705c4,	0xe691d679,	0x2a72edfa,
+0x353adfa6,	0x89aa4a58,	0x22247d90,	0x5a97fc14,
+0x09843de7,	0x4537f188,	0x7cd7cb9c,	0x7395900f,
+0xa178c352,	0x96fff660,	0x3b1d36a9,	0x7872cd2c,
+0x4e8e86ac,	0x6d0d129e,	0x366d1810,	0x84e4869f,
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+0x25449a3d,	0x1e76f046,	0x708114f9,	0x02a9ad00,
+0x5186ab9f,	0x8a301145,	0x8175f0f4,	0xacdff2ab,
+0xbaca756d,	0x65d33620,	0xe35a5db7,	0x69bb75cb,
+0x2f5c123d,	0x841f9c77,	0xffcf384e,	0x3aa6d707,
+0x3207be98,	0x83784052,	0x4eb0c27d,	0x6def8ca4,
+0x427910cf,	0x28bfceb8,	0x0ebda330,	0x9850fd1e,
+0x81e639f4,	0xa838aa33,	0x0174e6e7,	0xd768e4a2,
+0x2abe1041,	0x9cc6ecd8,	0x58c20300,	0x5824ebfa,
+0xadb81dfc,	0x3770a8b2,	0x473d8f26,	0x1e775e35,
+0x259f5ad7,	0x13fef5c5,	0x3aa92640,	0x5a76c79b,
+0xdfa3ff6b,	0x43d6bba4,	0xae2a900e,	0x8c698a3e,
+0x51ce5a96,	0x66908c24,	0x0911f46e,	0x70d619f7,
+0x972efb65,	0xb5c23792,	0x1b3ee153,	0x909746c1,
+0x8370fa25,	0xbcde8c5c,	0x1aa4f41d,	0x373a398a,
+0x3c8559a2,	0x4b528ba2,	0x54019afe,	0xe409c632,
+0x160581e2,	0x7e30d7d4,	0xf841f0a0,	0xdc1d200a,
+0x46ed47de,	0x0f77093c,	0xac835c24,	0x2ce29974,
+0xc031bfe9,	0xe879d971,	0xa67200ee,	0x3fe62089,
+0x90a38599,	0xcf7107d2,	0x45b49b01,	0xebb5ad89,
+0x8f42d795,	0x77b19427,	0x800e71fa,	0x6bc93b64,
+0xc0cdf4d6,	0x97dc9d9f,	0x7cf2edd3,	0xcb482372,
+0x6221fd9e,	0x84492515,	0xbd2b7283,	0xfc15f19e,
+0x547a79ae,	0x73337e65,	0xec64a1de,	0x822bf271,
+0x65c6b44a,	0x6d3246ea,	0x464aa85a,	0xd5110102,
+0x2578e4ef,	0xb5c4273f,	0xef03fde4,	0x1c5358fd,
+0x9b30fb66,	0x214b5514,	0xc7c50eb5,	0x76372928,
+0x5ec235f3,	0x20df4fbc,	0x12c684c5,	0x141308c1,
+0x1ffda6ae,	0x1a64f972,	0xad2f29b8,	0x4de7315a,
+0xd0fa953d,	0x8c55fe93,	0xa375129d,	0xd120f9b8,
+0xbb20cb19,	0x535d873d,	0x1fa8e047,	0x6dd4c1f5,
+0xd456632c,	0xa388867b,	0x762656d5,	0x00812012,
+0x1225a049,	0xf7900f05,	0x5b50f75d,	0xf720a919,
+0xbb8dcb70,	0xa6d48d13,	0xf750522c,	0x8ad277b3,
+0x334daf09,	0x5f882b42,	0x38a53713,	0xe9bbeef7,
+0xcc7fd1d6,	0xda484573,	0x4b3e2894,	0xbc0ef5ab,
+0xb2be1128,	0x88f27a64,	0x84ccdf55,	0x93aca22b,
+0x80b9641e,	0xa2bc2354,	0x5d78ca97,	0xb36ab105,
+0xdeb4d233,	0xe7e653bc,	0x7a29de17,	0x950c7ece,
+0xca5e997c,	0x5b8d4b6c,	0xaa5b0c7f,	0x2048cacf,
+0x71bd96bf,	0x580520f9,	0xc4da2129,	0xa3f0d78e,
+0x5235e085,	0x30c220c3,	0x2edbb5eb,	0xd12227ed,
+0x67f8faf5,	0x0d5f8ef1,	0xd8176ac6,	0x1ee955f7,
+0x13b75133,	0xb935ee9d,	0xdfe2d54f,	0x43ff1de9,
+0x6e848017,	0x4011e255,	0x5180f71b,	0x72ed0330,
+0xc737adbd,	0x7f6839a6,	0x142bd2d2,	0x66d6143b,
+0x69cf3cd0,	0x9b492cb9,	0x3266f995,	0x8ce763fe,
+0xdf8493e0,	0x8a981e31,	0xe6351c8e,	0xb0fd34fe,
+0xdc236978,	0x385f0118,	0x1c44fcdb,	0xcf70bb77,
+0x6046d066,	0x2d9475af,	0x3799ac4b,	0xe9efc39c,
+0x90d0450c,	0xa40a5fc6,	0xcfb5ef83,	0x049854c0,
+0x7215e231,	0x0424cc7e,	0x56ad0075,	0xff0a28a0,
+0x7488be97,	0xe1f82798,	0xc445794d,	0xeb7dd129,
+0x631403b5,	0xfcfd85de,	0xbf795cac,	0x00aafac9,
+0x6a2fe3ec,	0x294c2bde,	0x12861212,	0xddff6bfb,
+0xb0b29b5a,	0x46387e2d,	0x4a5a42a2,	0x4549f462,
+0x4f20df9b,	0xd189a190,	0x0ef70bb7,	0xa544ce4b,
+0x44a69377,	0x5e8c0f35,	0x2ecf5b5c,	0x0c1b08be,
+0x7f054c31,	0x73ed91a2,	0x82cd81c4,	0xf693111c,
+0x1ce7be10,	0x55d7acf8,	0x015c32a7,	0x5a3d7795,
+0x1372ac6d,	0x038755f6,	0xd1ed8be2,	0xe1b2bd04,
+0x20f3c81c,	0x326ffd81,	0x658c1e11,	0x37f74017,
+0x0a8388b2,	0xa8e74512,	0xcb9f97ab,	0x3588376e,
+0x483048d2,	0xe3ee2145,	0x029eba71,	0x2a6efdb8,
+0x7e629d7c,	0xe7458f31,	0xd2edd71b,	0xa265588c,
+0xee3a7a3d,	0xc3f6a74d,	0xb55fbbb2,	0xac3dc469,
+0x350e24ac,	0xfdfb094c,	0xc6760d93,	0x014aad92,
+0x4bf74e51,	0x9ab932af,	0xc600d00f,	0x5dd0c96d,
+0x6b081fbe,	0xecba3e1c,	0x19abcf55,	0x46905ea0,
+0x41ff2a8f,	0x9305e1c0,	0xdbfa1df1,	0x8100370e,
+0x0df9b3df,	0x09763efc,	0x60447b79,	0xb64eb88a,
+0xe4c706de,	0x2dadc973,	0xf6bc6357,	0x7395486a,
+0xf15aae31,	0x1daca268,	0xa5b8395f,	0x127bcb11,
+0xe84c9715,	0xe0417152,	0xc3d8520e,	0x0bdcbb00,
+0xf3daba82,	0xe1925ffb,	0x3526a2e8,	0xda189c78,
+0xa32bf2fc,	0xe7de02ab,	0x2f344593,	0x07b916dd,
+0xe2d46b57,	0x83921885,	0x6f066626,	0x7ce5ab67,
+0xebcaf5de,	0xbb0f6b00,	0x6d1faffb,	0x1eff0018,
+0x2debe6bc,	0x57d003b3,	0x3a3f5f80,	0xec6b7c0e,
+0x9f1dd663,	0xbebdbf56,	0x98e5774e,	0xb7a29504,
+0x5166a8c5,	0xaf7ce332,	0xca5e70c5,	0xfe235309,
+0x9c23f707,	0x99b08cc4,	0x2fe1edd1,	0xba36918f,
+0x262dd395,	0x423edc8c,	0x801e8f1f,	0x5b4cc6c5,
+0x3fcdf7f4,	0x5a490992,	0xd4006978,	0x977e2f86,
+0x6311af7b,	0x06bb2412,	0x2be72eb1,	0x5706b252,
+0xa000c75b,	0xe3ea5cff,	0xc9208730,	0xd9e369fb,
+0x1aed50e2,	0x8916d70d,	0x87f01eb6,	0x663b8f67,
+0x3dc68ee3,	0x5197b72b,	0xddb19fb8,	0x6839be2a,
+0x99fcfc25,	0x5542f267,	0xa922eea9,	0xc9ae9d93,
+0xcf8a9d64,	0x76bfeec4,	0xacbcd4c6,	0x81960ab0,
+0x7b24eb81,	0x8e8cad81,	0xfb2c1362,	0x9ccf1224,
+0x16d2c962,	0x18f7d553,	0x2a7f9c1e,	0x3678f775,
+0x1210588a,	0xe1644769,	0x3dd29db7,	0xbe9daa2c,
+0xe9c4e13a,	0x8d9de528,	0x19c3075e,	0x68a336d4,
+0x0ba157f3,	0xe3780ca6,	0x69c54c28,	0x9f96bb00,
+0xa78204e9,	0x1c8627cf,	0x2fd52aa9,	0x957b15ed,
+0xd3d61e03,	0x658cea71,	0x42d77750,	0x0c0755bc,
+0xde372a0d,	0x0d3687d7,	0xc04c56f6,	0xc3882257,
+0x98fd462c,	0xb65fac1e,	0x01b5ecab,	0xd554413d,
+0xb4beec40,	0xb4caab5e,	0xdeee4085,	0xd1b0500c,
+0x6845de70,	0x5a06e889,	0xfc89a4a7,	0xedbfd435,
+0xac039058,	0x9c1acd2f,	0x876fbfac,	0x9d8b83f3,
+0x8aa71c5f,	0x2e0f12ef,	0x87ff0c68,	0x53a9d19a,
+0x0ee62d27,	0x5d93a3f4,	0x7f13dc77,	0xd4ec7c79,
+0xd72a35c8,	0xb84ba058,	0x21e1d1ad,	0xbcf9c0fe,
+0x106fb166,	0x84ff4a86,	0x3b2d960f,	0x4cf3ab0e,
+0x65d25f76,	0xdcda7e29,	0xc444ddc8,	0xe97096dc,
+0xbfe1815c,	0x25b9dec5,	0x7aed80de,	0x6cbb6f7a,
+0x2daf76b7,	0x249ee47f,	0xdc6e770d,	0xa5a02e7d,
+0xd019d0d7,	0x17feead1,	0xbf80c1f6,	0x83644ac0,
+0x412f1ce4,	0x59c1de41,	0x1a47db26,	0x8848ab89,
+0xc2c17745,	0x31183c80,	0x9bb13cc3,	0x6da9c349,
+0x414b378d,	0xd58df4ba,	0x41f5ca37,	0x02a5162f,
+0x2843bb24,	0xbd2bb85a,	0x0b2c6e81,	0x2d50fe1d,
+0xc67b2c07,	0x630ce2b3,	0x73274d84,	0x3b4ba900,
+0x5e672d3c,	0x7ef23846,	0x81036625,	0x380b3d3b,
+0x391470b1,	0x5b3dcbed,	0x63038751,	0xa0c7aed8,
+0xc185b677,	0x516b8170,	0xbf79f025,	0x2b4c9edb,
+0x29354139,	0x9deabe33,	0x2838f581,	0x0574281f,
+0xc1267da2,	0x0c070755,	0x6832a8b9,	0x57436eed,
+0xe604c645,	0x4f13172a,	0x3227ac12,	0xf6b78267,
+0xbbd5d003,	0x5f8ae7ed,	0x74b6682c,	0x356b9e81,
+0x82703c20,	0x8ccf1f78,	0xa6b79197,	0x434d5316,
+0x1ba0853a,	0xe6ae4829,	0x1193ed0a,	0xa2d171f0,
+0x4f565a15,	0xf78ea4af,	0xa9a27e39,	0x30a45316,
+0xc005a8f6,	0x79a23d86,	0x07edcbe3,	0x3b76806b,
+0x3df6268a,	0xb0f33186,	0x2fd51855,	0xb34efefe,
+0xa24ce423,	0x6c62d711,	0x335c7252,	0x0d2ddcff,
+0x64485539,	0x00c8a89e,	0x4827ad2d,	0x01de50f4,
+0x593a9a38,	0xee90b919,	0xf523cd40,	0x97ed7009,
+0x1038e6b0,	0x95931966,	0xaaac22b9,	0xef1b9915,
+0x23f6d33c,	0xe417a460,	0x4e9b59c2,	0x3fd38b75,
+0x7ceabd08,	0x8279d672,	0xf24936e8,	0x668630f8,
+0x3cb0ddc0,	0x56c56418,	0x91221ef8,	0xc8926c65,
+0x4d7436b6,	0xc06b5b1e,	0xdea496b1,	0x4fa4c971,
+0xeea15028,	0x7aead456,	0x1329b826,	0xcf9a4d4f,
+0xabd69aba,	0x9dd78c2e,	0x5e9782ff,	0x563f3cb0,
+0xfc2db55c,	0xb2d5f64b,	0x9478caeb,	0x7409ae76,
+0xc4690516,	0xb12bb352,	0xad5283c7,	0x608e7a23,
+0xc8b4b59a,	0x0da06391,	0x9a6ccd78,	0xe4af91ad,
+0xb156f74a,	0x790b21dd,	0x6ce9970b,	0x46e89ac1,
+0x07815d28,	0x1f2fc3ac,	0x690cd168,	0x6ae48bb4,
+0x1ed48c84,	0xe5f121a3,	0x49a762cf,	0xc5e8fd6a,
+0x75d45162,	0xf49c2c5e,	0xd161eb4a,	0xb6351b73,
+0xc2605562,	0xb097aa9d,	0x114421ee,	0xf93baf78,
+0x82b9b2ab,	0x0374be4d,	0xd715656b,	0x3524549f,
+0xb37dc283,	0xfa8308d0,	0x3f69f2be,	0x238bc31e,
+0x839f3f68,	0x0639b8d7,	0xa8cdbe8e,	0xd15c7cb3,
+0x0a31ec87,	0x39a57286,	0x7c3ffef5,	0x461d70b2,
+0x7d1e8a90,	0x629b803f,	0x351b6cb8,	0x255391c2,
+0x07215420,	0x5e1aef8c,	0xa3b48e74,	0x8fa78c73,
+0xb6fab65c,	0xb13cb77f,	0x5bd44236,	0x31cbeab2,
+0x9f68d29a,	0x207a2b05,	0x668ac8a7,	0xb6de6033,
+0x3d2a4173,	0x04a2543a,	0x559b1b7c,	0x5e9116d4,
+0x5cb3ee57,	0x4a47f644,	0x90be9381,	0xbccc9cd2,
+0x3160e0d5,	0xed791f87,	0xdd9da7a8,	0x3e6d398b,
+0x6a68ad78,	0x418974ef,	0xfd010940,	0x8bed7055,
+0xf21e4d13,	0xac8160b9,	0x85f10ecb,	0xd637b0e2,
+0x987dd54e,	0x9835f225,	0xdbee940c,	0x9a34e16d,
+0x15fcfb54,	0x6720e48c,	0x9a42e266,	0x31eb0270,
+0x714dee04,	0xbcd417d8,	0xedf7757e,	0x099c4e89,
+0xee3e6c2e,	0x6246d530,	0xfbdad1d6,	0xbbe301a3,
+0xe08f829c,	0xa3c7d9c4,	0xe753a1dd,	0xf1466da1,
+0xa1e353a7,	0x33828150,	0x267d4059,	0x458bd806,
+0xac0ed307,	0x2079bf7c,	0xb25200db,	0x9dfd338c,
+0x0b94573e,	0x8188fa16,	0x9e641b63,	0xafa2a60c,
+0x61e5f820,	0x63a38983,	0x172d3a6f,	0xc98a34b2,
+0x532b56f5,	0x1883cb1a,	0x93ba9692,	0x7d85d109,
+0xd20ffd1a,	0xcc6e9937,	0xb3813eb1,	0xea7e1b45,
+0xf1e09c71,	0x35aa1ab9,	0xbd2d43d7,	0xc53a07ef,
+0xf3fa3fd6,	0xf3cd1e20,	0x5e620481,	0xd7bec1b0,
+0xc7d3caf6,	0xe9eae29f,	0x19c5b2c1,	0x940e3186,
+0x200f0a30,	0xbaf511b1,	0x103cb39c,	0x3f46b067,
+0xba6c5e9a,	0xc32b5592,	0x393e8503,	0x7ea29847,
+0x04d4a493,	0x18fc67d5,	0xea4ff94e,	0xc0281d5e,
+0xaeeaae85,	0x13be6b70,	0xa1bc8be4,	0xa1edbe06,
+0x572b8b35,	0x3baca7c5,	0x06ac9591,	0x8309b11d,
+0x7f381b05,	0xb16dd9b2,	0xf9b5d898,	0xb2e04c3a,
+0xed89b7dd,	0xd30e7e33,	0x4ac6cb61,	0xd2c50800,
+0x6554ae61,	0xa263efe2,	0x666244c3,	0xb6aaa480,
+0xcb4344ee,	0x31cf3efa,	0x14a4a476,	0xf6804765,
+0xaca47c23,	0x7e15ae69,	0xaffade7d,	0x693a6ff9,
+0x3f0f22c0,	0xe6135bcb,	0xf0632009,	0x06fa2abb,
+0xad0c1085,	0x3ce130b3,	0x70001594,	0xd80c452b,
+0x486c9d1f,	0x93b94966,	0x81612f95,	0x7573faea,
+0x1568ddb9,	0x3c1d26e5,	0x0a5d7b45,	0x5ea78077,
+0x1c5491f9,	0x24363c4b,	0x54b8e62a,	0xb86697e6,
+0x18750c76,	0xa355cee8,	0x9c09de46,	0xb022ec2b,
+0xfa142272,	0xd1e1dcce,	0xc7c2f6c9,	0xd8e72fc1,
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
new file mode 100644
index 0000000..3343d11
--- /dev/null
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_INTEL_MODEL_206AX_H
+#define _CPU_INTEL_MODEL_206AX_H
+
+/* SandyBridge bus clock is fixed at 100MHz */
+#define SANDYBRIDGE_BCLK		100
+
+#define IA32_FEATURE_CONTROL		0x3a
+#define  CPUID_VMX			(1 << 5)
+#define  CPUID_SMX			(1 << 6)
+#define MSR_FEATURE_CONFIG		0x13c
+#define IA32_PLATFORM_DCA_CAP		0x1f8
+#define IA32_MISC_ENABLE		0x1a0
+#define IA32_PERF_CTL 			0x199
+#define IA32_THERM_INTERRUPT		0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+#define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
+#define MSR_LT_LOCK_MEMORY		0x2e7
+#define IA32_MC0_STATUS 		0x401
+
+#define MSR_PIC_MSG_CONTROL		0x2e
+#define MSR_PLATFORM_INFO		0xce
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PMG_IO_CAPTURE_BASE		0xe4
+
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
+#define MSR_TURBO_RATIO_LIMIT		0x1ad
+#define MSR_POWER_CTL			0x1fc
+
+#define MSR_PKGC3_IRTL			0x60a
+#define MSR_PKGC6_IRTL			0x60b
+#define MSR_PKGC7_IRTL			0x60c
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
+/* long duration in low dword, short duration in high dword */
+#define MSR_PKG_POWER_LIMIT		0x610
+#define  PKG_POWER_LIMIT_MASK		0x7fff
+#define  PKG_POWER_LIMIT_EN		(1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT	17
+#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+
+#define MSR_PP0_CURRENT_CONFIG		0x601
+#define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG		0x602
+#define  PP1_CURRENT_LIMIT		(35 << 3) /* 35 A */
+#define MSR_PKG_POWER_SKU_UNIT		0x606
+#define MSR_PKG_POWER_SKU		0x614
+#define MSR_PP0_POWER_LIMIT		0x638
+#define MSR_PP1_POWER_LIMIT		0x640
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES			8
+#define PSS_RATIO_STEP			2
+#define PSS_LATENCY_TRANSITION		10
+#define PSS_LATENCY_BUSMASTER		10
+
+#ifdef __SMM__
+/* Lock MSRs */
+void intel_model_206ax_finalize_smm(void);
+#else
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+#endif
+
+#endif
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
new file mode 100644
index 0000000..dc78cee
--- /dev/null
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -0,0 +1,559 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/name.h>
+#include <pc80/mc146818rtc.h>
+#include <usbdebug.h>
+#include "model_206ax.h"
+
+/*
+ * List of suported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* MWAIT State 0 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C3 */
+		.latency = 63,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 4: C6 */
+		.latency = 87,
+		.power = 350,
+		.resource = {
+			.addrl = 0x20,	/* MWAIT State 2 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 5: C7 */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 6: C7S */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{ 0 }
+};
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_00000025.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+static void enable_vmx(void)
+{
+	struct cpuid_result regs;
+	msr_t msr;
+	int enable = 0;
+
+	if (get_option(&enable, "enable_vmx") < 0)
+		enable = 0;
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		/* VMX locked. If we set it again we get an illegal
+		 * instruction
+		 */
+		return;
+	}
+
+	regs = cpuid(1);
+	if (regs.ecx & CPUID_VMX) {
+		if (enable)
+			msr.lo |= (1 << 2);
+		else
+			msr.lo &= ~(1 << 2);
+
+		if (regs.ecx & CPUID_SMX) {
+			if (enable)
+				msr.lo |= (1 << 1);
+			else
+				msr.lo &= ~(1 << 1);
+		}
+	}
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+	[0]   = 0x00,
+	[1]   = 0x0a,
+	[2]   = 0x0b,
+	[3]   = 0x4b,
+	[4]   = 0x0c,
+	[5]   = 0x2c,
+	[6]   = 0x4c,
+	[7]   = 0x6c,
+	[8]   = 0x0d,
+	[10]  = 0x2d,
+	[12]  = 0x4d,
+	[14]  = 0x6d,
+	[16]  = 0x0e,
+	[20]  = 0x2e,
+	[24]  = 0x4e,
+	[28]  = 0x6e,
+	[32]  = 0x0f,
+	[40]  = 0x2f,
+	[48]  = 0x4f,
+	[56]  = 0x6f,
+	[64]  = 0x10,
+	[80]  = 0x30,
+	[96]  = 0x50,
+	[112] = 0x70,
+	[128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+	[0x00] = 0,
+	[0x0a] = 1,
+	[0x0b] = 2,
+	[0x4b] = 3,
+	[0x0c] = 4,
+	[0x2c] = 5,
+	[0x4c] = 6,
+	[0x6c] = 7,
+	[0x0d] = 8,
+	[0x2d] = 10,
+	[0x4d] = 12,
+	[0x6d] = 14,
+	[0x0e] = 16,
+	[0x2e] = 20,
+	[0x4e] = 24,
+	[0x6e] = 28,
+	[0x0f] = 32,
+	[0x2f] = 40,
+	[0x4f] = 48,
+	[0x6f] = 56,
+	[0x10] = 64,
+	[0x30] = 80,
+	[0x50] = 96,
+	[0x70] = 112,
+	[0x11] = 128,
+};
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void set_power_limits(u8 power_limit_1_time)
+{
+	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+	msr_t limit;
+	unsigned power_unit;
+	unsigned tdp, min_power, max_power, max_time;
+	u8 power_limit_1_val;
+
+	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+		return;
+
+	if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+		return;
+
+	/* Get units */
+	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+	/* Get power defaults for this SKU */
+	msr = rdmsr(MSR_PKG_POWER_SKU);
+	tdp = msr.lo & 0x7fff;
+	min_power = (msr.lo >> 16) & 0x7fff;
+	max_power = msr.hi & 0x7fff;
+	max_time = (msr.hi >> 16) & 0x7f;
+
+	printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
+
+	if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+		power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+	if (min_power > 0 && tdp < min_power)
+		tdp = min_power;
+
+	if (max_power > 0 && tdp > max_power)
+		tdp = max_power;
+
+	power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+	/* Set long term power limit to TDP */
+	limit.lo = 0;
+	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+	limit.lo |= PKG_POWER_LIMIT_EN;
+	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+		PKG_POWER_LIMIT_TIME_SHIFT;
+
+	/* Set short term power limit to 1.25 * TDP */
+	limit.hi = 0;
+	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+	limit.hi |= PKG_POWER_LIMIT_EN;
+	/* Power limit 2 time is only programmable on SNB EP/EX */
+
+	wrmsr(MSR_PKG_POWER_LIMIT, limit);
+}
+
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 28);	// C1 Auto Undemotion Enable
+	msr.lo |= (1 << 27);	// C3 Auto Undemotion Enable
+	msr.lo |= (1 << 26);	// C1 Auto Demotion Enable
+	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
+	msr.lo &= ~(1 << 10);	// Disable IO MWAIT redirection
+	msr.lo |= 7;		// No package C-state limit
+	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+
+	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
+	msr.lo &= ~0x7ffff;
+	msr.lo |= (PMB0_BASE + 4);	// LVL_2 base address
+	msr.lo |= (2 << 16);		// CST Range: C7 is max C-state
+	wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
+
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
+	wrmsr(MSR_MISC_PWR_MGMT, msr);
+
+	msr = rdmsr(MSR_POWER_CTL);
+	msr.lo |= (1 << 18);	// Enable Energy Perf Bias MSR 0x1b0
+	msr.lo |= (1 << 1);	// C1E Enable
+	msr.lo |= (1 << 0);	// Bi-directional PROCHOT#
+	wrmsr(MSR_POWER_CTL, msr);
+
+	/* C3 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+	wrmsr(MSR_PKGC3_IRTL, msr);
+
+	/* C6 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+	wrmsr(MSR_PKGC6_IRTL, msr);
+
+	/* C7 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+	wrmsr(MSR_PKGC7_IRTL, msr);
+
+	/* Primary Plane Current Limit */
+	msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= PP0_CURRENT_LIMIT;
+	wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
+
+	/* Secondary Plane Current Limit */
+	msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= PP1_CURRENT_LIMIT;
+	wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
+}
+
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+	struct cpuid_result cpuid_regs;
+	msr_t msr;
+
+	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.ecx & (1 << 18)) {
+		msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+		msr.lo |= 1;
+		wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+	}
+}
+
+static void set_max_ratio(void)
+{
+	msr_t msr;
+
+	/* Platform Info bits 15:8 give max ratio */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	msr.hi = 0;
+	msr.lo &= 0xff00;
+	wrmsr(IA32_PERF_CTL, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: frequency set to %d\n",
+	       ((msr.lo >> 8) & 0xff) * 100);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+	msr_t msr;
+
+	/* Energy Policy is bits 3:0 */
+	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: energy policy set to %u\n",
+	       policy);
+}
+
+static void configure_mca(void)
+{
+	msr_t msr;
+	int i;
+
+	msr.lo = msr.hi = 0;
+	/* This should only be done on a cold boot */
+	for (i = 0; i < 7; i++)
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static void intel_cores_init(device_t cpu)
+{
+	struct cpuid_result result;
+	unsigned cores, threads, i;
+
+	result = cpuid_ext(0xb, 0); /* Threads per core */
+	threads = result.ebx & 0xff;
+
+	result = cpuid_ext(0xb, 1); /* Cores per package */
+	cores = result.ebx & 0xff;
+
+	/* Only initialize extra cores from BSP */
+	if (cpu->path.apic.apic_id)
+		return;
+
+	printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n",
+	       cpu->path.apic.apic_id, cores, threads);
+
+	for (i = 1; i < cores; ++i) {
+		struct device_path cpu_path;
+		device_t new;
+
+		/* Build the cpu device path */
+		cpu_path.type = DEVICE_PATH_APIC;
+		cpu_path.apic.apic_id =
+			cpu->path.apic.apic_id + i;
+
+		/* Update APIC ID if no hyperthreading */
+		if (threads == 1)
+			cpu_path.apic.apic_id <<= 1;
+
+		/* Allocate the new cpu device structure */
+		new = alloc_dev(cpu->bus, &cpu_path);
+		if (!new)
+			continue;
+
+		printk(BIOS_DEBUG, "CPU: %u has core %u\n",
+		       cpu->path.apic.apic_id,
+		       new->path.apic.apic_id);
+
+		/* Start the new cpu */
+		if (!start_cpu(new)) {
+			/* Record the error in cpu? */
+			printk(BIOS_ERR, "CPU %u would not start!\n",
+			       new->path.apic.apic_id);
+		}
+	}
+}
+
+static void model_206ax_init(device_t cpu)
+{
+	char processor_name[49];
+	struct cpuid_result cpuid_regs;
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG
+	// Is this caution really needed?
+	if(!ehci_debug_addr)
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs based on physical address size */
+	cpuid_regs = cpuid(0x80000008);
+	x86_setup_fixed_mtrrs();
+	x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+	x86_mtrr_check();
+
+	/* Setup Page Attribute Tables (PAT) */
+	// TODO set up PAT
+
+#if CONFIG_USBDEBUG
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+	setup_lapic();
+
+	/* Enable virtualization if enabled in CMOS */
+	enable_vmx();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Set Max Ratio */
+	set_max_ratio();
+
+	/* Enable Turbo */
+	enable_turbo();
+
+	/* Start up extra cores */
+	intel_cores_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_206ax_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */
+	{ X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */
+	{ X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+	.cstates  = cstate_map,
+};
+
diff --git a/src/cpu/intel/model_306ax/Kconfig b/src/cpu/intel/model_306ax/Kconfig
new file mode 100644
index 0000000..1954d75
--- /dev/null
+++ b/src/cpu/intel/model_306ax/Kconfig
@@ -0,0 +1,19 @@
+config CPU_INTEL_MODEL_206AX
+	bool
+	select SMP
+	select SSE2
+	select UDELAY_LAPIC
+	select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_MODEL_206AX
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/model_206ax/bootblock.c"
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+endif
+
diff --git a/src/cpu/intel/model_306ax/Makefile.inc b/src/cpu/intel/model_306ax/Makefile.inc
new file mode 100644
index 0000000..67ead07
--- /dev/null
+++ b/src/cpu/intel/model_306ax/Makefile.inc
@@ -0,0 +1,6 @@
+driver-y += model_206ax_init.c
+subdirs-y += ../../x86/name
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_306ax/acpi.c b/src/cpu/intel/model_306ax/acpi.c
new file mode 100644
index 0000000..5160a64
--- /dev/null
+++ b/src/cpu/intel/model_306ax/acpi.c
@@ -0,0 +1,255 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/acpi.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "chip.h"
+
+#define MIN_POWER 16000
+#define MAX_POWER 35000
+
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	switch (c.x86_model) {
+	case 0x2a: /* SandyBridge */
+		result = cpuid_ext(0xb, 1);
+		cores = result.ebx & 0xff;
+		break;
+	default:
+		cores = (cpuid_ebx(1) >> 16) & 0xff;
+		break;
+	}
+
+	return cores;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0)
+		length += acpigen_write_CST_package(1, &cstates[c1]);
+	if (c2 > 0)
+		length += acpigen_write_CST_package(2, &cstates[c2]);
+	if (c3 > 0)
+		length += acpigen_write_CST_package(3, &cstates[c3]);
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_CST_table(struct cpu_intel_model_206ax_config *conf)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa1);		/* ElseOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					 conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+void generate_cpu_entries(void)
+{
+	int len_pr, len_ps;
+	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+	msr_t msr;
+	int totalcores = dev_count_cpu();
+	int cores_per_package = get_cores_per_package();
+	int numcpus = totalcores/cores_per_package;
+	int fsb = 100; /* BCLK fixed at 100MHz for SandyBridge */
+	struct cpu_intel_model_206ax_config *conf = NULL;
+	u8 coord_type = HW_ALL;
+	device_t cpu;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	cpu = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!cpu)
+		return;
+	conf = cpu->chip_info;
+	coord_type = conf->pstate_coord_type;
+
+	if (conf->disable_acpi) {
+		printk(BIOS_DEBUG, "ACPI: P-state and C-state tables "
+		       "disabled by devicetree\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+	       numcpus, cores_per_package);
+
+	for (cpuID=1; cpuID <=numcpus; cpuID++) {
+		for (coreID=1; coreID<=cores_per_package; coreID++) {
+			if (coreID>1) {
+				pcontrol_blk = 0;
+				plen = 0;
+			}
+			len_pr = acpigen_write_processor(
+				(cpuID-1)*cores_per_package+coreID-1,
+				pcontrol_blk, plen);
+			len_pr += acpigen_write_empty_PCT();
+			len_pr += acpigen_write_PSD_package(
+				cpuID-1,cores_per_package,coord_type);
+			len_pr += acpigen_write_name("_PSS");
+
+			int max_states=8;
+			int bus_step=2;
+			msr = rdmsr(0xce);
+			int bus_min=(msr.hi >> (40-32)) & 0xff;
+			int bus_max=(msr.lo >> 8) & 0xff;
+			int clock_max=fsb*bus_max;
+			int clock_min=fsb*bus_min;
+			printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n",
+			       clock_min, clock_max);
+			int power_max=MAX_POWER;
+			int power_min=MIN_POWER;
+			int num_states=(bus_max-bus_min)/bus_step;
+			while (num_states > max_states-1) {
+				bus_step <<= 1;
+				num_states >>= 1;
+			}
+			printk(BIOS_DEBUG, "adding %x P-States between "
+			       "busratio %x and %x, incl. P0\n",
+			       num_states+1, bus_min, bus_max);
+			int power_step=(power_max-power_min)/num_states;
+			int clock_step=(clock_max-clock_min)/num_states;
+
+			/* P[0] is Turbo if enabled */
+			if (get_turbo_state() == TURBO_ENABLED) {
+				len_ps = acpigen_write_package(num_states+2);
+				msr = rdmsr(0x1ad);
+				int bus_turbo = msr.lo & 0xff;
+				len_ps += acpigen_write_PSS_package(
+					clock_max+1 /*mhz*/,
+					power_max+1 /*mW*/,
+					10 /*lat1*/,
+					10 /*lat2*/,
+					bus_turbo<<8 /*control*/,
+					bus_turbo<<8 /*status*/);
+			} else {
+				len_ps = acpigen_write_package(num_states+1);
+			}
+
+			len_ps += acpigen_write_PSS_package(
+				clock_max /*mhz*/,
+				power_max /*mW*/,
+				10 /*lat1*/,
+				10 /*lat2*/,
+				bus_max<<8 /*control*/,
+				bus_max<<8 /*status*/);
+			int current_bus=bus_min+((num_states-1)*bus_step);
+			int current_power=power_min+((num_states-1)*power_step);
+			int current_clock=clock_min+((num_states-1)*clock_step);
+			int i;
+			for (i=0;i<num_states; i++) {
+				len_ps += acpigen_write_PSS_package(
+					current_clock /*mhz*/,
+					current_power /*mW*/,
+					10 /*lat1*/,
+					10 /*lat2*/,
+					current_bus<<8 /*control*/,
+					current_bus<<8 /*status*/);
+				current_bus -= bus_step;
+				current_power -= power_step;
+				current_clock -= clock_step;
+			}
+			len_ps--;
+			acpigen_patch_len(len_ps);
+			len_pr += acpigen_write_PPC(0);
+			/* Generate C-state tables */
+			len_pr += generate_CST_table(conf);
+		len_pr += len_ps;
+		len_pr--;
+		acpigen_patch_len(len_pr);
+		}
+	}
+}
+
+struct chip_operations cpu_intel_model_206ax_ops = {
+	CHIP_NAME("Intel SandyBridge CPU")
+};
diff --git a/src/cpu/intel/model_306ax/bootblock.c b/src/cpu/intel/model_306ax/bootblock.c
new file mode 100644
index 0000000..6b12b89
--- /dev/null
+++ b/src/cpu/intel/model_306ax/bootblock.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_0000001A.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+struct microcode {
+	u32 hdrver;	/* Header Version */
+	u32 rev;	/* Patch ID       */
+	u32 date;	/* DATE           */
+	u32 sig;	/* CPUID          */
+
+	u32 cksum;	/* Checksum       */
+	u32 ldrver;	/* Loader Version */
+	u32 pf;		/* Platform ID    */
+
+	u32 data_size;	/* Data size      */
+	u32 total_size;	/* Total size     */
+
+	u32 reserved[3];
+	u32 bits[1012];
+};
+
+static inline u32 read_microcode_rev(void)
+{
+	/* Some Intel Cpus can be very finicky about the
+	 * CPUID sequence used.  So this is implemented in
+	 * assembly so that it works reliably.
+	 */
+	msr_t msr;
+	__asm__ volatile (
+		"wrmsr\n\t"
+		"xorl %%eax, %%eax\n\t"
+		"xorl %%edx, %%edx\n\t"
+		"movl $0x8b, %%ecx\n\t"
+		"wrmsr\n\t"
+		"movl $0x01, %%eax\n\t"
+		"cpuid\n\t"
+		"movl $0x08b, %%ecx\n\t"
+		"rdmsr \n\t"
+		: /* outputs */
+		"=a" (msr.lo), "=d" (msr.hi)
+		: /* inputs */
+		: /* trashed */
+		 "ecx"
+	);
+	return msr.hi;
+}
+
+void intel_update_microcode(const void *microcode_updates)
+{
+	unsigned int eax;
+	unsigned int pf, rev, sig;
+	unsigned int x86_model, x86_family;
+	const struct microcode *m;
+	const char *c;
+	msr_t msr;
+
+	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(0x8B, msr);
+	eax = cpuid_eax(1);
+	msr = rdmsr(0x8B);
+	rev = msr.hi;
+	x86_model = (eax >>4) & 0x0f;
+	x86_family = (eax >>8) & 0x0f;
+	sig = eax;
+
+	pf = 0;
+	if ((x86_model >= 5)||(x86_family>6)) {
+		msr = rdmsr(0x17);
+		pf = 1 << ((msr.hi >> 18) & 7);
+	}
+
+	m = microcode_updates;
+	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
+		if ((m->sig == sig) && (m->pf & pf)) {
+			unsigned int new_rev;
+			msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
+			msr.hi = 0;
+			wrmsr(0x79, msr);
+
+			/* Read back the new microcode version */
+			new_rev = read_microcode_rev();
+			break;
+		}
+		if (m->total_size) {
+			c += m->total_size;
+		} else {
+			c += 2048;
+		}
+	}
+}
+
+static void bootblock_cpu_init(void)
+{
+	intel_update_microcode(microcode_updates);
+}
diff --git a/src/cpu/intel/model_306ax/cache_as_ram.inc b/src/cpu/intel/model_306ax/cache_as_ram.inc
new file mode 100644
index 0000000..9d9a5ab
--- /dev/null
+++ b/src/cpu/intel/model_306ax/cache_as_ram.inc
@@ -0,0 +1,323 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <cpu/x86/stack.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
+
+cache_as_ram:
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
+
+	/* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+	movl	(%esi), %eax
+	bt	$12, %eax
+	jc	wait_for_sipi
+
+	post_code(0x21)
+	/* Zero out all fixed range and variable range MTRRs. */
+	movl	$mtrr_table, %esi
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+clear_mtrrs:
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	post_code(0x22)
+	/* Configure the default memory type to uncacheable. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	post_code(0x23)
+	/* Set Cache-as-RAM base address. */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	post_code(0x24)
+	/* Set Cache-as-RAM mask. */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x25)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+        movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* Clear the cache memory reagion. */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	// movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+
+	post_code(0x26)
+	/* Enable Cache-as-RAM mode by disabling cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
+#if CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$0x0000000f, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	wrmsr
+
+	post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for ram init code to run faster */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+#endif
+
+	post_code(0x28)
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0
+
+	/* Set up the stack pointer below MRC variable space. */
+	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
+		  CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+before_romstage:
+	post_code(0x29)
+	/* Call romstage.c main function. */
+	call	main
+
+	post_code(0x2f)
+
+	/* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+	cld
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	$24, %ecx
+	rep	movsb
+#endif
+
+	post_code(0x30)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x31)
+
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~MTRRdefTypeEn), %eax
+	wrmsr
+
+	post_code(0x31)
+
+	invd
+#if CONFIG_CACHE_MRC_BIN
+	/* Clear MTRR that was used to cache MRC */
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	movl	$MTRRphysBase_MSR(2), %ecx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	wrmsr
+#endif
+
+	post_code(0x33)
+
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x36)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x38)
+
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
+	movl	$MTRRphysBase_MSR(0), %ecx
+	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(0), %ecx
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx	// 36bit address space
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+	post_code(0x3c)
+
+#if CONFIG_HAVE_ACPI_RESUME
+	movl	CBMEM_BOOT_MODE, %eax
+	cmpl	$0x2, %eax // Resume?
+	jne	__acpi_resume_backup_done
+
+	/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+	 * through stage 2. We could keep stuff like stack and heap in high
+	 * tables memory completely, but that's a wonderful clean up task for
+	 * another day.
+	 */
+	cld
+	movl	$CONFIG_RAMBASE, %esi
+	movl	CBMEM_RESUME_BACKUP, %edi
+	movl	$HIGH_MEMORY_SAVE / 4, %ecx
+	rep	movsl
+
+__acpi_resume_backup_done:
+#endif
+
+	post_code(0x3d)
+
+	/* Clear boot_complete flag. */
+	xorl	%ebp, %ebp
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+
+	movl	%ebp, %esi
+
+	movl	$ROMSTAGE_STACK, %esp
+	movl	%esp, %ebp
+	pushl	%esi
+	call	copy_and_run
+
+.Lhlt:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.Lhlt
+
+mtrr_table:
+	/* Fixed MTRRs */
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
+	/* Variable MTRRs */
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
+
diff --git a/src/cpu/intel/model_306ax/chip.h b/src/cpu/intel/model_306ax/chip.h
new file mode 100644
index 0000000..48e0c89
--- /dev/null
+++ b/src/cpu/intel/model_306ax/chip.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_model_206ax_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_model_206ax_config {
+	u8 disable_acpi;	/* Do not generate CPU ACPI tables */
+
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* ACPI C1 on Battery Power */
+	int c2_battery;		/* ACPI C2 on Battery Power */
+	int c3_battery;		/* ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* ACPI C1 on AC Power */
+	int c2_acpower;		/* ACPI C2 on AC Power */
+	int c3_acpower;		/* ACPI C3 on AC Power */
+};
diff --git a/src/cpu/intel/model_306ax/model_306ax_init.c b/src/cpu/intel/model_306ax/model_306ax_init.c
new file mode 100644
index 0000000..b9c484f
--- /dev/null
+++ b/src/cpu/intel/model_306ax/model_306ax_init.c
@@ -0,0 +1,474 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/name.h>
+#include <usbdebug.h>
+
+/*
+ * List of suported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* MWAIT State 0 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C3 */
+		.latency = 63,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{	/* 4: C6 */
+		.latency = 87,
+		.power = 350,
+		.resource = {
+			.addrl = 0x20,	/* MWAIT State 2 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{	/* 5: C7 */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{	/* 6: C7S */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{ 0 }
+};
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_0000001A.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+#define IA32_FEATURE_CONTROL 0x003a
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+static void enable_vmx(void)
+{
+	struct cpuid_result regs;
+	msr_t msr;
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		/* VMX locked. If we set it again we get an illegal
+		 * instruction
+		 */
+		return;
+	}
+
+	regs = cpuid(1);
+	if (regs.ecx & CPUID_VMX) {
+		msr.lo |= (1 << 2);
+		if (regs.ecx & CPUID_SMX)
+			msr.lo |= (1 << 1);
+	}
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+
+	msr.lo |= (1 << 0); /* Set lock bit */
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+#define PMG_CST_CONFIG_CONTROL	0xe2
+#define PMG_IO_CAPTURE_BASE	0xe4
+#define MISC_PWR_MGMT		0x1aa
+#define POWER_CTL		0x1fc
+#define PP0_CURRENT_CONFIG	0x601
+#define PP1_CURRENT_CONFIG	0x602
+#define PKGC3_IRTL		0x60a
+#define PKGC6_IRTL		0x60b
+#define PKGC7_IRTL		0x60c
+#define  IRTL_VALID		(1 << 15)
+#define  IRTL_1_NS		(0 << 10)
+#define  IRTL_32_NS		(1 << 10)
+#define  IRTL_1024_NS		(2 << 10)
+#define  IRTL_32768_NS		(3 << 10)
+#define  IRTL_1048576_NS	(4 << 10)
+#define  IRTL_33554432_NS	(5 << 10)
+#define  IRTL_RESPONSE_MASK	(0x3ff)
+
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 28);	// C1 Auto Undemotion Enable
+	msr.lo |= (1 << 27);	// C3 Auto Undemotion Enable
+	msr.lo |= (1 << 26);	// C1 Auto Demotion Enable
+	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
+	msr.lo |= (1 << 15);	// config lock until next reset
+	msr.lo |= (1 << 10);	// Enable IO MWAIT redirection
+	msr.lo |= 7;		// No package C-state limit
+	wrmsr(PMG_CST_CONFIG_CONTROL, msr);
+
+	msr = rdmsr(PMG_IO_CAPTURE_BASE);
+	msr.lo &= ~0x7ffff;
+	msr.lo |= (PMB0_BASE + 4);	// LVL_2 base address
+	msr.lo |= (2 << 16);		// CST Range: C7 is max C-state
+	wrmsr(PMG_IO_CAPTURE_BASE, msr);
+
+	msr = rdmsr(MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
+	msr.lo |= (1 << 22);	// Lock TM interrupt
+	wrmsr(MISC_PWR_MGMT, msr);
+
+	msr = rdmsr(POWER_CTL);
+	msr.lo |= (1 << 18);	// Enable Energy Perf Bias MSR 0x1b0
+	msr.lo |= (1 << 1);	// C1E Enable
+	msr.lo |= (1 << 0);	// Bi-directional PROCHOT#
+	wrmsr(POWER_CTL, msr);
+
+	/* C3 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+	wrmsr(PKGC3_IRTL, msr);
+
+	/* C6 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+	wrmsr(PKGC6_IRTL, msr);
+
+	/* C7 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+	wrmsr(PKGC7_IRTL, msr);
+
+	/* Primary Plane Current Limit */
+	msr = rdmsr(PP0_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= 1000;
+	wrmsr(PP0_CURRENT_CONFIG, msr);
+
+	/* Secondary Plane Current Limit */
+	msr = rdmsr(PP1_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= 300;
+	wrmsr(PP1_CURRENT_CONFIG, msr);
+}
+
+#define IA32_MISC_ENABLE	0x1a0
+#define IA32_THERM_INTERRUPT		0x19b
+#define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+#define MSR_PIC_MSG_CONTROL	0x2e
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+#define IA32_PLATFORM_DCA_CAP	0x1f8
+static void configure_dca_cap(void)
+{
+	struct cpuid_result cpuid_regs;
+	msr_t msr;
+
+	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.ecx & (1 << 18)) {
+		msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+		msr.lo |= 1;
+		wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+	}
+}
+
+#define MSR_PLATFORM_INFO	0xce
+#define IA32_PERF_CTL 		0x199
+
+static void set_max_ratio(void)
+{
+	msr_t msr;
+
+	/* Platform Info bits 15:8 give max ratio */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	msr.hi = 0;
+	msr.lo &= 0xff00;
+	wrmsr(IA32_PERF_CTL, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: frequency set to %d\n",
+	       ((msr.lo >> 8) & 0xff) * 100);
+}
+
+#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define ENERGY_POLICY_PERFORMANCE	0
+#define ENERGY_POLICY_NORMAL		6
+#define ENERGY_POLICY_POWERSAVE		15
+
+static void set_energy_perf_bias(u8 policy)
+{
+	msr_t msr;
+
+	/* Energy Policy is bits 3:0 */
+	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: energy policy set to %u\n",
+	       policy);
+}
+
+#define IA32_MC0_STATUS 0x401
+static void configure_mca(void)
+{
+	msr_t msr;
+	int i;
+
+	msr.lo = msr.hi = 0;
+	/* This should only be done on a cold boot */
+	for (i = 0; i < 7; i++)
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static void intel_cores_init(device_t cpu)
+{
+	struct cpuid_result result;
+	unsigned cores, threads, i;
+
+	result = cpuid_ext(0xb, 0); /* Threads per core */
+	threads = result.ebx & 0xff;
+
+	result = cpuid_ext(0xb, 1); /* Cores per package */
+	cores = result.ebx & 0xff;
+
+	/* Only initialize extra cores from BSP */
+	if (cpu->path.apic.apic_id)
+		return;
+
+	printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n",
+	       cpu->path.apic.apic_id, cores, threads);
+
+	for (i = 1; i < cores; ++i) {
+		struct device_path cpu_path;
+		device_t new;
+
+		/* Build the cpu device path */
+		cpu_path.type = DEVICE_PATH_APIC;
+		cpu_path.apic.apic_id =
+			cpu->path.apic.apic_id + i;
+
+		/* Update APIC ID if no hyperthreading */
+		if (threads == 1)
+			cpu_path.apic.apic_id <<= 1;
+
+		/* Allocate the new cpu device structure */
+		new = alloc_dev(cpu->bus, &cpu_path);
+		if (!new)
+			continue;
+
+		printk(BIOS_DEBUG, "CPU: %u has core %u\n",
+		       cpu->path.apic.apic_id,
+		       new->path.apic.apic_id);
+
+		/* Start the new cpu */
+		if (!start_cpu(new)) {
+			/* Record the error in cpu? */
+			printk(BIOS_ERR, "CPU %u would not start!\n",
+			       new->path.apic.apic_id);
+		}
+	}
+}
+
+static void model_206ax_init(device_t cpu)
+{
+	char processor_name[49];
+	struct cpuid_result cpuid_regs;
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG
+	// Is this caution really needed?
+	if(!ehci_debug_addr)
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs based on physical address size */
+	cpuid_regs = cpuid(0x80000008);
+	x86_setup_mtrrs(cpuid_regs.eax & 0xff);
+	x86_mtrr_check();
+
+	/* Setup Page Attribute Tables (PAT) */
+	// TODO set up PAT
+
+#if CONFIG_USBDEBUG
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+	setup_lapic();
+
+	/* Enable virtualization */
+	enable_vmx();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Set Max Ratio */
+	set_max_ratio();
+
+	/* Enable Turbo */
+	enable_turbo();
+
+	/* Start up extra cores */
+	intel_cores_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_206ax_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */
+	{ X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */
+	{ X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+	.cstates  = cstate_map,
+};
+
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index f73c8a9..fb6bdc6 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -8,6 +8,7 @@
 	select CPU_INTEL_MODEL_106CX
 	select MMX
 	select SSE
+	select SSE2
 	select CACHE_AS_RAM
 
 config DCACHE_RAM_BASE
diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig
new file mode 100644
index 0000000..b0bdeb46
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/Kconfig
@@ -0,0 +1,37 @@
+config CPU_INTEL_SOCKET_RPGA989
+	bool
+
+if CPU_INTEL_SOCKET_RPGA989
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CPU_INTEL_MODEL_206AX
+	select MMX
+	select SSE
+	select CACHE_AS_RAM
+
+config CACHE_MRC_BIN
+	bool
+	default n
+
+config CACHE_MRC_SIZE_KB
+	int "MRC Cache Size in KB"
+	default 256
+
+config DCACHE_MRC_BASE
+	hex
+	default 0xfffd0000
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	hex
+	default 0x4000
+
+endif
diff --git a/src/cpu/intel/socket_rPGA989/Makefile.inc b/src/cpu/intel/socket_rPGA989/Makefile.inc
new file mode 100644
index 0000000..cef0606
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/Makefile.inc
@@ -0,0 +1,9 @@
+ramstage-y += socket_rPGA989.c
+subdirs-y += ../model_206ax
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../turbo
diff --git a/src/cpu/intel/socket_rPGA989/chip.h b/src/cpu/intel/socket_rPGA989/chip.h
new file mode 100644
index 0000000..f843e74
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_rPGA989_ops;
+
+struct cpu_intel_socket_rPGA989_config {
+};
diff --git a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c
new file mode 100644
index 0000000..2484571
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_intel_socket_rPGA989_ops = {
+	CHIP_NAME("Socket rPGA989 CPU")
+};
diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc
index c717a33..753dbcd 100644
--- a/src/cpu/intel/speedstep/Makefile.inc
+++ b/src/cpu/intel/speedstep/Makefile.inc
@@ -1 +1 @@
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 48e1a3c..64d9bc6 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -28,6 +28,8 @@
 #include <cpu/intel/acpi.h>
 #include <cpu/intel/speedstep.h>
 #include <device/device.h>
+#include <device/pci.h>
+#include "chip.h"
 
 // XXX: PSS table values for power consumption are for Merom only
 
@@ -48,18 +50,122 @@
 	return count;
 }
 
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	switch (c.x86_model) {
+	case 0x2a: /* SandyBridge */
+		result = cpuid_ext(0xb, 1);
+		cores = result.ebx & 0xff;
+		break;
+	default:
+		cores = (cpuid_ebx(1) >> 16) & 0xff;
+		break;
+	}
+
+	return cores;
+}
+
 static int get_fsb(void)
 {
-	u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7;
-	switch (fsbcode) {
-		case 0: return 266;
-		case 1: return 133;
-		case 2: return 200;
-		case 3: return 166;
-		case 5: return 100;
+	struct cpuinfo_x86 c;
+	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
+	int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 };
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return -1;
+
+	switch (c.x86_model) {
+	case 0xe:  /* Core Solo/Duo */
+	case 0x1c: /* Atom */
+		return core_fsb[rdmsr(0xcd).lo & 7];
+	case 0xf:  /* Core 2*/
+	case 0x17: /* Enhanced Core */
+		return core2_fsb[rdmsr(0xcd).lo & 7];
+	case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+		return 0; // DISABLED
 	}
-	printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
-	return 200;
+
+	printk(BIOS_DEBUG, "Warning: No supported FSB frequency\n");
+	return -1;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0)
+		length += acpigen_write_CST_package(1, &cstates[c1]);
+	if (c2 > 0)
+		length += acpigen_write_CST_package(2, &cstates[c2]);
+	if (c3 > 0)
+		length += acpigen_write_CST_package(3, &cstates[c3]);
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_CST_table(struct cpu_intel_speedstep_config *conf)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(len - 1);
+	return len;
 }
 
 void generate_cpu_entries(void)
@@ -68,8 +174,23 @@
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	msr_t msr;
 	int totalcores = determine_total_number_of_cores();
-	int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
+	int cores_per_package = get_cores_per_package();
 	int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
+	int fsb = get_fsb();
+	struct cpu_intel_speedstep_config *conf = NULL;
+	u8 coord_type = SW_ANY;
+	device_t cpu;
+
+	if (fsb <= 0)
+		return;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	cpu = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (cpu) {
+		conf = cpu->chip_info;
+		coord_type = conf->pstate_coord_type;
+	}
+
 	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
 
 	for (cpuID=1; cpuID <=numcpus; cpuID++) {
@@ -80,7 +201,8 @@
 		}
 		len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
 			len_pr += acpigen_write_empty_PCT();
-			len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
+			len_pr += acpigen_write_PSD_package(
+				cpuID-1,cores_per_package,coord_type);
 			len_pr += acpigen_write_name("_PSS");
 
 			int max_states=8;
@@ -91,8 +213,8 @@
 			int vid_min=msr.lo & 0x3f;
 			msr = rdmsr(IA32_PLATFORM_ID);
 			int vid_max=msr.lo & 0x3f;
-			int clock_max=get_fsb()*busratio_max;
-			int clock_min=get_fsb()*busratio_min;
+			int clock_max=fsb*busratio_max;
+			int clock_min=fsb*busratio_min;
 			printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
 #define MEROM_MIN_POWER 16000
 #define MEROM_MAX_POWER 35000
@@ -125,6 +247,8 @@
 			len_ps--;
 			acpigen_patch_len(len_ps);
 			len_pr += acpigen_write_PPC(0);
+			/* Generate C-state tables */
+			len_pr += generate_CST_table(conf);
 		len_pr += len_ps;
 		len_pr--;
 		acpigen_patch_len(len_pr);
diff --git a/src/cpu/intel/speedstep/chip.h b/src/cpu/intel/speedstep/chip.h
new file mode 100644
index 0000000..44f336a
--- /dev/null
+++ b/src/cpu/intel/speedstep/chip.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_speedstep_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_speedstep_config {
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* CPU C-state for ACPI C1 on Battery Power */
+	int c2_battery;		/* CPU C-state for ACPI C2 on Battery Power */
+	int c3_battery;		/* CPU C-state for ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* CPU C-state for ACPI C1 on AC Power */
+	int c2_acpower;		/* CPU C-state for ACPI C2 on AC Power */
+	int c3_acpower;		/* CPU C-state for ACPI C3 on AC Power */
+};
diff --git a/src/cpu/x86/mmx_disable.inc b/src/cpu/intel/speedstep/speedstep.c
similarity index 77%
copy from src/cpu/x86/mmx_disable.inc
copy to src/cpu/intel/speedstep/speedstep.c
index 1a4e70f..ff285c6 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/cpu/intel/speedstep/speedstep.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#include <device/device.h>
+#include "chip.h"
 
+struct chip_operations cpu_intel_speedstep_ops = {
+	CHIP_NAME("Intel SpeedStep CPU")
+};
diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc
new file mode 100644
index 0000000..48ec55d
--- /dev/null
+++ b/src/cpu/intel/turbo/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += turbo.c
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
new file mode 100644
index 0000000..779550e
--- /dev/null
+++ b/src/cpu/intel/turbo/turbo.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/msr.h>
+#include <arch/cpu.h>
+
+static int turbo_state = TURBO_UNKNOWN;
+
+static const char *turbo_state_desc[] = {
+	[TURBO_UNKNOWN]		= "unknown",
+	[TURBO_UNAVAILABLE]	= "unavailable",
+	[TURBO_DISABLED]	= "available but hidden",
+	[TURBO_ENABLED]		= "available and visible"
+};
+
+/*
+ * Determine the current state of Turbo and cache it for later.
+ * Turbo is a package level config so it does not need to be
+ * enabled on every core.
+ */
+int get_turbo_state(void)
+{
+	struct cpuid_result cpuid_regs;
+	int turbo_en, turbo_cap;
+	msr_t msr;
+
+	/* Return cached state if available */
+	if (turbo_state != TURBO_UNKNOWN)
+		return turbo_state;
+
+	cpuid_regs = cpuid(CPUID_LEAF_PM);
+	turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
+
+	msr = rdmsr(MSR_IA32_MISC_ENABLES);
+	turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
+
+	if (!turbo_cap && turbo_en) {
+		/* Unavailable */
+		turbo_state = TURBO_UNAVAILABLE;
+	} else if (!turbo_cap && !turbo_en) {
+		/* Available but disabled */
+		turbo_state = TURBO_DISABLED;
+	} else if (turbo_cap && turbo_en) {
+		/* Available */
+		turbo_state = TURBO_ENABLED;
+	}
+
+	printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]);
+	return turbo_state;
+}
+
+/*
+ * Try to enable Turbo mode.
+ */
+void enable_turbo(void)
+{
+	msr_t msr;
+
+	/* Only possible if turbo is available but hidden */
+	if (get_turbo_state() == TURBO_DISABLED) {
+		/* Clear Turbo Disable bit in Misc Enables */
+		msr = rdmsr(MSR_IA32_MISC_ENABLES);
+		msr.hi &= ~H_MISC_DISABLE_TURBO;
+		wrmsr(MSR_IA32_MISC_ENABLES, msr);
+
+		/* Update cached turbo state */
+		turbo_state = TURBO_ENABLED;
+		printk(BIOS_INFO, "Turbo has been enabled\n");
+	}
+}
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 1eb92c8..9f4c0e3 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -45,7 +45,6 @@
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
 
-
 	/* Invalidating the cache here seems to be a bad idea on
 	 * modern processors.  Don't.
 	 * If we are hyperthreaded or we have multiple cores it is bad,
@@ -55,6 +54,13 @@
 	 * entry16.inc.
 	 */
 
+	/* Load an IDT with NULL limit to prevent the 16bit IDT being used
+	 * in protected mode before c_start.S sets up a 32bit IDT when entering
+	 * ram stage.
+	 */
+	movw $nullidt_offset, %bx
+	lidt %cs:(%bx)
+
 	/* Note: gas handles memory addresses in 16 bit code very poorly.
 	 * In particular it doesn't appear to have a directive allowing you
 	 * associate a section or even an absolute offset with a segment register.
@@ -118,6 +124,13 @@
 	.word	gdt_end - gdt -1 /* compute the table limit */
 	.long	gdt		 /* we know the offset */
 
+.align	4
+.globl nullidt
+nullidt:
+	.word	0	/* limit */
+	.long	0
+	.word	0
+
 .globl _estart
 _estart:
 	.code32
diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds
index 0580f0e..112d429 100644
--- a/src/cpu/x86/16bit/entry16.lds
+++ b/src/cpu/x86/16bit/entry16.lds
@@ -1 +1,2 @@
 	gdtptr16_offset = gdtptr16 & 0xffff;
+	nullidt_offset = nullidt & 0xffff;
diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc
index 1be0e3a..8dba3c8 100644
--- a/src/cpu/x86/16bit/reset16.inc
+++ b/src/cpu/x86/16bit/reset16.inc
@@ -2,6 +2,7 @@
 	.code16
 .globl	reset_vector
 reset_vector:
+	wbinvd
 	.byte  0xe9
 	.int   _start - ( . + 2 )
 	/* Note: The above jump is hand coded to work around bugs in binutils.
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index ec559b5..19efb00 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -39,4 +39,14 @@
 	bool
 	default y
 
+config CACHE_ROM
+	bool
+	default n
 
+config SMM_TSEG
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+	default 0
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956..f3fcadc 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index a4737b3..f51fe21 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -20,6 +20,7 @@
 
 #include <stdint.h>
 #include <delay.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 
@@ -27,14 +28,40 @@
  * memory init.
  */
 
-#define FSB_CLOCK_STS 0xcd
+static u32 timer_fsb = 0;
 
-static u32 timer_fsb = 200; // default to 200MHz
+static int set_timer_fsb(void)
+{
+	struct cpuinfo_x86 c;
+	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
+	int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 };
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return -1;
+
+	switch (c.x86_model) {
+	case 0xe:  /* Core Solo/Duo */
+	case 0x1c: /* Atom */
+		timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
+		break;
+	case 0xf:  /* Core 2*/
+	case 0x17: /* Enhanced Core */
+		timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
+		break;
+	case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+		timer_fsb = 100;
+		break;
+	default:
+		timer_fsb = 200;
+		break;
+	}
+
+	return 0;
+}
 
 void init_timer(void)
 {
-	msr_t fsb_clock_sts;
-
 	/* Set the apic timer to no interrupts and periodic mode */
 	lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0));
 
@@ -45,19 +72,16 @@
 	lapic_write(LAPIC_TMICT, 0xffffffff);
 
 	/* Set FSB frequency to a reasonable value */
-	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
-	switch ((fsb_clock_sts.lo >> 4) & 0x07) {
-	case 0: timer_fsb = 266; break;
-	case 1: timer_fsb = 133; break;
-	case 2: timer_fsb = 200; break;
-	case 3: timer_fsb = 166; break;
-	case 5: timer_fsb = 100; break;
-	}
+	set_timer_fsb();
 }
 
 void udelay(u32 usecs)
 {
 	u32 start, value, ticks;
+
+	if (!timer_fsb)
+		init_timer();
+
 	/* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */
 	ticks = usecs * timer_fsb;
 	start = lapic_read(LAPIC_TMCCT);
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index bca73e1..50dc0bf 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,6 +1,7 @@
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 
-static int boot_cpu(void)
+int boot_cpu(void)
 {
 	int bsp;
 	msr_t msr;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 53bbe79..232fe35 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -14,6 +14,7 @@
 #include <smp/atomic.h>
 #include <smp/spinlock.h>
 #include <cpu/cpu.h>
+#include <cpu/intel/speedstep/chip.h>
 
 #if CONFIG_SMP == 1
 /* This is a lot more paranoid now, since Linux can NOT handle
@@ -108,7 +109,7 @@
 		}
 		return 0;
 	}
-#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
+#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX
 	mdelay(10);
 #endif
 
@@ -136,7 +137,7 @@
 
 	start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 
-#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
+#if !CONFIG_CPU_AMD_MODEL_10XXX
 	num_starts = 2;
 #else
 	num_starts = 1;
@@ -400,6 +401,8 @@
 {
 	device_t cpu;
 	int old_active_count, active_count;
+	long loopcount = 0;
+
 	/* Now loop until the other cpus have finished initializing */
 	old_active_count = 1;
 	active_count = atomic_read(&active_cpus);
@@ -410,17 +413,21 @@
 		}
 		udelay(10);
 		active_count = atomic_read(&active_cpus);
+		loopcount++;
 	}
 	for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 		if (cpu->path.type != DEVICE_PATH_APIC) {
 			continue;
 		}
+		if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) {
+			continue;
+		}
 		if (!cpu->initialized) {
 			printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
 				cpu->path.apic.apic_id);
 		}
 	}
-	printk(BIOS_DEBUG, "All AP CPUs stopped\n");
+	printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
 }
 
 #else /* CONFIG_SMP */
@@ -475,9 +482,9 @@
 	#if CONFIG_SERIAL_CPU_INIT == 1
 	start_other_cpus(cpu_bus, info->cpu);
 	#endif
+#endif
 
 	/* Now wait the rest of the cpus stop*/
 	wait_other_cpus_stop(cpu_bus);
-#endif
 }
 
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e7beea..43c21ec 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,6 +36,8 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -47,6 +49,23 @@
 	MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 
+/* 2 MTRRS are reserved for the operating system */
+#define BIOS_MTRRS 6
+#define OS_MTRRS   2
+#define MTRRS      (BIOS_MTRRS + OS_MTRRS)
+
+static int total_mtrrs = MTRRS;
+static int bios_mtrrs = BIOS_MTRRS;
+
+static void detect_var_mtrrs(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MTRRcap_MSR);
+
+	total_mtrrs = msr.lo & 0xff;
+	bios_mtrrs = total_mtrrs - 2;
+}
 
 void enable_fixed_mtrr(void)
 {
@@ -74,8 +93,8 @@
 	msr_t base, mask;
 	unsigned address_mask_high;
 
-        if (reg >= 8)
-                return;
+        if (reg >= total_mtrrs)
+               return;
 
         // it is recommended that we disable and enable cache when we
         // do this.
@@ -167,16 +186,6 @@
  * or a 156MB (128MB + 32MB - 4MB SMA) example:
  *	ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
  */
-/* 2 MTRRS are reserved for the operating system */
-#if 1
-#define BIOS_MTRRS 6
-#define OS_MTRRS   2
-#else
-#define BIOS_MTRRS 8
-#define OS_MTRRS   0
-#endif
-#define MTRRS        (BIOS_MTRRS + OS_MTRRS)
-
 
 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
 {
@@ -233,6 +242,8 @@
 	unsigned long next_range_startk, unsigned char type,
 	unsigned int address_bits, unsigned int above4gb)
 {
+	unsigned long hole_startk = 0, hole_sizek = 0;
+
 	if (!range_sizek) {
 		/* If there's no MTRR hole, this function will bail out
 		 * here when called for the hole.
@@ -241,7 +252,7 @@
 		return reg;
 	}
 
-	if (reg >= BIOS_MTRRS) {
+	if (reg >= bios_mtrrs) {
 		printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
 				range_startk >>10, range_sizek >> 10,
 				(type==MTRR_TYPE_UNCACHEABLE)?"UC":
@@ -249,6 +260,19 @@
 		return reg;
 	}
 
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+	    range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
+		/*
+		 * If this range is not divisible then instead
+		 * make a larger range and carve out an uncached hole.
+		 */
+		hole_startk = range_startk + range_sizek;
+		hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
+		range_sizek += hole_sizek;
+	}
+
 	while(range_sizek) {
 		unsigned long max_align, align;
 		unsigned long sizek;
@@ -272,11 +296,20 @@
 			set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
 		range_startk += sizek;
 		range_sizek -= sizek;
-		if (reg >= BIOS_MTRRS) {
+		if (reg >= bios_mtrrs) {
 			printk(BIOS_ERR, "Running out of variable MTRRs!\n");
 			break;
 		}
 	}
+
+	if (hole_sizek) {
+		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
+		       hole_startk >> 10, (hole_startk + hole_sizek) >> 10);
+		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
+			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
+			      address_bits, above4gb);
+	}
+
 	return reg;
 }
 
@@ -323,7 +356,7 @@
 {
 	struct var_mtrr_state *state = gp;
 	unsigned long basek, sizek;
-	if (state->reg >= BIOS_MTRRS)
+	if (state->reg >= bios_mtrrs)
 		return;
 	basek = resk(res->base);
 	sizek = resk(res->size);
@@ -339,7 +372,7 @@
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
 #if CONFIG_VAR_MTRR_HOLE
-		if (state->hole_sizek == 0) {
+		if (state->hole_sizek == 0 && state->above4gb != 2) {
 			/* We need to put that on to hole */
 			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
@@ -422,6 +455,10 @@
 	var_state.address_bits = address_bits;
 	var_state.above4gb = above4gb;
 
+	/* Detect number of variable MTRRs */
+	if (above4gb == 2)
+		detect_var_mtrrs();
+
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_var_mtrr_resource, &var_state);
@@ -433,7 +470,8 @@
 	} else {
 #if CONFIG_VAR_MTRR_HOLE
 		// Increase the base range and set up UMA as an UC hole instead
-		var_state.range_sizek += (uma_memory_size >> 10);
+		if (above4gb != 2)
+			var_state.range_sizek += (uma_memory_size >> 10);
 
 		var_state.hole_startk = (uma_memory_base >> 10);
 		var_state.hole_sizek = (uma_memory_size >> 10);
@@ -452,9 +490,20 @@
 	printk(BIOS_DEBUG, "DONE variable MTRRs\n");
 	printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
-	while(var_state.reg < MTRRS) {
+	while(var_state.reg < total_mtrrs) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
+
+#if CONFIG_CACHE_ROM
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	if (boot_cpu() && (acpi_slp_type != 3)) {
+		set_var_mtrr(total_mtrrs-1, (4096-8)*1024, 8*1024,
+			MTRR_TYPE_WRPROT, address_bits);
+	}
+#endif
+
 	printk(BIOS_SPEW, "call enable_var_mtrr()\n");
 	enable_var_mtrr();
 	printk(BIOS_SPEW, "Leave %s\n", __func__);
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 85bb454..108f8f9 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -22,15 +22,25 @@
 ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap
 endif
 
+# Use TSEG specific entry point and linker script
+ifeq ($(CONFIG_SMM_TSEG),y)
+smm-y += smmhandler_tseg.S
+SMM_LDFLAGS  := $(LDFLAGS) -pie
+SMM_LDSCRIPT := smm_tseg.ld
+else
 smm-y += smmhandler.S
+SMM_LDFLAGS  := $(LDFLAGFS)
+SMM_LDSCRIPT := smm.ld
+endif
+
 smm-y += smihandler.c
 smm-y += smiutil.c
 
 $(obj)/cpu/x86/smm/smm.o: $$(smm-objs)
 	$(CC) $(LDFLAGS) -nostdlib -r -o $@ $^
 
-$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions
-	$(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions
+	$(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o
 	$(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm
 
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index bdaedf8..a971d81 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -25,6 +25,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 
+#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
 
 /* SMI multiprocessing semaphore */
@@ -56,6 +57,7 @@
 		: "eax"
 	);
 }
+#endif
 
 #define LAPIC_ID 0xfee00020
 static inline __attribute__((always_inline)) unsigned long nodeid(void)
@@ -116,6 +118,7 @@
 	unsigned int node;
 	smm_state_save_area_t state_save;
 
+#if !CONFIG_SMM_TSEG
 	/* Are we ok to execute the handler? */
 	if (!smi_obtain_lock()) {
 		/* For security reasons we don't release the other CPUs
@@ -124,6 +127,7 @@
 		while (smi_handler_status == SMI_LOCKED) /* wait */ ;
 		return;
 	}
+#endif
 
 	smi_backup_pci_address();
 
@@ -141,6 +145,7 @@
 			(0xa8000 + 0x7e00 - (node * 0x400));
 		break;
 	case 0x00030100:
+	case 0x00030101: /* SandyBridge */
 		state_save.type = EM64T;
 		state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
 			(0xa8000 + 0x7d00 - (node * 0x400));
@@ -169,7 +174,9 @@
 
 	smi_restore_pci_address();
 
+#if !CONFIG_SMM_TSEG
 	smi_release_lock();
+#endif
 
 	/* De-assert SMI# signal to allow another SMI */
 	smi_set_eos();
diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c
index d9057d8..9cd63ed 100644
--- a/src/cpu/x86/smm/smiutil.c
+++ b/src/cpu/x86/smm/smiutil.c
@@ -23,18 +23,8 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-
 #include <console/console.h>
 #include <console/vtxprintf.h>
-#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
-#include <uart8250.h>
-#endif
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-#if CONFIG_CONSOLE_NE2K
-#include <console/ne2k.h>
-#endif
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
 static u32 serial8250mem_base_address = 0;
diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld
new file mode 100644
index 0000000..f3a8dae
--- /dev/null
+++ b/src/cpu/x86/smm/smm_tseg.ld
@@ -0,0 +1,58 @@
+/* Maximum number of CPUs/cores */
+CPUS = 4;
+
+SECTIONS
+{
+	/* This is the actual SMM handler.
+	 *
+	 * We just put code, rodata, data and bss all in a row.
+	 */
+	.handler (.): {
+		/* Assembler stub */
+		*(.handler)
+
+		/* C code of the SMM handler */
+		*(.text);
+		*(.text.*);
+
+		/* C read-only data of the SMM handler */
+		. = ALIGN(16);
+		*(.rodata)
+		*(.rodata.*)
+		*(.data.rel.ro.*)
+
+		/* C read-write data of the SMM handler */
+		 . = ALIGN(4);
+		*(.data)
+
+		/* C uninitialized data of the SMM handler */
+		 . = ALIGN(4);
+		*(.bss)
+		*(.sbss)
+
+		/* What is this? */
+		*(COMMON)
+		 . = ALIGN(4);
+	}
+
+	/* We are using the TSEG interleaved to stuff the SMM handlers
+	 * for all CPU cores in there. The jump table redirects the execution
+	 * to the actual SMM handler
+	 */
+	. = 0x8000 - (( CPUS - 1) * 0x400);
+	.jumptable : {
+		*(.jumptable)
+	}
+
+	/* Data used in early SMM TSEG handler. */
+	. = 0x8400;
+	.earlydata : {
+		*(.earlydata)
+	}
+
+	/DISCARD/ : {
+		*(.comment)
+		*(.note)
+		*(.note.*)
+	}
+}
diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S
new file mode 100644
index 0000000..0b41b37
--- /dev/null
+++ b/src/cpu/x86/smm/smmhandler_tseg.S
@@ -0,0 +1,264 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * +--------------------------------+ 0xffff
+ * |  Save State Map Node 0         |
+ * |  Save State Map Node 1         |
+ * |  Save State Map Node 2         |
+ * |  Save State Map Node 3         |
+ * |  ...                           |
+ * +--------------------------------+ 0xf000
+ * |                                |
+ * |                                |
+ * | EARLY DATA (lock, vectors)     |
+ * +--------------------------------+ 0x8400
+ * | SMM Entry Node 0 (+ stack)     |
+ * +--------------------------------+ 0x8000
+ * | SMM Entry Node 1 (+ stack)     |
+ * | SMM Entry Node 2 (+ stack)     |
+ * | SMM Entry Node 3 (+ stack)     |
+ * | ...                            |
+ * +--------------------------------+ 0x7400
+ * |                                |
+ * | SMM Handler                    |
+ * |                                |
+ * +--------------------------------+ TSEG
+ *
+ */
+
+#define LAPIC_ID	0xfee00020
+#define SMM_STACK_SIZE	(0x400 - 0x10)
+
+/* Values for the xchg lock */
+#define SMI_LOCKED	0
+#define SMI_UNLOCKED	1
+
+#define __PRE_RAM__
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
+#error "Northbridge must define TSEG_BAR."
+#endif
+
+/* initially SMM is some sort of real mode. Let gcc know
+ * how to treat the SMM handler stub
+ */
+
+.section ".handler", "a", @progbits
+
+.code16
+
+/**
+ * SMM code to enable protected mode and jump to the
+ * C-written function void smi_handler(u32 smm_revision)
+ *
+ * All the bad magic is not all that bad after all.
+ */
+smm_handler_start:
+	movl	$(TSEG_BAR), %eax	/* Get TSEG base from PCIE */
+	addr32	movl (%eax), %edx	/* Save TSEG_BAR in %edx */
+	andl	$~1, %edx		/* Remove lock bit */
+
+	/* Obtain lock */
+	movl	%edx, %ebx
+	addl	$(smm_lock), %ebx
+	movw	$SMI_LOCKED, %ax
+	addr32	xchg %ax, (%ebx)
+	cmpw	$SMI_UNLOCKED, %ax
+
+	/* Proceed if we got the lock */
+	je	smm_check_prot_vector
+
+	/* If we did not get the lock, wait for release */
+wait_for_unlock:
+	addr32	movw (%ebx), %ax
+	cmpw	$SMI_LOCKED, %ax
+	je	wait_for_unlock
+	rsm
+
+smm_check_prot_vector:
+	/* See if we need to adjust protected vector */
+	movl	%edx, %eax
+	addl	$(smm_prot_vector), %eax
+	addr32	movl (%eax), %ebx
+	cmpl	$(smm_prot_start), %ebx
+	jne	smm_check_gdt_vector
+
+	/* Adjust vector with TSEG offset */
+	addl	%edx, %ebx
+	addr32	movl %ebx, (%eax)
+
+smm_check_gdt_vector:
+	/* See if we need to adjust GDT vector */
+	movl	%edx, %eax
+	addl	$(smm_gdt_vector + 2), %eax
+	addr32	movl (%eax), %ebx
+	cmpl	$(smm_gdt - smm_handler_start), %ebx
+	jne	smm_load_gdt
+
+	/* Adjust vector with TSEG offset */
+	addl	%edx, %ebx
+	addr32	movl %ebx, (%eax)
+
+smm_load_gdt:
+	movl    $(smm_gdt_vector), %ebx
+	addl	%edx, %ebx        /* TSEG base in %edx */
+	data32  lgdt (%ebx)
+
+	movl    %cr0, %eax
+	andl    $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */
+	orl     $0x1, %eax        /* PE = 1 */
+	movl    %eax, %cr0
+
+	/* Enable protected mode */
+	movl	$(smm_prot_vector), %eax
+	addl	%edx, %eax
+	data32	ljmp *(%eax)
+
+.code32
+smm_prot_start:
+	/* Use flat data segment */
+	movw    $0x10, %ax
+	movw    %ax, %ds
+	movw    %ax, %es
+	movw    %ax, %ss
+	movw    %ax, %fs
+	movw    %ax, %gs
+
+	/* Get this CPU's LAPIC ID */
+	movl	$LAPIC_ID, %esi
+	movl	(%esi), %ecx
+	shr	$24, %ecx
+
+	/* calculate stack offset by multiplying the APIC ID
+	 * by 1024 (0x400), and save that offset in ebp.
+	 */
+	shl	$10, %ecx
+	movl	%ecx, %ebp
+
+	/* We put the stack for each core right above
+	 * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000,
+	 * we spare 0x10 bytes for the jump to be sure.
+	 */
+	movl	$0x8010, %eax	/* core 0 address */
+	addl	%edx, %eax	/* addjust for TSEG */
+	subl	%ecx, %eax	/* subtract offset, see above */
+	movl	%eax, %ebx	/* Save bottom of stack in ebx */
+
+	/* clear stack */
+	cld
+	movl	%eax, %edi
+	movl	$(SMM_STACK_SIZE >> 2), %ecx
+	xorl	%eax, %eax
+	rep	stosl
+
+	/* set new stack */
+	addl	$SMM_STACK_SIZE, %ebx
+	movl	%ebx, %esp
+
+	/* Get SMM revision */
+	movl	$0xfefc, %ebx	/* core 0 address */
+	addl	%edx, %ebx	/* addjust for TSEG */
+	subl	%ebp, %ebx	/* subtract core X offset */
+	movl	(%ebx), %eax
+	pushl	%eax
+
+	/* Call 32bit C handler */
+	call	smi_handler
+
+	/* Release lock */
+	movl	$(TSEG_BAR), %eax	/* Get TSEG base from PCIE */
+	movl	(%eax), %ebx		/* Save TSEG_BAR in %ebx */
+	andl	$~1, %ebx		/* Remove lock bit */
+	addl	$(smm_lock), %ebx
+	movw	$SMI_UNLOCKED, %ax
+	xchg	%ax, (%ebx)
+
+	/* To return, just do rsm. It will "clean up" protected mode */
+	rsm
+
+smm_gdt:
+	/* The first GDT entry can not be used. Keep it zero */
+	.long	0x00000000, 0x00000000
+
+	/* gdt selector 0x08, flat code segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */
+
+	/* gdt selector 0x10, flat data segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x93, 0xcf, 0x00
+
+smm_gdt_end:
+
+.section ".earlydata", "a", @progbits
+
+.code16
+
+.align	4, 0xff
+
+smm_lock:
+	.word	SMI_UNLOCKED
+
+.align	4, 0xff
+
+smm_prot_vector:
+	.long	smm_prot_start
+	.short	8
+
+.align	4, 0xff
+
+smm_gdt_vector:
+	.word	smm_gdt_end - smm_gdt - 1
+	.long	smm_gdt - smm_handler_start
+
+.section ".jumptable", "a", @progbits
+
+/* This is the SMM jump table. All cores use the same SMM handler
+ * for simplicity. But SMM Entry needs to be different due to the
+ * save state area. The jump table makes sure all CPUs jump into the
+ * real handler on SMM entry.
+ */
+
+/* This code currently supports up to 4 CPU cores. If more than 4 CPU cores
+ * shall be used, below table has to be updated, as well as smm.ld
+ */
+
+/* When using TSEG do a relative jump and fix up the CS later since we
+ * do not know what our TSEG base is yet.
+ */
+
+.code16
+jumptable:
+	/* core 3 */
+	jmp smm_handler_start
+.align 1024, 0x00
+	/* core 2 */
+	jmp smm_handler_start
+.align 1024, 0x00
+	/* core 1 */
+	jmp smm_handler_start
+.align 1024, 0x00
+	/* core 0 */
+	jmp smm_handler_start
+.align 1024, 0x00
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 7b38348..89834a5 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -35,10 +35,24 @@
 #include "../../../southbridge/intel/i82801dx/i82801dx.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_SCH
 #include "../../../southbridge/intel/sch/sch.h"
+#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+#include "../../../southbridge/intel/bd82x6x/pch.h"
 #else
 #error "Southbridge needs SMM handler support."
 #endif
 
+#if CONFIG_SMM_TSEG
+
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
+#error "Northbridge must define TSEG_BAR."
+#endif
+#include <cpu/x86/mtrr.h>
+
+#endif /* CONFIG_SMM_TSEG */
+
 #define LAPIC_ID 0xfee00020
 
 .global smm_relocation_start
@@ -100,6 +114,7 @@
 	/* Check revision to see if AMD64 style SMM_BASE
 	 *   Intel Core Solo/Duo:  0x30007
 	 *   Intel Core2 Solo/Duo: 0x30100
+	 *   Intel SandyBridge:    0x30101
 	 *   AMD64:                0x3XX64
 	 * This check does not make much sense, unless someone ports
 	 * SMI handling to AMD64 CPUs.
@@ -127,11 +142,53 @@
 	movl %ecx, %edx
 	shl $10, %edx
 
+#if CONFIG_SMM_TSEG
+	movl	$(TSEG_BAR), %ecx	/* Get TSEG base from PCIE */
+	addr32	movl (%ecx), %eax	/* Save TSEG_BAR in %eax */
+	andl	$~1, %eax		/* Remove lock bit */
+#else
 	movl $0xa0000, %eax
+#endif
 	subl %edx, %eax	/* subtract offset, see above */
 
 	addr32 movl %eax, (%ebx)
 
+#if CONFIG_SMM_TSEG
+	/* Check for SMRR capability in MTRRCAP[11] */
+	movl	$MTRRcap_MSR, %ecx
+	rdmsr
+	bt	$11, %eax
+	jnc	skip_smrr
+
+	/* TSEG base */
+	movl	$(TSEG_BAR), %ecx	/* Get TSEG base from PCIE */
+	addr32	movl (%ecx), %eax	/* Save TSEG_BAR in %eax */
+	andl	$~1, %eax		/* Remove lock bit */
+	movl	%eax, %ebx
+
+	/* Set SMRR base address. */
+	movl	$SMRRphysBase_MSR, %ecx
+	orl	$MTRR_TYPE_WRBACK, %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Set SMRR mask. */
+	movl	$SMRRphysMask_MSR, %ecx
+	movl	$(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+	/*
+	 * IED base is top 4M of TSEG
+	 */
+	addl	$(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx
+	movl	$(0x30000 + 0x8000 + 0x7eec), %eax
+	addr32	movl %ebx, (%eax)
+#endif
+
+skip_smrr:
+#endif
 
 	/* The next section of code is potentially southbridge specific */
 
diff --git a/src/cpu/x86/sse_disable.inc b/src/cpu/x86/sse_disable.inc
deleted file mode 100644
index 37458c9..0000000
--- a/src/cpu/x86/sse_disable.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	/*
-	 * Put the processor back into a reset state
-	 * with respect to the XMM registers.
-	 */
-	xorps %xmm0, %xmm0
-	xorps %xmm1, %xmm1
-	xorps %xmm2, %xmm2
-	xorps %xmm3, %xmm3
-	xorps %xmm4, %xmm4
-	xorps %xmm5, %xmm5
-	xorps %xmm6, %xmm6
-	xorps %xmm7, %xmm7
-
-	/*
-	 * Disable SSE instructions.
-	 *
-	 * Clear CR4[9] (OSFXSR) and CR4[10] (OSXMMEXCPT) so that the
-	 * processor can no longer execute SSE instructions, and unmasked
-	 * SIMD floating point exceptions will generate an invalid opcode
-	 * exception (#UD).
-	 */
-	movl	%cr4, %eax
-	andl	$~(3 << 9), %eax
-	movl	%eax, %cr4
-
diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 9e5ea6e..7429bda 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -33,6 +33,13 @@
 	  Execute VGA option ROMs, if found. This is required to enable
 	  PCI/AGP/PCI-E video cards.
 
+config S3_VGA_ROM_RUN
+	bool "Re-run VGA option ROMs on S3 resume"
+	default y
+	depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
+	help
+	  Execute VGA option ROMs when coming out of an S3 resume.
+
 config PCI_ROM_RUN
 	bool "Run non-VGA option ROMs"
 	default y
@@ -42,6 +49,19 @@
 	  Examples include IDE/SATA controller option ROMs and option ROMs
 	  for network cards (NICs).
 
+config ON_DEVICE_ROM_RUN
+	bool "Run option ROMs on PCI devices"
+	default y
+	help
+	  Execute option ROMs that are stored on PCI/PCIe/AGP devices.
+
+	  If disabled, only option ROMs stored in CBFS will be executed. If
+	  you are concerned about security, you might want to disable this
+	  option, but it might leave your system in a state of degraded
+	  functionality.
+
+	  If unsure, say Y
+
 choice
 	prompt "Option ROM execution type"
 	default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
@@ -143,3 +163,17 @@
 config CARDBUS_PLUGIN_SUPPORT
 	bool
 	default y
+
+config PCIEXP_COMMON_CLOCK
+	prompt "Enable PCIe Common Clock"
+	bool
+	default n
+	help
+	  Detect and enable Common Clock on PCIe links.
+
+config PCIEXP_ASPM
+	prompt "Enable PCIe ASPM"
+	bool
+	default n
+	help
+	  Detect and enable ASPM on PCIe links.
diff --git a/src/devices/device.c b/src/devices/device.c
index a2619bf..f559da5 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -41,6 +41,9 @@
 #include <stdlib.h>
 #include <string.h>
 #include <smp/spinlock.h>
+#if CONFIG_ARCH_X86
+#include <arch/ebda.h>
+#endif
 
 /** Linked list of ALL devices */
 struct device *all_devices = &dev_root;
@@ -1102,6 +1105,11 @@
 
 	printk(BIOS_INFO, "Initializing devices...\n");
 
+#if CONFIG_ARCH_X86
+	/* Ensure EBDA is prepared before Option ROMs. */
+	setup_default_ebda();
+#endif
+
 	/* First call the mainboard init. */
 	init_dev(&dev_root);
 
diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 9081a36..86124b4 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -110,6 +110,26 @@
 }
 
 /**
+ * Given a Local APIC ID, find the device structure.
+ *
+ * @param apic_id The Local APIC ID number.
+ * @return Pointer to the device structure (if found), 0 otherwise.
+ */
+device_t dev_find_lapic(unsigned apic_id)
+{
+	device_t dev, result = NULL;
+
+	for (dev = all_devices; dev; dev = dev->next) {
+		if (dev->path.type == DEVICE_PATH_APIC &&
+		    dev->path.apic.apic_id == apic_id) {
+			result = dev;
+			break;
+		}
+	}
+	return result;
+}
+
+/**
  * Find a device of a given vendor and type.
  *
  * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel).
@@ -583,6 +603,8 @@
 					if (subbus->link_num
 					== IOINDEX_SUBTRACTIVE_LINK(res->index))
 						break;
+					if (!subbus) /* Why can subbus be NULL?  */
+						break;
 				search_bus_resources(subbus, type_mask, type,
 						     search, gp);
 				continue;
@@ -828,3 +850,21 @@
 
 	return tolm;
 }
+
+/* Count of enabled CPUs */
+int dev_count_cpu(void)
+{
+	device_t cpu;
+	int count = 0;
+
+	for (cpu = all_devices; cpu; cpu = cpu->next) {
+		if ((cpu->path.type != DEVICE_PATH_APIC) ||
+		    (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
+			continue;
+		if (!cpu->enabled)
+			continue;
+		count++;
+	}
+
+	return count;
+}
diff --git a/src/devices/oprom/include/vbe.h b/src/devices/oprom/include/vbe.h
new file mode 100644
index 0000000..f857b67
--- /dev/null
+++ b/src/devices/oprom/include/vbe.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     IBM Corporation - initial implementation
+ *****************************************************************************/
+
+// these structs are for input from and output to OF
+typedef struct {
+	u8 display_type;	// 0=NONE, 1= analog, 2=digital
+	u16 screen_width;
+	u16 screen_height;
+	u16 screen_linebytes;	// bytes per line in framebuffer, may be more than screen_width
+	u8 color_depth;	// color depth in bpp
+	u32 framebuffer_address;
+	u8 edid_block_zero[128];
+} __attribute__ ((__packed__)) screen_info_t;
+
+typedef struct {
+	u8 signature[4];
+	u16 size_reserved;
+	u8 monitor_number;
+	u16 max_screen_width;
+	u8 color_depth;
+} __attribute__ ((__packed__)) screen_info_input_t;
+
+// these structs only store a subset of the VBE defined fields
+// only those needed.
+typedef struct {
+	char signature[4];
+	u16 version;
+	u8 *oem_string_ptr;
+	u32 capabilities;
+	u16 video_mode_list[256];	// lets hope we never have more than 256 video modes...
+	u16 total_memory;
+} vbe_info_t;
+
+typedef struct {
+	u16 mode_attributes; // 00
+	u8 win_a_attributes; // 02
+	u8 win_b_attributes; // 03
+	u16 win_granularity; // 04
+	u16 win_size;        // 06
+	u16 win_a_segment;   // 08
+	u16 win_b_segment;   // 0a
+	u32 win_func_ptr;    // 0c
+	u16 bytes_per_scanline; // 10
+	u16 x_resolution;    // 12
+	u16 y_resolution;    // 14
+	u8 x_charsize;       // 16
+	u8 y_charsize;       // 17
+	u8 number_of_planes; // 18
+	u8 bits_per_pixel;   // 19
+	u8 number_of_banks;  // 20
+	u8 memory_model;     // 21
+	u8 bank_size;        // 22
+	u8 number_of_image_pages; // 23
+	u8 reserved_page;
+	u8 red_mask_size;
+	u8 red_mask_pos;
+	u8 green_mask_size;
+	u8 green_mask_pos;
+	u8 blue_mask_size;
+	u8 blue_mask_pos;
+	u8 reserved_mask_size;
+	u8 reserved_mask_pos;
+	u8 direct_color_mode_info;
+	u32 phys_base_ptr;
+	u32 offscreen_mem_offset;
+	u16 offscreen_mem_size;
+	u8 reserved[206];
+} __attribute__ ((__packed__)) vesa_mode_info_t;
+
+typedef struct {
+	u16 video_mode;
+	union {
+		vesa_mode_info_t vesa;
+		u8 mode_info_block[256];
+	};
+	// our crap
+	//u16 attributes;
+	//u16 linebytes;
+	//u16 x_resolution;
+	//u16 y_resolution;
+	//u8 x_charsize;
+	//u8 y_charsize;
+	//u8 bits_per_pixel;
+	//u8 memory_model;
+	//u32 framebuffer_address;
+} vbe_mode_info_t;
+
+typedef struct {
+	u8 port_number;	// i.e. monitor number
+	u8 edid_transfer_time;
+	u8 ddc_level;
+	u8 edid_block_zero[128];
+} vbe_ddc_info_t;
+
+struct lb_framebuffer;
+
+void vbe_set_graphics(void);
+void vbe_textmode_console(void);
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+
+#define VESA_GET_INFO		0x4f00
+#define VESA_GET_MODE_INFO	0x4f01
+#define VESA_SET_MODE		0x4f02
+
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 37b45e6..7e31cb4 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -25,42 +25,20 @@
 #include <arch/registers.h>
 #include <console/console.h>
 #include <arch/interrupt.h>
-
-#define REALMODE_BASE ((void *)0x600)
-
-struct realmode_idt {
-	u16 offset, cs;
-};
-
-void x86_exception(struct eregs *info);
-
-/* From x86_asm.S */
-extern unsigned char __idt_handler, __idt_handler_size;
-extern unsigned char __realmode_code, __realmode_code_size;
-extern unsigned char __realmode_call, __realmode_interrupt;
+#include <cbfs.h>
+#include <delay.h>
+#include <pc80/i8259.h>
+#include "x86.h"
+#include "vbe.h"
+#include "../../src/lib/jpeg.h"
 
 void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
-		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call;
+		u32 esi, u32 edi) __attribute__((regparm(0))) =
+						(void *)&__realmode_call;
 
 void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
-		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt;
-
-#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB
-#define INITIAL_EBDA_SEGMENT 0xF600
-#define INITIAL_EBDA_SIZE 0x400
-
-static void setup_bda(void)
-{
-	/* clear BIOS DATA AREA */
-	memset((void *)0x400, 0, 0x200);
-
-	write16(0x413, FAKE_MEMORY_SIZE / 1024);
-	write16(0x40e, INITIAL_EBDA_SEGMENT);
-
-	/* Set up EBDA */
-	memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE);
-	write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024);
-}
+		u32 esi, u32 edi) __attribute__((regparm(0))) =
+						(void *)&__realmode_interrupt;
 
 static void setup_rombios(void)
 {
@@ -80,14 +58,9 @@
 {
 	printk(BIOS_INFO, "Oops, exception %d while executing option rom\n",
 			regs->vector);
-#if 0
-	// Odd: The i945GM VGA oprom chokes on a pushl %eax and will
-	// die with an exception #6 if we run the coreboot exception 
-	// handler. Just continue, as it executes fine.
 	x86_exception(regs);	// Call coreboot exception handler
-#endif
 
-	return 0;		// Never returns?
+	return 0;		// Never really returns
 }
 
 static int intXX_unknown_handler(struct eregs *regs)
@@ -104,79 +77,6 @@
 	intXX_handler[intXX] = intXX_func;
 }
 
-static int int10_handler(struct eregs *regs)
-{
-	int res=-1;
-	static u8 cursor_row=0, cursor_col=0;
-	switch((regs->eax & 0xff00)>>8) {
-	case 0x01: // Set cursor shape
-		res = 0;
-		break;
-	case 0x02: // Set cursor position
-		if (cursor_row != ((regs->edx >> 8) & 0xff) ||
-		    cursor_col >= (regs->edx & 0xff)) {
-			printk(BIOS_INFO, "\n");
-		}
-		cursor_row = (regs->edx >> 8) & 0xff;
-		cursor_col = regs->edx & 0xff;
-		res = 0;
-		break;
-	case 0x03: // Get cursor position
-		regs->eax &= 0x00ff;
-		regs->ecx = 0x0607;
-		regs->edx = (cursor_row << 8) | cursor_col;
-		res = 0;
-		break;
-	case 0x06: // Scroll up
-		printk(BIOS_INFO, "\n");
-		res = 0;
-		break;
-	case 0x08: // Get Character and Mode at Cursor Position
-		regs->eax = 0x0f00 | 'A'; // White on black 'A'
-		res = 0;
-		break;
-	case 0x09: // Write Character and attribute
-	case 0x10: // Write Character
-		printk(BIOS_INFO, "%c", regs->eax & 0xff);
-		res = 0;
-		break;
-	case 0x0f: // Get video mode
-		regs->eax = 0x5002; //80x25
-		regs->ebx &= 0x00ff;
-		res = 0;
-		break;
-        default:
-		printk(BIOS_WARNING, "Unknown INT10 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-
-static int int16_handler(struct eregs *regs)
-{
-	int res=-1;
-	switch((regs->eax & 0xff00)>>8) {
-	case 0x00: // Check for Keystroke
-		regs->eax = 0x6120; // Space Bar, Space
-		res = 0;
-		break;
-	case 0x01: // Check for Keystroke
-		regs->eflags |= 1<<6; // Zero Flag set (no key available)
-		res = 0;
-		break;
-        default:
-		printk(BIOS_WARNING, "Unknown INT16 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-
-int int12_handler(struct eregs *regs);
-int int15_handler(struct eregs *regs);
-int int1a_handler(struct eregs *regs);
-
 static void setup_interrupt_handlers(void)
 {
 	int i;
@@ -195,9 +95,9 @@
 		if(!intXX_handler[i])
 		{
 			/* Now set the default functions that are actually
-			 * needed to initialize the option roms. This is very
-			 * slick, as it allows us to implement mainboard specific
-			 * interrupt handlers, such as the int15
+			 * needed to initialize the option roms. This is
+			 * very slick, as it allows us to implement mainboard
+			 * specific interrupt handlers, such as the int15.
 			 */
 			switch (i) {
 			case 0x10:
@@ -206,9 +106,6 @@
 			case 0x12:
 				intXX_handler[0x12] = &int12_handler;
 				break;
-			case 0x15:
-				intXX_handler[0x15] = &int15_handler;
-				break;
 			case 0x16:
 				intXX_handler[0x16] = &int16_handler;
 				break;
@@ -269,12 +166,98 @@
 	write_idt_stub((void *)0xffe6e, 0x1a);
 }
 
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+static u8 vbe_get_mode_info(vbe_mode_info_t * mode_info)
+{
+	printk(BIOS_DEBUG, "Getting information about VESA mode %04x\n",
+		mode_info->video_mode);
+	char *buffer = (char *)&__buffer;
+	u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
+	u16 buffer_adr = ((unsigned long)buffer) & 0xffff;
+	realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000,
+			mode_info->video_mode, 0x0000, buffer_seg, buffer_adr);
+	memcpy(mode_info->mode_info_block, buffer, sizeof(vbe_mode_info_t));
+	return 0;
+}
+
+static u8 vbe_set_mode(vbe_mode_info_t * mode_info)
+{
+	printk(BIOS_DEBUG, "Setting VESA mode %04x\n", mode_info->video_mode);
+	// request linear framebuffer mode
+	mode_info->video_mode |= (1 << 14);
+	// request clearing of framebuffer
+	mode_info->video_mode &= ~(1 << 15);
+	realmode_interrupt(0x10, VESA_SET_MODE, mode_info->video_mode,
+			0x0000, 0x0000, 0x0000, 0x0000);
+	return 0;
+}
+
+vbe_mode_info_t mode_info;
+
+/* These two functions could probably even be generic between
+ * yabel and x86 native. TBD later.
+ */
+void vbe_set_graphics(void)
+{
+	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
+	vbe_get_mode_info(&mode_info);
+	unsigned char *framebuffer =
+		(unsigned char *)mode_info.vesa.phys_base_ptr;
+	printk(BIOS_DEBUG, "framebuffer: %p\n", framebuffer);
+	vbe_set_mode(&mode_info);
+#if CONFIG_BOOTSPLASH
+	struct jpeg_decdata *decdata;
+	decdata = malloc(sizeof(*decdata));
+	unsigned char *jpeg = cbfs_find_file("bootsplash.jpg",
+						CBFS_TYPE_BOOTSPLASH);
+	if (!jpeg) {
+		return;
+	}
+	int ret = 0;
+	ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata);
+#endif
+}
+
+void vbe_textmode_console(void)
+{
+	delay(2);
+	realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000,
+				0x0000, 0x0000, 0x0000);
+}
+
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+{
+	framebuffer->physical_address = mode_info.vesa.phys_base_ptr;
+
+	framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
+	framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
+	framebuffer->bytes_per_line =
+				le16_to_cpu(mode_info.vesa.bytes_per_scanline);
+	framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel;
+
+	framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos;
+	framebuffer->red_mask_size = mode_info.vesa.red_mask_size;
+
+	framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos;
+	framebuffer->green_mask_size = mode_info.vesa.green_mask_size;
+
+	framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos;
+	framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size;
+
+	framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos;
+	framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size;
+}
+#endif
+
 void run_bios(struct device *dev, unsigned long addr)
 {
 	u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn;
 
-	/* Set up BIOS Data Area */
-	setup_bda();
+	/* Setting up required hardware.
+	 * Removing this will cause random illegal instruction exceptions
+	 * in some option roms.
+	 */
+	setup_i8259();
 
 	/* Set up some legacy information in the F segment */
 	setup_rombios();
@@ -294,6 +277,10 @@
 	/* Option ROM entry point is at OPROM start + 3 */
 	realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0);
 	printk(BIOS_DEBUG, "... Option ROM returned.\n");
+
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+	vbe_set_graphics();
+#endif
 }
 
 #if CONFIG_GEODE_VSA
diff --git a/src/devices/oprom/x86.h b/src/devices/oprom/x86.h
new file mode 100644
index 0000000..a4c740e
--- /dev/null
+++ b/src/devices/oprom/x86.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#define REALMODE_BASE ((void *)0x600)
+
+struct realmode_idt {
+	u16 offset, cs;
+};
+
+void x86_exception(struct eregs *info);
+
+/* From x86_asm.S */
+extern unsigned char __idt_handler, __idt_handler_size;
+extern unsigned char __realmode_code, __realmode_code_size;
+extern unsigned char __realmode_call, __realmode_interrupt;
+extern unsigned char __buffer;
+
+extern void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+		u32 esi, u32 edi) __attribute__((regparm(0)));
+
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+		u32 esi, u32 edi) __attribute__((regparm(0)));
+
+#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB
+#define INITIAL_EBDA_SEGMENT 0xF600
+#define INITIAL_EBDA_SIZE 0x400
+
+int int10_handler(struct eregs *regs);
+int int12_handler(struct eregs *regs);
+int int16_handler(struct eregs *regs);
+int int1a_handler(struct eregs *regs);
+
diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S
index d5b5e18..57c5338 100644
--- a/src/devices/oprom/x86_asm.S
+++ b/src/devices/oprom/x86_asm.S
@@ -66,6 +66,11 @@
 	.long 0 /* 16 - ESI */
 	.long 0 /* 20 - EDI */
 
+/* 256 byte buffer, used by int10 */
+	.globl __buffer
+__buffer = RELOCATED(.)
+	.skip 256
+
 	.code32
 	.globl __realmode_call
 __realmode_call = RELOCATED(.)
diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c
index 1dd645b..86d20d7 100644
--- a/src/devices/oprom/x86_interrupts.c
+++ b/src/devices/oprom/x86_interrupts.c
@@ -26,17 +26,7 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <arch/registers.h>
-
-enum {
-	PCIBIOS_CHECK = 0xb101,
-	PCIBIOS_FINDDEV = 0xb102,
-	PCIBIOS_READCONFBYTE = 0xb108,
-	PCIBIOS_READCONFWORD = 0xb109,
-	PCIBIOS_READCONFDWORD = 0xb10a,
-	PCIBIOS_WRITECONFBYTE = 0xb10b,
-	PCIBIOS_WRITECONFWORD = 0xb10c,
-	PCIBIOS_WRITECONFDWORD = 0xb10d
-};
+#include "x86.h"
 
 // errors go in AH. Just set these up so that word assigns
 // will work. KISS.
@@ -48,9 +38,54 @@
 	PCIBIOS_BADREG = 0x8700
 };
 
-int int12_handler(struct eregs *regs);
-int int1a_handler(struct eregs *regs);
-int int15_handler(struct eregs *regs);
+int int10_handler(struct eregs *regs)
+{
+	int res=-1;
+	static u8 cursor_row=0, cursor_col=0;
+	switch((regs->eax & 0xff00)>>8) {
+	case 0x01: // Set cursor shape
+		res = 0;
+		break;
+	case 0x02: // Set cursor position
+		if (cursor_row != ((regs->edx >> 8) & 0xff) ||
+		    cursor_col >= (regs->edx & 0xff)) {
+			printk(BIOS_INFO, "\n");
+		}
+		cursor_row = (regs->edx >> 8) & 0xff;
+		cursor_col = regs->edx & 0xff;
+		res = 0;
+		break;
+	case 0x03: // Get cursor position
+		regs->eax &= 0x00ff;
+		regs->ecx = 0x0607;
+		regs->edx = (cursor_row << 8) | cursor_col;
+		res = 0;
+		break;
+	case 0x06: // Scroll up
+		printk(BIOS_INFO, "\n");
+		res = 0;
+		break;
+	case 0x08: // Get Character and Mode at Cursor Position
+		regs->eax = 0x0f00 | 'A'; // White on black 'A'
+		res = 0;
+		break;
+	case 0x09: // Write Character and attribute
+	case 0x10: // Write Character
+		printk(BIOS_INFO, "%c", regs->eax & 0xff);
+		res = 0;
+		break;
+	case 0x0f: // Get video mode
+		regs->eax = 0x5002; //80x25
+		regs->ebx &= 0x00ff;
+		res = 0;
+		break;
+        default:
+		printk(BIOS_WARNING, "Unknown INT10 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
 
 int int12_handler(struct eregs *regs)
 {
@@ -58,6 +93,26 @@
 	return 0;
 }
 
+int int16_handler(struct eregs *regs)
+{
+	int res=-1;
+	switch((regs->eax & 0xff00)>>8) {
+	case 0x00: // Check for Keystroke
+		regs->eax = 0x6120; // Space Bar, Space
+		res = 0;
+		break;
+	case 0x01: // Check for Keystroke
+		regs->eflags |= 1<<6; // Zero Flag set (no key available)
+		res = 0;
+		break;
+        default:
+		printk(BIOS_WARNING, "Unknown INT16 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+
 #define PCI_CONFIG_SPACE_TYPE1	(1 << 0)
 #define PCI_CONFIG_SPACE_TYPE2	(1 << 1)
 #define PCI_SPECIAL_CYCLE_TYPE1	(1 << 4)
@@ -77,7 +132,7 @@
 	u8 byte, reg;
 
 	switch (func) {
-	case PCIBIOS_CHECK:
+	case 0xb101: /* PCIBIOS Check */
 		regs->edx = 0x20494350;	/* ' ICP' */
 		regs->eax &= 0xffff0000; /* Clear AH / AL */
 		regs->eax |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1;
@@ -87,7 +142,7 @@
 		regs->edi = 0x00000000;	/* protected mode entry */
 		retval = 0;
 		break;
-	case PCIBIOS_FINDDEV:
+	case 0xb102: /* Find Device */
 		devid = regs->ecx;
 		vendorid = regs->edx;
 		devindex = regs->esi;
@@ -114,12 +169,12 @@
 			retval = -1;
 		}
 		break;
-	case PCIBIOS_READCONFDWORD:
-	case PCIBIOS_READCONFWORD:
-	case PCIBIOS_READCONFBYTE:
-	case PCIBIOS_WRITECONFDWORD:
-	case PCIBIOS_WRITECONFWORD:
-	case PCIBIOS_WRITECONFBYTE:
+	case 0xb10a: /* Read Config Dword */
+	case 0xb109: /* Read Config Word */
+	case 0xb108: /* Read Config Byte */
+	case 0xb10d: /* Write Config Dword */
+	case 0xb10c: /* Write Config Word */
+	case 0xb10b: /* Write Config Byte */
 		devfn = regs->ebx & 0xff;
 		bus = regs->ebx >> 8;
 		reg = regs->edi;
@@ -133,27 +188,27 @@
 			return retval;
 		}
 		switch (func) {
-		case PCIBIOS_READCONFBYTE:
+		case 0xb108: /* Read Config Byte */
 			byte = pci_read_config8(dev, reg);
 			regs->ecx = byte;
 			break;
-		case PCIBIOS_READCONFWORD:
+		case 0xb109: /* Read Config Word */
 			word = pci_read_config16(dev, reg);
 			regs->ecx = word;
 			break;
-		case PCIBIOS_READCONFDWORD:
+		case 0xb10a: /* Read Config Dword */
 			dword = pci_read_config32(dev, reg);
 			regs->ecx = dword;
 			break;
-		case PCIBIOS_WRITECONFBYTE:
+		case 0xb10b: /* Write Config Byte */
 			byte = regs->ecx;
 			pci_write_config8(dev, reg, byte);
 			break;
-		case PCIBIOS_WRITECONFWORD:
+		case 0xb10c: /* Write Config Word */
 			word = regs->ecx;
 			pci_write_config16(dev, reg, word);
 			break;
-		case PCIBIOS_WRITECONFDWORD:
+		case 0xb10d: /* Write Config Dword */
 			dword = regs->ecx;
 			pci_write_config32(dev, reg, dword);
 			break;
@@ -178,42 +233,3 @@
 	return retval;
 }
 
-int int15_handler(struct eregs *regs)
-{
-	int res = -1;
-
-	/* This int15 handler is Intel IGD. specific. Other chipsets need other
-	 * handlers. The right way to do this is to move this handler code into
-	 * the mainboard or northbridge code.
-	 * TODO: completely move to mainboards / chipsets.
-	 */
-	switch (regs->eax & 0xffff) {
-	/* And now Intel IGD code */
-#define BOOT_DISPLAY_DEFAULT    0
-#define BOOT_DISPLAY_CRT        (1 << 0)
-#define BOOT_DISPLAY_TV         (1 << 1)
-#define BOOT_DISPLAY_EFP        (1 << 2)
-#define BOOT_DISPLAY_LCD        (1 << 3)
-#define BOOT_DISPLAY_CRT2       (1 << 4)
-#define BOOT_DISPLAY_TV2        (1 << 5)
-#define BOOT_DISPLAY_EFP2       (1 << 6)
-#define BOOT_DISPLAY_LCD2       (1 << 7)
-	case 0x5f35:
-		regs->eax = 0x5f;
-		regs->ecx = BOOT_DISPLAY_DEFAULT;
-		res = 0;
-		break;
-	case 0x5f40:
-		regs->eax = 0x5f;
-		regs->ecx = 3; // This is mainboard specific
-		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
-		res = 0;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
-				regs->eax & 0xffff);
-	}
-
-	return res;
-}
-
diff --git a/src/devices/oprom/x86emu/debug.h b/src/devices/oprom/x86emu/debug.h
index ba180ba..1b2c3a3 100644
--- a/src/devices/oprom/x86emu/debug.h
+++ b/src/devices/oprom/x86emu/debug.h
@@ -198,6 +198,12 @@
 #define	DB(x)
 #endif
 
+#ifdef DEBUG
+#define X86EMU_DEBUG_ONLY(x) x
+#else
+#define X86EMU_DEBUG_ONLY(x) X86EMU_UNUSED(x)
+#endif
+
 /*-------------------------- Function Prototypes --------------------------*/
 
 #ifdef  __cplusplus
diff --git a/src/devices/oprom/x86emu/fpu.c b/src/devices/oprom/x86emu/fpu.c
index daa2ffa..7edebd4 100644
--- a/src/devices/oprom/x86emu/fpu.c
+++ b/src/devices/oprom/x86emu/fpu.c
@@ -50,6 +50,12 @@
     END_OF_INSTR_NO_TRACE();
 }
 
+#ifdef X86EMU_FPU_PRESENT
+#define X86EMU_FPU_ONLY(x) x
+#else
+#define X86EMU_FPU_ONLY(x) X86EMU_UNUSED(x)
+#endif
+
 #ifdef DEBUG
 
 static const char *x86emu_fpu_op_d9_tab[] = {
@@ -95,8 +101,8 @@
 void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -322,8 +328,8 @@
 void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -403,7 +409,7 @@
 void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
+    uint X86EMU_FPU_ONLY(destoffset);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -530,8 +536,8 @@
 void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -640,8 +646,8 @@
 void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -747,8 +753,8 @@
 void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -866,8 +872,8 @@
 void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c
index c66da95..70e048d 100644
--- a/src/devices/oprom/x86emu/ops.c
+++ b/src/devices/oprom/x86emu/ops.c
@@ -3562,7 +3562,7 @@
 ****************************************************************************/
 static void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
 
     START_OF_INSTR();
     DECODE_PRINTF("INT 3\n");
@@ -3590,7 +3590,7 @@
 ****************************************************************************/
 static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
     u8 intnum;
 
     START_OF_INSTR();
@@ -3620,7 +3620,7 @@
 ****************************************************************************/
 static void x86emuOp_into(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
 
     START_OF_INSTR();
     DECODE_PRINTF("INTO\n");
@@ -4034,7 +4034,7 @@
 ****************************************************************************/
 static void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
 {
-    u8 a;
+    u8 X86EMU_UNUSED(a);
 
     START_OF_INSTR();
     DECODE_PRINTF("AAD\n");
diff --git a/src/devices/oprom/x86emu/ops2.c b/src/devices/oprom/x86emu/ops2.c
index 349a664..f559874 100644
--- a/src/devices/oprom/x86emu/ops2.c
+++ b/src/devices/oprom/x86emu/ops2.c
@@ -336,7 +336,7 @@
     int mod, rl, rh;
     uint destoffset;
     u8  *destreg;
-    const char *name = 0;
+    const char *X86EMU_DEBUG_ONLY(name) = 0;
     int cond = 0;
 
     START_OF_INSTR();
diff --git a/src/devices/oprom/yabel/compat/functions.c b/src/devices/oprom/yabel/compat/functions.c
index db37fbc..542c81f 100644
--- a/src/devices/oprom/yabel/compat/functions.c
+++ b/src/devices/oprom/yabel/compat/functions.c
@@ -38,7 +38,7 @@
 
 	biosemu(vmem, VMEM_SIZE, dev, addr);
 
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 	vbe_set_graphics();
 #endif
 }
diff --git a/src/devices/oprom/yabel/device.c b/src/devices/oprom/yabel/device.c
index 8259594..b09f50e 100644
--- a/src/devices/oprom/yabel/device.c
+++ b/src/devices/oprom/yabel/device.c
@@ -364,6 +364,7 @@
 		pci_ds.device_id = in16le(&pci_ds.device_id);
 		pci_ds.img_length = in16le(&pci_ds.img_length);
 		pci_ds.pci_ds_length = in16le(&pci_ds.pci_ds_length);
+#ifdef DO_THIS_TEST_TWICE
 		if (pci_ds.vendor_id != bios_device.pci_vendor_id) {
 			printf
 			    ("Image has invalid Vendor ID: %04x, expected: %04x\n",
@@ -376,6 +377,7 @@
 			     pci_ds.device_id, bios_device.pci_device_id);
 			break;
 		}
+#endif
 		DEBUG_PRINTF("Image Length: %d\n", pci_ds.img_length * 512);
 		DEBUG_PRINTF("Image Code Type: %d\n", pci_ds.code_type);
 		if (pci_ds.code_type == 0) {
diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c
index 75e8f3e..b1d6984 100644
--- a/src/devices/oprom/yabel/vbe.c
+++ b/src/devices/oprom/yabel/vbe.c
@@ -13,7 +13,7 @@
 
 #include <string.h>
 #include <types.h>
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 #include <boot/coreboot_tables.h>
 #endif
 
@@ -31,13 +31,14 @@
 #include "mem.h"
 #include "interrupt.h"
 #include "device.h"
-#include "vbe.h"
 
 #include <cbfs.h>
 
 #include <delay.h>
 #include "../../src/lib/jpeg.h"
 
+#include <vbe.h>
+
 // pointer to VBEInfoBuffer, set by vbe_prepare
 u8 *vbe_info_buffer = 0;
 
@@ -45,97 +46,6 @@
 u8 *biosmem;
 u32 biosmem_size;
 
-// these structs are for input from and output to OF
-typedef struct {
-	u8 display_type;	// 0=NONE, 1= analog, 2=digital
-	u16 screen_width;
-	u16 screen_height;
-	u16 screen_linebytes;	// bytes per line in framebuffer, may be more than screen_width
-	u8 color_depth;	// color depth in bpp
-	u32 framebuffer_address;
-	u8 edid_block_zero[128];
-} __attribute__ ((__packed__)) screen_info_t;
-
-typedef struct {
-	u8 signature[4];
-	u16 size_reserved;
-	u8 monitor_number;
-	u16 max_screen_width;
-	u8 color_depth;
-} __attribute__ ((__packed__)) screen_info_input_t;
-
-// these structs only store a subset of the VBE defined fields
-// only those needed.
-typedef struct {
-	char signature[4];
-	u16 version;
-	u8 *oem_string_ptr;
-	u32 capabilities;
-	u16 video_mode_list[256];	// lets hope we never have more than 256 video modes...
-	u16 total_memory;
-} vbe_info_t;
-
-typedef struct {
-	u16 mode_attributes; // 00
-	u8 win_a_attributes; // 02
-	u8 win_b_attributes; // 03
-	u16 win_granularity; // 04
-	u16 win_size;        // 06
-	u16 win_a_segment;   // 08
-	u16 win_b_segment;   // 0a
-	u32 win_func_ptr;    // 0c
-	u16 bytes_per_scanline; // 10
-	u16 x_resolution;    // 12
-	u16 y_resolution;    // 14
-	u8 x_charsize;       // 16
-	u8 y_charsize;       // 17
-	u8 number_of_planes; // 18
-	u8 bits_per_pixel;   // 19
-	u8 number_of_banks;  // 20
-	u8 memory_model;     // 21
-	u8 bank_size;        // 22
-	u8 number_of_image_pages; // 23
-	u8 reserved_page;
-	u8 red_mask_size;
-	u8 red_mask_pos;
-	u8 green_mask_size;
-	u8 green_mask_pos;
-	u8 blue_mask_size;
-	u8 blue_mask_pos;
-	u8 reserved_mask_size;
-	u8 reserved_mask_pos;
-	u8 direct_color_mode_info;
-	u32 phys_base_ptr;
-	u32 offscreen_mem_offset;
-	u16 offscreen_mem_size;
-	u8 reserved[206];
-} __attribute__ ((__packed__)) vesa_mode_info_t;
-
-typedef struct {
-	u16 video_mode;
-	union {
-		vesa_mode_info_t vesa;
-		u8 mode_info_block[256];
-	};
-	// our crap
-	//u16 attributes;
-	//u16 linebytes;
-	//u16 x_resolution;
-	//u16 y_resolution;
-	//u8 x_charsize;
-	//u8 y_charsize;
-	//u8 bits_per_pixel;
-	//u8 memory_model;
-	//u32 framebuffer_address;
-} vbe_mode_info_t;
-
-typedef struct {
-	u8 port_number;	// i.e. monitor number
-	u8 edid_transfer_time;
-	u8 ddc_level;
-	u8 edid_block_zero[128];
-} vbe_ddc_info_t;
-
 static inline u8
 vbe_prepare(void)
 {
@@ -154,7 +64,7 @@
 	return 0;		// successfull init
 }
 
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 // VBE Function 00h
 static u8
 vbe_info(vbe_info_t * info)
@@ -794,10 +704,12 @@
 
 	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
 	vbe_get_mode_info(&mode_info);
+	vbe_set_mode(&mode_info);
+
+#if CONFIG_BOOTSPLASH
 	unsigned char *framebuffer =
 		(unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr);
 	DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer);
-	vbe_set_mode(&mode_info);
 
 	struct jpeg_decdata *decdata;
 	decdata = malloc(sizeof(*decdata));
@@ -818,6 +730,7 @@
 	DEBUG_PRINTF_VBE("Decompressing boot splash screen...\n");
 	ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata);
 	DEBUG_PRINTF_VBE("returns %x\n", ret);
+#endif
 }
 
 void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..e6c43170 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -51,6 +51,12 @@
 #if CONFIG_PC80_SYSTEM == 1
 #include <pc80/i8259.h>
 #endif
+#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
+#include <arch/acpi.h>
+#endif
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
 
 u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
@@ -664,6 +670,15 @@
 	    ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
 		return;
 
+#if CONFIG_CHROMEOS
+	/* In ChromeOS we want to boot blazingly fast. Therefore
+	 * we don't run (VGA) option ROMs, unless we have to print
+	 * something on the screen before the kernel is loaded.
+	 */
+	if (!developer_mode_enabled() && !recovery_mode_enabled())
+		return;
+#endif
+
 	rom = pci_rom_probe(dev);
 	if (rom == NULL)
 		return;
@@ -672,6 +687,14 @@
 	if (ram == NULL)
 		return;
 
+#if !CONFIG_S3_VGA_ROM_RUN
+	/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
+	 * ROMs when coming out of an S3 resume.
+	 */
+	if ((acpi_slp_type == 3) &&
+		((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
+		return;
+#endif
 	run_bios(dev, (unsigned long)ram);
 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
 }
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 56712df..1b6f1da 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -37,6 +37,19 @@
 	/* If it's in FLASH, then don't check device for ROM. */
 	rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
 
+	u32 vendev = dev->vendor | (dev->device << 16);
+	u32 mapped_vendev = vendev;
+
+	if (map_oprom_vendev)
+		mapped_vendev = map_oprom_vendev(vendev);
+
+	if (!rom_header) {
+		if (vendev != mapped_vendev) {
+			rom_header = cbfs_load_optionrom(mapped_vendev &
+					0xffff, mapped_vendev >> 16, NULL);
+		}
+	}
+
 	if (rom_header) {
 		printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
 		       dev_path(dev), rom_header);
@@ -58,9 +71,15 @@
 					   rom_address|PCI_ROM_ADDRESS_ENABLE);
 		}
 
+#if CONFIG_ON_DEVICE_ROM_RUN
 		printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n",
 		       dev_path(dev), (unsigned long)rom_address);
 		rom_header = (struct rom_header *)rom_address;
+#else
+		printk(BIOS_DEBUG, "On card option ROM execution disabled "
+			"for %s\n", dev_path(dev));
+		return NULL;
+#endif
 	}
 
 	printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "
@@ -78,8 +97,10 @@
 
 	printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n",
 	       rom_data->vendor, rom_data->device);
-	if (dev->vendor != rom_data->vendor
-	    || dev->device != rom_data->device) {
+	/* If the device id is mapped, a mismatch is expected */
+	if ((dev->vendor != rom_data->vendor
+	    || dev->device != rom_data->device)
+	    && (vendev == mapped_vendev)) {
 		printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "
 		       "device ID %04x\n", rom_data->vendor, rom_data->device);
 		return NULL;
diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c
index 5d33942..36f3e6a 100644
--- a/src/devices/pciexp_device.c
+++ b/src/devices/pciexp_device.c
@@ -19,31 +19,197 @@
  */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pciexp.h>
 
+#if CONFIG_PCIEXP_COMMON_CLOCK
+/*
+ * Re-train a PCIe link
+ */
+#define PCIE_TRAIN_RETRY 10000
+static int pciexp_retrain_link(device_t dev, unsigned cap)
+{
+	unsigned try = PCIE_TRAIN_RETRY;
+	u16 lnk;
+
+	/* Start link retraining */
+	lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
+	lnk |= PCI_EXP_LNKCTL_RL;
+	pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk);
+
+	/* Wait for training to complete */
+	while (try--) {
+		lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
+		if (!(lnk & PCI_EXP_LNKSTA_LT))
+			return 0;
+		udelay(100);
+	}
+
+	printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
+	return -1;
+}
+
+/*
+ * Check the Slot Clock Configuration for root port and endpoint
+ * and enable Common Clock Configuration if possible.  If CCC is
+ * enabled the link must be retrained.
+ */
+static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
+				       device_t endp, unsigned endp_cap)
+{
+	u16 root_scc, endp_scc, lnkctl;
+
+	/* Get Slot Clock Configuration for root port */
+	root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA);
+	root_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Get Slot Clock Configuration for endpoint */
+	endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA);
+	endp_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Enable Common Clock Configuration and retrain */
+	if (root_scc && endp_scc) {
+		printk(BIOS_INFO, "Enabling Common Clock Configuration\n");
+
+		/* Set in endpoint */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set in root port */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Retrain link if CCC was enabled */
+		pciexp_retrain_link(root, root_cap);
+	}
+}
+#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
+
+#if CONFIG_PCIEXP_ASPM
+/*
+ * Determine the ASPM L0s or L1 exit latency for a link
+ * by checking both root port and endpoint and returning
+ * the highest latency value.
+ */
+static int pciexp_aspm_latency(device_t root, unsigned root_cap,
+			       device_t endp, unsigned endp_cap,
+			       enum aspm_type type)
+{
+	int root_lat = 0, endp_lat = 0;
+	u32 root_lnkcap, endp_lnkcap;
+
+	root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
+	endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
+
+	/* Make sure the link supports this ASPM type by checking
+	 * capability bits 11:10 with aspm_type offset by 1 */
+	if (!(root_lnkcap & (1 << (type + 9))) ||
+	    !(endp_lnkcap & (1 << (type + 9))))
+		return -1;
+
+	/* Find the one with higher latency */
+	switch (type) {
+	case PCIE_ASPM_L0S:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		break;
+	case PCIE_ASPM_L1:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		break;
+	default:
+		return -1;
+	}
+
+	return (endp_lat > root_lat) ? endp_lat : root_lat;
+}
+
+/*
+ * Enable ASPM on PCIe root port and endpoint.
+ *
+ * Returns APMC value:
+ *   -1 = Error
+ *    0 = no ASPM
+ *    1 = L0s Enabled
+ *    2 = L1 Enabled
+ *    3 = L0s and L1 Enabled
+ */
+static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap,
+					 device_t endp, unsigned endp_cap)
+{
+	const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
+	enum aspm_type apmc = PCIE_ASPM_NONE;
+	int exit_latency, ok_latency;
+	u16 lnkctl;
+	u32 devcap;
+
+	/* Get endpoint device capabilities for acceptable limits */
+	devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
+
+	/* Enable L0s if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L0S);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L0S;
+
+	/* Enable L1 if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L1);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L1;
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Set APMC in root port first */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set APMC in endpoint device next */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+	}
+
+	printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
+	return apmc;
+}
+#endif /* CONFIG_PCIEXP_ASPM */
+
 static void pciexp_tune_dev(device_t dev)
 {
-	unsigned int cap;
-#if CONFIG_PCIE_TUNING
-	u32 reg32;
-#endif
+	device_t root = dev->bus->dev;
+	unsigned int root_cap, cap;
 
 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (!cap)
 		return;
 
-#if CONFIG_PCIE_TUNING
-	printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
+	root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
+	if (!root_cap)
+		return;
 
-	// TODO make this depending on ASPM.
+#if CONFIG_PCIEXP_COMMON_CLOCK
+	/* Check for and enable Common Clock */
+	pciexp_enable_common_clock(root, root_cap, dev, cap);
+#endif
 
-	/* Enable ASPM role based error reporting. */
-	reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
-	reg32 |= PCI_EXP_DEVCAP_RBER;
-	pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+#if CONFIG_PCIEXP_ASPM
+	/* Check for and enable ASPM */
+	enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Enable ASPM role based error reporting. */
+		u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
+		reg32 |= PCI_EXP_DEVCAP_RBER;
+		pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	}
 #endif
 }
 
diff --git a/src/drivers/generic/Makefile.inc b/src/drivers/generic/Makefile.inc
index 0700a0c..08e6cc5 100644
--- a/src/drivers/generic/Makefile.inc
+++ b/src/drivers/generic/Makefile.inc
@@ -1 +1,2 @@
 subdirs-y += debug
+subdirs-y += generic
diff --git a/src/drivers/generic/generic/Makefile.inc b/src/drivers/generic/generic/Makefile.inc
new file mode 100644
index 0000000..b7db254
--- /dev/null
+++ b/src/drivers/generic/generic/Makefile.inc
@@ -0,0 +1 @@
+# Empty
diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc
index 7d3a26f..7f4aa58 100644
--- a/src/drivers/oxford/oxpcie/Makefile.inc
+++ b/src/drivers/oxford/oxpcie/Makefile.inc
@@ -1,3 +1,5 @@
 driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c
 
+ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y)
 romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c
+endif
diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
index 94c5b64..8afdd1f 100644
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -23,7 +23,6 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <uart8250.h>
 
 static void oxford_oxpcie_enable(device_t dev)
 {
@@ -41,9 +40,20 @@
 			(read32(res->base + 4) & 3));
 }
 
+
+static void oxford_oxpcie_set_resources(struct device *dev)
+{
+	pci_dev_set_resources(dev);
+
+#if CONFIG_CONSOLE_SERIAL8250MEM
+	/* Re-initialize OXPCIe base address after set_resources */
+	uartmem_init();
+#endif
+}
+
 static struct device_operations oxford_oxpcie_ops = {
 	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.set_resources    = oxford_oxpcie_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = oxford_oxpcie_enable,
 	.scan_bus         = 0,
@@ -54,3 +64,9 @@
 	.vendor = 0x1415,
 	.device = 0xc158,
 };
+
+static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = {
+	.ops    = &oxford_oxpcie_ops,
+	.vendor = 0x1415,
+	.device = 0xc11b,
+};
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 235c52c..52dae72 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -20,6 +20,8 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <cpu/x86/car.h>
+#include <delay.h>
 #include <uart8250.h>
 #include <device/pci_def.h>
 
@@ -29,11 +31,18 @@
 		CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
 
 #define OXPCIE_DEVICE \
-	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) 
+	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
+
+#define OXPCIE_DEVICE_3 \
+	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
+
+#if defined(__PRE_RAM__)
+int oxford_oxpcie_present CAR_GLOBAL;
 
 void oxford_init(void)
 {
 	u16 reg16;
+	oxford_oxpcie_present = 1;
 
 	/* First we reset the secondary bus */
 	reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
@@ -66,20 +75,44 @@
 	reg16 |= PCI_COMMAND_MEMORY;
 	pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
-	// FIXME Add a timeout or this will hang forever if 
-	// no device is in the slot.
+	u32 timeout = 20000; // Timeout in 10s of microseconds.
 	u32 id = 0;
-	while ((id == 0) || (id == 0xffffffff))
+	for (;;) {
 		id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+		if (!timeout-- || (id != 0 && id != 0xffffffff))
+			break;
+		udelay(10);
+	}
+
+	u32 device = OXPCIE_DEVICE; /* unknown default */
+	switch (id) {
+	case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
+		/* On this device function 0 is the parallel port, and
+		 * function 3 is the serial port. So let's go look for
+		 * the UART.
+		 */
+		id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
+		if (id != 0xc11b1415)
+			return;
+		device = OXPCIE_DEVICE_3;
+		break;
+	case 0xc1581415: /* e.g. Startech MPEX2S952 */
+		device = OXPCIE_DEVICE;
+		break;
+	default:
+		/* No UART here. */
+		oxford_oxpcie_present = 0;
+		return;
+	}
 
 	/* Setup base address on device */
-	pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
+	pci_write_config32(device, PCI_BASE_ADDRESS_0,
 				CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
 
 	/* Enable memory on device */
-	reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
+	reg16 = pci_read_config16(device, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
+	pci_write_config16(device, PCI_COMMAND, reg16);
 
 	/* Now the UART initialization */
 	u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
@@ -87,3 +120,4 @@
 	uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
 }
 
+#endif
diff --git a/src/ec/Kconfig b/src/ec/Kconfig
index 2a36a32..935b40b 100644
--- a/src/ec/Kconfig
+++ b/src/ec/Kconfig
@@ -1,2 +1,3 @@
 source src/ec/acpi/Kconfig
 source src/ec/lenovo/Kconfig
+source src/ec/smsc/Kconfig
diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc
index 69d0435..b334c1f 100644
--- a/src/ec/Makefile.inc
+++ b/src/ec/Makefile.inc
@@ -1,2 +1,2 @@
 subdirs-$(CONFIG_EC_ACPI) += acpi
-subdirs-y += lenovo
+subdirs-y += lenovo smsc
diff --git a/src/ec/smsc/Kconfig b/src/ec/smsc/Kconfig
new file mode 100644
index 0000000..afc6e4b
--- /dev/null
+++ b/src/ec/smsc/Kconfig
@@ -0,0 +1 @@
+source src/ec/smsc/mec1308/Kconfig
diff --git a/src/ec/smsc/Makefile.inc b/src/ec/smsc/Makefile.inc
new file mode 100644
index 0000000..3dd9cce
--- /dev/null
+++ b/src/ec/smsc/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_EC_SMSC_MEC1308) += mec1308
diff --git a/src/ec/smsc/mec1308/Kconfig b/src/ec/smsc/mec1308/Kconfig
new file mode 100644
index 0000000..0a0b04a
--- /dev/null
+++ b/src/ec/smsc/mec1308/Kconfig
@@ -0,0 +1,4 @@
+config EC_SMSC_MEC1308
+	bool
+	help
+	Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
diff --git a/src/ec/smsc/mec1308/Makefile.inc b/src/ec/smsc/mec1308/Makefile.inc
new file mode 100644
index 0000000..95c6c03
--- /dev/null
+++ b/src/ec/smsc/mec1308/Makefile.inc
@@ -0,0 +1,2 @@
+driver-y += ec.c
+smm-y += ec.c
diff --git a/src/ec/smsc/mec1308/acpi/ac.asl b/src/ec/smsc/mec1308/acpi/ac.asl
new file mode 100644
index 0000000..d14f3a4
--- /dev/null
+++ b/src/ec/smsc/mec1308/acpi/ac.asl
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+	Name (_HID, "ACPI0003")
+	Name (_PCL, Package () { \_SB })
+
+	Method (_PSR)
+	{
+		Return (ACEX)
+	}
+
+	Method (_STA)
+	{
+		Return (0x0F)
+	}
+}
diff --git a/src/ec/smsc/mec1308/acpi/battery.asl b/src/ec/smsc/mec1308/acpi/battery.asl
new file mode 100644
index 0000000..9b2f93b
--- /dev/null
+++ b/src/ec/smsc/mec1308/acpi/battery.asl
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define strings in the root scope to
+ * report device-specific battery information to the OS.
+ *
+ *  BATM: Model
+ *  BATS: Serial
+ *  BATV: Vendor
+ */
+
+// Scope (EC0)
+
+Device (BAT0)
+{
+	Name (_HID, EISAID ("PNP0C0A"))
+	Name (_UID, 1)
+	Name (_PCL, Package () { \_SB })
+
+	Name (PBIF, Package () {
+		0x00000001,  // Power Unit: mAh
+		0xFFFFFFFF,  // Design Capacity
+		0xFFFFFFFF,  // Last Full Charge Capacity
+		0x00000001,  // Battery Technology: Rechargeable
+		0xFFFFFFFF,  // Design Voltage
+		0x00000003,  // Design Capacity of Warning
+		0xFFFFFFFF,  // Design Capacity of Low
+		0x00000001,  // Capacity Granularity 1
+		0x00000001,  // Capacity Granularity 2
+		"",          // Model Number
+		"",          // Serial Number
+		"LION",      // Battery Type
+		""           // OEM Information
+	})
+
+	Name (PBST, Package () {
+		0x00000000,  // Battery State
+		0xFFFFFFFF,  // Battery Present Rate
+		0xFFFFFFFF,  // Battery Remaining Capacity
+		0xFFFFFFFF,  // Battery Present Voltage
+	})
+	Name (BSTP, Zero)
+
+	// Workaround for full battery status, enabled by default
+	Name (BFWK, One)
+
+	// Method to enable full battery workaround
+	Method (BFWE)
+	{
+		Store (One, BFWK)
+	}
+
+	// Method to disable full battery workaround
+	Method (BFWD)
+	{
+		Store (Zero, BFWK)
+	}
+
+	// Swap bytes in a word
+	Method (SWAB, 1, NotSerialized)
+	{
+		ShiftRight (Arg0, 8, Local0)
+		ShiftLeft (Arg0, 8, Local1)
+		And (Local1, 0xFF00, Local1)
+		Or (Local0, Local1, Local0)
+		If (LEqual (Local0, 0xFFFF)) {
+			Store (0xFFFFFFFF, Local0)
+		}
+		Return (Local0)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (BTEX) {
+			Return (0x1F)
+		} Else {
+			Return (0x0F)
+		}
+	}
+
+	Method (_BIF, 0, Serialized)
+	{
+		// Update fields from EC
+		Store (SWAB (BTDA), Index (PBIF, 1))
+		Store (SWAB (BTDF), Index (PBIF, 2))
+		Store (SWAB (BTDV), Index (PBIF, 4))
+		Store (SWAB (BTDL), Index (PBIF, 6))
+
+		// Get battery info from mainboard
+		Store (\BATM, Index (PBIF, 9))
+		Store (\BATS, Index (PBIF, 10))
+		Store (\BATV, Index (PBIF, 12))
+
+		Return (PBIF)
+	}
+
+	Method (_BST, 0, Serialized)
+	{
+		//
+		// 0: BATTERY STATE
+		//
+		// bit 0 = discharging
+		// bit 1 = charging
+		// bit 2 = critical level
+		//
+
+		// Get battery state from EC
+		Store (BTST, Local0)
+		Store (Zero, Local1)
+
+		// Check if AC is present
+		If (ACEX) {
+			// Set only charging/discharging bits
+			And (Local0, 0x03, Local1)
+		} Else {
+			// Always discharging when on battery power
+			Store (0x01, Local1)
+		}
+
+		// Flag if the battery level is critical
+		And (Local0, 0x04, Local4)
+		Or (Local1, Local4, Local1)
+		Store (Local1, Index (PBST, 0))
+
+		// Notify if battery state has changed since last time
+		If (LNotEqual (Local1, BSTP)) {
+			Store (Local1, BSTP)
+			Notify (BAT0, 0x80)
+		}
+
+		//
+		// 1: BATTERY PRESENT RATE
+		//
+
+		Store (SWAB (BTPR), Local1)
+		If (LAnd (LNotEqual (Local1, 0xFFFFFFFF),
+		          LGreaterEqual (Local1, 0x8000))) {
+			Xor (Local1, 0xFFFF, Local1)
+			Increment (Local1)
+		}
+		Store (Local1, Index (PBST, 1))
+
+		//
+		// 2: BATTERY REMAINING CAPACITY
+		//
+		Store (SWAB (BTRA), Local1)
+		If (LAnd (LNotEqual (Local1, 0xFFFFFFFF),
+		          LGreaterEqual (Local1, 0x8000))) {
+			Xor (Local1, 0xFFFF, Local1)
+			Increment (Local1)
+		}
+
+		If (LAnd (BFWK, LAnd (ACEX, LNot (Local0)))) {
+			// On AC power and battery is neither charging
+			// nor discharging.  Linux expects a full battery
+			// to report same capacity as last full charge.
+			// https://bugzilla.kernel.org/show_bug.cgi?id=12632
+			Store (SWAB (BTDF), Local2)
+
+			// See if within ~3% of full
+			ShiftRight (Local2, 5, Local3)
+			If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+			          LLess (Local1, Add (Local2, Local3))))
+			{
+				Store (Local2, Local1)
+			}
+		}
+		Store (Local1, Index (PBST, 2))
+
+		//
+		// 3: BATTERY PRESENT VOLTAGE
+		//
+		Store (SWAB (BTVO), Index (PBST, 3))
+
+		Return (PBST)
+	}
+}
diff --git a/src/ec/smsc/mec1308/acpi/ec.asl b/src/ec/smsc/mec1308/acpi/ec.asl
new file mode 100644
index 0000000..f0b77c2
--- /dev/null
+++ b/src/ec/smsc/mec1308/acpi/ec.asl
@@ -0,0 +1,272 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+	Name (_HID, EISAID ("PNP0C09"))
+	Name (_UID, 1)
+	Name (_GPE, EC_GPE)	// GPE for Runtime SCI
+
+	OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x80),
+		BTEX, 1,		// Battery Exists
+		, 1,
+		ACEX, 1,		// AC Exists
+		, 5,
+		Offset (0x83),
+		LIDS, 1,		// Lid Switch State
+		, 7,
+		BTST, 8,		// Battery State
+		Offset (0xA2),
+		BTRA, 16,		// Battery Remaining Capacity
+		BTPR, 16,		// Battery Present Rate
+		BTVO, 16,		// Battery Present Voltage
+		Offset (0xB0),
+		BTDA, 16,		// Battery Design Capacity
+		BTDF, 16,		// Battery Last Full Charge Capacity
+		BTDV, 16,		// Battery Design Voltage
+		BTDL, 16,		// Battery Design Low
+		Offset (0xC0),
+		CPUT, 8,		// CPU Temperature
+		Offset (0xCA),
+		FSL0, 1,		// Fan Speed Level 0
+		FSL1, 1,		// Fan Speed Level 1
+		FSL2, 1,		// Fan Speed Level 2
+		FSL3, 1,		// Fan Speed Level 3
+		FSL4, 1,		// Fan Speed Level 4
+		, 2,
+		FCOS, 1,		// Fan Speed OS Control
+	}
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 0, 1)
+			IO (Decode16, 0x66, 0x66, 0, 1)
+		})
+		Return (ECMD)
+	}
+
+	Method (_REG, 2, NotSerialized)
+	{
+		// Initialize AC power state
+		Store (ACEX, \PWRS)
+
+		// Initialize LID switch state
+		Store (LIDS, \LIDS)
+
+		// Enable OS control of fan speed
+		Store (One, FCOS)
+
+		// Force a read of CPU temperature
+		Store (CPUT, Local0)
+	}
+
+	PowerResource (FNP0, 0, 0)
+	{
+		Method (_STA) { Return (FSL0) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL0)
+				Store (0, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL0)
+				Store (1, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP1, 0, 0)
+	{
+		Method (_STA) { Return (FSL1) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL1)
+				Store (1, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL1)
+				Store (2, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP2, 0, 0)
+	{
+		Method (_STA) { Return (FSL2) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL2)
+				Store (2, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL2)
+				Store (3, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP3, 0, 0)
+	{
+		Method (_STA) { Return (FSL3) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL3)
+				Store (3, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL3)
+				Store (4, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP4, 0, 0)
+	{
+		Method (_STA) { Return (FSL4) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL4)
+				Store (4, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL4)
+				Store (5, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	Device (FAN0)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 0)
+		Name (_PR0, Package () { FNP0 })
+	}
+
+	Device (FAN1)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 1)
+		Name (_PR0, Package () { FNP1 })
+	}
+
+	Device (FAN2)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 2)
+		Name (_PR0, Package () { FNP2 })
+	}
+
+	Device (FAN3)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 3)
+		Name (_PR0, Package () { FNP3 })
+	}
+
+	Device (FAN4)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 4)
+		Name (_PR0, Package () { FNP4 })
+	}
+
+	// AC Power Connected
+	Method (_Q51, 0, NotSerialized)
+	{
+		Store (One, \PWRS)
+		Notify (AC, 0x80)
+		\PNOT ()
+	}
+
+	// AC Power Removed
+	Method (_Q52, 0, NotSerialized)
+	{
+		Store (Zero, \PWRS)
+		Notify (AC, 0x80)
+		\PNOT ()
+	}
+
+	// Battery State Change
+	Method (_Q53, 0, NotSerialized)
+	{
+		Notify (BAT0, 0x80)
+		Notify (BAT0, 0x81)
+	}
+
+	// Battery State Change
+	Method (_Q54, 0, NotSerialized)
+	{
+		Notify (BAT0, 0x80)
+		Notify (BAT0, 0x81)
+	}
+
+	// Power State Change
+	Method (_Q55, 0, NotSerialized)
+	{
+		\PNOT ()
+	}
+
+	// Lid Switch Event
+	Method (_Q5E, 0, NotSerialized)
+	{
+		Store (LIDS, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	// Lid Switch Event
+	Method (_Q5F, 0, NotSerialized)
+	{
+		Store (LIDS, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	#include "ac.asl"
+	#include "battery.asl"
+}
diff --git a/src/ec/smsc/mec1308/chip.h b/src/ec/smsc/mec1308/chip.h
new file mode 100644
index 0000000..3a8eae8
--- /dev/null
+++ b/src/ec/smsc/mec1308/chip.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _EC_SMSC_MEC1308_CHIP_H
+#define _EC_SMSC_MEC1308_CHIP_H
+
+struct ec_smsc_mec1308_config
+{
+	u16 mailbox_port;
+};
+
+struct chip_operations;
+extern struct chip_operations ec_smsc_mec1308_ops;
+
+#endif /* _EC_SMSC_MEC1308_CHIP_H */
diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c
new file mode 100644
index 0000000..bfd3c14
--- /dev/null
+++ b/src/ec/smsc/mec1308/ec.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "ec.h"
+#include "chip.h"
+
+static u16 ec_cmd_reg = 0;
+static u16 ec_data_reg = 0;
+
+static inline u8 __ec_read(u8 addr)
+{
+	outb(addr, ec_cmd_reg);
+	return inb(ec_data_reg);
+}
+
+static inline void __ec_write(u8 addr, u8 data)
+{
+	outb(addr, ec_cmd_reg);
+	outb(data, ec_data_reg);
+}
+
+static int ec_ready(void)
+{
+	u16 timeout = EC_TIMEOUT;
+
+	if (!ec_cmd_reg || !ec_data_reg) {
+		printk(BIOS_DEBUG, "Invalid ports: cmd=0x%x data=0x%x\n",
+		       ec_cmd_reg, ec_data_reg);
+		return -1;
+	}
+
+	while (__ec_read(EC_MAILBOX_COMMAND) != 0 && --timeout) {
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk(BIOS_SPEW, ".");
+	}
+	if (!timeout) {
+		printk(BIOS_DEBUG, "Timeout waiting for EC to be ready.\n");
+		return -1;
+	}
+	return 0;
+}
+
+int send_ec_command(u8 command)
+{
+	if (ec_ready() < 0)
+		return -1;
+	__ec_write(EC_MAILBOX_COMMAND, command);
+	return ec_ready();
+}
+
+int send_ec_command_data(u8 command, u8 data)
+{
+	if (ec_ready() < 0)
+		return -1;
+	__ec_write(EC_MAILBOX_DATA, data);
+	__ec_write(EC_MAILBOX_COMMAND, command);
+	return ec_ready();
+}
+
+u8 read_ec_command_byte(u8 command)
+{
+	send_ec_command(command);
+	return __ec_read(EC_MAILBOX_DATA);
+}
+
+u8 ec_read(u8 addr)
+{
+	if (send_ec_command_data(EC_RAM_READ, addr) < 0)
+		return 0;
+	return __ec_read(EC_MAILBOX_DATA);
+}
+
+int ec_write(u8 addr, u8 data)
+{
+	if (ec_ready() < 0)
+		return -1;
+	__ec_write(EC_MAILBOX_DATA, addr);
+	__ec_write(EC_MAILBOX_DATA_H, data);
+	__ec_write(EC_MAILBOX_COMMAND, EC_RAM_WRITE);
+	return ec_ready();
+}
+
+void ec_set_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) | (1 << bit));
+}
+
+void ec_clr_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) &  ~(1 << bit));
+}
+
+void ec_set_ports(u16 cmd_reg, u16 data_reg)
+{
+	ec_cmd_reg = cmd_reg;
+	ec_data_reg = data_reg;
+}
+
+static void mec1308_enable(device_t dev)
+{
+	struct ec_smsc_mec1308_config *conf = dev->chip_info;
+
+	if (conf->mailbox_port) {
+		ec_cmd_reg = conf->mailbox_port;
+		ec_data_reg = conf->mailbox_port + 1;
+	}
+}
+
+struct chip_operations ec_smsc_mec1308_ops = {
+	CHIP_NAME("SMSC MEC1308 EC Mailbox Interface")
+	.enable_dev = mec1308_enable
+};
diff --git a/src/ec/smsc/mec1308/ec.h b/src/ec/smsc/mec1308/ec.h
new file mode 100644
index 0000000..07bfc4f
--- /dev/null
+++ b/src/ec/smsc/mec1308/ec.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Mailbox EC communication interface for SMSC MEC1308 Embedded Controller.
+ */
+
+#ifndef _EC_SMSC_MEC1308_EC_H
+#define _EC_SMSC_MEC1308_EC_H
+
+#define EC_TIMEOUT           0xfff
+#define EC_MAILBOX_COMMAND   0x82  // Send a command
+#define EC_MAILBOX_DATA      0x84  // Send data with a command
+#define EC_MAILBOX_DATA_H    0x85  // Send data with a command
+#define EC_RAM_READ          0x88  // Read from RAM
+#define EC_RAM_WRITE         0x89  // Write to RAM
+
+int send_ec_command(u8 command);
+int send_ec_command_data(u8 command, u8 data);
+u8 read_ec_command_byte(u8 command);
+u8 ec_read(u8 addr);
+int ec_write(u8 addr, u8 data);
+void ec_set_bit(u8 addr, u8 bit);
+void ec_clr_bit(u8 addr, u8 bit);
+void ec_set_ports(u16 cmd_reg, u16 data_reg);
+
+#endif /* _EC_SMSC_MEC1308_EC_H */
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 983b03f..bf59271 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -146,7 +146,10 @@
 struct lb_serial {
 	uint32_t tag;
 	uint32_t size;
-	uint16_t ioport;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
 	uint32_t baud;
 };
 
@@ -192,6 +195,59 @@
 	uint8_t reserved_mask_size;
 };
 
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_FDT	0x0014
+struct lb_fdt {
+	uint32_t tag;
+	uint32_t size;		     /* size of the entire entry */
+	/* the actual FDT gets placed here */
+};
+
+#define LB_TAG_VDAT	0x0015
+struct lb_vdat {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*vdat_addr;
+	uint32_t vdat_size;
+};
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*cbmem_addr;
+};
+
+#define LB_TAG_VBNV		0x0019
+struct lb_vbnv {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t vbnv_start;
+	uint32_t vbnv_size;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index c1c1e33..d517fe8 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -49,6 +49,7 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
+#include <arch/byteorder.h>
 #include <boot/coreboot_tables.h>
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
@@ -72,17 +73,18 @@
 #define CBFS_TYPE_MBI        0x52
 #define CBFS_TYPE_MICROCODE  0x53
 #define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_FDT	     0xac
 #define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
 
 
 /** this is the master cbfs header - it need to be
     located somewhere in the bootblock.  Where it
     actually lives is up to coreboot. A pointer to
-    this header will live at 0xFFFFFFFc, so we can
+    this header will live at 0xfffffffc, so we can
     easily find it. */
 
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADPTR_ADDR 0xFFFFFFFc
+#define CBFS_HEADER_MAGIC  0x4f524243
+#define CBFS_HEADPTR_ADDR 0xfffffffc
 #define VERSION1 0x31313131
 
 struct cbfs_header {
@@ -152,11 +154,11 @@
 	struct cbfs_payload_segment segments;
 };
 
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_CODE   0x45444f43
 #define PAYLOAD_SEGMENT_DATA   0x41544144
 #define PAYLOAD_SEGMENT_BSS    0x20535342
 #define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+#define PAYLOAD_SEGMENT_ENTRY  0x52544e45
 
 struct cbfs_optionrom {
 	u32 compression;
@@ -169,10 +171,12 @@
 void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name);
 void * cbfs_load_stage(const char *name);
 int cbfs_execute_stage(const char *name);
-void * cbfs_get_file(const char *name);
 void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest);
 int run_address(void *f);
 struct cbfs_file *cbfs_find(const char *name);
 void *cbfs_find_file(const char *name, int type);
+struct cbfs_header *get_cbfs_header(void);
+void *get_cbfs_base(void);
+u32 get_cbfs_size(void);
 #endif
 
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index d9ec93c..c55a7ca 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -20,13 +20,22 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-/* Reserve 64k for ACPI and other tables */
-#define HIGH_MEMORY_DEF_SIZE	( 64 * 1024 )
-extern uint64_t high_tables_base, high_tables_size;
+/* Reserve 128k for ACPI and other tables */
+#if CONFIG_CONSOLE_CBMEM
+#define HIGH_MEMORY_DEF_SIZE	( 256 * 1024 )
+#else
+#define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
+#endif
 
 #if CONFIG_HAVE_ACPI_RESUME
 #define HIGH_MEMORY_SIZE	((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE)
 #define HIGH_MEMORY_SAVE	( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE )
+
+/* Delegation of resume backup memory so we don't have to
+ * (slowly) handle backing up OS memory in romstage.c
+ */
+#define CBMEM_BOOT_MODE		0x610
+#define CBMEM_RESUME_BACKUP	0x614
 #else
 #define HIGH_MEMORY_SIZE	HIGH_MEMORY_DEF_SIZE
 #endif
@@ -38,9 +47,18 @@
 #define CBMEM_ID_PIRQ		0x49525154
 #define CBMEM_ID_MPTABLE	0x534d5054
 #define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_CONSOLE	0x434f4e53
 #define CBMEM_ID_NONE		0x00000000
 
-void cbmem_initialize(void);
+#ifndef __ASSEMBLER__
+#ifndef __PRE_RAM__
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
+int cbmem_initialize(void);
 
 void cbmem_init(u64 baseaddr, u64 size);
 int cbmem_reinit(u64 baseaddr);
@@ -55,3 +73,4 @@
 void set_cbmem_toc(struct cbmem_entry *);
 #endif
 #endif
+#endif
diff --git a/src/cpu/x86/mmx_disable.inc b/src/include/console/cbmem_console.h
similarity index 68%
copy from src/cpu/x86/mmx_disable.inc
copy to src/include/console/cbmem_console.h
index 1a4e70f..37ea4d8 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/include/console/cbmem_console.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,13 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
+#ifndef _CONSOLE_CBMEM_CONSOLE_H_
+#define _CONSOLE_CBMEM_CONSOLE_H_
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+void cbmemc_init(void);
+void cbmemc_reinit(void);
+void cbmemc_tx_byte(unsigned char data);
 
+#endif
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 8283f66..3a8f47a 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -24,15 +24,24 @@
 #include <console/loglevel.h>
 #include <console/post_codes.h>
 
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
+#include <uart8250.h>
+#endif
+#ifdef CONFIG_USBDEBUG
+#include <usbdebug.h>
+#endif
+#if CONFIG_CONSOLE_NE2K
+#include <console/ne2k.h>
+#endif
+#if CONFIG_CONSOLE_CBMEM
+#include <console/cbmem_console.h>
+#endif
+
 #ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
 void console_tx_flush(void);
 unsigned char console_rx_byte(void);
 int console_tst_byte(void);
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-
 struct console_driver {
 	void (*init)(void);
 	void (*tx_byte)(unsigned char byte);
@@ -55,9 +64,6 @@
  * we could use the same code on all architectures.
  */
 #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-#if CONFIG_CONSOLE_SERIAL8250
-#include <uart8250.h>
-#endif
 #endif
 
 #ifndef __ROMCC__
diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h
new file mode 100644
index 0000000..b60c8cf
--- /dev/null
+++ b/src/include/cpu/intel/turbo.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_INTEL_TURBO_H
+#define _CPU_INTEL_TURBO_H
+
+#define CPUID_LEAF_PM		6
+#define PM_CAP_TURBO_MODE	(1 << 1)
+
+#define MSR_IA32_MISC_ENABLES	0x1a0
+#define H_MISC_DISABLE_TURBO	(1 << 6)
+
+enum {
+	TURBO_UNKNOWN,
+	TURBO_UNAVAILABLE,
+	TURBO_DISABLED,
+	TURBO_ENABLED,
+};
+
+/* Return current turbo state */
+int get_turbo_state(void);
+
+/* Enable turbo */
+void enable_turbo(void);
+
+#endif
diff --git a/src/cpu/x86/mmx_disable.inc b/src/include/cpu/x86/car.h
similarity index 61%
copy from src/cpu/x86/mmx_disable.inc
copy to src/include/cpu/x86/car.h
index 1a4e70f..2d2af03 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/include/cpu/x86/car.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,18 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef CPU_X86_CAR_H
+#define CPU_X86_CAR_H
 
+#ifdef __PRE_RAM__
+#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\",@nobits#")))
+#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\",@nobits#")))
+#else
+#define CAR_GLOBAL
+#define CAR_CBMEM
+#endif
+
+#endif
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 8b44a6c..2229a53 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -1,9 +1,11 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
+#ifndef __ROMCC__
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
 #include <arch/hlt.h>
+#include <delay.h>
 
 /* See if I need to initialize the local apic */
 #if CONFIG_SMP || CONFIG_IOAPIC
@@ -27,8 +29,6 @@
 	do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
 }
 
-
-
 static inline void enable_lapic(void)
 {
 
@@ -132,7 +132,7 @@
 	lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
 	timeout = 0;
 	do {
-#if 0
+#if 1
 		udelay(100);
 #endif
 		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
@@ -156,4 +156,7 @@
 
 #endif /* !__PRE_RAM__ */
 
+int boot_cpu(void);
+#endif
+
 #endif /* CPU_X86_LAPIC_H */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 44a2223..1a00cb0 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
 #define MTRRdefTypeEn		(1 << 11)
 #define MTRRdefTypeFixEn	(1 << 10)
 
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
@@ -35,6 +38,8 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
+#define NoEvictMod_MSR 0x2e0
+
 #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
@@ -67,7 +72,7 @@
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
-#if !defined (__ASSEMBLER__)
+#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
 #if defined(CONFIG_XIP_ROM_SIZE)
 # if CONFIG_TINY_BOOTBLOCK
    extern unsigned long AUTO_XIP_ROM_BASE;
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index 20b87c6..729f3c6 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -1,7 +1,6 @@
-
 #include <console/post_codes.h>
 
-#define post_code(value)        \
-	movb    $value, %al;    \
+#define post_code(value)     \
+	movb    $value, %al; \
 	outb    %al, $0x80
 
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index ad0984ea..9e5ddc1 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -263,4 +263,5 @@
 void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 
 void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
-
+void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ);
+void __attribute__((weak)) mainboard_smi_apmc(u8 apmc);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 42b68f6..0aea1d6 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -16,6 +16,9 @@
 struct chip_operations {
 	void (*enable_dev)(struct device *dev);
 	const char *name;
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
+#endif
 };
 
 #define CHIP_NAME(X) .name = X,
@@ -31,6 +34,9 @@
 	void (*enable)(device_t dev);
 	void (*set_link)(device_t dev, unsigned int link);
 	void (*reset_bus)(struct bus *bus);
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
+#endif
 	const struct pci_operations *ops_pci;
 	const struct smbus_bus_operations *ops_smbus_bus;
 	const struct pci_bus_operations *ops_pci_bus;
@@ -126,6 +132,8 @@
 device_t dev_find_class (unsigned int class, device_t from);
 device_t dev_find_slot (unsigned int bus, unsigned int devfn);
 device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
+device_t dev_find_lapic(unsigned apic_id);
+int dev_count_cpu(void);
 
 /* Debug functions */
 void print_resource_tree(struct device * root, int debug_level,
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index a5aa3a1..58a7321 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -371,8 +371,15 @@
 #define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
 #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
+#define  PCI_EXP_LNKCAP_ASPMS	0xc00	/* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL	0x7000	/* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL	0x38000	/* L1 Exit Latency */
 #define PCI_EXP_LNKCTL		16	/* Link Control */
+#define  PCI_EXP_LNKCTL_RL	0x20	/* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC	0x40	/* Common Clock COnfiguration */
 #define PCI_EXP_LNKSTA		18	/* Link Status */
+#define  PCI_EXP_LNKSTA_LT	0x800	/* Link Training */
+#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
 #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
 #define PCI_EXP_SLTCTL		24	/* Slot Control */
 #define PCI_EXP_SLTSTA		26	/* Slot Status */
diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h
index f268341..fe77276 100644
--- a/src/include/device/pci_rom.h
+++ b/src/include/device/pci_rom.h
@@ -35,5 +35,6 @@
 
 struct rom_header *pci_rom_probe(struct device *dev);
 struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header);
+u32 __attribute__((weak)) map_oprom_vendev(u32 vendev);
 
 #endif
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 409f211..87a5002 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -2,6 +2,13 @@
 #define DEVICE_PCIEXP_H
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
+enum aspm_type {
+	PCIE_ASPM_NONE = 0,
+	PCIE_ASPM_L0S  = 1,
+	PCIE_ASPM_L1   = 2,
+	PCIE_ASPM_BOTH = 3,
+};
+
 unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn, unsigned int max);
 unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);
diff --git a/src/include/fdt/fdt.h b/src/include/fdt/fdt.h
new file mode 100644
index 0000000..14da287
--- /dev/null
+++ b/src/include/fdt/fdt.h
@@ -0,0 +1,64 @@
+#ifndef _FDT_H
+#define _FDT_H
+
+#include <types.h>
+#include <string.h>
+#ifndef __ASSEMBLY__
+
+struct fdt_header {
+	uint32_t magic;			 /* magic word FDT_MAGIC */
+	uint32_t totalsize;		 /* total size of DT block */
+	uint32_t off_dt_struct;		 /* offset to structure */
+	uint32_t off_dt_strings;	 /* offset to strings */
+	uint32_t off_mem_rsvmap;	 /* offset to memory reserve map */
+	uint32_t version;		 /* format version */
+	uint32_t last_comp_version;	 /* last compatible version */
+
+	/* version 2 fields below */
+	uint32_t boot_cpuid_phys;	 /* Which physical CPU id we're
+					    booting on */
+	/* version 3 fields below */
+	uint32_t size_dt_strings;	 /* size of the strings block */
+
+	/* version 17 fields below */
+	uint32_t size_dt_struct;	 /* size of the structure block */
+};
+
+struct fdt_reserve_entry {
+	uint64_t address;
+	uint64_t size;
+};
+
+struct fdt_node_header {
+	uint32_t tag;
+	char name[0];
+};
+
+struct fdt_property {
+	uint32_t tag;
+	uint32_t len;
+	uint32_t nameoff;
+	char data[0];
+};
+
+#endif /* !__ASSEMBLY */
+
+#define FDT_MAGIC	0xd00dfeed	/* 4: version, 4: total size */
+#define FDT_TAGSIZE	sizeof(uint32_t)
+
+#define FDT_BEGIN_NODE	0x1		/* Start node: full name */
+#define FDT_END_NODE	0x2		/* End node */
+#define FDT_PROP	0x3		/* Property: name off,
+					   size, content */
+#define FDT_NOP		0x4		/* nop */
+#define FDT_END		0x9
+
+#define FDT_V1_SIZE	(7*sizeof(uint32_t))
+#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(uint32_t))
+#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(uint32_t))
+#define FDT_V16_SIZE	FDT_V3_SIZE
+#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(uint32_t))
+
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD	0x80
+#endif /* _FDT_H */
diff --git a/src/include/fdt/fdt_support.h b/src/include/fdt/fdt_support.h
new file mode 100644
index 0000000..863024f
--- /dev/null
+++ b/src/include/fdt/fdt_support.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2007
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FDT_SUPPORT_H
+#define __FDT_SUPPORT_H
+
+#ifdef CONFIG_OF_LIBFDT
+
+#include <fdt.h>
+
+u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
+				const u32 dflt);
+int fdt_chosen(void *fdt, int force);
+int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
+void do_fixup_by_path(void *fdt, const char *path, const char *prop,
+		      const void *val, int len, int create);
+void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
+			  u32 val, int create);
+void do_fixup_by_prop(void *fdt,
+		      const char *pname, const void *pval, int plen,
+		      const char *prop, const void *val, int len,
+		      int create);
+void do_fixup_by_prop_u32(void *fdt,
+			  const char *pname, const void *pval, int plen,
+			  const char *prop, u32 val, int create);
+void do_fixup_by_compat(void *fdt, const char *compat,
+			const char *prop, const void *val, int len, int create);
+void do_fixup_by_compat_u32(void *fdt, const char *compat,
+			    const char *prop, u32 val, int create);
+int fdt_fixup_memory(void *blob, u64 start, u64 size);
+int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+void fdt_fixup_ethernet(void *fdt);
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+			 const void *val, int len, int create);
+void fdt_fixup_qe_firmware(void *fdt);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+void fdt_fixup_dr_usb(void *blob, bd_t *bd);
+#else
+static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
+#endif /* CONFIG_HAS_FSL_DR_USB */
+
+#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
+void fdt_fixup_crypto_node(void *blob, int sec_rev);
+#else
+static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
+#endif
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+
+void set_working_fdt_addr(void *addr);
+int fdt_resize(void *blob);
+int fdt_increase_size(void *fdt, int add_len);
+
+int fdt_fixup_nor_flash_size(void *blob);
+
+void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
+void fdt_del_node_and_alias(void *blob, const char *alias);
+u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
+int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
+					phys_addr_t compat_off);
+int fdt_alloc_phandle(void *blob);
+int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle);
+int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
+
+int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
+			      u64 addr);
+u64 fdt_get_base_address(void *fdt, int node);
+
+#endif /* ifdef CONFIG_OF_LIBFDT */
+#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/src/include/fdt/libfdt.h b/src/include/fdt/libfdt.h
new file mode 100644
index 0000000..993a654
--- /dev/null
+++ b/src/include/fdt/libfdt.h
@@ -0,0 +1,1248 @@
+#ifndef _LIBFDT_H
+#define _LIBFDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <libfdt_env.h>
+#include <fdt.h>
+
+#define FDT_FIRST_SUPPORTED_VERSION	0x10
+#define FDT_LAST_SUPPORTED_VERSION	0x11
+
+/* Error codes: informative error codes */
+#define FDT_ERR_NOTFOUND	1
+	/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
+#define FDT_ERR_EXISTS		2
+	/* FDT_ERR_EXISTS: Attemped to create a node or property which
+	 * already exists */
+#define FDT_ERR_NOSPACE		3
+	/* FDT_ERR_NOSPACE: Operation needed to expand the device
+	 * tree, but its buffer did not have sufficient space to
+	 * contain the expanded tree. Use fdt_open_into() to move the
+	 * device tree to a buffer with more space. */
+
+/* Error codes: codes for bad parameters */
+#define FDT_ERR_BADOFFSET	4
+	/* FDT_ERR_BADOFFSET: Function was passed a structure block
+	 * offset which is out-of-bounds, or which points to an
+	 * unsuitable part of the structure for the operation. */
+#define FDT_ERR_BADPATH		5
+	/* FDT_ERR_BADPATH: Function was passed a badly formatted path
+	 * (e.g. missing a leading / for a function which requires an
+	 * absolute path) */
+#define FDT_ERR_BADPHANDLE	6
+	/* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle
+	 * value.  phandle values of 0 and -1 are not permitted. */
+#define FDT_ERR_BADSTATE	7
+	/* FDT_ERR_BADSTATE: Function was passed an incomplete device
+	 * tree created by the sequential-write functions, which is
+	 * not sufficiently complete for the requested operation. */
+
+/* Error codes: codes for bad device tree blobs */
+#define FDT_ERR_TRUNCATED	8
+	/* FDT_ERR_TRUNCATED: Structure block of the given device tree
+	 * ends without an FDT_END tag. */
+#define FDT_ERR_BADMAGIC	9
+	/* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
+	 * device tree at all - it is missing the flattened device
+	 * tree magic number. */
+#define FDT_ERR_BADVERSION	10
+	/* FDT_ERR_BADVERSION: Given device tree has a version which
+	 * can't be handled by the requested operation.  For
+	 * read-write functions, this may mean that fdt_open_into() is
+	 * required to convert the tree to the expected version. */
+#define FDT_ERR_BADSTRUCTURE	11
+	/* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
+	 * structure block or other serious error (e.g. misnested
+	 * nodes, or subnodes preceding properties). */
+#define FDT_ERR_BADLAYOUT	12
+	/* FDT_ERR_BADLAYOUT: For read-write functions, the given
+	 * device tree has it's sub-blocks in an order that the
+	 * function can't handle (memory reserve map, then structure,
+	 * then strings).  Use fdt_open_into() to reorganize the tree
+	 * into a form suitable for the read-write operations. */
+
+/* "Can't happen" error indicating a bug in libfdt */
+#define FDT_ERR_INTERNAL	13
+	/* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
+	 * Should never be returned, if it is, it indicates a bug in
+	 * libfdt itself. */
+
+#define FDT_ERR_MAX		13
+
+/**********************************************************************/
+/* Low-level functions (you probably don't need these)                */
+/**********************************************************************/
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
+static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
+{
+	return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
+}
+
+uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
+
+/**********************************************************************/
+/* Traversal functions                                                */
+/**********************************************************************/
+
+int fdt_next_node(const void *fdt, int offset, int *depth);
+
+/**********************************************************************/
+/* General functions                                                  */
+/**********************************************************************/
+
+#define fdt_get_header(fdt, field) \
+	(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
+#define fdt_magic(fdt)			(fdt_get_header(fdt, magic))
+#define fdt_totalsize(fdt)		(fdt_get_header(fdt, totalsize))
+#define fdt_off_dt_struct(fdt)		(fdt_get_header(fdt, off_dt_struct))
+#define fdt_off_dt_strings(fdt)		(fdt_get_header(fdt, off_dt_strings))
+#define fdt_off_mem_rsvmap(fdt)		(fdt_get_header(fdt, off_mem_rsvmap))
+#define fdt_version(fdt)		(fdt_get_header(fdt, version))
+#define fdt_last_comp_version(fdt)	(fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt)	(fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt)	(fdt_get_header(fdt, size_dt_strings))
+#define fdt_size_dt_struct(fdt)		(fdt_get_header(fdt, size_dt_struct))
+
+#define __fdt_set_hdr(name) \
+	static inline void fdt_set_##name(void *fdt, uint32_t val) \
+	{ \
+		struct fdt_header *fdth = (struct fdt_header*)fdt; \
+		fdth->name = cpu_to_fdt32(val); \
+	}
+__fdt_set_hdr(magic);
+__fdt_set_hdr(totalsize);
+__fdt_set_hdr(off_dt_struct);
+__fdt_set_hdr(off_dt_strings);
+__fdt_set_hdr(off_mem_rsvmap);
+__fdt_set_hdr(version);
+__fdt_set_hdr(last_comp_version);
+__fdt_set_hdr(boot_cpuid_phys);
+__fdt_set_hdr(size_dt_strings);
+__fdt_set_hdr(size_dt_struct);
+#undef __fdt_set_hdr
+
+/**
+ * fdt_check_header - sanity check a device tree or possible device tree
+ * @fdt: pointer to data which might be a flattened device tree
+ *
+ * fdt_check_header() checks that the given buffer contains what
+ * appears to be a flattened device tree with sane information in its
+ * header.
+ *
+ * returns:
+ *     0, if the buffer appears to contain a valid device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings, as above
+ */
+int fdt_check_header(const void *fdt);
+
+/**
+ * fdt_move - move a device tree around in memory
+ * @fdt: pointer to the device tree to move
+ * @buf: pointer to memory where the device is to be moved
+ * @bufsize: size of the memory space at buf
+ *
+ * fdt_move() relocates, if possible, the device tree blob located at
+ * fdt to the buffer at buf of size bufsize.  The buffer may overlap
+ * with the existing device tree blob at fdt.  Therefore,
+ *     fdt_move(fdt, fdt, fdt_totalsize(fdt))
+ * should always succeed.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_move(const void *fdt, void *buf, int bufsize);
+
+/**********************************************************************/
+/* Read-only functions                                                */
+/**********************************************************************/
+
+/**
+ * fdt_string - retrieve a string from the strings block of a device tree
+ * @fdt: pointer to the device tree blob
+ * @stroffset: offset of the string within the strings block (native endian)
+ *
+ * fdt_string() retrieves a pointer to a single string from the
+ * strings block of the device tree blob at fdt.
+ *
+ * returns:
+ *     a pointer to the string, on success
+ *     NULL, if stroffset is out of bounds
+ */
+const char *fdt_string(const void *fdt, int stroffset);
+
+/**
+ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
+ * @fdt: pointer to the device tree blob
+ *
+ * Returns the number of entries in the device tree blob's memory
+ * reservation map.  This does not include the terminating 0,0 entry
+ * or any other (0,0) entries reserved for expansion.
+ *
+ * returns:
+ *     the number of entries
+ */
+int fdt_num_mem_rsv(const void *fdt);
+
+/**
+ * fdt_get_mem_rsv - retrieve one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: pointers to 64-bit variables
+ *
+ * On success, *address and *size will contain the address and size of
+ * the n-th reserve map entry from the device tree blob, in
+ * native-endian format.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
+
+/**
+ * fdt_subnode_offset_namelen - find a subnode based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_subnode_offset(), but only examine the first
+ * namelen characters of name for matching the subnode name.  This is
+ * useful for finding subnodes based on a portion of a larger string,
+ * such as a full path.
+ */
+int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
+			       const char *name, int namelen);
+/**
+ * fdt_subnode_offset - find a subnode of a given node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_subnode_offset() finds a subnode of the node at structure block
+ * offset parentoffset with the given name.  name may include a unit
+ * address, in which case fdt_subnode_offset() will find the subnode
+ * with that unit address, or the unit address may be omitted, in
+ * which case fdt_subnode_offset() will find an arbitrary subnode
+ * whose name excluding unit address matches the given name.
+ *
+ * returns:
+ *	structure block offset of the requested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_path_offset - find a tree node by its full path
+ * @fdt: pointer to the device tree blob
+ * @path: full path of the node to locate
+ *
+ * fdt_path_offset() finds a node of a given path in the device tree.
+ * Each path component may omit the unit address portion, but the
+ * results of this are undefined if any such path component is
+ * ambiguous (that is if there are multiple nodes at the relevant
+ * level matching the given component, differentiated only by unit
+ * address).
+ *
+ * returns:
+ *	structure block offset of the node with the requested path (>=0), on success
+ *	-FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
+ *	-FDT_ERR_NOTFOUND, if the requested node does not exist
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_path_offset(const void *fdt, const char *path);
+
+/**
+ * fdt_get_name - retrieve the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the starting node
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_name() retrieves the name (including unit address) of the
+ * device tree node at structure block offset nodeoffset.  If lenp is
+ * non-NULL, the length of this name is also returned, in the integer
+ * pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the node's name, on success
+ *		If lenp is non-NULL, *lenp contains the length of that name (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE, standard meanings
+ */
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
+
+/**
+ * fdt_first_property_offset - find the offset of a node's first property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ *
+ * fdt_first_property_offset() finds the first property of the node at
+ * the given structure block offset.
+ *
+ * returns:
+ *	structure block offset of the property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested node has no properties
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_first_property_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_next_property_offset - step through a node's properties
+ * @fdt: pointer to the device tree blob
+ * @offset: structure block offset of a property
+ *
+ * fdt_next_property_offset() finds the property immediately after the
+ * one at the given structure block offset.  This will be a property
+ * of the same node as the given property.
+ *
+ * returns:
+ *	structure block offset of the next property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the given property is the last in its node
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_next_property_offset(const void *fdt, int offset);
+
+/**
+ * fdt_get_property_by_offset - retrieve the property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @offset: offset of the property to retrieve
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property_by_offset() retrieves a pointer to the
+ * fdt_property structure within the device tree blob at the given
+ * offset.  If lenp is non-NULL, the length of the property value is
+ * also returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+						      int offset,
+						      int *lenp);
+
+/**
+ * fdt_get_property_namelen - find a property based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_get_property_namelen(), but only examine the first
+ * namelen characters of name for matching the property name.
+ */
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+						    int nodeoffset,
+						    const char *name,
+						    int namelen, int *lenp);
+
+/**
+ * fdt_get_property - find a given property in a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property() retrieves a pointer to the fdt_property
+ * structure within the device tree blob corresponding to the property
+ * named 'name' of the node at offset nodeoffset.  If lenp is
+ * non-NULL, the length of the property value is also returned, in the
+ * integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
+					    const char *name, int *lenp);
+static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
+						      const char *name,
+						      int *lenp)
+{
+	return (struct fdt_property *)(uintptr_t)
+		fdt_get_property(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_getprop_by_offset - retrieve the value of a property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @ffset: offset of the property to read
+ * @namep: pointer to a string variable (will be overwritten) or NULL
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop_by_offset() retrieves a pointer to the value of the
+ * property at structure block offset 'offset' (this will be a pointer
+ * to within the device blob itself, not a copy of the value).  If
+ * lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.  If namep is non-NULL,
+ * the property's namne will also be returned in the char * pointed to
+ * by namep (this will be a pointer to within the device tree's string
+ * block, not a new copy of the name).
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *		if namep is non-NULL *namep contiains a pointer to the property
+ *		name.
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+				  const char **namep, int *lenp);
+
+/**
+ * fdt_getprop_namelen - get property value based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_getprop(), but only examine the first namelen
+ * characters of name for matching the property name.
+ */
+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
+				const char *name, int namelen, int *lenp);
+
+/**
+ * fdt_getprop - retrieve the value of a given property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop() retrieves a pointer to the value of the property
+ * named 'name' of the node at offset nodeoffset (this will be a
+ * pointer to within the device blob itself, not a copy of the value).
+ * If lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp);
+static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
+				  const char *name, int *lenp)
+{
+	return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_get_phandle - retrieve the phandle of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the node
+ *
+ * fdt_get_phandle() retrieves the phandle of the device tree node at
+ * structure block offset nodeoffset.
+ *
+ * returns:
+ *	the phandle of the node at nodeoffset, on success (!= 0, != -1)
+ *	0, if the node has no phandle, or another error occurs
+ */
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_get_alias_namelen - get alias based on substring
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_get_alias(), but only examine the first namelen
+ * characters of name for matching the alias name.
+ */
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen);
+
+/**
+ * fdt_get_alias - retreive the path referenced by a given alias
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ *
+ * fdt_get_alias() retrieves the value of a given alias.  That is, the
+ * value of the property named 'name' in the node /aliases.
+ *
+ * returns:
+ *	a pointer to the expansion of the alias named 'name', of it exists
+ *	NULL, if the given alias or the /aliases node does not exist
+ */
+const char *fdt_get_alias(const void *fdt, const char *name);
+
+/**
+ * fdt_get_path - determine the full path of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose path to find
+ * @buf: character buffer to contain the returned path (will be overwritten)
+ * @buflen: size of the character buffer at buf
+ *
+ * fdt_get_path() computes the full path of the node at offset
+ * nodeoffset, and records that path in the buffer at buf.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	0, on success
+ *		buf contains the absolute path of the node at
+ *		nodeoffset, as a NUL-terminated string.
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
+ *		characters and will not fit in the given buffer.
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
+
+/**
+ * fdt_supernode_atdepth_offset - find a specific ancestor of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ * @supernodedepth: depth of the ancestor to find
+ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_supernode_atdepth_offset() finds an ancestor of the given node
+ * at a specific depth from the root (where the root itself has depth
+ * 0, its immediate subnodes depth 1 and so forth).  So
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
+ * will always return 0, the offset of the root node.  If the node at
+ * nodeoffset has depth D, then:
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
+ * will return nodeoffset itself.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+
+ *	structure block offset of the node at node offset's ancestor
+ *		of depth supernodedepth (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+*	-FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth);
+
+/**
+ * fdt_node_depth - find the depth of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_node_depth() finds the depth of a given node.  The root node
+ * has depth 0, its immediate subnodes depth 1 and so forth.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	depth of the node at nodeoffset (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_depth(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_parent_offset - find the parent of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_parent_offset() locates the parent node of a given node (that
+ * is, it finds the offset of the node which contains the node at
+ * nodeoffset as a subnode).
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset, *twice*.
+ *
+ * returns:
+ *	structure block offset of the parent of the node at nodeoffset
+ *		(>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_parent_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_node_offset_by_prop_value - find nodes with a given property value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @propname: property name to check
+ * @propval: property value to search for
+ * @proplen: length of the value in propval
+ *
+ * fdt_node_offset_by_prop_value() returns the offset of the first
+ * node after startoffset, which has a property named propname whose
+ * value is of length proplen and has value equal to propval; or if
+ * startoffset is -1, the very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
+ *					       propval, proplen);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
+ *						       propval, proplen);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen);
+
+/**
+ * fdt_node_offset_by_phandle - find the node with a given phandle
+ * @fdt: pointer to the device tree blob
+ * @phandle: phandle value
+ *
+ * fdt_node_offset_by_phandle() returns the offset of the node
+ * which has the given phandle value.  If there is more than one node
+ * in the tree with the given phandle (an invalid tree), results are
+ * undefined.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0), on success
+ *	-FDT_ERR_NOTFOUND, no node with that phandle exists
+ *	-FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
+
+/**
+ * fdt_node_check_compatible: check a node's compatible property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of a tree node
+ * @compatible: string to match against
+ *
+ *
+ * fdt_node_check_compatible() returns 0 if the given node contains a
+ * 'compatible' property with the given string as one of its elements,
+ * it returns non-zero otherwise, or on error.
+ *
+ * returns:
+ *	0, if the node has a 'compatible' property listing the given string
+ *	1, if the node has a 'compatible' property, but it does not list
+ *		the given string
+ *	-FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
+ *	-FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible);
+
+/**
+ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @compatible: 'compatible' string to match against
+ *
+ * fdt_node_offset_by_compatible() returns the offset of the first
+ * node after startoffset, which has a 'compatible' property which
+ * lists the given compatible string; or if startoffset is -1, the
+ * very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible);
+
+/**********************************************************************/
+/* Write-in-place functions                                           */
+/**********************************************************************/
+
+/**
+ * fdt_setprop_inplace - change a property's value, but not its size
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to replace the property value with
+ * @len: length of the property value
+ *
+ * fdt_setprop_inplace() replaces the value of a given property with
+ * the data in val, of length len.  This function cannot change the
+ * size of a property, and so will only work if len is equal to the
+ * current length of the property.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if len is not equal to the property's current length
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len);
+
+/**
+ * fdt_setprop_inplace_cell - change the value of a single-cell property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: cell (32-bit integer) value to replace the property with
+ *
+ * fdt_setprop_inplace_cell() replaces the value of a given property
+ * with the 32-bit integer cell value in val, converting val to
+ * big-endian if necessary.  This function cannot change the size of a
+ * property, and so will only work if the property already exists and
+ * has length 4.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if the property's length is not equal to 4
+  *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
+					   const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_nop_property - replace a property with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_nop_property() will replace a given property's representation
+ * in the blob with FDT_NOP tags, effectively removing it from the
+ * tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the property, and will not alter or move any other part of the
+ * tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_nop_node - replace a node (subtree) with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_nop_node() will replace a given node's representation in the
+ * blob, including all its subnodes, if any, with FDT_NOP tags,
+ * effectively removing it from the tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the node and its properties and subnodes, and will not alter or
+ * move any other part of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Sequential write functions                                         */
+/**********************************************************************/
+
+int fdt_create(void *buf, int bufsize);
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
+int fdt_finish_reservemap(void *fdt);
+int fdt_begin_node(void *fdt, const char *name);
+int fdt_property(void *fdt, const char *name, const void *val, int len);
+static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_property(fdt, name, &val, sizeof(val));
+}
+#define fdt_property_string(fdt, name, str) \
+	fdt_property(fdt, name, str, strlen(str)+1)
+int fdt_end_node(void *fdt);
+int fdt_finish(void *fdt);
+
+/**********************************************************************/
+/* Read-write functions                                               */
+/**********************************************************************/
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize);
+int fdt_pack(void *fdt);
+
+/**
+ * fdt_add_mem_rsv - add one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: 64-bit values (native endian)
+ *
+ * Adds a reserve map entry to the given blob reserving a region at
+ * address address of length size.
+ *
+ * This function will insert data into the reserve map and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new reservation entry
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
+
+/**
+ * fdt_del_mem_rsv - remove a memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @n: entry to remove
+ *
+ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
+ * the blob.
+ *
+ * This function will delete data from the reservation table and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
+ *		are less than n+1 reserve map entries)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_mem_rsv(void *fdt, int n);
+
+/**
+ * fdt_set_name - change the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ * @name: name to give the node
+ *
+ * fdt_set_name() replaces the name (including unit address, if any)
+ * of the given node with the given string.  NOTE: this function can't
+ * efficiently check if the new name is unique amongst the given
+ * node's siblings; results are undefined if this function is invoked
+ * with a name equal to one of the given node's siblings.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob
+ *		to contain the new name
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_set_name(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_setprop - create or change a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to set the property value to
+ * @len: length of the property value
+ *
+ * fdt_setprop() sets the value of the named property in the given
+ * node to the given value and length, creating the property if it
+ * does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len);
+
+/**
+ * fdt_setprop_cell - set a property to a single cell value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_cell() sets the value of the named property in the
+ * given node to the given cell value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
+				   uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_setprop_string - set a property to a string value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value for the property
+ *
+ * fdt_setprop_string() sets the value of the named property in the
+ * given node to the given string value (using the length of the
+ * string to determine the new length of the property), or creates a
+ * new property with that value if it does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+#define fdt_setprop_string(fdt, nodeoffset, name, str) \
+	fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
+/**
+ * fdt_delprop - delete a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_del_property() will delete the given property.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_add_subnode_namelen - creates a new node based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_add_subnode(), but use only the first namelen
+ * characters of name as the name of the new node.  This is useful for
+ * creating subnodes based on a portion of a larger string, such as a
+ * full path.
+ */
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen);
+
+/**
+ * fdt_add_subnode - creates a new node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_add_subnode() creates a new node as a subnode of the node at
+ * structure block offset parentoffset, with the given name (which
+ * should include the unit address, if any).
+ *
+ * This function will insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+
+ * returns:
+ *	structure block offset of the created nodeequested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *	-FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
+ *		the given name
+ *	-FDT_ERR_NOSPACE, if there is insufficient free space in the
+ *		blob to contain the new node
+ *	-FDT_ERR_NOSPACE
+ *	-FDT_ERR_BADLAYOUT
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_del_node - delete a node (subtree)
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_del_node() will remove the given node, including all its
+ * subnodes if any, from the blob.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_node(void *fdt, int nodeoffset);
+
+/**
+ * fdt_get_base_addr - find base address of a node from its name
+ * @fdt: pointer to the device tree blob
+ * @offset: offset of the node to parse the name of
+ * @base_addr: pointer to place the node address retrieved from the name
+ *
+ * Retrieve base address from the string name of a node formatted as
+ * <name>@<base addr>.
+ *
+ * Return 0 on success, -1 on any errror.
+ */
+int fdt_get_base_addr(const void *fdt, int offset, u64 *base_addr);
+
+/**********************************************************************/
+/* Debugging / informational functions                                */
+/**********************************************************************/
+
+const char *fdt_strerror(int errval);
+
+#endif /* _LIBFDT_H */
diff --git a/src/include/fdt/libfdt_env.h b/src/include/fdt/libfdt_env.h
new file mode 100644
index 0000000..755a5a6
--- /dev/null
+++ b/src/include/fdt/libfdt_env.h
@@ -0,0 +1,31 @@
+/*
+ * libfdt - Flat Device Tree manipulation (build/run environment adaptation)
+ * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ * Original version written by David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _LIBFDT_ENV_H
+#define _LIBFDT_ENV_H
+
+#include <arch/byteorder.h>
+
+#define fdt32_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_fdt32(x)		cpu_to_be32(x)
+#define fdt64_to_cpu(x)		be64_to_cpu(x)
+#define cpu_to_fdt64(x)		cpu_to_be64(x)
+
+#endif /* _LIBFDT_ENV_H */
diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h
index b0d3a93..4c5e703 100644
--- a/src/include/pc80/i8254.h
+++ b/src/include/pc80/i8254.h
@@ -58,4 +58,7 @@
 #define PPCB_SPKR       0x02    /* Bit 1 */
 #define PPCB_T2GATE     0x01    /* Bit 0 */
 
+#ifndef __ROMCC__
+void setup_i8254(void);
+#endif
 #endif
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 032e385..f51c371 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -104,6 +104,22 @@
 	outb(addr, RTC_BASE_PORT + offs + 0);
 	outb(val, RTC_BASE_PORT + offs + 1);
 }
+
+static inline u32 cmos_read32(u8 offset)
+{
+	u32 value = 0;
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		value |= cmos_read(offset + i) << (i << 3);
+	return value;
+}
+
+static inline void cmos_write32(u8 offset, u32 value)
+{
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		cmos_write((value >> (i << 3)) & 0xff, offset + i);
+}
 #endif
 
 #if !defined(__ROMCC__)
diff --git a/src/cpu/x86/mmx_disable.inc b/src/include/pc80/tpm.h
similarity index 64%
copy from src/cpu/x86/mmx_disable.inc
copy to src/include/pc80/tpm.h
index 1a4e70f..2eff15a 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/include/pc80/tpm.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,16 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef TPM_H_
+#define TPM_H_
 
+int tis_init(void);
+int tis_open(void);
+int tis_close(void);
+int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf,
+			size_t *recv_len);
+
+#endif /* TPM_H_ */
diff --git a/src/include/smbios.h b/src/include/smbios.h
new file mode 100644
index 0000000..1210f0f
--- /dev/null
+++ b/src/include/smbios.h
@@ -0,0 +1,226 @@
+#ifndef SMBIOS_H
+#define SMBIOS_H
+
+#include <types.h>
+
+unsigned long smbios_write_tables(unsigned long start);
+int smbios_add_string(char *start, const char *str);
+int smbios_string_table_len(char *start);
+
+#define BIOS_CHARACTERISTICS_PCI_SUPPORTED  (1 << 7)
+#define BIOS_CHARACTERISTICS_PC_CARD  (1 << 8)
+#define BIOS_CHARACTERISTICS_PNP  (1 << 9)
+#define BIOS_CHARACTERISTICS_APM (1 << 10)
+#define BIOS_CHARACTERISTICS_UPGRADEABLE      (1 << 11)
+#define BIOS_CHARACTERISTICS_SHADOW           (1 << 12)
+#define BIOS_CHARACTERISTICS_BOOT_FROM_CD     (1 << 15)
+#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT  (1 << 16)
+#define BIOS_CHARACTERISTICS_BIOS_SOCKETED    (1 << 17)
+
+#define BIOS_EXT1_CHARACTERISTICS_ACPI    (1 << 0)
+#define BIOS_EXT2_CHARACTERISTICS_TARGET  (1 << 2)
+
+#define SMBIOS_STATE_SAFE 3
+typedef enum {
+	SMBIOS_BIOS_INFORMATION=0,
+	SMBIOS_SYSTEM_INFORMATION=1,
+	SMBIOS_SYSTEM_ENCLOSURE=3,
+	SMBIOS_PROCESSOR_INFORMATION=4,
+	SMBIOS_CACHE_INFORMATION=7,
+	SMBIOS_SYSTEM_SLOTS=9,
+	SMBIOS_PHYS_MEMORY_ARRAY=16,
+	SMBIOS_MEMORY_DEVICE=17,
+	SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19,
+	SMBIOS_SYSTEM_BOOT_INFORMATION=32,
+	SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION=41,
+	SMBIOS_END_OF_TABLE=127,
+} smbios_struct_type_t;
+
+struct smbios_entry {
+	u8 anchor[4];
+	u8 checksum;
+	u8 length;
+	u8 major_version;
+	u8 minor_version;
+	u16 max_struct_size;
+	u8 entry_point_rev;
+	u8 formwatted_area[5];
+	u8 intermediate_anchor_string[5];
+	u8 intermediate_checksum;
+	u16 struct_table_length;
+	u32 struct_table_address;
+	u16 struct_count;
+	u8 smbios_bcd_revision;
+} __attribute__((packed));
+
+struct smbios_type0 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 vendor;
+	u8 bios_version;
+	u16 bios_start_segment;
+	u8 bios_release_date;
+	u8 bios_rom_size;
+	u64 bios_characteristics;
+	u8 bios_characteristics_ext1;
+	u8 bios_characteristics_ext2;
+	u8 system_bios_major_release;
+	u8 system_bios_minor_release;
+	u8 ec_major_release;
+	u8 ec_minor_release;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type1 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 manufacturer;
+	u8 product_name;
+	u8 version;
+	u8 serial_number;
+	u8 uuid[16];
+	u8 wakeup_type;
+	u8 sku;
+	u8 family;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type3 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 manufacturer;
+	u8 _type;
+	u8 version;
+	u8 serial_number;
+	u8 asset_tag_number;
+	u8 bootup_state;
+	u8 power_supply_state;
+	u8 thermal_state;
+	u8 security_status;
+	u32 oem_defined;
+	u8 height;
+	u8 number_of_power_cords;
+	u8 element_count;
+	u8 element_record_length;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type4 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 socket_designation;
+	u8 processor_type;
+	u8 processor_family;
+	u8 processor_manufacturer;
+	u32 processor_id[2];
+	u8 processor_version;
+	u8 voltage;
+	u16 external_clock;
+	u16 max_speed;
+	u16 current_speed;
+	u8 status;
+	u8 processor_upgrade;
+	u16 l1_cache_handle;
+	u16 l2_cache_handle;
+	u16 l3_cache_handle;
+	u8 serial_number;
+	u8 asset_tag;
+	u8 part_number;
+	u8 core_count;
+	u8 core_enabled;
+	u8 thread_count;
+	u16 processor_characteristics;
+	u16 processor_family2;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type16 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 location;
+	u8 use;
+	u8 memory_error_correction;
+	u32 maximum_capacity;
+	u16 memory_error_information_handle;
+	u16 number_of_memory_devices;
+	u64 extended_maximum_capacity;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type17 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u16 phys_memory_array_handle;
+	u16 memory_error_information_handle;
+	u16 total_width;
+	u16 data_width;
+	u16 size;
+	u8 form_factor;
+	u8 device_set;
+	u8 device_locator;
+	u8 bank_locator;
+	u8 memory_type;
+	u16 type_detail;
+	u16 speed;
+	u8 manufacturer;
+	u8 serial_number;
+	u8 asset_tag;
+	u8 part_number;
+	u8 attributes;
+	u16 extended_size;
+	u16 clock_speed;
+
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type32 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 reserved[6];
+	u8 boot_status;
+	u8 eos[2];
+} __attribute__((packed));
+
+typedef enum {
+	SMBIOS_DEVICE_TYPE_OTHER = 0x01,
+	SMBIOS_DEVICE_TYPE_UNKNOWN,
+	SMBIOS_DEVICE_TYPE_VIDEO,
+	SMBIOS_DEVICE_TYPE_SCSI,
+	SMBIOS_DEVICE_TYPE_ETHERNET,
+	SMBIOS_DEVICE_TYPE_TOKEN_RING,
+	SMBIOS_DEVICE_TYPE_SOUND,
+	SMBIOS_DEVICE_TYPE_PATA,
+	SMBIOS_DEVICE_TYPE_SATA,
+	SMBIOS_DEVICE_TYPE_SAS,
+} smbios_onboard_device_type;
+
+struct smbios_type41 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 reference_designation;
+	u8 device_type: 7;
+	u8 device_status: 1;
+	u8 device_type_instance;
+	u16 segment_group_number;
+	u8 bus_number;
+	u8 function_number: 3;
+	u8 device_number: 5;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type127 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 eos[2];
+} __attribute__((packed));
+
+#endif
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 45420d7..5465c14 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -5,7 +5,7 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1)
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
 #define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 
 #define MIN(a,b) ((a) < (b) ? (a) : (b))
diff --git a/src/include/string.h b/src/include/string.h
index 2168947..708961b 100644
--- a/src/include/string.h
+++ b/src/include/string.h
@@ -8,6 +8,7 @@
 void *memmove(void *dest, const void *src, size_t n);
 void *memset(void *s, int c, size_t n);
 int memcmp(const void *s1, const void *s2, size_t n);
+void *memchr(const void *s, int c, size_t n);
 #if !defined(__PRE_RAM__)
 int sprintf(char * buf, const char *fmt, ...);
 #endif
diff --git a/src/include/swab.h b/src/include/swab.h
index 3a16686..c5e4370 100644
--- a/src/include/swab.h
+++ b/src/include/swab.h
@@ -30,4 +30,15 @@
 		(((unsigned int)(x) & (unsigned int)0x00ff0000UL) >>  8) | \
 		(((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
 
+#define swab64(x) \
+	((uint64_t)( \
+		(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \
+		(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \
+		(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \
+		(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) | \
+		(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) | \
+		(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
+		(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
+		(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) ))
+
 #endif /* _SWAB_H */
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
new file mode 100644
index 0000000..0bb323c
--- /dev/null
+++ b/src/include/timestamp.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef __TIMESTAMP_H__
+#define __TIMESTAMP_H__
+
+#include <cpu/x86/tsc.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint32_t	max_entries;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+};
+
+#if CONFIG_COLLECT_TIMESTAMPS
+void timestamp_init(tsc_t base);
+void timestamp_add(enum timestamp_id id, tsc_t ts_time);
+void timestamp_add_now(enum timestamp_id id);
+#else
+#define timestamp_init(base)
+#define timestamp_add(id, time)
+#define timestamp_add_now(id)
+#endif
+
+#endif
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index bbf2d8c..14b28c8 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -20,26 +20,7 @@
 #ifndef UART8250_H
 #define UART8250_H
 
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE 0x3f8
-#endif
-
-#ifndef CONFIG_TTYS0_BAUD
-#define CONFIG_TTYS0_BAUD 115200
-#endif
-#if ((115200%CONFIG_TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-
-/* Line Control Settings */
-#ifndef CONFIG_TTYS0_LCS
-/* Set 8bit, 1 stop bit, no parity */
-#define CONFIG_TTYS0_LCS	0x3
-#endif
-
-#define UART_LCS	CONFIG_TTYS0_LCS
-
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
 
 /* Data */
 #define UART_RBR 0x00
@@ -126,6 +107,12 @@
 #define UART_SCR 0x07
 #define UART_SPR 0x07
 
+#if ((115200 % CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttyS0 baud rate
+#endif
+
+/* Line Control Settings */
+#define UART_LCS	CONFIG_TTYS0_LCS
 
 #ifndef __ROMCC__
 unsigned char uart8250_rx_byte(unsigned base_port);
@@ -144,10 +131,19 @@
 void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
 void uart8250_mem_init(unsigned base_port, unsigned divisor);
 u32 uart_mem_init(void);
+void uartmem_init(void);
+u32 uartmem_getbaseaddr(void);
 
+#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \
+	CONFIG_CONSOLE_SERIAL8250MEM
 /* and special init for OXPCIe based cards */
-void oxford_init(void);
+extern int oxford_oxpcie_present;
 
+void oxford_init(void);
 #endif
 
+#endif /* __ROMCC__ */
+
+#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
+
 #endif /* UART8250_H */
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 281ccde..c912f56 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -39,6 +39,7 @@
 unsigned get_ehci_debug(void);
 void set_debug_port(unsigned port);
 int early_usbdebug_init(void);
+void enable_usbdebug(unsigned int port); /* Implemented by southbridge */
 void usbdebug_tx_byte(unsigned char data);
 
 #endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 3817161..ba83fda 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -1,7 +1,12 @@
 
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 romstage-y += memset.c
+endif
+romstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
+endif
 romstage-y += memcmp.c
 romstage-y += cbfs.c
 romstage-y += lzma.c
@@ -10,12 +15,20 @@
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
-romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+romstage-y += compute_ip_checksum.c
+romstage-y += memmove.c
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 ramstage-y += memset.c
+endif
+ramstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c
+endif
 ramstage-y += memcmp.c
 ramstage-y += memmove.c
 ramstage-y += malloc.c
@@ -31,13 +44,28 @@
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 smm-y += memcpy.c
+endif
 smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+smm-$(CONFIG_USBDEBUG) += usbdebug.c
 
 $(obj)/lib/version.ramstage.o : $(obj)/build.h
+
+OPTION_TABLE_H:=
+ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
+OPTION_TABLE_H:=$(obj)/option_table.h
+endif
+
+$(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H)
+$(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H)
+
+subdirs-$(CONFIG_ADD_FDT) += libfdt
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 690033e..9573739 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -24,6 +24,11 @@
 #include <lib.h>
 #include <arch/byteorder.h>
 
+#if CONFIG_DEBUG_CBFS
+#define debug(x...) printk(BIOS_SPEW, x)
+#else
+#define debug(x...)
+#endif
 
 /**
  * Decompression wrapper for CBFS
@@ -48,7 +53,7 @@
 		return 0;
 
 	default:
-		printk(BIOS_INFO,  "CBFS:  Unknown compression type %d\n", algo);
+		printk(BIOS_INFO,  "CBFS: Unknown compression type %d\n", algo);
 		return -1;
 	}
 }
@@ -58,57 +63,98 @@
 	return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0;
 }
 
-static struct cbfs_header *cbfs_master_header(void)
+struct cbfs_header *get_cbfs_header(void)
 {
 	struct cbfs_header *header;
 
 	void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR);
-	printk(BIOS_SPEW, "Check CBFS header at %p\n", ptr);
+	debug("CBFS: Check master header at %p\n", ptr);
 	header = (struct cbfs_header *) ptr;
 
-	printk(BIOS_SPEW, "magic is %08x\n", ntohl(header->magic));
+	debug("magic is %08x\n", ntohl(header->magic));
 	if (ntohl(header->magic) != CBFS_HEADER_MAGIC) {
 		printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n");
 		if (header->magic == 0xffffffff) {
-			printk(BIOS_ERR, "Maybe the ROM isn't entirely mapped yet?\n"
-				"See (and report to) http://www.coreboot.org/Infrastructure_Projects#CBFS\n");
+			printk(BIOS_ERR, "Maybe the ROM isn't entirely mapped "
+				"yet?\nSee (and report to) http://www.coreboot"
+				".org/Infrastructure_Projects#CBFS\n");
 		}
 		return NULL;
 	}
 
-	printk(BIOS_SPEW, "Found CBFS header at %p\n", ptr);
+	debug("CBFS: Found master header at %p\n", ptr);
 	return header;
 }
 
+u32 get_cbfs_size(void)
+{
+	struct cbfs_header *header = get_cbfs_header();
+
+	if (!header)
+		return 0;
+
+	return ntohl(header->romsize);
+}
+
+void *get_cbfs_base(void)
+{
+	u32 cbfs_size = get_cbfs_size();
+
+	if (cbfs_size)
+		return (void *)(unsigned long)(0x100000000ULL - cbfs_size);
+
+	return NULL;
+}
+
 struct cbfs_file *cbfs_find(const char *name)
 {
-	struct cbfs_header *header = cbfs_master_header();
+	struct cbfs_header *header = get_cbfs_header();
 	unsigned long offset;
+	u32 cbfs_size = get_cbfs_size();
+	u32 cbfs_base = (u32)get_cbfs_base();
 
 	if (header == NULL)
 		return NULL;
-	offset = 0 - ntohl(header->romsize) + ntohl(header->offset);
 
-	int align= ntohl(header->align);
+	offset = (unsigned long)(0x100000000ULL - ntohl(header->romsize) +
+			ntohl(header->offset));
 
+	if ((offset < cbfs_base) || (offset > (cbfs_base + cbfs_size - 1)))
+		printk(BIOS_WARNING, "WARNING: CBFS seems to live outside "
+			"of ROM\n");
+
+	int align = ntohl(header->align);
+
+	printk(BIOS_SPEW, "CBFS: Looking for '%s'\n", name);
 	while(1) {
 		struct cbfs_file *file = (struct cbfs_file *) offset;
 		if (!cbfs_check_magic(file)) return NULL;
-		printk(BIOS_SPEW, "Check %s\n", CBFS_NAME(file));
-		if (!strcmp(CBFS_NAME(file), name))
+		debug("CBFS: Check %s\n", CBFS_NAME(file));
+		if (!strcmp(CBFS_NAME(file), name)) {
+			printk(BIOS_SPEW, "CBFS: found.\n");
 			return file;
+		}
 
 		int flen = ntohl(file->len);
 		int foffset = ntohl(file->offset);
-		printk(BIOS_SPEW, "CBFS: follow chain: %p + %x + %x + align -> ", (void *)offset, foffset, flen);
+		debug("CBFS: follow chain: %p + %x + %x + align -> ",
+						(void *)offset, foffset, flen);
 
 		unsigned long oldoffset = offset;
 		offset = ALIGN(offset + foffset + flen, align);
-		printk(BIOS_SPEW, "%p\n", (void *)offset);
-		if (offset <= oldoffset) return NULL;
+		debug("%p\n", (void *)offset);
 
-		if (offset < 0xFFFFFFFF - ntohl(header->romsize))
+		/* The offset above will overflow when we hit 4GB,
+		 * at which point CBFS is done and did not find a
+		 * file.
+		 */
+		if (offset <= oldoffset)
 			return NULL;
+
+		if (offset < 0xFFFFFFFF - ntohl(header->romsize)) {
+			printk(BIOS_SPEW, "CBFS: not found.\n");
+			return NULL;
+		}
 	}
 }
 
@@ -117,13 +163,13 @@
 	struct cbfs_file *file = cbfs_find(name);
 
 	if (file == NULL) {
-		printk(BIOS_INFO,  "CBFS:  Could not find file %s\n",
+		printk(BIOS_INFO,  "CBFS: Could not find file %s\n",
 		       name);
 		return NULL;
 	}
 
 	if (ntohl(file->type) != type) {
-		printk(BIOS_INFO,  "CBFS:  File %s is of type %x instead of"
+		printk(BIOS_INFO,  "CBFS: File %s is of type %x instead of "
 		       "type %x\n", name, file->type, type);
 
 		return NULL;
@@ -134,25 +180,25 @@
 
 static inline int tohex4(unsigned int c)
 {
-	return (c<=9)?(c+'0'):(c-10+'a');
+	return (c <= 9) ? (c + '0') : (c - 10 + 'a');
 }
 
-static void tohex16(unsigned int val, char* dest)
+static void tohex16(unsigned int val, char *dest)
 {
-	dest[0]=tohex4(val>>12);
-	dest[1]=tohex4((val>>8) & 0xf);
-	dest[2]=tohex4((val>>4) & 0xf);
-	dest[3]=tohex4(val & 0xf);
+	dest[0] = tohex4(val >> 12);
+	dest[1] = tohex4((val >> 8) & 0xf);
+	dest[2] = tohex4((val >> 4) & 0xf);
+	dest[3] = tohex4(val & 0xf);
 }
 
-void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest)
+void *cbfs_load_optionrom(u16 vendor, u16 device, void *dest)
 {
-	char name[17]="pciXXXX,XXXX.rom";
+	char name[17] = "pciXXXX,XXXX.rom";
 	struct cbfs_optionrom *orom;
 	u8 *src;
 
-	tohex16(vendor, name+3);
-	tohex16(device, name+8);
+	tohex16(vendor, name + 3);
+	tohex16(device, name + 8);
 
 	orom = (struct cbfs_optionrom *)
 		cbfs_find_file(name, CBFS_TYPE_OPTIONROM);
@@ -193,10 +239,10 @@
 	if (stage == NULL)
 		return (void *) -1;
 
-	printk(BIOS_INFO, "Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n",
-			name,
-			(u32) stage->load, stage->memlen,
+	printk(BIOS_INFO, "CBFS: loading stage %s @ 0x%x (%d bytes), entry "
+			"@ 0x%llx\n", name, (u32) stage->load, stage->memlen,
 			stage->entry);
+
 	memset((void *) (u32) stage->load, 0, stage->memlen);
 
 	if (cbfs_decompress(stage->compression,
@@ -206,7 +252,7 @@
 			     stage->len))
 		return (void *) -1;
 
-	printk(BIOS_DEBUG, "Stage: done loading.\n");
+	printk(BIOS_DEBUG, "CBFS: stage loaded.\n");
 
 	entry = stage->entry;
 	// entry = ntohl((u32) stage->entry);
@@ -223,13 +269,13 @@
 		return 1;
 
 	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
-		printk(BIOS_INFO,  "CBFS:  Unable to run %s:  Compressed file"
+		printk(BIOS_INFO, "CBFS: Unable to run %s:  Compressed file"
 		       "Not supported for in-place execution\n", name);
 		return 1;
 	}
 
 	/* FIXME: This isn't right */
-	printk(BIOS_INFO,  "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
+	printk(BIOS_INFO, "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
 	return run_address((void *) ntohl((u32) stage->entry));
 }
 
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 5417ab8..8bc35d7 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -21,6 +21,9 @@
 #include <string.h>
 #include <cbmem.h>
 #include <console/console.h>
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+#include <arch/acpi.h>
+#endif
 
 // The CBMEM TOC reserves 512 bytes to keep
 // the other entries somewhat aligned.
@@ -118,6 +121,22 @@
 {
 	struct cbmem_entry *cbmem_toc;
 	int i;
+	void *p;
+
+	/*
+	 * This could be a restart, check if the section is there already. It
+	 * is remotely possible that the dram contents persisted over the
+	 * bootloader upgrade AND the same section now needs more room, but
+	 * this is quite a remote possibility and it is ignored here.
+	 */
+	p = cbmem_find(id);
+	if (p) {
+		printk(BIOS_NOTICE,
+		       "CBMEM section %x: using existing location at %p.\n",
+		       id, p);
+		return p;
+	}
+
 	cbmem_toc = get_cbmem_toc();
 
 	if (cbmem_toc == NULL) {
@@ -183,28 +202,33 @@
 	return (void *)NULL;
 }
 
-#ifndef __PRE_RAM__
-#if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
+#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
+/* Returns True if it was not intialized before. */
+int cbmem_initialize(void)
+{
+	int rv = 0;
+
+#ifdef __PRE_RAM__
+	extern unsigned long get_top_of_ram(void);
+	uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+	uint64_t high_tables_size = HIGH_MEMORY_SIZE;
 #endif
 
-void cbmem_initialize(void)
-{
-#if CONFIG_HAVE_ACPI_RESUME
-	if (acpi_slp_type == 3) {
-		if (!cbmem_reinit(high_tables_base)) {
-			/* Something went wrong, our high memory area got wiped */
+	/* We expect the romstage to always initialize it. */
+	if (!cbmem_reinit(high_tables_base)) {
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+		if (acpi_slp_type == 3)
 			acpi_slp_type = 0;
-			cbmem_init(high_tables_base, high_tables_size);
-		}
-	} else {
-		cbmem_init(high_tables_base, high_tables_size);
-	}
-#else
-	cbmem_init(high_tables_base, high_tables_size);
 #endif
+		cbmem_init(high_tables_base, high_tables_size);
+		rv = 1;
+	}
+#ifndef __PRE_RAM__
 	cbmem_arch_init();
+#endif
+	return rv;
 }
+#endif
 
 #ifndef __PRE_RAM__
 void cbmem_list(void)
@@ -229,6 +253,10 @@
 		case CBMEM_ID_PIRQ:	 printk(BIOS_DEBUG, "IRQ TABLE  "); break;
 		case CBMEM_ID_MPTABLE:	 printk(BIOS_DEBUG, "SMP TABLE  "); break;
 		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
+		case CBMEM_ID_SMBIOS:    printk(BIOS_DEBUG, "SMBIOS     "); break;
+		case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break;
+		case CBMEM_ID_MRCDATA:   printk(BIOS_DEBUG, "MRC DATA   "); break;
+		case CBMEM_ID_CONSOLE:   printk(BIOS_DEBUG, "CONSOLE    "); break;
 		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
 		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);
@@ -237,5 +265,4 @@
 }
 #endif
 
-#endif
 
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
new file mode 100644
index 0000000..431ea1f
--- /dev/null
+++ b/src/lib/cbmem_console.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/x86/car.h>
+#include <string.h>
+
+/*
+ * Structure describing console buffer. It is overlaid on a flat memory area,
+ * whith buffer_body covering the extent of the memory. Once the buffer is
+ * full, the cursor keeps going but the data is dropped on the floor. This
+ * allows to tell how much data was lost in the process.
+ */
+struct cbmem_console {
+	u32 buffer_size;
+	u32 buffer_cursor;
+	u8  buffer_body[0];
+}  __attribute__ ((__packed__));
+
+#ifdef __PRE_RAM__
+/*
+ * While running from ROM, before DRAM is initialized, some area in cache as
+ * ram space is used for the console buffer storage. The size and location of
+ * the area are defined in the config.
+ */
+
+static struct cbmem_console car_cbmem_console CAR_CBMEM;
+#define cbmem_console_p (&car_cbmem_console)
+
+/*
+ * Once DRAM is initialized and the cache as ram mode is disabled, while still
+ * running from ROM, the console buffer in the cache as RAM area becomes
+ * unavailable.
+ *
+ * By this time the console log buffer is already available in
+ * CBMEM. The location at 0x600 is used as the redirect pointer allowing to
+ * find out where the actual console log buffer is.
+ */
+#define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600))
+#else
+
+/*
+ * When running from RAM, a lot of console output is generated before CBMEM is
+ * reinitialized. This static buffer is used to store that output temporarily,
+ * to be concatenated with the CBMEM console buffer contents accumulated
+ * during the ROM stage, once CBMEM becomes avaiklable at RAM stage.
+ */
+static u8 static_console[40000];
+static struct cbmem_console *cbmem_console_p;
+#endif
+
+void cbmemc_init(void)
+{
+#ifdef __PRE_RAM__
+	cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+#else
+	/*
+	 * Initializing before CBMEM is available, use static buffer to store
+	 * the log.
+	 */
+	cbmem_console_p = (struct cbmem_console *) static_console;
+	cbmem_console_p->buffer_size = sizeof(static_console) -
+		sizeof(struct cbmem_console);
+#endif
+	cbmem_console_p->buffer_cursor = 0;
+}
+
+void cbmemc_tx_byte(unsigned char data)
+{
+	struct cbmem_console *cbm_cons_p = cbmem_console_p;
+	u32 cursor;
+#ifdef __PRE_RAM__
+	/*
+	 * This check allows to tell if the cache as RAM mode has been exited
+	 * or not. If it has been exited, the real memory is being used
+	 * (resulting in the variable on the stack located below
+	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
+	 * actual console buffer is.
+	 */
+	if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console)
+		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
+#endif
+	if (!cbm_cons_p)
+		return;
+
+	cursor = cbm_cons_p->buffer_cursor++;
+	if (cursor < cbm_cons_p->buffer_size)
+		cbm_cons_p->buffer_body[cursor] = data;
+}
+
+/*
+ * Copy the current console buffer (either from the cache as RAM area, or from
+ * the static buffer, pointed at by cbmem_console_p) into the CBMEM console
+ * buffer space (pointed at by new_cons_p), concatenating the copied data with
+ * the CBMEM console buffer contents.
+ *
+ * If there is overflow - add to the destination area a string, reporting the
+ * overflow and the number of dropped charactes.
+ */
+static void copy_console_buffer(struct cbmem_console *new_cons_p)
+{
+	u32 copy_size;
+	u32 cursor = new_cons_p->buffer_cursor;
+	int overflow = cbmem_console_p->buffer_cursor >
+		cbmem_console_p->buffer_size;
+
+	copy_size = overflow ?
+		cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor;
+
+	memcpy(new_cons_p->buffer_body + cursor,
+	       cbmem_console_p->buffer_body,
+	       copy_size);
+
+	cursor += copy_size;
+
+	if (overflow) {
+		const char loss_str1[] = "\n\n*** Log truncated, ";
+		const char loss_str2[] = " characters dropped. ***\n\n";
+		u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size;
+
+		/*
+		 * When running from ROM sprintf is not available, a simple
+		 * itoa implementation is used instead.
+		 */
+		int got_first_digit = 0;
+
+		/* Way more than possible number of dropped characters. */
+		u32 mult = 100000;
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1);
+		cursor += sizeof(loss_str1) - 1;
+
+		while (mult) {
+			int digit = dropped_chars / mult;
+			if (got_first_digit || digit) {
+				new_cons_p->buffer_body[cursor++] = digit + '0';
+				dropped_chars %= mult;
+				/* Excessive, but keeps it simple */
+				got_first_digit = 1;
+			}
+			mult /= 10;
+		}
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2);
+		cursor += sizeof(loss_str2) - 1;
+	}
+	new_cons_p->buffer_cursor = cursor;
+}
+
+void cbmemc_reinit(void)
+{
+	struct cbmem_console *cbm_cons_p;
+
+#ifdef __PRE_RAM__
+	cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE,
+			       CONFIG_CONSOLE_CBMEM_BUFFER_SIZE);
+	if (!cbm_cons_p) {
+		CBMEM_CONSOLE_REDIRECT = NULL;
+		return;
+	}
+
+	cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+
+	cbm_cons_p->buffer_cursor = 0;
+
+	copy_console_buffer(cbm_cons_p);
+
+	CBMEM_CONSOLE_REDIRECT = cbm_cons_p;
+#else
+	cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE);
+
+	if (!cbm_cons_p)
+		return;
+
+	copy_console_buffer(cbm_cons_p);
+
+	cbmem_console_p = cbm_cons_p;
+#endif
+}
diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index a8fe377..b5ec6c3 100644
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -28,7 +28,7 @@
 
 void boot_successful(void)
 {
-#if CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
 	void vbe_textmode_console(void);
 
 	vbe_textmode_console();
diff --git a/src/lib/libfdt/Makefile b/src/lib/libfdt/Makefile
new file mode 100644
index 0000000..c965577
--- /dev/null
+++ b/src/lib/libfdt/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)libfdt.o
+
+SOBJS	=
+
+COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o
+
+COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
+COBJS-$(CONFIG_FIT) += $(COBJS-libfdt)
+
+
+COBJS	:= $(sort $(COBJS-y))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/src/lib/libfdt/Makefile.inc b/src/lib/libfdt/Makefile.inc
new file mode 100644
index 0000000..42e1736
--- /dev/null
+++ b/src/lib/libfdt/Makefile.inc
@@ -0,0 +1,10 @@
+ramstage-y += fdt.c
+ramstage-y += fdt_ro.c
+ramstage-y += fdt_rw.c
+ramstage-y += fdt_strerror.c
+ramstage-y += fdt_sw.c
+ramstage-y += fdt_wip.c
+
+romstage-y += fdt_ro.c
+romstage-y += fdt.c
+
diff --git a/src/lib/libfdt/README b/src/lib/libfdt/README
new file mode 100644
index 0000000..e059876
--- /dev/null
+++ b/src/lib/libfdt/README
@@ -0,0 +1,23 @@
+The libfdt functionality was written by David Gibson.  The original
+source came from the git repository:
+
+URL:		git://ozlabs.org/home/dgibson/git/libfdt.git
+
+author		David Gibson <dgibson@sneetch.(none)>
+		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
+committer	David Gibson <dgibson@sneetch.(none)>
+		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
+commit		857f54e79f74429af20c2b5ecc00ee98af6a3b8b
+tree		2f648f0f88225a51ded452968d28b4402df8ade0
+parent		07a12a08005f3b5cd9337900a6551e450c07b515
+
+To adapt for u-boot usage, only the applicable files were copied and
+imported into the u-boot git repository.
+Omitted:
+* GPL - u-boot comes with a copy of the GPL license
+* test subdirectory - not directly useful for u-boot
+
+After importing, other customizations were performed.  See the git log
+for details.
+
+Jerry Van Baren
diff --git a/src/lib/libfdt/fdt.c b/src/lib/libfdt/fdt.c
new file mode 100644
index 0000000..4157b21
--- /dev/null
+++ b/src/lib/libfdt/fdt.c
@@ -0,0 +1,226 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+int fdt_check_header(const void *fdt)
+{
+	if (fdt_magic(fdt) == FDT_MAGIC) {
+		/* Complete tree */
+		if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+		if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+	} else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
+		/* Unfinished sequential-write blob */
+		if (fdt_size_dt_struct(fdt) == 0)
+			return -FDT_ERR_BADSTATE;
+	} else {
+		return -FDT_ERR_BADMAGIC;
+	}
+
+	return 0;
+}
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
+{
+	const char *p;
+
+	if (fdt_version(fdt) >= 0x11)
+		if (((offset + len) < offset)
+		    || ((offset + len) > fdt_size_dt_struct(fdt)))
+			return NULL;
+
+	p = _fdt_offset_ptr(fdt, offset);
+
+	if (p + len < p)
+		return NULL;
+	return p;
+}
+
+uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
+{
+	const uint32_t *tagp, *lenp;
+	uint32_t tag;
+	int offset = startoffset;
+	const char *p;
+
+	*nextoffset = -FDT_ERR_TRUNCATED;
+	tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
+	if (!tagp)
+		return FDT_END; /* premature end */
+	tag = fdt32_to_cpu(*tagp);
+	offset += FDT_TAGSIZE;
+
+	*nextoffset = -FDT_ERR_BADSTRUCTURE;
+	switch (tag) {
+	case FDT_BEGIN_NODE:
+		/* skip name */
+		do {
+			p = fdt_offset_ptr(fdt, offset++, 1);
+		} while (p && (*p != '\0'));
+		if (!p)
+			return FDT_END; /* premature end */
+		break;
+
+	case FDT_PROP:
+		lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
+		if (!lenp)
+			return FDT_END; /* premature end */
+		/* skip-name offset, length and value */
+		offset += sizeof(struct fdt_property) - FDT_TAGSIZE
+			+ fdt32_to_cpu(*lenp);
+		break;
+
+	case FDT_END:
+	case FDT_END_NODE:
+	case FDT_NOP:
+		break;
+
+	default:
+		return FDT_END;
+	}
+
+	if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset))
+		return FDT_END; /* premature end */
+
+	*nextoffset = FDT_TAGALIGN(offset);
+	return tag;
+}
+
+int _fdt_check_node_offset(const void *fdt, int offset)
+{
+	if ((offset < 0) || (offset % FDT_TAGSIZE)
+	    || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
+		return -FDT_ERR_BADOFFSET;
+
+	return offset;
+}
+
+int _fdt_check_prop_offset(const void *fdt, int offset)
+{
+	if ((offset < 0) || (offset % FDT_TAGSIZE)
+	    || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP))
+		return -FDT_ERR_BADOFFSET;
+
+	return offset;
+}
+
+int fdt_next_node(const void *fdt, int offset, int *depth)
+{
+	int nextoffset = 0;
+	uint32_t tag;
+
+	if (offset >= 0)
+		if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0)
+			return nextoffset;
+
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_PROP:
+		case FDT_NOP:
+			break;
+
+		case FDT_BEGIN_NODE:
+			if (depth)
+				(*depth)++;
+			break;
+
+		case FDT_END_NODE:
+			if (depth && ((--(*depth)) < 0))
+				return nextoffset;
+			break;
+
+		case FDT_END:
+			if ((nextoffset >= 0)
+			    || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth))
+				return -FDT_ERR_NOTFOUND;
+			else
+				return nextoffset;
+		}
+	} while (tag != FDT_BEGIN_NODE);
+
+	return offset;
+}
+
+const char *_fdt_find_string(const char *strtab, int tabsize, const char *s)
+{
+	int len = strlen(s) + 1;
+	const char *last = strtab + tabsize - len;
+	const char *p;
+
+	for (p = strtab; p <= last; p++)
+		if (memcmp(p, s, len) == 0)
+			return p;
+	return NULL;
+}
+
+int fdt_move(const void *fdt, void *buf, int bufsize)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if (fdt_totalsize(fdt) > bufsize)
+		return -FDT_ERR_NOSPACE;
+
+	memmove(buf, fdt, fdt_totalsize(fdt));
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_ro.c b/src/lib/libfdt/fdt_ro.c
new file mode 100644
index 0000000..bcdc77d
--- /dev/null
+++ b/src/lib/libfdt/fdt_ro.c
@@ -0,0 +1,619 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+static int _fdt_nodename_eq(const void *fdt, int offset,
+			    const char *s, int len)
+{
+	const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1);
+
+	if (! p)
+		/* short match */
+		return 0;
+
+	if (memcmp(p, s, len) != 0)
+		return 0;
+
+	if (p[len] == '\0')
+		return 1;
+	else if (!memchr(s, '@', len) && (p[len] == '@'))
+		return 1;
+	else
+		return 0;
+}
+
+const char *fdt_string(const void *fdt, int stroffset)
+{
+	return (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset;
+}
+
+static int _fdt_string_eq(const void *fdt, int stroffset,
+			  const char *s, int len)
+{
+	const char *p = fdt_string(fdt, stroffset);
+
+	return (strlen(p) == len) && (memcmp(p, s, len) == 0);
+}
+
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
+{
+	FDT_CHECK_HEADER(fdt);
+	*address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address);
+	*size = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->size);
+	return 0;
+}
+
+int fdt_num_mem_rsv(const void *fdt)
+{
+	int i = 0;
+
+	while (fdt64_to_cpu(_fdt_mem_rsv(fdt, i)->size) != 0)
+		i++;
+	return i;
+}
+
+static int _nextprop(const void *fdt, int offset)
+{
+	uint32_t tag;
+	int nextoffset;
+
+	do {
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_END:
+			if (nextoffset >= 0)
+				return -FDT_ERR_BADSTRUCTURE;
+			else
+				return nextoffset;
+
+		case FDT_PROP:
+			return offset;
+		}
+		offset = nextoffset;
+	} while (tag == FDT_NOP);
+
+	return -FDT_ERR_NOTFOUND;
+}
+
+int fdt_subnode_offset_namelen(const void *fdt, int offset,
+			       const char *name, int namelen)
+{
+	int depth;
+
+	FDT_CHECK_HEADER(fdt);
+
+	for (depth = 0;
+	     (offset >= 0) && (depth >= 0);
+	     offset = fdt_next_node(fdt, offset, &depth))
+		if ((depth == 1)
+		    && _fdt_nodename_eq(fdt, offset, name, namelen))
+			return offset;
+
+	if (depth < 0)
+		return -FDT_ERR_NOTFOUND;
+	return offset; /* error */
+}
+
+int fdt_subnode_offset(const void *fdt, int parentoffset,
+		       const char *name)
+{
+	return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_path_offset(const void *fdt, const char *path)
+{
+	const char *end = path + strlen(path);
+	const char *p = path;
+	int offset = 0;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* see if we have an alias */
+	if (*path != '/') {
+		const char *q = strchr(path, '/');
+
+		if (!q)
+			q = end;
+
+		p = fdt_get_alias_namelen(fdt, p, q - p);
+		if (!p)
+			return -FDT_ERR_BADPATH;
+		offset = fdt_path_offset(fdt, p);
+
+		p = q;
+	}
+
+	while (*p) {
+		const char *q;
+
+		while (*p == '/')
+			p++;
+		if (! *p)
+			return offset;
+		q = strchr(p, '/');
+		if (! q)
+			q = end;
+
+		offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
+		if (offset < 0)
+			return offset;
+
+		p = q;
+	}
+
+	return offset;
+}
+
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
+{
+	const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset);
+	int err;
+
+	if (((err = fdt_check_header(fdt)) != 0)
+	    || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+			goto fail;
+
+	if (len)
+		*len = strlen(nh->name);
+
+	return nh->name;
+
+ fail:
+	if (len)
+		*len = err;
+	return NULL;
+}
+
+int fdt_first_property_offset(const void *fdt, int nodeoffset)
+{
+	int offset;
+
+	if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+		return offset;
+
+	return _nextprop(fdt, offset);
+}
+
+int fdt_next_property_offset(const void *fdt, int offset)
+{
+	if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0)
+		return offset;
+
+	return _nextprop(fdt, offset);
+}
+
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+						      int offset,
+						      int *lenp)
+{
+	int err;
+	const struct fdt_property *prop;
+
+	if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) {
+		if (lenp)
+			*lenp = err;
+		return NULL;
+	}
+
+	prop = _fdt_offset_ptr(fdt, offset);
+
+	if (lenp)
+		*lenp = fdt32_to_cpu(prop->len);
+
+	return prop;
+}
+
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+						    int offset,
+						    const char *name,
+						    int namelen, int *lenp)
+{
+	for (offset = fdt_first_property_offset(fdt, offset);
+	     (offset >= 0);
+	     (offset = fdt_next_property_offset(fdt, offset))) {
+		const struct fdt_property *prop;
+
+		if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) {
+			offset = -FDT_ERR_INTERNAL;
+			break;
+		}
+		if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff),
+				   name, namelen))
+			return prop;
+	}
+
+	if (lenp)
+		*lenp = offset;
+	return NULL;
+}
+
+const struct fdt_property *fdt_get_property(const void *fdt,
+					    int nodeoffset,
+					    const char *name, int *lenp)
+{
+	return fdt_get_property_namelen(fdt, nodeoffset, name,
+					strlen(name), lenp);
+}
+
+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
+				const char *name, int namelen, int *lenp)
+{
+	const struct fdt_property *prop;
+
+	prop = fdt_get_property_namelen(fdt, nodeoffset, name, namelen, lenp);
+	if (! prop)
+		return NULL;
+
+	return prop->data;
+}
+
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+				  const char **namep, int *lenp)
+{
+	const struct fdt_property *prop;
+
+	prop = fdt_get_property_by_offset(fdt, offset, lenp);
+	if (!prop)
+		return NULL;
+	if (namep)
+		*namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
+	return prop->data;
+}
+
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp)
+{
+	return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp);
+}
+
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
+{
+	const uint32_t *php;
+	int len;
+
+	/* FIXME: This is a bit sub-optimal, since we potentially scan
+	 * over all the properties twice. */
+	php = fdt_getprop(fdt, nodeoffset, "phandle", &len);
+	if (!php || (len != sizeof(*php))) {
+		php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
+		if (!php || (len != sizeof(*php)))
+			return 0;
+	}
+
+	return fdt32_to_cpu(*php);
+}
+
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen)
+{
+	int aliasoffset;
+
+	aliasoffset = fdt_path_offset(fdt, "/aliases");
+	if (aliasoffset < 0)
+		return NULL;
+
+	return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
+}
+
+const char *fdt_get_alias(const void *fdt, const char *name)
+{
+	return fdt_get_alias_namelen(fdt, name, strlen(name));
+}
+
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
+{
+	int pdepth = 0, p = 0;
+	int offset, depth, namelen;
+	const char *name;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (buflen < 2)
+		return -FDT_ERR_NOSPACE;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		while (pdepth > depth) {
+			do {
+				p--;
+			} while (buf[p-1] != '/');
+			pdepth--;
+		}
+
+		if (pdepth >= depth) {
+			name = fdt_get_name(fdt, offset, &namelen);
+			if (!name)
+				return namelen;
+			if ((p + namelen + 1) <= buflen) {
+				memcpy(buf + p, name, namelen);
+				p += namelen;
+				buf[p++] = '/';
+				pdepth++;
+			}
+		}
+
+		if (offset == nodeoffset) {
+			if (pdepth < (depth + 1))
+				return -FDT_ERR_NOSPACE;
+
+			if (p > 1) /* special case so that root path is "/", not "" */
+				p--;
+			buf[p] = '\0';
+			return 0;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth)
+{
+	int offset, depth;
+	int supernodeoffset = -FDT_ERR_INTERNAL;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (supernodedepth < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		if (depth == supernodedepth)
+			supernodeoffset = offset;
+
+		if (offset == nodeoffset) {
+			if (nodedepth)
+				*nodedepth = depth;
+
+			if (supernodedepth > depth)
+				return -FDT_ERR_NOTFOUND;
+			else
+				return supernodeoffset;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_depth(const void *fdt, int nodeoffset)
+{
+	int nodedepth;
+	int err;
+
+	err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);
+	if (err)
+		return (err < 0) ? err : -FDT_ERR_INTERNAL;
+	return nodedepth;
+}
+
+int fdt_parent_offset(const void *fdt, int nodeoffset)
+{
+	int nodedepth = fdt_node_depth(fdt, nodeoffset);
+
+	if (nodedepth < 0)
+		return nodedepth;
+	return fdt_supernode_atdepth_offset(fdt, nodeoffset,
+					    nodedepth - 1, NULL);
+}
+
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen)
+{
+	int offset;
+	const void *val;
+	int len;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_getprop(), then if that didn't
+	 * find what we want, we scan over them again making our way
+	 * to the next node.  Still it's the easiest to implement
+	 * approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		val = fdt_getprop(fdt, offset, propname, &len);
+		if (val && (len == proplen)
+		    && (memcmp(val, propval, len) == 0))
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
+{
+	int offset;
+
+	if ((phandle == 0) || (phandle == -1))
+		return -FDT_ERR_BADPHANDLE;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we
+	 * potentially scan each property of a node in
+	 * fdt_get_phandle(), then if that didn't find what
+	 * we want, we scan over them again making our way to the next
+	 * node.  Still it's the easiest to implement approach;
+	 * performance can come later. */
+	for (offset = fdt_next_node(fdt, -1, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		if (fdt_get_phandle(fdt, offset) == phandle)
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+static int _fdt_stringlist_contains(const char *strlist, int listlen,
+				    const char *str)
+{
+	int len = strlen(str);
+	const char *p;
+
+	while (listlen >= len) {
+		if (memcmp(str, strlist, len+1) == 0)
+			return 1;
+		p = memchr(strlist, '\0', listlen);
+		if (!p)
+			return 0; /* malformed strlist.. */
+		listlen -= (p-strlist) + 1;
+		strlist = p + 1;
+	}
+	return 0;
+}
+
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible)
+{
+	const void *prop;
+	int len;
+
+	prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
+	if (!prop)
+		return len;
+	if (_fdt_stringlist_contains(prop, len, compatible))
+		return 0;
+	else
+		return 1;
+}
+
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible)
+{
+	int offset, err;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_node_check_compatible(), then if
+	 * that didn't find what we want, we scan over them again
+	 * making our way to the next node.  Still it's the easiest to
+	 * implement approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		err = fdt_node_check_compatible(fdt, offset, compatible);
+		if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
+			return err;
+		else if (err == 0)
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+static int ascii_to_hex(char c)
+{
+	if ((c >= '0') && (c <= '9'))
+		return c - '0';
+
+	if (c > 'F')
+		c -= 'a' - 'A';
+
+	if ((c >= 'A') && (c <= 'F'))
+		return c - 'A' + 10;
+
+	return -1;
+}
+
+int fdt_get_base_addr(const void *fdt, int offset, u64 *base_addr)
+{
+	const char *fmap_node_name, *fmap_base_addr;
+	u64 addr = 0;
+	int len;
+
+	fmap_node_name = fdt_get_name(fdt, offset, &len);
+	if (!fmap_node_name)
+		return -1;
+
+	fmap_base_addr = memchr(fmap_node_name, '@', len);
+	if (!fmap_base_addr++)
+		return -1;
+
+	// get the address representnation length
+	len -= fmap_base_addr - fmap_node_name;
+	while (len--) {
+		int nibble = ascii_to_hex(*fmap_base_addr++);
+		if (nibble < 0)
+			return -1;
+		addr <<= 4;
+		addr += nibble;
+	}
+	*base_addr = addr;
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_rw.c b/src/lib/libfdt/fdt_rw.c
new file mode 100644
index 0000000..ca21059
--- /dev/null
+++ b/src/lib/libfdt/fdt_rw.c
@@ -0,0 +1,469 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+static int _fdt_blocks_misordered(const void *fdt,
+			      int mem_rsv_size, int struct_size)
+{
+	return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
+		|| (fdt_off_dt_struct(fdt) <
+		    (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
+		|| (fdt_off_dt_strings(fdt) <
+		    (fdt_off_dt_struct(fdt) + struct_size))
+		|| (fdt_totalsize(fdt) <
+		    (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
+}
+
+static int _fdt_rw_check_header(void *fdt)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if (fdt_version(fdt) < 17)
+		return -FDT_ERR_BADVERSION;
+	if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry),
+				   fdt_size_dt_struct(fdt)))
+		return -FDT_ERR_BADLAYOUT;
+	if (fdt_version(fdt) > 17)
+		fdt_set_version(fdt, 17);
+
+	return 0;
+}
+
+#define FDT_RW_CHECK_HEADER(fdt) \
+	{ \
+		int _err; \
+		if ((_err = _fdt_rw_check_header(fdt)) != 0) \
+			return _err; \
+	}
+
+static inline int _fdt_data_size(void *fdt)
+{
+	return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+}
+
+static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen)
+{
+	char *p = splicepoint;
+	char *end = (char *)fdt + _fdt_data_size(fdt);
+
+	if (((p + oldlen) < p) || ((p + oldlen) > end))
+		return -FDT_ERR_BADOFFSET;
+	if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
+		return -FDT_ERR_NOSPACE;
+	memmove(p + newlen, p + oldlen, end - p - oldlen);
+	return 0;
+}
+
+static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p,
+			       int oldn, int newn)
+{
+	int delta = (newn - oldn) * sizeof(*p);
+	int err;
+	err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
+	if (err)
+		return err;
+	fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_struct(void *fdt, void *p,
+			      int oldlen, int newlen)
+{
+	int delta = newlen - oldlen;
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, oldlen, newlen)))
+		return err;
+
+	fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_string(void *fdt, int newlen)
+{
+	void *p = (char *)fdt
+		+ fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, 0, newlen)))
+		return err;
+
+	fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
+	return 0;
+}
+
+static int _fdt_find_add_string(void *fdt, const char *s)
+{
+	char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
+	const char *p;
+	char *new;
+	int len = strlen(s) + 1;
+	int err;
+
+	p = _fdt_find_string(strtab, fdt_size_dt_strings(fdt), s);
+	if (p)
+		/* found it */
+		return (p - strtab);
+
+	new = strtab + fdt_size_dt_strings(fdt);
+	err = _fdt_splice_string(fdt, len);
+	if (err)
+		return err;
+
+	memcpy(new, s, len);
+	return (new - strtab);
+}
+
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)
+{
+	struct fdt_reserve_entry *re;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
+	err = _fdt_splice_mem_rsv(fdt, re, 0, 1);
+	if (err)
+		return err;
+
+	re->address = cpu_to_fdt64(address);
+	re->size = cpu_to_fdt64(size);
+	return 0;
+}
+
+int fdt_del_mem_rsv(void *fdt, int n)
+{
+	struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	if (n >= fdt_num_mem_rsv(fdt))
+		return -FDT_ERR_NOTFOUND;
+
+	err = _fdt_splice_mem_rsv(fdt, re, 1, 0);
+	if (err)
+		return err;
+	return 0;
+}
+
+static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
+				int len, struct fdt_property **prop)
+{
+	int oldlen;
+	int err;
+
+	*prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
+	if (! (*prop))
+		return oldlen;
+
+	if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
+				      FDT_TAGALIGN(len))))
+		return err;
+
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+static int _fdt_add_property(void *fdt, int nodeoffset, const char *name,
+			     int len, struct fdt_property **prop)
+{
+	int proplen;
+	int nextoffset;
+	int namestroff;
+	int err;
+
+	if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+		return nextoffset;
+
+	namestroff = _fdt_find_add_string(fdt, name);
+	if (namestroff < 0)
+		return namestroff;
+
+	*prop = _fdt_offset_ptr_w(fdt, nextoffset);
+	proplen = sizeof(**prop) + FDT_TAGALIGN(len);
+
+	err = _fdt_splice_struct(fdt, *prop, 0, proplen);
+	if (err)
+		return err;
+
+	(*prop)->tag = cpu_to_fdt32(FDT_PROP);
+	(*prop)->nameoff = cpu_to_fdt32(namestroff);
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+int fdt_set_name(void *fdt, int nodeoffset, const char *name)
+{
+	char *namep;
+	int oldlen, newlen;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
+	if (!namep)
+		return oldlen;
+
+	newlen = strlen(name);
+
+	err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1),
+				 FDT_TAGALIGN(newlen+1));
+	if (err)
+		return err;
+
+	memcpy(namep, name, newlen+1);
+	return 0;
+}
+
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len)
+{
+	struct fdt_property *prop;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop);
+	if (err == -FDT_ERR_NOTFOUND)
+		err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
+	if (err)
+		return err;
+
+	memcpy(prop->data, val, len);
+	return 0;
+}
+
+int fdt_delprop(void *fdt, int nodeoffset, const char *name)
+{
+	struct fdt_property *prop;
+	int len, proplen;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
+	if (! prop)
+		return len;
+
+	proplen = sizeof(*prop) + FDT_TAGALIGN(len);
+	return _fdt_splice_struct(fdt, prop, proplen, 0);
+}
+
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen)
+{
+	struct fdt_node_header *nh;
+	int offset, nextoffset;
+	int nodelen;
+	int err;
+	uint32_t tag;
+	uint32_t *endtag;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
+	if (offset >= 0)
+		return -FDT_ERR_EXISTS;
+	else if (offset != -FDT_ERR_NOTFOUND)
+		return offset;
+
+	/* Try to place the new node after the parent's properties */
+	fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+	} while ((tag == FDT_PROP) || (tag == FDT_NOP));
+
+	nh = _fdt_offset_ptr_w(fdt, offset);
+	nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
+
+	err = _fdt_splice_struct(fdt, nh, 0, nodelen);
+	if (err)
+		return err;
+
+	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
+	memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
+	memcpy(nh->name, name, namelen);
+	endtag = (uint32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
+	*endtag = cpu_to_fdt32(FDT_END_NODE);
+
+	return offset;
+}
+
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name)
+{
+	return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_del_node(void *fdt, int nodeoffset)
+{
+	int endoffset;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	endoffset = _fdt_node_end_offset(fdt, nodeoffset);
+	if (endoffset < 0)
+		return endoffset;
+
+	return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset),
+				  endoffset - nodeoffset, 0);
+}
+
+static void _fdt_packblocks(const char *old, char *new,
+			    int mem_rsv_size, int struct_size)
+{
+	int mem_rsv_off, struct_off, strings_off;
+
+	mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
+	struct_off = mem_rsv_off + mem_rsv_size;
+	strings_off = struct_off + struct_size;
+
+	memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);
+	fdt_set_off_mem_rsvmap(new, mem_rsv_off);
+
+	memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);
+	fdt_set_off_dt_struct(new, struct_off);
+	fdt_set_size_dt_struct(new, struct_size);
+
+	memmove(new + strings_off, old + fdt_off_dt_strings(old),
+		fdt_size_dt_strings(old));
+	fdt_set_off_dt_strings(new, strings_off);
+	fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));
+}
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize)
+{