diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..305ef4f
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,5 @@
+build
+coreboot-builds
+.config
+.config.old
+.xcompile
diff --git a/Makefile b/Makefile
index ac7115d..04fbb02 100644
--- a/Makefile
+++ b/Makefile
@@ -109,7 +109,7 @@
 endif
 
 ifeq ($(CONFIG_CCACHE),y)
-CCACHE:=$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH))))
+CCACHE:=$(word 1,$(wildcard $(addsuffix /ccache,$(subst :, ,$(PATH)))))
 ifeq ($(CCACHE),)
 $(error ccache selected, but not found in PATH)
 endif
@@ -176,7 +176,7 @@
 	$(foreach class,$(classes), \
 		$(eval $(class)-srcs+= \
 			$$(subst $(top)/,, \
-			$$(abspath $$(addprefix $(dir $(1)),$$($(class)-y)))))) \
+			$$(abspath $$(subst $(dir $(1))/,/,$$(addprefix $(dir $(1)),$$($(class)-y))))))) \
 	$(foreach special,$(special-classes), \
 		$(foreach item,$($(special)-y), $(call $(special)-handler,$(dir $(1)),$(item)))) \
 	$(eval subdirs+=$$(subst $(CURDIR)/,,$$(abspath $$(addprefix $(dir $(1)),$$(subdirs-y)))))
diff --git a/Makefile.inc b/Makefile.inc
index 6267539..94edd81 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -19,8 +19,8 @@
 
 #######################################################################
 # misleadingly named, this is the coreboot version
-REV=-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)
-export KERNELVERSION      := 4.0$(REV)
+KERNELREVISION?=-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)
+export KERNELVERSION      := 4.0$(KERNELREVISION)
 
 #######################################################################
 # Basic component discovery
@@ -43,6 +43,7 @@
 subdirs-y += util/cbfstool util/sconfig
 subdirs-y += src/arch/$(ARCHDIR-y)
 subdirs-y += src/mainboard/$(MAINBOARDDIR)
+subdirs-y += src/vendorcode
 
 subdirs-$(CONFIG_ARCH_X86) += src/pc80
 
@@ -55,6 +56,11 @@
 smm-c-ccopts:=-D__SMM__
 smm-S-ccopts:=-D__SMM__
 
+# SMM TSEG base is dynamic
+ifeq ($(CONFIG_SMM_TSEG),y)
+smm-c-ccopts += -fpic
+endif
+
 ramstage-c-deps:=$$(OPTION_TABLE_H)
 romstage-c-deps:=$$(OPTION_TABLE_H)
 
@@ -64,7 +70,8 @@
 $(obj)/$(1).ramstage.o: src/$(1).asl $(obj)/config.h
 	@printf "    IASL       $$(subst $(top)/,,$$(@))\n"
 	$(CC) -x assembler-with-cpp -E -MMD -MT $$(@) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$@).asl
-	iasl -p $$(obj)/$(1) -tc $$(basename $$@).asl
+	cd $$(dir $$@); iasl -p $$(notdir $$(basename $$(obj)/$(1))) \
+				-tc $$(notdir $$(basename $$@)).asl
 	mv $$(obj)/$(1).hex $$(basename $$@).c
 	$(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$@).c
 	# keep %.o: %.c rule from catching the temporary .c file after a make clean
@@ -102,7 +109,7 @@
 endif
 
 INCLUDES := -Isrc -Isrc/include -I$(obj) -Isrc/arch/$(ARCHDIR-y)/include
-INCLUDES += -Isrc/devices/oprom/include
+INCLUDES += -Isrc/devices/oprom/include -Isrc/include/fdt
 # abspath is a workaround for romcc
 INCLUDES += -include $(abspath $(obj)/config.h)
 
@@ -131,6 +138,7 @@
 	printf "#define COREBOOT_VERSION \"$(KERNELVERSION)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht
+	printf "#define COREBOOT_DMI_DATE \"`LANG= date +"%m/%d/%Y"`\"\n" >> $(obj)/build.ht
 	printf "\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_COMPILER \"$(shell LANG= $(CC) --version | head -n1)\"\n" >> $(obj)/build.ht
 	printf "#define COREBOOT_ASSEMBLER \"$(shell LANG= $(AS) --version | head -n1)\"\n" >> $(obj)/build.ht
@@ -182,7 +190,7 @@
 	@printf "    HOSTCC     $(subst $(objutil)/,,$(@))\n"
 	$(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $<
 
-$(obj)/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
+$(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H)
 	@printf "    CC         $(subst $(obj)/,,$(@))\n"
 	$(CC) -MMD $(CFLAGS) -c -o $@ $<
 
diff --git a/PRESUBMIT.cfg b/PRESUBMIT.cfg
new file mode 100644
index 0000000..b9a7fca
--- /dev/null
+++ b/PRESUBMIT.cfg
@@ -0,0 +1,10 @@
+# This config file disables some of the ChromiumOS source style checks for
+# coreboot as they are directly conflicting with the coreboot coding
+# guidelines.
+
+[Hook Overrides]
+#stray_whitespace_check: false
+#long_line_check: false
+cros_license_check: false
+tab_check: false
+
diff --git a/README b/README
index d879695..16a805f 100644
--- a/README
+++ b/README
@@ -42,6 +42,7 @@
  * gdb (for better debugging facilities on some targets)
  * ncurses (for 'make menuconfig')
  * flex and bison (for regenerating parsers)
+ * git (for internal SeaBIOS payload)
 
 
 Building coreboot
diff --git a/config.lumpy b/config.lumpy
new file mode 100644
index 0000000..95756bd
--- /dev/null
+++ b/config.lumpy
@@ -0,0 +1,353 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version: 4.0-r6552
+# Sat Mar  3 00:42:46 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_ADD_FDT=y
+CONFIG_FDT_FILE_NAME="u-boot.dtb"
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTEC_GROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_DIGITAL_LOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EVOC is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PC_ENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+CONFIG_VENDOR_SAMSUNG=y
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="samsung/lumpy"
+CONFIG_MAINBOARD_PART_NUMBER="Lumpy"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="SAMSUNG"
+CONFIG_MAX_CPUS=8
+CONFIG_MAX_PHYSICAL_CPUS=1
+CONFIG_DCACHE_RAM_BASE=0xff7f0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_ID_SECTION_OFFSET=0x10
+CONFIG_STACK_SIZE=0x8000
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS_ID="8086,0106"
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_VGA_BIOS_FILE="3rdparty/intel/sandybridge/lumpy/snm_2130_coreboot.bin"
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1ae0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xc000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is not set
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+CONFIG_BOARD_SAMSUNG_LUMPY=y
+# CONFIG_BOARD_SAMSUNG_STUMPY is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+CONFIG_AP_IN_SIPI_WAIT=y
+CONFIG_ROMBASE=0xffff0000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_TINY_BOOTBLOCK=y
+# CONFIG_BIG_BOOTBLOCK is not set
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_BASE=0xffff0000
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_DIMM_SUPPORT=0x0004
+# CONFIG_UDELAY_IO is not set
+CONFIG_UPDATE_CPU_MICROCODE=y
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_CPU_INTEL_MODEL_206AX=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_SIZE_KB=256
+CONFIG_DCACHE_MRC_BASE=0xfffd0000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_MMX=y
+CONFIG_SSE=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_SMSC_MEC1308=y
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_SMSC_MEC1308=y
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+CONFIG_VGA_BIOS=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x114
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_DEBUG_INTEL_ME is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_CHROMEOS=y
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
diff --git a/config.stumpy b/config.stumpy
new file mode 100644
index 0000000..9b92a36
--- /dev/null
+++ b/config.stumpy
@@ -0,0 +1,352 @@
+#
+# Automatically generated make config: don't edit
+# coreboot version: 4.0-r6552
+# Sat Mar  3 01:00:42 2012
+#
+
+#
+# General setup
+#
+CONFIG_EXPERT=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+# CONFIG_SCANBUILD_ENABLE is not set
+# CONFIG_CCACHE is not set
+# CONFIG_SCONFIG_GENPARSER is not set
+# CONFIG_USE_OPTION_TABLE is not set
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_ADD_FDT=y
+CONFIG_FDT_FILE_NAME="u-boot.dtb"
+CONFIG_EARLY_CBMEM_INIT=y
+CONFIG_COLLECT_TIMESTAMPS=y
+
+#
+# Mainboard
+#
+# CONFIG_VENDOR_ABIT is not set
+# CONFIG_VENDOR_ADVANTECH is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_ARIMA is not set
+# CONFIG_VENDOR_ARTEC_GROUP is not set
+# CONFIG_VENDOR_ASI is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_A_TREND is not set
+# CONFIG_VENDOR_AXUS is not set
+# CONFIG_VENDOR_AZZA is not set
+# CONFIG_VENDOR_BCOM is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BROADCOM is not set
+# CONFIG_VENDOR_COMPAQ is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_DIGITAL_LOGIC is not set
+# CONFIG_VENDOR_EAGLELION is not set
+# CONFIG_VENDOR_ECS is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EVOC is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_IBM is not set
+# CONFIG_VENDOR_IEI is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_IWAVE is not set
+# CONFIG_VENDOR_IWILL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LANNER is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MITAC is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_NEC is not set
+# CONFIG_VENDOR_NEWISYS is not set
+# CONFIG_VENDOR_NOKIA is not set
+# CONFIG_VENDOR_NVIDIA is not set
+# CONFIG_VENDOR_PC_ENGINES is not set
+# CONFIG_VENDOR_RCA is not set
+# CONFIG_VENDOR_RODA is not set
+CONFIG_VENDOR_SAMSUNG=y
+# CONFIG_VENDOR_SOYO is not set
+# CONFIG_VENDOR_SUNW is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_TECHNEXION is not set
+# CONFIG_VENDOR_TECHNOLOGIC is not set
+# CONFIG_VENDOR_TELEVIDEO is not set
+# CONFIG_VENDOR_THOMSON is not set
+# CONFIG_VENDOR_TRAVERSE is not set
+# CONFIG_VENDOR_TYAN is not set
+# CONFIG_VENDOR_VIA is not set
+# CONFIG_VENDOR_WINENT is not set
+# CONFIG_VENDOR_WYSE is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_DIR="samsung/stumpy"
+CONFIG_MAINBOARD_PART_NUMBER="Stumpy"
+CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_MAINBOARD_VENDOR="SAMSUNG"
+CONFIG_MAX_CPUS=8
+CONFIG_MAX_PHYSICAL_CPUS=1
+CONFIG_DCACHE_RAM_BASE=0xff7f0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE=0x0
+CONFIG_RAMTOP=0x200000
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_RAMBASE=0x100000
+# CONFIG_SERIAL_CPU_INIT is not set
+CONFIG_ACPI_SSDTX_NUM=0
+CONFIG_ID_SECTION_OFFSET=0x10
+CONFIG_STACK_SIZE=0x8000
+CONFIG_DRIVERS_PS2_KEYBOARD=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_VGA_BIOS_ID="8086,0106"
+# CONFIG_PCI_64BIT_PREF_MEM is not set
+CONFIG_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_VGA_BIOS_FILE="3rdparty/intel/sandybridge/stumpy/snm_2124_coreboot.bin"
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1ae0
+CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0xc000
+CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT="southbridge/intel/bd82x6x/bootblock.c"
+# CONFIG_MMCONF_SUPPORT_DEFAULT is not set
+# CONFIG_POWER_BUTTON_FORCE_ENABLE is not set
+# CONFIG_GENERATE_PIRQ_TABLE is not set
+CONFIG_LOGICAL_CPUS=y
+CONFIG_IOAPIC=y
+CONFIG_SMP=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+# CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL is not set
+# CONFIG_CONSOLE_SERIAL8250 is not set
+# CONFIG_PCI_ROM_RUN is not set
+# CONFIG_USBDEBUG is not set
+CONFIG_VAR_MTRR_HOLE=y
+# CONFIG_LIFT_BSP_APIC_ID is not set
+# CONFIG_WAIT_BEFORE_CPUS_INIT is not set
+# CONFIG_K8_REV_F_SUPPORT is not set
+# CONFIG_BOARD_SAMSUNG_LUMPY is not set
+CONFIG_BOARD_SAMSUNG_STUMPY=y
+# CONFIG_COREBOOT_ROMSIZE_KB_128 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_1024=y
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=1024
+CONFIG_ROM_SIZE=0x100000
+CONFIG_ARCH_X86=y
+
+#
+# Architecture (x86)
+#
+CONFIG_AP_IN_SIPI_WAIT=y
+CONFIG_ROMBASE=0xffff0000
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_TINY_BOOTBLOCK=y
+# CONFIG_BIG_BOOTBLOCK is not set
+CONFIG_X86_BOOTBLOCK_SIMPLE=y
+# CONFIG_X86_BOOTBLOCK_NORMAL is not set
+CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_ROMCC is not set
+CONFIG_PC80_SYSTEM=y
+# CONFIG_HAVE_CMOS_DEFAULT is not set
+CONFIG_HAVE_ARCH_MEMSET=y
+CONFIG_HAVE_ARCH_MEMCPY=y
+# CONFIG_BIG_ENDIAN is not set
+CONFIG_LITTLE_ENDIAN=y
+
+#
+# Chipset
+#
+
+#
+# CPU
+#
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_ADDR_BITS=36
+CONFIG_XIP_ROM_BASE=0xffff0000
+CONFIG_XIP_ROM_SIZE=0x10000
+CONFIG_DIMM_SUPPORT=0x0004
+# CONFIG_UDELAY_IO is not set
+CONFIG_UPDATE_CPU_MICROCODE=y
+CONFIG_HAVE_INIT_TIMER=y
+CONFIG_BOOTBLOCK_CPU_INIT="cpu/intel/model_206ax/bootblock.c"
+CONFIG_CACHE_MRC_BIN=y
+CONFIG_CPU_INTEL_MODEL_206AX=y
+CONFIG_SMM_TSEG_SIZE=0x800000
+CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_RPGA989=y
+CONFIG_CACHE_MRC_SIZE_KB=256
+CONFIG_DCACHE_MRC_BASE=0xfffd0000
+CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x4000
+CONFIG_UDELAY_LAPIC=y
+# CONFIG_UDELAY_TSC is not set
+# CONFIG_TSC_CALIBRATE_WITH_IO is not set
+CONFIG_CACHE_ROM=y
+CONFIG_SMM_TSEG=y
+CONFIG_CACHE_AS_RAM=y
+CONFIG_MMX=y
+CONFIG_SSE=y
+
+#
+# Northbridge
+#
+CONFIG_VIDEO_MB=0
+CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
+
+#
+# Southbridge
+#
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_EHCI_DEBUG_OFFSET=0xa0
+CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
+
+#
+# Super I/O
+#
+CONFIG_SUPERIO_ITE_IT8772F=y
+
+#
+# Devices
+#
+CONFIG_VGA_BRIDGE_SETUP=y
+CONFIG_VGA_ROM_RUN=y
+# CONFIG_S3_VGA_ROM_RUN is not set
+# CONFIG_ON_DEVICE_ROM_RUN is not set
+CONFIG_PCI_OPTION_ROM_RUN_REALMODE=y
+# CONFIG_PCI_OPTION_ROM_RUN_YABEL is not set
+# CONFIG_MULTIPLE_VGA_ADAPTERS is not set
+# CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not set
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_AGP_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_COMMON_CLOCK=y
+CONFIG_PCIEXP_ASPM=y
+
+#
+# Embedded Controllers
+#
+
+#
+# Generic Drivers
+#
+# CONFIG_DRIVERS_OXFORD_OXPCIE is not set
+# CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_PCI_BUS_SEGN_BITS=0
+CONFIG_MMCONF_SUPPORT=y
+
+#
+# Console
+#
+CONFIG_HAVE_USBDEBUG=y
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x10000
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00
+CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_8=y
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_MAXIMUM_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+# CONFIG_CONSOLE_LOGBUF is not set
+# CONFIG_NO_POST is not set
+# CONFIG_CONSOLE_POST is not set
+CONFIG_HAVE_UART_IO_MAPPED=y
+# CONFIG_HAVE_UART_MEMORY_MAPPED is not set
+CONFIG_HAVE_ACPI_RESUME=y
+# CONFIG_HAVE_ACPI_SLIC is not set
+CONFIG_HAVE_HARD_RESET=y
+CONFIG_HAVE_MAINBOARD_RESOURCES=y
+CONFIG_HAVE_OPTION_TABLE=y
+# CONFIG_PIRQ_ROUTE is not set
+CONFIG_HAVE_SMI_HANDLER=y
+# CONFIG_PCI_IO_CFG_EXT is not set
+CONFIG_TPM=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+# CONFIG_VGA is not set
+CONFIG_GFXUMA=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_GENERATE_ACPI_TABLES=y
+# CONFIG_GENERATE_MP_TABLE is not set
+CONFIG_GENERATE_SMBIOS_TABLES=y
+
+#
+# System tables
+#
+CONFIG_WRITE_HIGH_TABLES=y
+# CONFIG_MULTIBOOT is not set
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_COMPRESSED_PAYLOAD_NRV2B is not set
+
+#
+# VGA BIOS
+#
+CONFIG_VGA_BIOS=y
+
+#
+# Display
+#
+CONFIG_FRAMEBUFFER_SET_VESA_MODE=y
+CONFIG_FRAMEBUFFER_VESA_MODE=0x114
+CONFIG_FRAMEBUFFER_KEEP_VESA_MODE=y
+# CONFIG_BOOTSPLASH is not set
+
+#
+# Debugging
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_HAVE_DEBUG_RAM_SETUP is not set
+# CONFIG_HAVE_DEBUG_CAR is not set
+# CONFIG_HAVE_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_DEBUG_SMM_RELOCATION is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_REALMODE_DEBUG is not set
+# CONFIG_LLSHELL is not set
+# CONFIG_DEBUG_INTEL_ME is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_AP_CODE_IN_CAR is not set
+# CONFIG_RAMINIT_SYSINFO is not set
+# CONFIG_ENABLE_APIC_EXT_ID is not set
+# CONFIG_POWER_BUTTON_DEFAULT_ENABLE is not set
+# CONFIG_POWER_BUTTON_DEFAULT_DISABLE is not set
+# CONFIG_POWER_BUTTON_FORCE_DISABLE is not set
+# CONFIG_POWER_BUTTON_IS_OPTIONAL is not set
+
+#
+# Deprecated
+#
+# CONFIG_BOARD_HAS_HARD_RESET is not set
+CONFIG_BOARD_HAS_FADT=y
+# CONFIG_HAVE_BUS_CONFIG is not set
+# CONFIG_PCIE_TUNING is not set
+CONFIG_CHROMEOS=y
+CONFIG_VBNV_OFFSET=0x26
+CONFIG_VBNV_SIZE=0x10
+CONFIG_CHROMEOS_RAMOOPS=y
+CONFIG_CHROMEOS_RAMOOPS_RAM_START=0x00f00000
+CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE=0x00100000
diff --git a/payloads/external/FILO/.gitignore b/payloads/external/FILO/.gitignore
new file mode 100644
index 0000000..dd2c4d2
--- /dev/null
+++ b/payloads/external/FILO/.gitignore
@@ -0,0 +1 @@
+filo
diff --git a/payloads/external/SeaBIOS/.gitignore b/payloads/external/SeaBIOS/.gitignore
new file mode 100644
index 0000000..41f077c
--- /dev/null
+++ b/payloads/external/SeaBIOS/.gitignore
@@ -0,0 +1 @@
+seabios
diff --git a/payloads/libpayload/arch/i386/coreboot.c b/payloads/libpayload/arch/i386/coreboot.c
index 8441903..b5e722c 100644
--- a/payloads/libpayload/arch/i386/coreboot.c
+++ b/payloads/libpayload/arch/i386/coreboot.c
@@ -77,7 +77,9 @@
 static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_serial *ser = (struct cb_serial *)ptr;
-	info->ser_ioport = ser->ioport;
+	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
+		return;
+	info->ser_ioport = ser->baseaddr;
 }
 
 #ifdef CONFIG_NVRAM
diff --git a/payloads/libpayload/arch/powerpc/coreboot.c b/payloads/libpayload/arch/powerpc/coreboot.c
index 95d8f16..7d5dc02 100644
--- a/payloads/libpayload/arch/powerpc/coreboot.c
+++ b/payloads/libpayload/arch/powerpc/coreboot.c
@@ -77,7 +77,9 @@
 static void cb_parse_serial(unsigned char *ptr, struct sysinfo_t *info)
 {
 	struct cb_serial *ser = (struct cb_serial *)ptr;
-	info->ser_ioport = ser->ioport;
+	if (ser->type != CB_SERIAL_TYPE_IO_MAPPED)
+		return;
+	info->ser_ioport = ser->baseaddr;
 }
 
 #ifdef CONFIG_NVRAM
diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h
index c4dc115..d342c99 100644
--- a/payloads/libpayload/include/coreboot_tables.h
+++ b/payloads/libpayload/include/coreboot_tables.h
@@ -60,9 +60,13 @@
 	u32 type;
 };
 
-#define CB_MEM_RAM      1
-#define CB_MEM_RESERVED 2
-#define CB_MEM_TABLE    16
+#define CB_MEM_RAM          1
+#define CB_MEM_RESERVED     2
+#define CB_MEM_ACPI         3
+#define CB_MEM_NVS          4
+#define CB_MEM_UNUSABLE     5
+#define CB_MEM_VENDOR_RSVD  6
+#define CB_MEM_TABLE       16
 
 struct cb_memory {
 	u32 tag;
@@ -110,7 +114,11 @@
 struct cb_serial {
 	u32 tag;
 	u32 size;
-	u16 ioport;
+#define CB_SERIAL_TYPE_IO_MAPPED     1
+#define CB_SERIAL_TYPE_MEMORY_MAPPED 2
+	u32 type;
+	u32 baseaddr;
+	u32 baud;
 };
 
 #define CB_TAG_CONSOLE       0x00010
diff --git a/src/Kconfig b/src/Kconfig
index 9abbc21..06fd39e 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -87,7 +87,7 @@
 	help
 	  Enable this option if you are working on the sconfig
 	  device tree parser and made changes to sconfig.l and
-	  sconfig.y. 
+	  sconfig.y.
 	  Otherwise, say N.
 
 config USE_OPTION_TABLE
@@ -106,6 +106,37 @@
 	  that decompression might slow down booting if the boot flash
 	  is connected through a slow Link (i.e. SPI)
 
+config ADD_FDT
+	bool "Add FDT to the coreboot table"
+	default n
+	help
+	  Make coreboot look for the Flat Device Tree (FDT) in CBFS and once
+	  found insert the device tree into the coreboot table (potentially
+	  modifying the tree as needed). The FDT is used by the payload.
+
+config FDT_FILE_NAME
+	depends on ADD_FDT
+	string "Name of the CBFS file containing the compiled FDT"
+	default "u-boot.dtb"
+	help
+	  Name of the CBFS file containing the binary representation of the
+	  device tree to be optionally modified and passed to the payload.
+
+config EARLY_CBMEM_INIT
+	bool "Initialize CBMEM while in ROM stage"
+	default n
+	help
+	  Make coreboot initialize the cbmem structures while running in rom
+	  stage. This could be useful when the rom stage wants to communicate
+	  some, for instance, execution timestamps.
+
+config COLLECT_TIMESTAMPS
+	bool "Create a table of timestamps collected during boot"
+	depends on EARLY_CBMEM_INIT
+	help
+	  Make coreboot create a table of timer id/timer value pairs to
+	  allow measuring time spent at different phases of the boot
+	  process.
 endmenu
 
 source src/mainboard/Kconfig
@@ -233,6 +264,10 @@
 	bool
 	default n
 
+config TPM
+	bool
+	default n
+
 # TODO: Can probably be removed once all chipsets have kconfig options for it.
 config VIDEO_MB
 	int
@@ -298,6 +333,10 @@
 	bool
 	default HAVE_PIRQ_TABLE
 
+config GENERATE_SMBIOS_TABLES
+	bool
+	default y
+
 menu "System tables"
 
 config WRITE_HIGH_TABLES
@@ -336,6 +375,15 @@
 
 	  If unsure, say Y.
 
+config GENERATE_SMBIOS_TABLES
+	depends on ARCH_X86
+	bool "Generate SMBIOS tables"
+	default y
+	help
+	  Generate SMBIOS tables for this board.
+
+	  If unsure, say Y.
+
 endmenu
 
 menu "Payload"
@@ -497,13 +545,42 @@
 
 endmenu
 
-menu "Bootsplash"
-	depends on PCI_OPTION_ROM_RUN_YABEL
+menu "Display"
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+
+config FRAMEBUFFER_SET_VESA_MODE
+	prompt "Set VESA framebuffer mode"
+	bool
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+	help
+	  Set VESA framebuffer mode (needed for bootsplash)
+
+# TODO: Turn this into a "choice".
+config FRAMEBUFFER_VESA_MODE
+	prompt "VESA framebuffer video mode"
+	hex
+	default 0x117
+	depends on FRAMEBUFFER_SET_VESA_MODE
+	help
+	  This option sets the resolution used for the coreboot framebuffer (and
+	  bootsplash screen). Set to 0x117 for 1024x768x16. A diligent soul will
+	  some day make this a "choice".
+
+config FRAMEBUFFER_KEEP_VESA_MODE
+	prompt "Keep VESA framebuffer"
+	bool
+	depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE
+	help
+	  This option keeps the framebuffer mode set after coreboot finishes
+	  execution. If this option is enabled, coreboot will pass a
+	  framebuffer entry in its coreboot table and the payload will need a
+	  framebuffer driver. If this option is disabled, coreboot will switch
+	  back to text mode before handing control to a payload.
 
 config BOOTSPLASH
 	prompt "Show graphical bootsplash"
 	bool
-	depends on PCI_OPTION_ROM_RUN_YABEL
+	depends on FRAMEBUFFER_SET_VESA_MODE
 	help
 	  This option shows a graphical bootsplash screen. The grapics are
 	  loaded from the CBFS file bootsplash.jpg.
@@ -515,29 +592,6 @@
 	help
 	  The path and filename of the file to use as graphical bootsplash
 	  screen. The file format has to be jpg.
-
-# TODO: Turn this into a "choice".
-config FRAMEBUFFER_VESA_MODE
-	prompt "VESA framebuffer video mode"
-	hex
-	default 0x117
-	depends on BOOTSPLASH
-	help
-	  This option sets the resolution used for the coreboot framebuffer and
-	  bootsplash screen. Set to 0x117 for 1024x768x16. A diligent soul will
-	  some day make this a "choice".
-
-config COREBOOT_KEEP_FRAMEBUFFER
-	prompt "Keep VESA framebuffer"
-	bool
-	depends on BOOTSPLASH
-	help
-	  This option keeps the framebuffer mode set after coreboot finishes
-	  execution. If this option is enabled, coreboot will pass a
-	  framebuffer entry in its coreboot table and the payload will need a
-	  framebuffer driver. If this option is disabled, coreboot will switch
-	  back to text mode before handing control to a payload.
-
 endmenu
 
 menu "Debugging"
@@ -809,6 +863,23 @@
 	  Put llshell() in your (romstage) code to start the shell.
 	  See src/arch/x86/llshell/llshell.inc for details.
 
+if SOUTHBRIDGE_INTEL_BD82X6X && DEFAULT_CONSOLE_LOGLEVEL_8
+# Only visible with the right southbridge and loglevel.
+config DEBUG_INTEL_ME
+	bool "Verbose logging for Intel Management Engine"
+	default n
+	help
+	  Enable verbose logging for Intel Management Engine driver that
+	  is present on Intel 6-series chipsets.
+endif
+
+config DEBUG_CBFS
+	bool "Output verbose CBFS debug messages"
+	default n
+	help
+	  This option enables additional CBFS related debug messages when
+	  enabling console loglevel SPEW.
+
 endmenu
 
 config LIFT_BSP_APIC_ID
@@ -876,3 +947,4 @@
 	  Internal option that controls ENABLE_POWER_BUTTON visibility.
 
 source src/Kconfig.deprecated_options
+source src/vendorcode/Kconfig
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index f98cf5b..c173938 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -91,6 +91,14 @@
 config BOOTBLOCK_SOUTHBRIDGE_INIT
 	string
 
+config HAVE_ARCH_MEMSET
+	bool
+	default y
+
+config HAVE_ARCH_MEMCPY
+	bool
+	default y
+
 config BIG_ENDIAN
 	bool
 	default n
diff --git a/src/arch/x86/Makefile.bootblock.inc b/src/arch/x86/Makefile.bootblock.inc
index f076238..5204ad1 100644
--- a/src/arch/x86/Makefile.bootblock.inc
+++ b/src/arch/x86/Makefile.bootblock.inc
@@ -3,9 +3,11 @@
 
 $(obj)/coreboot.pre: $(obj)/coreboot.romstage $(obj)/coreboot.pre1 $(CBFSTOOL)
 	@printf "    CBFS       $(subst $(obj)/,,$(@))\n"
-	rm -f $@
-	cp $(obj)/coreboot.pre1 $@
-	$(CBFSTOOL) $@ add-stage $(obj)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	cp $(obj)/coreboot.pre1 $@.tmp
+	$(CBFSTOOL) $@.tmp add-stage $(obj)/romstage.elf \
+            $(CONFIG_CBFS_PREFIX)/romstage x 0x$(shell cat $(obj)/location.txt)
+	mv $@.tmp $@
+
 #FIXME: location.txt might require an offset of header size
 
 #######################################################################
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 8c1a887..7abc34f 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -58,13 +58,15 @@
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
 prebuild-files = \
 	$(foreach file,$(cbfs-files), \
-		$(CBFSTOOL) $@ add $(call extract_nth,1,$(file)) $(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) $(call extract_nth,4,$(file)); )
+	$(CBFSTOOL) $@.tmp add $(call extract_nth,1,$(file)) \
+	$(call extract_nth,2,$(file)) $(call extract_nth,3,$(file)) \
+	$(call extract_nth,4,$(file)) &&)
 prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file)))
 
 $(obj)/coreboot.pre1: $(obj)/coreboot.bootblock $$(prebuilt-files) $(CBFSTOOL)
-	rm -f $@
-	$(CBFSTOOL) $@ create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
-	$(prebuild-files)
+	$(CBFSTOOL) $@.tmp create $(CONFIG_COREBOOT_ROMSIZE_KB)K $(obj)/coreboot.bootblock
+	$(prebuild-files) true
+	mv $@.tmp $@
 else
 $(obj)/coreboot.pre1: $(CBFSTOOL)
 	mv $(obj)/coreboot.rom $@
@@ -206,13 +208,6 @@
 
 crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc
 
-ifeq ($(CONFIG_SSE),y)
-crt0s += $(src)/cpu/x86/sse_disable.inc
-endif
-ifeq ($(CONFIG_MMX),y)
-crt0s += $(src)/cpu/x86/mmx_disable.inc
-endif
-
 ifeq ($(CONFIG_BIG_BOOTBLOCK),y)
 crt0s += $(chipset_bootblock_inc)
 ldscripts += $(chipset_bootblock_lds)
@@ -240,7 +235,8 @@
 
 $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc
 	@printf "    POST       romstage.inc\n"
-	sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $^ > $@.tmp
+	sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \
+		-e 's/\^\.section \.text/.section .rom.text/g' $^ > $@.tmp
 	mv $@.tmp $@
 endif
 
diff --git a/src/arch/x86/boot/Makefile.inc b/src/arch/x86/boot/Makefile.inc
index d4a377f..3f11c01 100644
--- a/src/arch/x86/boot/Makefile.inc
+++ b/src/arch/x86/boot/Makefile.inc
@@ -6,8 +6,10 @@
 ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
 ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
 ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.c
 ramstage-$(CONFIG_HAVE_ACPI_RESUME) += wakeup.S
 
 $(obj)/arch/x86/boot/coreboot_table.ramstage.o : $(OPTION_TABLE_H)
+$(obj)/arch/x86/boot/smbios.ramstage.o: $(obj)/build.h
 
diff --git a/src/arch/x86/boot/acpi.c b/src/arch/x86/boot/acpi.c
index 957ec45..7de6674 100644
--- a/src/arch/x86/boot/acpi.c
+++ b/src/arch/x86/boot/acpi.c
@@ -29,8 +29,12 @@
 #include <string.h>
 #include <arch/acpi.h>
 #include <arch/acpigen.h>
+#include <arch/io.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
+#endif
 
 u8 acpi_checksum(u8 *table, u32 length)
 {
@@ -472,8 +476,12 @@
 
 	/* If we happen to be resuming find wakeup vector and jump to OS. */
 	wake_vec = acpi_find_wakeup_vector();
-	if (wake_vec)
+	if (wake_vec) {
+		/* Call mainboard resume handler first, if defined. */
+		if (mainboard_suspend_resume)
+			mainboard_suspend_resume();
 		acpi_jump_to_wakeup(wake_vec);
+	}
 }
 
 /* This is to be filled by SB code - startup value what was found. */
@@ -598,6 +606,10 @@
 	/* Copy wakeup trampoline in place. */
 	memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_ACPI_WAKE_JUMP);
+#endif
+
 	acpi_do_wakeup((u32)vector, acpi_backup_memory, CONFIG_RAMBASE,
 		       HIGH_MEMORY_SAVE);
 }
diff --git a/src/arch/x86/boot/acpigen.c b/src/arch/x86/boot/acpigen.c
index e8cd724..e62aa47 100644
--- a/src/arch/x86/boot/acpigen.c
+++ b/src/arch/x86/boot/acpigen.c
@@ -26,6 +26,7 @@
 #define ACPIGEN_MAXLEN 0xfff
 
 #include <string.h>
+#include <arch/acpi.h>
 #include <arch/acpigen.h>
 #include <console/console.h>
 #include <device/device.h>
@@ -35,7 +36,7 @@
 char *len_stack[ACPIGEN_LENSTACK_SIZE];
 int ltop = 0;
 
-static int acpigen_write_len_f(void)
+int acpigen_write_len_f(void)
 {
 	ASSERT(ltop < (ACPIGEN_LENSTACK_SIZE - 1))
 	    len_stack[ltop++] = gencurrent;
@@ -71,6 +72,26 @@
 	return 1;
 }
 
+int acpigen_write_register(acpi_addr_t *addr)
+{
+	acpigen_emit_byte(0x82);		/* Register Descriptor */
+	acpigen_emit_byte(0x0c);		/* Register Length 7:0 */
+	acpigen_emit_byte(0x00);		/* Register Length 15:8 */
+	acpigen_emit_byte(addr->space_id);	/* Address Space ID */
+	acpigen_emit_byte(addr->bit_width);	/* Register Bit Width */
+	acpigen_emit_byte(addr->bit_offset);	/* Register Bit Offset */
+	acpigen_emit_byte(addr->resv);		/* Register Access Size */
+	acpigen_emit_byte(addr->addrl & 0xff);	/* Register Address Low */
+	acpigen_emit_byte((addr->addrl >> 8) & 0xff);
+	acpigen_emit_byte((addr->addrl >> 16) & 0xff);
+	acpigen_emit_byte((addr->addrl >> 24) & 0xff);
+	acpigen_emit_byte(addr->addrh & 0xff);	/* Register Address High */
+	acpigen_emit_byte((addr->addrh >> 8) & 0xff);
+	acpigen_emit_byte((addr->addrh >> 16) & 0xff);
+	acpigen_emit_byte((addr->addrh >> 24) & 0xff);
+	return 15;
+}
+
 int acpigen_write_package(int nr_el)
 {
 	int len;
@@ -89,6 +110,15 @@
 	return 2;
 }
 
+int acpigen_write_word(unsigned int data)
+{
+	/* word op */
+	acpigen_emit_byte(0xb);
+	acpigen_emit_byte(data & 0xff);
+	acpigen_emit_byte((data >> 8) & 0xff);
+	return 3;
+}
+
 int acpigen_write_dword(unsigned int data)
 {
 	/* dword op */
@@ -315,6 +345,59 @@
 	return acpigen_emit_stream(stream, ARRAY_SIZE(stream));
 }
 
+int acpigen_write_empty_PTC(void)
+{
+/*
+    Name (_PTC, Package (0x02)
+    {
+        ResourceTemplate ()
+        {
+            Register (FFixedHW,
+                0x00,               // Bit Width
+                0x00,               // Bit Offset
+                0x0000000000000000, // Address
+                ,)
+        },
+
+        ResourceTemplate ()
+        {
+            Register (FFixedHW,
+                0x00,               // Bit Width
+                0x00,               // Bit Offset
+                0x0000000000000000, // Address
+                ,)
+        }
+    })
+*/
+	int len, nlen, rlen;
+	acpi_addr_t addr = {
+		.space_id   = ACPI_ADDRESS_SPACE_FIXED,
+		.bit_width  = 0,
+		.bit_offset = 0,
+		.resv       = 0,
+		.addrl      = 0,
+		.addrh      = 0,
+	};
+
+	nlen = acpigen_write_name("_PTC");
+	len = acpigen_write_package(2);
+
+	/* ControlRegister */
+	rlen = acpigen_write_resourcetemplate_header();
+	rlen += acpigen_write_register(&addr);
+	len += acpigen_write_resourcetemplate_footer(rlen);
+	len += rlen;
+
+	/* StatusRegister */
+	rlen = acpigen_write_resourcetemplate_header();
+	rlen += acpigen_write_register(&addr);
+	len += acpigen_write_resourcetemplate_footer(rlen);
+	len += rlen;
+
+	acpigen_patch_len(len - 1);
+	return len + nlen;
+}
+
 /* generates a func with max supported P states */
 int acpigen_write_PPC(u8 nr)
 {
@@ -341,6 +424,91 @@
 	return len;
 }
 
+int acpigen_write_TPC(const char *gnvs_tpc_limit)
+{
+/*
+    // Sample _TPC method
+    Method (_TPC, 0, NotSerialized)
+    {
+        Return (\TLVL)
+    }
+ */
+	int len;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_TPC");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+	len += acpigen_emit_byte(0xa4);		/* ReturnOp */
+	len += acpigen_emit_namestring(gnvs_tpc_limit);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+int acpigen_write_CST_package(u8 level, acpi_cstate_t *cstate)
+{
+/*
+    // Sample C2 state _CST package
+    Package (0x04)
+    {
+        ResourceTemplate ()
+        {
+            Register (SystemIO,
+                0x08,               // Register Bit Width
+                0x00,               // Register Bit Offset
+                0x0000000000000514, // Register Address
+            )
+        },
+        0x02,
+        0x0002,
+        0x000001F4
+    }
+ */
+	int len, rlen;
+	len = acpigen_write_package(4);
+	rlen = acpigen_write_resourcetemplate_header();
+	rlen += acpigen_write_register(&cstate->resource);
+	len += acpigen_write_resourcetemplate_footer(rlen);
+	len += rlen;
+	len += acpigen_write_byte((level > 3) ? 3 : level);
+	len += acpigen_write_word(cstate->latency);
+	len += acpigen_write_dword(cstate->power);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list)
+{
+/*
+    // Sample _TSS package with 100% and 50% duty cycles
+    Name (_TSS, Package (0x02)
+    {
+        Package(){100, 1000, 0, 0x00, 0)
+        Package(){50, 520, 0, 0x18, 0)
+    })
+ */
+	int i, len, plen, nlen;
+	acpi_tstate_t *tstate = tstate_list;
+
+	nlen = acpigen_write_name("_TSS");
+	plen = acpigen_write_package(entries);
+
+	for (i = 0; i < entries; i++) {
+		len = acpigen_write_package(5);
+		len += acpigen_write_dword(tstate->percent);
+		len += acpigen_write_dword(tstate->power);
+		len += acpigen_write_dword(tstate->latency);
+		len += acpigen_write_dword(tstate->control);
+		len += acpigen_write_dword(tstate->status);
+		acpigen_patch_len(len - 1);
+		tstate++;
+		plen += len;
+	}
+
+	acpigen_patch_len(plen - 1);
+	return plen + nlen;
+}
+
 int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat,
 			      u32 busmLat, u32 control, u32 status)
 {
@@ -354,6 +522,10 @@
 	len += acpigen_write_dword(status);
 	//pkglen without the len opcode
 	acpigen_patch_len(len - 1);
+
+	printk(BIOS_DEBUG, "PSS: %uMHz power %u control 0x%x status 0x%x\n",
+	       coreFreq, power, control, status);
+
 	return len;
 }
 
@@ -374,6 +546,23 @@
 	return len + lenh;
 }
 
+int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype)
+{
+	int len, lenh, lenp;
+	lenh = acpigen_write_name("_TSD");
+	lenp = acpigen_write_package(1);
+	len = acpigen_write_package(5);
+	len += acpigen_write_byte(5);	// 5 values
+	len += acpigen_write_byte(0);	// revision 0
+	len += acpigen_write_dword(domain);
+	len += acpigen_write_dword(coordtype);
+	len += acpigen_write_dword(numprocs);
+	acpigen_patch_len(len - 1);
+	len += lenp;
+	acpigen_patch_len(len - 1);
+	return len + lenh;
+}
+
 int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size)
 {
 	/*
diff --git a/src/arch/x86/boot/coreboot_table.c b/src/arch/x86/boot/coreboot_table.c
index db3a8a9..524da6a 100644
--- a/src/arch/x86/boot/coreboot_table.c
+++ b/src/arch/x86/boot/coreboot_table.c
@@ -29,9 +29,21 @@
 #include <version.h>
 #include <device/device.h>
 #include <stdlib.h>
-#if (CONFIG_USE_OPTION_TABLE == 1)
-#include <option_table.h>
 #include <cbfs.h>
+#include <cbmem.h>
+#if CONFIG_USE_OPTION_TABLE
+#include <option_table.h>
+#endif
+#if CONFIG_CHROMEOS
+#include <arch/acpi.h>
+#endif
+#if CONFIG_ADD_FDT
+#include <fdt/fdt.h>
+#include <fdt/libfdt.h>
+#include <fdt/libfdt_env.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
 #endif
 
 static struct lb_header *lb_table_init(unsigned long addr)
@@ -91,7 +103,6 @@
 	return rec;
 }
 
-
 static struct lb_memory *lb_memory(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -112,14 +123,32 @@
 	serial = (struct lb_serial *)rec;
 	serial->tag = LB_TAG_SERIAL;
 	serial->size = sizeof(*serial);
-	serial->ioport = CONFIG_TTYS0_BASE;
+	serial->type = LB_SERIAL_TYPE_IO_MAPPED;
+	serial->baseaddr = CONFIG_TTYS0_BASE;
 	serial->baud = CONFIG_TTYS0_BAUD;
 	return serial;
+#elif CONFIG_CONSOLE_SERIAL8250MEM
+	if (uartmem_getbaseaddr()) {
+		struct lb_record *rec;
+		struct lb_serial *serial;
+		rec = lb_new_record(header);
+		serial = (struct lb_serial *)rec;
+		serial->tag = LB_TAG_SERIAL;
+		serial->size = sizeof(*serial);
+		serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED;
+		serial->baseaddr = uartmem_getbaseaddr();
+		serial->baud = CONFIG_TTYS0_BAUD;
+		return serial;
+	} else {
+		return NULL;
+	}
 #else
 	return NULL;
 #endif
 }
 
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \
+    CONFIG_CONSOLE_LOGBUF || CONFIG_USBDEBUG
 static void add_console(struct lb_header *header, u16 consoletype)
 {
 	struct lb_console *console;
@@ -129,6 +158,7 @@
 	console->size = sizeof(*console);
 	console->type = consoletype;
 }
+#endif
 
 static void lb_console(struct lb_header *header)
 {
@@ -148,7 +178,7 @@
 
 static void lb_framebuffer(struct lb_header *header)
 {
-#if CONFIG_BOOTSPLASH && CONFIG_COREBOOT_KEEP_FRAMEBUFFER
+#if CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
 	void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
 
 	struct lb_framebuffer *framebuffer;
@@ -159,6 +189,187 @@
 #endif
 }
 
+#if CONFIG_CHROMEOS
+static void lb_gpios(struct lb_header *header)
+{
+	struct lb_gpios *gpios;
+	gpios = (struct lb_gpios *)lb_new_record(header);
+	gpios->tag = LB_TAG_GPIO;
+	gpios->size = sizeof(*gpios);
+	gpios->count = 0;
+	fill_lb_gpios(gpios);
+}
+
+static void lb_vdat(struct lb_header *header)
+{
+	struct lb_vdat* vdat;
+
+	vdat = (struct lb_vdat *)lb_new_record(header);
+	vdat->tag = LB_TAG_VDAT;
+	vdat->size = sizeof(*vdat);
+	acpi_get_vdat_info(&vdat->vdat_addr, &vdat->vdat_size);
+}
+
+static void lb_vbnv(struct lb_header *header)
+{
+	struct lb_vbnv* vbnv;
+
+	vbnv = (struct lb_vbnv *)lb_new_record(header);
+	vbnv->tag = LB_TAG_VBNV;
+	vbnv->size = sizeof(*vbnv);
+	vbnv->vbnv_start = CONFIG_VBNV_OFFSET + 14;
+	vbnv->vbnv_size = CONFIG_VBNV_SIZE;
+
+}
+#endif
+
+#if CONFIG_ADD_FDT
+static void lb_map_lb_serial_to_fdt(struct fdt_header *fdt_header, struct lb_serial *serial)
+{
+	char serial_node_name[64];
+	const int name_len = ARRAY_SIZE(serial_node_name) - 1;
+	serial_node_name[name_len] = 0;
+	int root_offset = fdt_path_offset(fdt_header, "/");
+
+	/* Pick a name for the serial node. */
+	if (serial) {
+		sprintf(serial_node_name, "serial@%x", serial->baseaddr);
+	} else {
+		strncpy(serial_node_name, "null-serial@0", name_len);
+	}
+
+	/* Find or create the /aliases node. */
+	int alias_offset = fdt_path_offset(fdt_header, "/aliases");
+	if (alias_offset < 0) {
+		/* It wasn't found, so try to create it. */
+		alias_offset = fdt_add_subnode(fdt_header, root_offset,
+			"/aliases");
+	}
+	if (alias_offset < 0)
+		printk(BIOS_ERR, "Couldn't find/make fdt \"aliases\" node.\n");
+
+	/* Add a "console" property, and point it at the serial node. */
+	if (alias_offset >= 0) {
+		char alias[name_len + 2];
+		sprintf(alias, "/%s", serial_node_name);
+		fdt_setprop_string(fdt_header, alias_offset, "console", alias);
+	}
+
+	/* Add the serial node itself. */
+	int serial_offset =
+		fdt_add_subnode(fdt_header, root_offset, serial_node_name);
+	if (serial_offset < 0) {
+		printk(BIOS_ERR, "Couldn't create serial node \"%s\"\n",
+			serial_node_name);
+	}
+
+	/* If there's a serial node and device, populate the node. */
+	if (serial_offset >= 0 && serial) {
+		fdt_setprop_string(fdt_header, serial_offset,
+			"compatible", "ns16550");
+		uint32_t reg[2] = {
+			cpu_to_fdt32(serial->baseaddr),
+			cpu_to_fdt32(0x8)
+		};
+		fdt_setprop(fdt_header, serial_offset,
+			"reg", reg, sizeof(reg));
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"id", 1);
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"reg-shift", 1);
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"baudrate", serial->baud);
+#if CONFIG_DRIVERS_OXFORD_OXPCIE
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"clock-frequency", 4000000);
+#else
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"clock-frequency", 115200);
+#endif
+		fdt_setprop_cell(fdt_header, serial_offset,
+			"multiplier", 1);
+		if (serial->type == LB_SERIAL_TYPE_IO_MAPPED) {
+			fdt_setprop_cell(fdt_header, serial_offset,
+				"io-mapped", 1);
+		}
+		fdt_setprop_string(fdt_header, serial_offset,
+			"status", "ok");
+	}
+}
+
+static void lb_fdt(struct lb_header *header, struct lb_serial *serial)
+{
+	struct lb_fdt *fdt_record;
+	struct fdt_header *fdt_header;
+	u32 magic, fdt_size;
+
+	fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT);
+	if (!fdt_header) {
+		printk(BIOS_ERR, "Can't find FDT (%s)\n", CONFIG_FDT_FILE_NAME);
+		return;
+	}
+
+	magic = fdt32_to_cpu(fdt_header->magic);
+	if (magic != FDT_MAGIC) {
+		printk(BIOS_ERR, "FDT header corrupted (0x%x)\n", magic);
+		return;
+	}
+
+	fdt_size = fdt32_to_cpu(fdt_header->totalsize);
+	fdt_record = (struct lb_fdt *) lb_new_record(header);
+	fdt_record->tag = LB_TAG_FDT;
+	fdt_record->size = sizeof(*fdt_record) + fdt_size;
+	memcpy(fdt_record + 1, fdt_header, fdt_size);
+	fdt_header = (struct fdt_header *)(fdt_record + 1);
+
+#if CONFIG_CHROMEOS
+	chromeos_set_vboot_data_ptr(fdt_header);
+#endif
+
+	lb_map_lb_serial_to_fdt(fdt_header, serial);
+
+	fdt_size = fdt32_to_cpu(fdt_header->totalsize);
+	fdt_record->size = sizeof(*fdt_record) + fdt_size;
+
+	printk(BIOS_SPEW, "FDT of %d bytes added\n", fdt_size);
+}
+#endif
+
+static void add_cbmem_pointers(struct lb_header *header)
+{
+	/*
+	 * These CBMEM sections' addresses are included in the coreboot table
+	 * with the appropriate tags.
+	 */
+	const struct section_id {
+		int cbmem_id;
+		int table_tag;
+	} section_ids[] = {
+		{CBMEM_ID_TIMESTAMP, LB_TAG_TIMESTAMPS},
+		{CBMEM_ID_MRCDATA, LB_TAG_MRC_CACHE},
+		{CBMEM_ID_CONSOLE, LB_TAG_CBMEM_CONSOLE}
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(section_ids); i++) {
+		const struct section_id *sid = section_ids + i;
+		struct lb_cbmem_ref *cbmem_ref;
+		void *cbmem_addr = cbmem_find(sid->cbmem_id);
+
+		if (!cbmem_addr)
+			continue;  /* This section is not present */
+
+		cbmem_ref = (struct lb_cbmem_ref *)lb_new_record(header);
+		if (!cbmem_ref) {
+			printk(BIOS_ERR, "No more room in coreboot table!\n");
+			break;
+		}
+		cbmem_ref->tag = sid->table_tag;
+		cbmem_ref->size = sizeof(*cbmem_ref);
+		cbmem_ref->cbmem_addr = cbmem_addr;
+	}
+}
+
 static struct lb_mainboard *lb_mainboard(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -183,7 +394,7 @@
 	return mainboard;
 }
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 static struct cmos_checksum *lb_cmos_checksum(struct lb_header *header)
 {
 	struct lb_record *rec;
@@ -305,9 +516,10 @@
 	head->table_checksum = compute_ip_checksum(first_rec, head->table_bytes);
 	head->header_checksum = 0;
 	head->header_checksum = compute_ip_checksum(head, sizeof(*head));
-	printk(BIOS_DEBUG, "Wrote coreboot table at: %p - %p  checksum %x\n",
-		head, rec, head->table_checksum);
-	return (unsigned long)rec;
+	printk(BIOS_DEBUG,
+	       "Wrote coreboot table at: %p, 0x%x bytes, checksum %x\n",
+	       head, head->table_bytes, head->table_checksum);
+	return (unsigned long)rec + rec->size;
 }
 
 static void lb_cleanup_memory_ranges(struct lb_memory *mem)
@@ -497,10 +709,6 @@
 		lb_add_rsvd_range, mem);
 }
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
-extern uint64_t high_tables_base, high_tables_size;
-#endif
-
 unsigned long write_coreboot_table(
 	unsigned long low_table_start, unsigned long low_table_end,
 	unsigned long rom_table_start, unsigned long rom_table_end)
@@ -508,7 +716,7 @@
 	struct lb_header *head;
 	struct lb_memory *mem;
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Writing high table forward entry at 0x%08lx\n",
 			low_table_end);
 	head = lb_table_init(low_table_end);
@@ -544,7 +752,7 @@
 	rom_table_end &= ~0xffff;
 	printk(BIOS_DEBUG, "0x%08lx \n", rom_table_end);
 
-#if (CONFIG_USE_OPTION_TABLE == 1)
+#if CONFIG_USE_OPTION_TABLE
 	{
 		struct cmos_option_table *option_table = cbfs_find_file("cmos_layout.bin", 0x1aa);
 		if (option_table) {
@@ -569,7 +777,7 @@
 	lb_add_memory_range(mem, LB_MEM_TABLE,
 		rom_table_start, rom_table_end-rom_table_start);
 
-#if CONFIG_WRITE_HIGH_TABLES == 1
+#if CONFIG_WRITE_HIGH_TABLES
 	printk(BIOS_DEBUG, "Adding high table area\n");
 	// should this be LB_MEM_ACPI?
 	lb_add_memory_range(mem, LB_MEM_TABLE,
@@ -579,7 +787,7 @@
 	/* Add reserved regions */
 	add_lb_reserved(mem);
 
-#if (CONFIG_HAVE_MAINBOARD_RESOURCES == 1)
+#if CONFIG_HAVE_MAINBOARD_RESOURCES
 	add_mainboard_resources(mem);
 #endif
 
@@ -595,7 +803,8 @@
 	/* Record our motherboard */
 	lb_mainboard(head);
 	/* Record the serial port, if present */
-	lb_serial(head);
+	struct lb_serial *serial;
+	serial = lb_serial(head);
 	/* Record our console setup */
 	lb_console(head);
 	/* Record our various random string information */
@@ -603,6 +812,25 @@
 	/* Record our framebuffer */
 	lb_framebuffer(head);
 
+#if CONFIG_CHROMEOS
+	/* Record our GPIO settings (ChromeOS specific) */
+	lb_gpios(head);
+
+	/* pass along the VDAT buffer adress */
+	lb_vdat(head);
+
+	/* pass along VBNV offsets in CMOS */
+	lb_vbnv(head);
+#endif
+#if CONFIG_ADD_FDT
+	/*
+	 * Copy FDT from CBFS into the coreboot table possibly augmenting it
+	 * along the way.
+	 */
+	lb_fdt(head, serial);
+#endif
+	add_cbmem_pointers(head);
+
 	/* Remember where my valid memory ranges are */
 	return lb_table_fini(head, 1);
 
diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
new file mode 100644
index 0000000..dc0c53d
--- /dev/null
+++ b/src/arch/x86/boot/smbios.c
@@ -0,0 +1,308 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include <smbios.h>
+#include <console/console.h>
+#include <build.h>
+#include <device/device.h>
+#include <arch/cpu.h>
+#include <cpu/x86/name.h>
+#include <cbfs.h>
+#include <arch/byteorder.h>
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
+
+static u8 smbios_checksum(u8 *p, u32 length)
+{
+	u8 ret = 0;
+	while (length--)
+		ret += *p++;
+	return -ret;
+}
+
+
+int smbios_add_string(char *start, const char *str)
+{
+	int i = 1;
+	char *p = start;
+
+	for(;;) {
+		if (!*p) {
+			strcpy(p, str);
+			p += strlen(str);
+			*p++ = '\0';
+			*p++ = '\0';
+			return i;
+		}
+
+		if (!strcmp(p, str))
+			return i;
+
+		p += strlen(p)+1;
+		i++;
+	}
+}
+
+int smbios_string_table_len(char *start)
+{
+	char *p = start;
+	int i, len = 0;
+
+	while(*p) {
+		i = strlen(p) + 1;
+		p += i;
+		len += i;
+	}
+	return len + 1;
+}
+
+static int smbios_cpu_vendor(char *start)
+{
+	char tmp[13];
+	u32 *_tmp = (u32 *)tmp;
+	struct cpuid_result res = cpuid(0);
+
+	_tmp[0] = res.ebx;
+	_tmp[1] = res.edx;
+	_tmp[2] = res.ecx;
+	tmp[12] = '\0';
+	return smbios_add_string(start, tmp);
+
+}
+
+static int smbios_processor_name(char *start)
+{
+	char tmp[49];
+	u32  *_tmp = (u32 *)tmp;
+	struct cpuid_result res;
+	int i;
+
+	for (i = 0; i < 3; i++) {
+		res = cpuid(0x80000002 + i);
+		_tmp[i * 4 + 0] = res.eax;
+		_tmp[i * 4 + 1] = res.ebx;
+		_tmp[i * 4 + 2] = res.ecx;
+		_tmp[i * 4 + 3] = res.edx;
+	}
+
+	tmp[48] = 0;
+	return smbios_add_string(start, tmp);
+}
+
+static int smbios_write_type0(unsigned long *current, int handle)
+{
+	struct cbfs_header *hdr;
+	struct smbios_type0 *t = (struct smbios_type0 *)*current;
+	int len = sizeof(struct smbios_type0);
+
+	memset(t, 0, sizeof(struct smbios_type0));
+	t->type = SMBIOS_BIOS_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+
+	t->vendor = smbios_add_string(t->eos, "coreboot");
+#if !CONFIG_CHROMEOS
+	t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
+	t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION);
+#else
+#define SPACES \
+	"                                                                  "
+	t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE);
+	u32 version_offset = (u32)smbios_string_table_len(t->eos);
+	t->bios_version = smbios_add_string(t->eos, SPACES);
+	/* SMBIOS offsets start at 1 rather than 0 */
+	vboot_data->vbt10 = (u32)t->eos + (version_offset - 1);
+#endif
+
+	if ((hdr = get_cbfs_header()) != (struct cbfs_header *)0xffffffff)
+		t->bios_rom_size = (ntohl(hdr->romsize) / 65535) - 1;
+	t->system_bios_major_release = 4;
+	t->bios_characteristics =
+		BIOS_CHARACTERISTICS_PCI_SUPPORTED |
+#if CONFIG_CARDBUS_PLUGIN_SUPPORT
+		BIOS_CHARACTERISTICS_PC_CARD |
+#endif
+		BIOS_CHARACTERISTICS_SELECTABLE_BOOT |
+		BIOS_CHARACTERISTICS_UPGRADEABLE;
+
+#if CONFIG_GENERATE_ACPI_TABLES
+	t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI;
+#endif
+	t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET;
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type1(unsigned long *current, int handle)
+{
+	struct smbios_type1 *t = (struct smbios_type1 *)*current;
+	int len = sizeof(struct smbios_type1);
+
+	memset(t, 0, sizeof(struct smbios_type1));
+	t->type = SMBIOS_SYSTEM_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR);
+	t->product_name = smbios_add_string(t->eos, CONFIG_MAINBOARD_PART_NUMBER);
+	t->serial_number = smbios_add_string(t->eos, "123456789");
+	t->version = smbios_add_string(t->eos, "1.0");
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type3(unsigned long *current, int handle)
+{
+	struct smbios_type3 *t = (struct smbios_type3 *)*current;
+	int len = sizeof(struct smbios_type3);
+
+	memset(t, 0, sizeof(struct smbios_type3));
+	t->type = SMBIOS_SYSTEM_ENCLOSURE;
+	t->handle = handle;
+	t->length = len - 2;
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR);
+	t->bootup_state = SMBIOS_STATE_SAFE;
+	t->power_supply_state = SMBIOS_STATE_SAFE;
+	t->thermal_state = SMBIOS_STATE_SAFE;
+	t->_type = 3;
+	t->security_status = SMBIOS_STATE_SAFE;
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type4(unsigned long *current, int handle)
+{
+	struct cpuid_result res;
+	struct smbios_type4 *t = (struct smbios_type4 *)*current;
+	int len = sizeof(struct smbios_type4);
+
+	res = cpuid(1);
+
+	memset(t, 0, sizeof(struct smbios_type4));
+	t->type = SMBIOS_PROCESSOR_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+	t->processor_id[0] = res.eax;
+	t->processor_id[1] = res.edx;
+	t->processor_manufacturer = smbios_cpu_vendor(t->eos);
+	t->processor_version = smbios_processor_name(t->eos);
+	t->processor_family = 0x0c;
+	t->processor_type = 3; /* System Processor */
+	t->processor_upgrade = 0x06;
+	t->core_count = (res.ebx >> 16) & 0xff;
+	t->l1_cache_handle = 0xffff;
+	t->l2_cache_handle = 0xffff;
+	t->l3_cache_handle = 0xffff;
+	t->processor_upgrade = 1;
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type32(unsigned long *current, int handle)
+{
+	struct smbios_type32 *t = (struct smbios_type32 *)*current;
+	int len = sizeof(struct smbios_type32);
+
+	memset(t, 0, sizeof(struct smbios_type32));
+	t->type = SMBIOS_SYSTEM_BOOT_INFORMATION;
+	t->handle = handle;
+	t->length = len - 2;
+	*current += len;
+	return len;
+}
+
+static int smbios_write_type127(unsigned long *current, int handle)
+{
+	struct smbios_type127 *t = (struct smbios_type127 *)*current;
+	int len = sizeof(struct smbios_type127);
+
+	memset(t, 0, sizeof(struct smbios_type127));
+	t->type = SMBIOS_END_OF_TABLE;
+	t->handle = handle;
+	t->length = len - 2;
+	*current += len;
+	return len;
+}
+
+static int smbios_walk_device_tree(device_t tree, int *handle, unsigned long *current)
+{
+	device_t dev;
+	int len = 0;
+
+	for(dev = tree; dev; dev = dev->next) {
+		printk(BIOS_INFO, "%s (%s)\n", dev_path(dev), dev->chip_ops ? dev->chip_ops->name : "");
+
+		if (dev->ops && dev->ops->get_smbios_data)
+			len += dev->ops->get_smbios_data(dev, handle, current);
+
+		if (dev->chip_ops && dev->chip_ops->get_smbios_data)
+			len += dev->chip_ops->get_smbios_data(dev, handle, current);
+	}
+	return len;
+}
+
+unsigned long smbios_write_tables(unsigned long current)
+{
+	struct smbios_entry *se;
+	unsigned long tables;
+	int len, handle = 0;
+
+	current = ALIGN(current, 16);
+	printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current);
+
+	se = (struct smbios_entry *)current;
+	current += sizeof(struct smbios_entry);
+	current = ALIGN(current, 16);
+
+	tables = current;
+	len = smbios_write_type0(&current, handle++);
+	len += smbios_write_type1(&current, handle++);
+	len += smbios_write_type3(&current, handle++);
+	len += smbios_write_type4(&current, handle++);
+	len += smbios_write_type32(&current, handle++);
+
+	len += smbios_walk_device_tree(all_devices, &handle, &current);
+
+	len += smbios_write_type127(&current, handle++);
+
+	memset(se, 0, sizeof(struct smbios_entry));
+	memcpy(se->anchor, "_SM_", 4);
+	se->length = sizeof(struct smbios_entry);
+	se->major_version = 2;
+	se->minor_version = 7;
+	se->max_struct_size = 24;
+	se->struct_count = handle;
+	memcpy(se->intermediate_anchor_string, "_DMI_", 5);
+
+	se->struct_table_address = (u32)tables;
+	se->struct_table_length = len;
+
+	se->intermediate_checksum = smbios_checksum((u8 *)se + 0x10,
+						    sizeof(struct smbios_entry) - 0x10);
+	se->checksum = smbios_checksum((u8 *)se, sizeof(struct smbios_entry));
+	return current;
+}
diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c
index d816e76..b7dc4fe 100644
--- a/src/arch/x86/boot/tables.c
+++ b/src/arch/x86/boot/tables.c
@@ -31,6 +31,7 @@
 #include <cpu/x86/multiboot.h>
 #include <cbmem.h>
 #include <lib.h>
+#include <smbios.h>
 
 uint64_t high_tables_base = 0;
 uint64_t high_tables_size;
@@ -120,7 +121,7 @@
 #endif /* CONFIG_GENERATE_MP_TABLE */
 
 #if CONFIG_GENERATE_ACPI_TABLES == 1
-#define MAX_ACPI_SIZE (47 * 1024)
+#define MAX_ACPI_SIZE (45 * 1024)
 	post_code(0x9c);
 
 	/* Write ACPI tables to F segment and high tables area */
@@ -178,9 +179,30 @@
 	}
 
 #endif
+#define MAX_SMBIOS_SIZE 2048
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_SMBIOS, MAX_SMBIOS_SIZE);
+	if (high_table_pointer) {
+		unsigned long new_high_table_pointer;
 
+		new_high_table_pointer = smbios_write_tables(high_table_pointer);
+		rom_table_end = ALIGN(rom_table_end, 16);
+		memcpy((void *)rom_table_end, (void *)high_table_pointer, sizeof(struct smbios_entry));
+		rom_table_end += sizeof(struct smbios_entry);
 
-#define MAX_COREBOOT_TABLE_SIZE (8 * 1024)
+		if (new_high_table_pointer > ( high_table_pointer + MAX_SMBIOS_SIZE)) {
+			printk(BIOS_ERR, "ERROR: Increase SMBIOS size\n");
+		}
+                printk(BIOS_DEBUG, "SMBIOS tables: %ld bytes.\n",
+				new_high_table_pointer - high_table_pointer);
+	} else {
+		unsigned long new_rom_table_end = smbios_write_tables(rom_table_end);
+		printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end - rom_table_end);
+		rom_table_end = ALIGN(new_rom_table_end, 16);
+	}
+#endif
+
+#define MAX_COREBOOT_TABLE_SIZE (32 * 1024)
 	post_code(0x9d);
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, MAX_COREBOOT_TABLE_SIZE);
diff --git a/src/arch/x86/boot/wakeup.S b/src/arch/x86/boot/wakeup.S
index a1df4d5..2f3f6eb 100644
--- a/src/arch/x86/boot/wakeup.S
+++ b/src/arch/x86/boot/wakeup.S
@@ -38,23 +38,11 @@
 	movw	%ax, (__wakeup_segment)
 
 	/* Then overwrite coreboot with our backed up memory */
-	movl 8(%esp), %esi
-	movl 12(%esp), %edi
-	movl 16(%esp), %ecx
-	shrl	$4, %ecx
-1:
-	movl	0(%esi),%eax
-	movl	4(%esi),%edx
-	movl	8(%esi),%ebx
-	movl	12(%esi),%ebp
-	addl	$16,%esi
-	subl	$1,%ecx
-	movl	%eax,0(%edi)
-	movl	%edx,4(%edi)
-	movl	%ebx,8(%edi)
-	movl	%ebp,12(%edi)
-	leal	16(%edi),%edi
-	jne	1b
+	movl	8(%esp), %esi
+	movl	12(%esp), %edi
+	movl	16(%esp), %ecx
+	shrl	$2, %ecx
+	rep	movsl
 
 	/* Activate the right segment descriptor real mode. */
 	ljmp	$0x28, $RELOCATED(1f)
diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h
index 030745d..dc674d0 100644
--- a/src/arch/x86/include/arch/acpi.h
+++ b/src/arch/x86/include/arch/acpi.h
@@ -66,6 +66,12 @@
 #define ACPI_ADDRESS_SPACE_EC		   3	/* Embedded controller */
 #define ACPI_ADDRESS_SPACE_SMBUS	   4	/* SMBus */
 #define ACPI_ADDRESS_SPACE_FIXED	0x7f	/* Functional fixed hardware */
+#define  ACPI_FFIXEDHW_VENDOR_INTEL	   1	/* Intel */
+#define  ACPI_FFIXEDHW_CLASS_HLT	   0	/* C1 Halt */
+#define  ACPI_FFIXEDHW_CLASS_IO_HLT	   1	/* C1 I/O then Halt */
+#define  ACPI_FFIXEDHW_CLASS_MWAIT	   2    /* MWAIT Native C-state */
+#define  ACPI_FFIXEDHW_FLAG_HW_COORD	   1	/* Hardware Coordination bit */
+#define  ACPI_FFIXEDHW_FLAG_BM_STS  	   2	/* BM_STS avoidance bit */
 /* 0x80-0xbf: Reserved */
 /* 0xc0-0xff: OEM defined */
 
@@ -357,6 +363,20 @@
 	u8 ec_id[];				/* EC ID  */
 } __attribute__ ((packed)) acpi_ecdt_t;
 
+typedef struct acpi_cstate {
+	u16 latency;
+	u32 power;
+	acpi_addr_t resource;
+} __attribute__ ((packed)) acpi_cstate_t;
+
+typedef struct acpi_tstate {
+	u32 percent;
+	u32 power;
+	u32 latency;
+	u32 control;
+	u32 status;
+} __attribute__ ((packed)) acpi_tstate_t;
+
 /* These are implemented by the target port or north/southbridge. */
 unsigned long write_acpi_tables(unsigned long addr);
 unsigned long acpi_fill_madt(unsigned long current);
@@ -417,12 +437,14 @@
 extern u8 acpi_slp_type;
 
 void suspend_resume(void);
+void __attribute__((weak)) mainboard_suspend_resume(void);
 void *acpi_find_wakeup_vector(void);
 void *acpi_get_wakeup_rsdp(void);
 void acpi_jump_to_wakeup(void *wakeup_addr);
 
 int acpi_get_sleep_type(void);
-
+#else
+#define acpi_slp_type 0
 #endif
 
 /* northbridge/amd/amdfam10/amdfam10_acpi.c */
@@ -434,7 +456,11 @@
 #else // CONFIG_GENERATE_ACPI_TABLES
 
 #define write_acpi_tables(start) (start)
+#define acpi_slp_type 0
 
 #endif
 
+#if CONFIG_CHROMEOS
+void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size);
+#endif
 #endif
diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h
index 6f13a7a..676ed6b 100644
--- a/src/arch/x86/include/arch/acpigen.h
+++ b/src/arch/x86/include/arch/acpigen.h
@@ -24,14 +24,19 @@
 #include <stdlib.h>
 #include <stdint.h>
 
+#include <arch/acpi.h>
+
 void acpigen_patch_len(int len);
 void acpigen_set_current(char *curr);
 char *acpigen_get_current(void);
+int acpigen_write_len_f(void);
 int acpigen_write_package(int nr_el);
+int acpigen_write_register(acpi_addr_t *addr);
 int acpigen_write_byte(unsigned int data);
 int acpigen_emit_byte(unsigned char data);
 int acpigen_emit_stream(const char *data, int size);
 int acpigen_emit_namestring(const char *namepath);
+int acpigen_write_word(unsigned int data);
 int acpigen_write_dword(unsigned int data);
 int acpigen_write_qword(uint64_t data);
 int acpigen_write_name(const char *name);
@@ -40,11 +45,16 @@
 int acpigen_write_name_byte(const char *name, uint8_t val);
 int acpigen_write_scope(const char *name);
 int acpigen_write_PPC(u8 nr);
+int acpigen_write_TPC(const char *gnvs_tpc_limit);
 int acpigen_write_empty_PCT(void);
+int acpigen_write_empty_PTC(void);
+int acpigen_write_CST_package(u8 level, acpi_cstate_t *cstate);
+int acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list);
 int acpigen_write_PSS_package(u32 coreFreq, u32 power, u32 transLat, u32 busmLat,
 			u32 control, u32 status);
 typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord;
 int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
+int acpigen_write_TSD_package(u32 domain, u32 numprocs, PSD_coord coordtype);
 int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len);
 int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size);
 int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16);
diff --git a/src/arch/x86/include/arch/byteorder.h b/src/arch/x86/include/arch/byteorder.h
index ab344e6..7ba6290 100644
--- a/src/arch/x86/include/arch/byteorder.h
+++ b/src/arch/x86/include/arch/byteorder.h
@@ -5,10 +5,14 @@
 
 #include <swab.h>
 
+#define cpu_to_le64(x) ((unsigned long)(x))
+#define le64_to_cpu(x) ((unsigned long)(x))
 #define cpu_to_le32(x) ((unsigned int)(x))
 #define le32_to_cpu(x) ((unsigned int)(x))
 #define cpu_to_le16(x) ((unsigned short)(x))
 #define le16_to_cpu(x) ((unsigned short)(x))
+#define cpu_to_be64(x) swab64(x)
+#define be64_to_cpu(x) swab64(x)
 #define cpu_to_be32(x) swab32((x))
 #define be32_to_cpu(x) swab32((x))
 #define cpu_to_be16(x) swab16((x))
diff --git a/src/arch/x86/include/arch/coreboot_tables.h b/src/arch/x86/include/arch/coreboot_tables.h
index 773e053..b177949 100644
--- a/src/arch/x86/include/arch/coreboot_tables.h
+++ b/src/arch/x86/include/arch/coreboot_tables.h
@@ -20,4 +20,6 @@
 int add_mainboard_resources(struct lb_memory *mem);
 int add_northbridge_resources(struct lb_memory *mem);
 
+void fill_lb_gpios(struct lb_gpios *gpios);
+
 #endif /* COREBOOT_TABLE_H */
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 4d7be86..14acfdf 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -36,12 +36,36 @@
 {
 	struct cpuid_result result;
 	asm volatile(
-		"cpuid"
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
 		: "=a" (result.eax),
-		  "=b" (result.ebx),
+		  "=S" (result.ebx),
 		  "=c" (result.ecx),
 		  "=d" (result.edx)
-		: "0" (op));
+		: "0" (op)
+		: "edi");
+	return result;
+}
+
+/*
+ * Generic Extended CPUID function
+ */
+static inline struct cpuid_result cpuid_ext(int op, unsigned ecx)
+{
+	struct cpuid_result result;
+	asm volatile(
+		"mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%ebx, %%esi;"
+		"mov %%edi, %%ebx;"
+		: "=a" (result.eax),
+		  "=S" (result.ebx),
+		  "=c" (result.ecx),
+		  "=d" (result.edx)
+		: "0" (op), "2" (ecx)
+		: "edi");
 	return result;
 }
 
@@ -52,10 +76,12 @@
 {
 	unsigned int eax;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax)
 		: "0" (op)
-		: "ebx", "ecx", "edx");
+		: "ecx", "edx", "edi");
 	return eax;
 }
 
@@ -63,10 +89,13 @@
 {
 	unsigned int eax, ebx;
 
-	__asm__("cpuid"
-		: "=a" (eax), "=b" (ebx)
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
+		"mov %%edi, %%esi;"
+		: "=a" (eax), "=S" (ebx)
 		: "0" (op)
-		: "ecx", "edx" );
+		: "ecx", "edx", "edi");
 	return ebx;
 }
 
@@ -74,10 +103,12 @@
 {
 	unsigned int eax, ecx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=c" (ecx)
 		: "0" (op)
-		: "ebx", "edx" );
+		: "edx", "edi");
 	return ecx;
 }
 
@@ -85,10 +116,12 @@
 {
 	unsigned int eax, edx;
 
-	__asm__("cpuid"
+	__asm__("mov %%ebx, %%edi;"
+		"cpuid;"
+		"mov %%edi, %%ebx;"
 		: "=a" (eax), "=d" (edx)
 		: "0" (op)
-		: "ebx", "ecx");
+		: "ecx", "edi");
 	return edx;
 }
 
@@ -113,11 +146,16 @@
 	unsigned device;
 };
 
+struct acpi_cstate;
 struct cpu_driver {
 	struct device_operations *ops;
 	struct cpu_device_id *id_table;
+	struct acpi_cstate *cstates;
 };
 
+struct device;
+struct cpu_driver *find_cpu_driver(struct device *cpu);
+
 struct cpu_info {
 	device_t cpu;
 	unsigned long index;
diff --git a/src/arch/x86/include/arch/ebda.h b/src/arch/x86/include/arch/ebda.h
new file mode 100644
index 0000000..1de6097
--- /dev/null
+++ b/src/arch/x86/include/arch/ebda.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARCH_EBDA_H
+#define __ARCH_EBDA_H
+
+#define X86_BDA_SIZE		0x200
+#define X86_BDA_BASE		0x400
+#define X86_EBDA_SEGMENT	0x40e
+#define X86_EBDA_LOWMEM		0x413
+
+#define DEFAULT_EBDA_LOWMEM	(1024 << 10)
+#define DEFAULT_EBDA_SEGMENT	0xF600
+#define DEFAULT_EBDA_SIZE	0x400
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size);
+void setup_default_ebda(void);
+
+#endif
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index aad8408..544d6e22 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -6,9 +6,9 @@
 /*
  * This file contains the definitions for the x86 IO instructions
  * inb/inw/inl/outb/outw/outl and the "string versions" of the same
- * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
- * versions of the single-IO instructions (inb_p/inw_p/..).
+ * (insb/insw/insl/outsb/outsw/outsl).
  */
+
 #if defined(__ROMCC__)
 static inline void outb(uint8_t value, uint16_t port)
 {
diff --git a/src/arch/x86/include/arch/stages.h b/src/arch/x86/include/arch/stages.h
index 00d2a93..3ddba51 100644
--- a/src/arch/x86/include/arch/stages.h
+++ b/src/arch/x86/include/arch/stages.h
@@ -19,7 +19,6 @@
 
 #ifndef __ARCH_STAGES_H
 #define __ARCH_STAGES_H
-void cbfs_and_run_core(const char *filename, unsigned int ebp);
 void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset);
 void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr);
 #endif
diff --git a/src/arch/x86/include/bootblock_common.h b/src/arch/x86/include/bootblock_common.h
index 4c4a092..c53b478 100644
--- a/src/arch/x86/include/bootblock_common.h
+++ b/src/arch/x86/include/bootblock_common.h
@@ -1,3 +1,14 @@
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/tsc.h>
+
+static void post_code(uint16_t value)
+{
+	outb(value, 0x80);
+	outb(value >> 8, 0x90);
+}
+
 #if CONFIG_LOGICAL_CPUS && \
  (defined(CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT) || defined(CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT))
 #include <cpu/x86/lapic/boot_cpu.c>
diff --git a/src/arch/x86/init/bootblock.ld b/src/arch/x86/init/bootblock.ld
index eab64cf..45b752d 100644
--- a/src/arch/x86/init/bootblock.ld
+++ b/src/arch/x86/init/bootblock.ld
@@ -50,5 +50,12 @@
 		*(.note.*)
 	}
 
+	. = CONFIG_DCACHE_RAM_BASE;
+	.car.data . (NOLOAD) : {
+		*(.car.global_data);
+		*(.car.cbmem_console);
+	}
+
+	_bogus = ASSERT((SIZEOF(.car.data) <= CONFIG_DCACHE_RAM_SIZE), "Cache as RAM area is too full");
 	_bogus = ASSERT((SIZEOF(.bss) + SIZEOF(.data)) == 0 || CONFIG_AMD_AGESA, "Do not use global variables in romstage");
 }
diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc
index 3092388..8483b62 100644
--- a/src/arch/x86/lib/Makefile.inc
+++ b/src/arch/x86/lib/Makefile.inc
@@ -6,8 +6,15 @@
 ramstage-y += pci_ops_auto.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c
+ramstage-y += memset.c
+ramstage-y += memcpy.c
+ramstage-y += ebda.c
 
 romstage-y += romstage_console.c
 romstage-y += cbfs_and_run.c
+romstage-y += memset.c
+romstage-y += memcpy.c
+
+smm-y += memcpy.c
 
 $(obj)/arch/x86/lib/console.ramstage.o :: $(obj)/build.h
diff --git a/src/arch/x86/lib/cbfs_and_run.c b/src/arch/x86/lib/cbfs_and_run.c
index 5e3d8fe..67e21c3 100644
--- a/src/arch/x86/lib/cbfs_and_run.c
+++ b/src/arch/x86/lib/cbfs_and_run.c
@@ -20,16 +20,19 @@
 #include <console/console.h>
 #include <cbfs.h>
 #include <arch/stages.h>
+#include <timestamp.h>
 
-void cbfs_and_run_core(const char *filename, unsigned ebp)
+static void cbfs_and_run_core(const char *filename, unsigned ebp)
 {
 	u8 *dst;
 
+        timestamp_add_now(TS_START_COPYRAM);
 	print_debug("Loading image.\n");
 	dst = cbfs_load_stage(filename);
 	if ((void *)dst == (void *) -1)
 		die("FATAL: Essential component is missing.\n");
 
+        timestamp_add_now(TS_END_COPYRAM);
 	print_debug("Jumping to image.\n");
 	__asm__ volatile (
 		"movl %%eax, %%ebp\n"
diff --git a/src/arch/x86/lib/cpu.c b/src/arch/x86/lib/cpu.c
index 3732ae2..596a592 100644
--- a/src/arch/x86/lib/cpu.c
+++ b/src/arch/x86/lib/cpu.c
@@ -192,23 +192,27 @@
 	}
 }
 
-static void set_cpu_ops(struct device *cpu)
+struct cpu_driver *find_cpu_driver(struct device *cpu)
 {
 	struct cpu_driver *driver;
-	cpu->ops = 0;
 	for (driver = cpu_drivers; driver < ecpu_drivers; driver++) {
 		struct cpu_device_id *id;
-		for(id = driver->id_table; id->vendor != X86_VENDOR_INVALID; id++) {
+		for (id = driver->id_table;
+		     id->vendor != X86_VENDOR_INVALID; id++) {
 			if ((cpu->vendor == id->vendor) &&
 				(cpu->device == id->device))
 			{
-				goto found;
+				return driver;
 			}
 		}
 	}
-	return;
- found:
-	cpu->ops = driver->ops;
+	return NULL;
+}
+
+static void set_cpu_ops(struct device *cpu)
+{
+	struct cpu_driver *driver = find_cpu_driver(cpu);
+	cpu->ops = driver ? driver->ops : NULL;
 }
 
 void cpu_initialize(void)
diff --git a/src/arch/x86/lib/ebda.c b/src/arch/x86/lib/ebda.c
new file mode 100644
index 0000000..fb407b6
--- /dev/null
+++ b/src/arch/x86/lib/ebda.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/ebda.h>
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
+
+void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Skip in S3 resume path */
+	if (acpi_slp_type == 3)
+		return;
+#endif
+
+	if (!low_memory_size || !ebda_segment || !ebda_size)
+		return;
+
+	/* clear BIOS DATA AREA */
+	memset((void *)X86_BDA_BASE, 0, X86_BDA_SIZE);
+
+	write16(X86_EBDA_LOWMEM, (low_memory_size >> 10));
+	write16(X86_EBDA_SEGMENT, ebda_segment);
+
+	/* Set up EBDA */
+	memset((void *)(ebda_segment << 4), 0, ebda_size);
+	write16((ebda_segment << 4), (ebda_size >> 10));
+}
+
+void setup_default_ebda(void)
+{
+	setup_ebda(DEFAULT_EBDA_LOWMEM,
+		   DEFAULT_EBDA_SEGMENT,
+		   DEFAULT_EBDA_SIZE);
+}
diff --git a/src/arch/x86/lib/memcpy.c b/src/arch/x86/lib/memcpy.c
new file mode 100644
index 0000000..de21092
--- /dev/null
+++ b/src/arch/x86/lib/memcpy.c
@@ -0,0 +1,13 @@
+#include <string.h>
+
+void *memcpy(void *__restrict __dest,
+	     __const void *__restrict __src, size_t __n)
+{
+	asm("cld\n"
+	    "rep\n"
+	    "movsb"
+	    :	/* no input (?) */
+	    :"S"(__src), "D"(__dest), "c"(__n)
+	);
+	return __dest;
+}
diff --git a/src/arch/x86/lib/memset.c b/src/arch/x86/lib/memset.c
new file mode 100644
index 0000000..e850726
--- /dev/null
+++ b/src/arch/x86/lib/memset.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (C) 1991,1992,1993,1997,1998,2003, 2005 Free Software Foundation, Inc.
+ * This file is part of the GNU C Library.
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* From glibc-2.14, sysdeps/i386/memset.c */
+
+#include <string.h>
+#include <stdint.h>
+
+typedef uint32_t op_t;
+
+void *memset(void *dstpp, int c, size_t len)
+{
+	int d0;
+	unsigned long int dstp = (unsigned long int) dstpp;
+
+	/* This explicit register allocation improves code very much indeed. */
+	register op_t x asm("ax");
+
+	x = (unsigned char) c;
+
+	/* Clear the direction flag, so filling will move forward.  */
+	asm volatile("cld");
+
+	/* This threshold value is optimal.  */
+	if (len >= 12) {
+		/* Fill X with four copies of the char we want to fill with. */
+		x |= (x << 8);
+		x |= (x << 16);
+
+		/* Adjust LEN for the bytes handled in the first loop.  */
+		len -= (-dstp) % sizeof(op_t);
+
+		/*
+		 * There are at least some bytes to set. No need to test for
+		 * LEN == 0 in this alignment loop.
+		 */
+
+		/* Fill bytes until DSTP is aligned on a longword boundary. */
+		asm volatile(
+			"rep\n"
+			"stosb" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" ((-dstp) % sizeof(op_t)), "a" (x) :
+			"memory");
+
+		/* Fill longwords.  */
+		asm volatile(
+			"rep\n"
+			"stosl" /* %0, %2, %3 */ :
+			"=D" (dstp), "=c" (d0) :
+			"0" (dstp), "1" (len / sizeof(op_t)), "a" (x) :
+			"memory");
+		len %= sizeof(op_t);
+	}
+
+	/* Write the last few bytes. */
+	asm volatile(
+		"rep\n"
+		"stosb" /* %0, %2, %3 */ :
+		"=D" (dstp), "=c" (d0) :
+		"0" (dstp), "1" (len), "a" (x) :
+		"memory");
+
+	return dstpp;
+}
diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c
index 13ee1f0..0e1f4e6 100644
--- a/src/arch/x86/lib/romcc_console.c
+++ b/src/arch/x86/lib/romcc_console.c
@@ -46,6 +46,9 @@
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 static void __console_tx_nibble(unsigned nibble)
diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c
index a5f2e2b..67e8122 100644
--- a/src/arch/x86/lib/romstage_console.c
+++ b/src/arch/x86/lib/romstage_console.c
@@ -35,7 +35,10 @@
 		console_tx_byte('\r');
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
-	uart8250_mem_tx_byte(CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	if (oxford_oxpcie_present) {
+		uart8250_mem_tx_byte(
+			CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000, byte);
+	}
 #endif
 #if CONFIG_CONSOLE_SERIAL8250
 	uart8250_tx_byte(CONFIG_TTYS0_BASE, byte);
@@ -46,6 +49,9 @@
 #if CONFIG_CONSOLE_NE2K
 	ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_tx_byte(byte);
+#endif
 }
 
 int do_printk(int msg_level, const char *fmt, ...)
diff --git a/src/boot/hardwaremain.c b/src/boot/hardwaremain.c
index 3d15b55..489caa3 100644
--- a/src/boot/hardwaremain.c
+++ b/src/boot/hardwaremain.c
@@ -41,6 +41,7 @@
 #if CONFIG_WRITE_HIGH_TABLES
 #include <cbmem.h>
 #endif
+#include <timestamp.h>
 
 /**
  * @brief Main function of the RAM part of coreboot.
@@ -56,7 +57,9 @@
 void hardwaremain(int boot_complete)
 {
 	struct lb_memory *lb_mem;
+	tsc_t timestamps[6];
 
+	timestamps[0] = rdtsc();
 	post_code(POST_ENTRY_RAMSTAGE);
 
 	/* console_init() MUST PRECEDE ALL printk()! */
@@ -78,30 +81,51 @@
 	/* FIXME: Is there a better way to handle this? */
 	init_timer();
 
+	timestamps[1] = rdtsc();
 	/* Find the devices we don't have hard coded knowledge about. */
 	dev_enumerate();
 	post_code(POST_DEVICE_ENUMERATION_COMPLETE);
+
+	timestamps[2] = rdtsc();
 	/* Now compute and assign the bus resources. */
 	dev_configure();
 	post_code(POST_DEVICE_CONFIGURATION_COMPLETE);
+
+	timestamps[3] = rdtsc();
 	/* Now actually enable devices on the bus */
 	dev_enable();
+
+	timestamps[4] = rdtsc();
 	/* And of course initialize devices on the bus */
 	dev_initialize();
 	post_code(POST_DEVICES_ENABLED);
 
+	timestamps[5] = rdtsc();
 #if CONFIG_WRITE_HIGH_TABLES == 1
 	cbmem_initialize();
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_reinit();
+#endif
 #endif
 #if CONFIG_HAVE_ACPI_RESUME == 1
 	suspend_resume();
 	post_code(0x8a);
 #endif
 
+	timestamp_add(TS_START_RAMSTAGE, timestamps[0]);
+	timestamp_add(TS_DEVICE_ENUMERATE, timestamps[1]);
+	timestamp_add(TS_DEVICE_CONFIGURE, timestamps[2]);
+	timestamp_add(TS_DEVICE_ENABLE, timestamps[3]);
+	timestamp_add(TS_DEVICE_INITIALIZE, timestamps[4]);
+	timestamp_add(TS_DEVICE_DONE, timestamps[5]);
+	timestamp_add_now(TS_WRITE_TABLES);
+
 	/* Now that we have collected all of our information
 	 * write our configuration tables.
 	 */
 	lb_mem = write_tables();
+
+	timestamp_add_now(TS_LOAD_PAYLOAD);
 	cbfs_load_payload(lb_mem, CONFIG_CBFS_PREFIX "/payload");
 	printk(BIOS_ERR, "Boot failed.\n");
 }
diff --git a/src/boot/selfboot.c b/src/boot/selfboot.c
index 5f7a8f1..75c9de5 100644
--- a/src/boot/selfboot.c
+++ b/src/boot/selfboot.c
@@ -18,6 +18,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
 
+#include <arch/byteorder.h>
 #include <console/console.h>
 #include <fallback.h>
 #include <boot/elf.h>
@@ -29,12 +30,8 @@
 #include <string.h>
 #include <cbfs.h>
 #include <lib.h>
-
-#if !CONFIG_BIG_ENDIAN
-#define ntohl(x) ( ((x&0xff)<<24) | ((x&0xff00)<<8) | \
-		((x&0xff0000) >> 8) | ((x&0xff000000) >> 24) )
-#else
-#define ntohl(x) (x)
+#if CONFIG_COLLECT_TIMESTAMPS
+#include <timestamp.h>
 #endif
 
 /* Maximum physical address we can use for the coreboot bounce buffer.
@@ -49,8 +46,6 @@
 struct segment {
 	struct segment *next;
 	struct segment *prev;
-	struct segment *phdr_next;
-	struct segment *phdr_prev;
 	unsigned long s_dstaddr;
 	unsigned long s_srcaddr;
 	unsigned long s_memsz;
@@ -58,36 +53,6 @@
 	int compression;
 };
 
-struct verify_callback {
-	struct verify_callback *next;
-	int (*callback)(struct verify_callback *vcb,
-		Elf_ehdr *ehdr, Elf_phdr *phdr, struct segment *head);
-	unsigned long desc_offset;
-	unsigned long desc_addr;
-};
-
-struct ip_checksum_vcb {
-	struct verify_callback data;
-	unsigned short ip_checksum;
-};
-
-static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload);
-
-void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name)
-{
-	struct cbfs_payload *payload;
-
-	payload = (struct cbfs_payload *)cbfs_find_file(name, CBFS_TYPE_PAYLOAD);
-	if (payload == NULL)
-		return (void *) -1;
-	printk(BIOS_DEBUG, "Got a payload\n");
-
-	selfboot(lb_mem, payload);
-	printk(BIOS_EMERG, "SELFBOOT RETURNED!\n");
-
-	return (void *) -1;
-}
-
 /* The problem:
  * Static executables all want to share the same addresses
  * in memory because only a few addresses are reliably present on
@@ -171,15 +136,20 @@
 		mtype = mem->map[i].type;
 		mstart = unpack_lb64(mem->map[i].start);
 		mend = mstart + unpack_lb64(mem->map[i].size);
-		if ((mtype == LB_MEM_RAM) && (start < mend) && (end > mstart)) {
+		if ((mtype == LB_MEM_RAM) && (start >= mstart) && (end < mend)) {
 			break;
 		}
-		if ((mtype == LB_MEM_TABLE) && (start < mend) && (end > mstart)) {
+		if ((mtype == LB_MEM_TABLE) && (start >= mstart) && (end < mend)) {
 			printk(BIOS_ERR, "Payload is overwriting coreboot tables.\n");
 			break;
 		}
 	}
 	if (i == mem_entries) {
+		if (start < (1024*1024) && end <=(1024*1024)) {
+			printk(BIOS_DEBUG, "Payload (probably SeaBIOS) loaded"
+				" into a reserved area in the lower 1MB\n");
+			return 1;
+		}
 		printk(BIOS_ERR, "No matching ram area found for range:\n");
 		printk(BIOS_ERR, "  [0x%016lx, 0x%016lx)\n", start, end);
 		printk(BIOS_ERR, "Ram areas\n");
@@ -259,11 +229,6 @@
 			new->prev = seg->prev;
 			seg->prev->next = new;
 			seg->prev = new;
-			/* Order by original program header order */
-			new->phdr_next = seg;
-			new->phdr_prev = seg->phdr_prev;
-			seg->phdr_prev->phdr_next = new;
-			seg->phdr_prev = new;
 
 			/* compute the new value of start */
 			start = seg->s_dstaddr;
@@ -299,11 +264,6 @@
 			new->prev = seg;
 			seg->next->prev = new;
 			seg->next = new;
-			/* Order by original program header order */
-			new->phdr_next = seg->phdr_next;
-			new->phdr_prev = seg;
-			seg->phdr_next->phdr_prev = new;
-			seg->phdr_next = new;
 
 			printk(BIOS_SPEW, "   late: [0x%016lx, 0x%016lx, 0x%016lx)\n",
 				new->s_dstaddr,
@@ -331,13 +291,14 @@
 static int build_self_segment_list(
 	struct segment *head,
 	struct lb_memory *mem,
-	struct cbfs_payload *payload, u32 *entry)
+	struct cbfs_payload *payload,
+	u32 payload_len,
+	u32 *entry)
 {
 	struct segment *new;
 	struct segment *ptr;
 	struct cbfs_payload_segment *segment, *first_segment;
 	memset(head, 0, sizeof(*head));
-	head->phdr_next = head->phdr_prev = head;
 	head->next = head->prev = head;
 	first_segment = segment = &payload->segments;
 
@@ -361,6 +322,13 @@
 
 			new->s_srcaddr = (u32) ((unsigned char *) first_segment) + ntohl(segment->offset);
 			new->s_filesz = ntohl(segment->len);
+
+			if ((new->s_srcaddr < (u32)payload) ||
+				((new->s_srcaddr + new->s_filesz) >
+				(payload_len + (u32)payload))) {
+				printk(BIOS_WARNING, "WARNING: source address not within payload file!\n");
+			}
+
 			printk(BIOS_DEBUG, "  New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n",
 				new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz);
 			/* Clean up the values */
@@ -398,9 +366,10 @@
 			return -1;
 		}
 
+		/* We have found another CODE, DATA or BSS segment */
 		segment++;
 
-		// FIXME: Explain what this is
+		/* Find place where to insert our segment */
 		for(ptr = head->next; ptr != head; ptr = ptr->next) {
 			if (new->s_srcaddr < ntohl((u32) segment->load_addr))
 				break;
@@ -411,12 +380,6 @@
 		new->prev = ptr->prev;
 		ptr->prev->next = new;
 		ptr->prev = new;
-
-		/* Order by original program header order */
-		new->phdr_next = head;
-		new->phdr_prev = head->phdr_prev;
-		head->phdr_prev->phdr_next  = new;
-		head->phdr_prev = new;
 	}
 
 	return 1;
@@ -431,7 +394,8 @@
 
 	unsigned long bounce_high = lb_end;
 	for(ptr = head->next; ptr != head; ptr = ptr->next) {
-		if (!overlaps_coreboot(ptr)) continue;
+		if (!overlaps_coreboot(ptr))
+			continue;
 		if (ptr->s_dstaddr + ptr->s_memsz > bounce_high)
 			bounce_high = ptr->s_dstaddr + ptr->s_memsz;
 	}
@@ -534,13 +498,13 @@
 	return 1;
 }
 
-static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload)
+static int selfboot(struct lb_memory *mem, struct cbfs_payload *payload, u32 payload_len)
 {
 	u32 entry=0;
 	struct segment head;
 
 	/* Preprocess the self segments */
-	if (!build_self_segment_list(&head, mem, payload, &entry))
+	if (!build_self_segment_list(&head, mem, payload, payload_len, &entry))
 		goto out;
 
 	/* Load the segments */
@@ -555,6 +519,10 @@
 	printk(BIOS_DEBUG, "Jumping to boot code at %x\n", entry);
 	post_code(POST_ENTER_ELF_BOOT);
 
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_add_now(TS_SELFBOOT_JUMP);
+#endif
+
 	/* Jump to kernel */
 	jmp_to_elf_entry((void*)entry, bounce_buffer, bounce_size);
 	return 1;
@@ -563,3 +531,33 @@
 	return 0;
 }
 
+void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name)
+{
+	struct cbfs_payload *payload;
+	struct cbfs_file *file = cbfs_find(name);
+
+	if (file == NULL) {
+		printk(BIOS_INFO,  "CBFS: Could not find file %s\n",
+		       name);
+		return (void *) -1;
+	}
+
+	if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) {
+		printk(BIOS_INFO,  "CBFS: File %s is of type %x instead of "
+		       "type %x\n", name, file->type, CBFS_TYPE_PAYLOAD);
+
+		return (void *) -1;
+	}
+
+	payload = (struct cbfs_payload *)CBFS_SUBHEADER(file);
+	if (payload == NULL)
+		return (void *) -1;
+
+	printk(BIOS_DEBUG, "Got a payload\n");
+
+	selfboot(lb_mem, payload, ntohl(file->len));
+	printk(BIOS_EMERG, "SELFBOOT RETURNED!\n");
+
+	return (void *) -1;
+}
+
diff --git a/src/console/Kconfig b/src/console/Kconfig
index 02244d7d..38f1023 100644
--- a/src/console/Kconfig
+++ b/src/console/Kconfig
@@ -190,6 +190,33 @@
 	  32 bytes of IO spaces will be used (and align on 32 bytes
 	  boundary, qemu needs broader align)
 
+config CONSOLE_CBMEM
+	depends on EARLY_CBMEM_INIT
+	bool "Send console output to a CBMEM buffer"
+	default n
+	help
+	  Enable this to save the console output in a CBMEM buffer. This would
+	  allow to see coreboot console output from Linux space.
+
+config CONSOLE_CBMEM_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in CBMEM"
+	default 0x10000
+	help
+	  Space allocated for console output storage in CBMEM. The default
+	  value (almost 45K or 0xaeoo bytes) is large enough to accommodate
+	  even the BIOS_SPEW level.
+
+config CONSOLE_CAR_BUFFER_SIZE
+	depends on CONSOLE_CBMEM
+	hex "Room allocated for console output in Cache as RAM"
+	default 0xc00
+	help
+	  Console is used before RAM is initialized. This is the room reserved
+	  in the DCACHE based RAM to keep console output before it can be
+	  saved in a CBMEM buffer. 3K bytes should be enough even for the
+	  BIOS_SPEW level.
+
 
 choice
 	prompt "Maximum console log level"
diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc
index 4a30918..f3b8758 100644
--- a/src/console/Makefile.inc
+++ b/src/console/Makefile.inc
@@ -18,6 +18,8 @@
 driver-$(CONFIG_USBDEBUG) += usbdebug_console.c
 driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c
+driver-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
+
 
 $(obj)/console/console.ramstage.o : $(obj)/build.h
 $(obj)/console/console.romstage.o : $(obj)/build.h
diff --git a/src/cpu/x86/mmx_disable.inc b/src/console/cbmem_console.c
similarity index 61%
copy from src/cpu/x86/mmx_disable.inc
copy to src/console/cbmem_console.c
index 1a4e70f..2c43f5c 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/console/cbmem_console.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,22 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#include <console/console.h>
 
+static void cbmemc_init_(void)
+{
+	cbmemc_init();
+}
+
+static void cbmemc_tx_byte_(unsigned char data)
+{
+	cbmemc_tx_byte(data);
+}
+
+static const struct console_driver cbmem_console __console = {
+	.init     = cbmemc_init_,
+	.tx_byte  = cbmemc_tx_byte_,
+};
diff --git a/src/console/console.c b/src/console/console.c
index a73616e..8f60f04 100644
--- a/src/console/console.c
+++ b/src/console/console.c
@@ -22,14 +22,6 @@
 #include <arch/hlt.h>
 #include <arch/io.h>
 
-#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
-#include <uart8250.h>
-#endif
-
-#if CONFIG_CONSOLE_NE2K
-#include <console/ne2k.h>
-#endif
-
 #ifndef __PRE_RAM__
 #include <string.h>
 #include <pc80/mc146818rtc.h>
@@ -48,14 +40,6 @@
 	}
 }
 
-static void __console_tx_byte(unsigned char byte)
-{
-	struct console_driver *driver;
-	for(driver = console_drivers; driver < econsole_drivers; driver++) {
-		driver->tx_byte(byte);
-	}
-}
-
 void console_tx_flush(void)
 {
 	struct console_driver *driver;
@@ -66,6 +50,14 @@
 	}
 }
 
+static void __console_tx_byte(unsigned char byte)
+{
+	struct console_driver *driver;
+	for(driver = console_drivers; driver < econsole_drivers; driver++) {
+		driver->tx_byte(byte);
+	}
+}
+
 void console_tx_byte(unsigned char byte)
 {
 	if (byte == '\n')
@@ -95,7 +87,7 @@
 	return 0;
 }
 
-#else
+#else // __PRE_RAM__   ^^^ NOT defined   vvv defined
 
 void console_init(void)
 {
@@ -112,6 +104,9 @@
 #if CONFIG_CONSOLE_NE2K
 	ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
 #endif
+#if CONFIG_CONSOLE_CBMEM
+	cbmemc_init();
+#endif
 	static const char console_test[] =
 		"\n\ncoreboot-"
 		COREBOOT_VERSION
diff --git a/src/console/uart8250mem_console.c b/src/console/uart8250mem_console.c
index a6968dd..3c5cfc6 100644
--- a/src/console/uart8250mem_console.c
+++ b/src/console/uart8250mem_console.c
@@ -23,11 +23,16 @@
 
 static u32 uart_bar = 0;
 
-static void uartmem_init(void)
+void uartmem_init(void)
 {
 	uart_bar = uart_mem_init();
 }
 
+u32 uartmem_getbaseaddr(void)
+{
+	return uart_bar;
+}
+
 static void uartmem_tx_byte(unsigned char data)
 {
 	if (!uart_bar)
diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c
index 944fd5b..d2efc8d 100644
--- a/src/console/vtxprintf.c
+++ b/src/console/vtxprintf.c
@@ -6,6 +6,7 @@
 
 #include <string.h>
 #include <div64.h>
+#include <console/console.h>
 #include <console/vtxprintf.h>
 
 /* haha, don't need ctype.c */
@@ -115,6 +116,11 @@
 
 	int count;
 
+#if defined(__SMM__) && CONFIG_SMM_TSEG
+	/* Fix pointer in TSEG */
+	tx_byte = console_tx_byte;
+#endif
+
 	for (count=0; *fmt ; ++fmt) {
 		if (*fmt != '%') {
 			tx_byte(*fmt), count++;
diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig
index 8cf30c9..774b7fe 100644
--- a/src/cpu/intel/Kconfig
+++ b/src/cpu/intel/Kconfig
@@ -9,6 +9,7 @@
 source src/cpu/intel/model_6fx/Kconfig
 source src/cpu/intel/model_1067x/Kconfig
 source src/cpu/intel/model_106cx/Kconfig
+source src/cpu/intel/model_206ax/Kconfig
 source src/cpu/intel/model_f0x/Kconfig
 source src/cpu/intel/model_f1x/Kconfig
 source src/cpu/intel/model_f2x/Kconfig
@@ -28,3 +29,4 @@
 source src/cpu/intel/socket_mPGA604/Kconfig
 source src/cpu/intel/socket_PGA370/Kconfig
 source src/cpu/intel/socket_441/Kconfig
+source src/cpu/intel/socket_rPGA989/Kconfig
diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc
index 93ab7de..40d92f1 100644
--- a/src/cpu/intel/Makefile.inc
+++ b/src/cpu/intel/Makefile.inc
@@ -14,6 +14,7 @@
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989
 subdirs-$(CONFIG_CPU_INTEL_SLOT_2) += slot_2
 subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1
 
diff --git a/src/cpu/intel/microcode/update-microcodes.sh b/src/cpu/intel/microcode/update-microcodes.sh
index 7a234a8..46691c9 100755
--- a/src/cpu/intel/microcode/update-microcodes.sh
+++ b/src/cpu/intel/microcode/update-microcodes.sh
@@ -18,10 +18,10 @@
 # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 #
 
-MICROCODE_VERSION=20100914
+MICROCODE_VERSION=20110428
 MICROCODE_ARCHIVE=microcode-$MICROCODE_VERSION.tgz
-MICROCODE_FILE=microcode-$MICROCODE_VERSION.dat
-INTEL_MICROCODE=http://downloadmirror.intel.com/19342/eng/$MICROCODE_ARCHIVE
+MICROCODE_FILE=microcode.dat
+INTEL_MICROCODE=http://downloadmirror.intel.com/20050/eng/$MICROCODE_ARCHIVE
 
 #
 # Getting Intel(R) Microcode
diff --git a/src/cpu/intel/model_106cx/Kconfig b/src/cpu/intel/model_106cx/Kconfig
index 09449cb..e640e6b6 100644
--- a/src/cpu/intel/model_106cx/Kconfig
+++ b/src/cpu/intel/model_106cx/Kconfig
@@ -4,3 +4,20 @@
 	select SSE2
 	select UDELAY_LAPIC
 	select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_MODEL_106CX
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/model_106cx/bootblock.c"
+
+config CACHE_MRC_BIN
+	bool
+	default n
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+endif
+
diff --git a/src/cpu/intel/model_106cx/bootblock.c b/src/cpu/intel/model_106cx/bootblock.c
new file mode 100644
index 0000000..0e36bd2
--- /dev/null
+++ b/src/cpu/intel/model_106cx/bootblock.c
@@ -0,0 +1,136 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+//#include <arch/io.h>
+//#include <arch/romcc_io.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+static const uint32_t microcode_updates[] = {
+	//#include "microcode-2963-M01106C2217.h"
+	//#include "microcode-2964-M04106C2218.h"
+	//#include "microcode-2965-M08106C2219.h"
+	//#include "microcode-3098-M01106CA107.h"
+	#include "microcode-3101-M04106CA107.h"
+	//#include "microcode-3104-M08106CA107.h"
+	//#include "microcode-3107-M10106CA107.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+
+
+struct microcode {
+	u32 hdrver;	/* Header Version */
+	u32 rev;	/* Patch ID       */
+	u32 date;	/* DATE           */
+	u32 sig;	/* CPUID          */
+
+	u32 cksum;	/* Checksum       */
+	u32 ldrver;	/* Loader Version */
+	u32 pf;		/* Platform ID    */
+
+	u32 data_size;	/* Data size      */
+	u32 total_size;	/* Total size     */
+
+	u32 reserved[3];
+	u32 bits[1012];
+};
+
+static inline u32 read_microcode_rev(void)
+{
+	/* Some Intel Cpus can be very finicky about the
+	 * CPUID sequence used.  So this is implemented in
+	 * assembly so that it works reliably.
+	 */
+	msr_t msr;
+	__asm__ volatile (
+		"wrmsr\n\t"
+		"xorl %%eax, %%eax\n\t"
+		"xorl %%edx, %%edx\n\t"
+		"movl $0x8b, %%ecx\n\t"
+		"wrmsr\n\t"
+		"movl $0x01, %%eax\n\t"
+		"cpuid\n\t"
+		"movl $0x08b, %%ecx\n\t"
+		"rdmsr \n\t"
+		: /* outputs */
+		"=a" (msr.lo), "=d" (msr.hi)
+		: /* inputs */
+		: /* trashed */
+		 "ecx"
+	);
+	return msr.hi;
+}
+
+void intel_update_microcode(const void *microcode_updates)
+{
+	unsigned int eax;
+	unsigned int pf, rev, sig;
+	unsigned int x86_model, x86_family;
+	const struct microcode *m;
+	const char *c;
+	msr_t msr;
+
+	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(0x8B, msr);
+	eax = cpuid_eax(1);
+	msr = rdmsr(0x8B);
+	rev = msr.hi;
+	x86_model = (eax >>4) & 0x0f;
+	x86_family = (eax >>8) & 0x0f;
+	sig = eax;
+
+	pf = 0;
+	if ((x86_model >= 5)||(x86_family>6)) {
+		msr = rdmsr(0x17);
+		pf = 1 << ((msr.hi >> 18) & 7);
+	}
+
+	m = microcode_updates;
+	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
+		if ((m->sig == sig) && (m->pf & pf)) {
+			unsigned int new_rev;
+			msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
+			msr.hi = 0;
+			wrmsr(0x79, msr);
+
+			/* Read back the new microcode version */
+			new_rev = read_microcode_rev();
+			break;
+		}
+		if (m->total_size) {
+			c += m->total_size;
+		} else {
+			c += 2048;
+		}
+	}
+}
+
+static void bootblock_cpu_init(void)
+{
+	intel_update_microcode(microcode_updates);
+}
diff --git a/src/cpu/intel/model_106cx/cache_as_ram.inc b/src/cpu/intel/model_106cx/cache_as_ram.inc
index da14db2..de2848c 100644
--- a/src/cpu/intel/model_106cx/cache_as_ram.inc
+++ b/src/cpu/intel/model_106cx/cache_as_ram.inc
@@ -63,22 +63,27 @@
 
 	/* Set Cache-as-RAM mask. */
 	movl	$(MTRRphysMask_MSR(0)), %ecx
-	movl	$(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
 	xorl	%edx, %edx
 	wrmsr
 
 	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
-	orl	$(1 << 11), %eax
+	orl	$MTRRdefTypeEn, %eax
 	wrmsr
 
 	/* Enable L2 cache. */
 	movl	$0x11e, %ecx
 	rdmsr
+	bt	$0, %eax
+	jnc	L2done
+	bt	$23, %eax
+	jc	L2done
 	orl	$(1 << 8), %eax
 	wrmsr
 
+L2done:
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
         movl	%cr0, %eax
 	andl	$(~((1 << 30) | (1 << 29))), %eax
@@ -98,7 +103,6 @@
 	orl	$(1 << 30), %eax
 	movl	%eax, %cr0
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
 	/* Enable cache for our code in Flash because we do XIP here */
 	movl	$MTRRphysBase_MSR(1), %ecx
 	xorl	%edx, %edx
@@ -113,14 +117,27 @@
 	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$REAL_XIP_ROM_BASE, %eax
-	orl	$MTRR_TYPE_WRBACK, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
 	wrmsr
 
 	movl	$MTRRphysMask_MSR(1), %ecx
 	xorl	%edx, %edx
-	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
 	wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for the last 32k of memory for 
+	 * ram init code to run faster
+	 */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(0xffff0000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$((~((64*1024) - 1)) | MTRRphysMaskValid), %eax
+	xorl	%edx, %edx
+	wrmsr
+#endif
 
 	/* Enable cache. */
 	movl	%cr0, %eax
@@ -148,6 +165,15 @@
 
 	post_code(0x2f)
 
+#if CONFIG_USBDEBUG
+	/* Copy global variable space (for USBDEBUG) to memory */
+	cld
+	movl	$(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	24, %ecx
+	rep	movsb
+#endif
+
 	post_code(0x30)
 
 	/* Disable cache. */
@@ -160,7 +186,7 @@
 	/* Disable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
-	andl	$(~(1 << 11)), %eax
+	andl	$(~MTRRdefTypeEn), %eax
 	wrmsr
 
 	post_code(0x31)
@@ -195,13 +221,27 @@
 
 	post_code(0x38)
 
-	/* Enable Write Back and Speculative Reads for the first 1MB. */
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
 	movl	$MTRRphysBase_MSR(0), %ecx
 	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
 	xorl	%edx, %edx
 	wrmsr
 	movl	$MTRRphysMask_MSR(0), %ecx
-	movl	$(~(1024 * 1024 - 1) | (1 << 11)), %eax
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
 	xorl	%edx, %edx
 	wrmsr
 
@@ -217,7 +257,7 @@
 	/* Enable MTRR. */
 	movl	$MTRRdefType_MSR, %ecx
 	rdmsr
-	orl	$(1 << 11), %eax
+	orl	$MTRRdefTypeEn, %eax
 	wrmsr
 
 	post_code(0x3b)
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 1199315..498fb07 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -31,6 +31,76 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/name.h>
 #include <usbdebug.h>
+#include <arch/acpi.h>
+
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* HLT */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_HLT,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C2 */
+		.latency = 2,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 4: C2E */
+		.latency = 2,
+		.power = 500,
+		.resource = {
+			.addrl = 0x11,	/* MWAIT State 1 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 5: C4 */
+		.latency = 57,
+		.power = 100,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 6: C4E */
+		.latency = 57,
+		.power = 100,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{ 0 }
+};
 
 static const uint32_t microcode_updates[] = {
 	#include "microcode-2963-M01106C2217.h"
@@ -84,23 +154,24 @@
 #define PMG_IO_BASE_ADDR	0xe3
 #define PMG_IO_CAPTURE_ADDR	0xe4
 
-#define HIGHEST_CLEVEL		3
+#define HIGHEST_CLEVEL		4 // Pineview-M only
 static void configure_c_states(void)
 {
 	msr_t msr;
 
 	msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 3);  // Enable Dynamic L2 shrinking
 	msr.lo |= (1 << 15); // Lock configuration
 	msr.lo |= (1 << 10); // redirect IO-based CState transition requests to MWAIT
 	msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
-	msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL; // support at most C3
-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
+	msr.lo &= ~7; msr.lo |= HIGHEST_CLEVEL;
 	wrmsr(PMG_CST_CONFIG_CONTROL, msr);
 
-	/* Set Processor MWAIT IO BASE (P_BLK) */
+	/* Set Processor MWAIT IO BASE (P_BLK)
+	 * PMB0 points to PBLK+4,
+	 * PMB1 points to IO address that will trap tp SMM (not used)
+	 */
 	msr.hi = 0;
-	// TODO Do we want PM1_BASE? Needs SMM?
-	//msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
 	msr.lo = ((PMB0_BASE + 4) & 0xffff);
 	wrmsr(PMG_IO_BASE_ADDR, msr);
 
@@ -116,6 +187,12 @@
 	msr_t msr;
 
 	msr = rdmsr(IA32_MISC_ENABLE);
+
+	msr.hi |= (1 << (32-32)); 	/* C4E enable */
+	msr.hi |= (1 << (33-32)); 	/* Hard C4E enable */
+	msr.lo |= (1 << 26); 	/* C2E enable */
+	msr.lo |= (1 << 25); 	/* C1E enable */
+
 	msr.lo |= (1 << 3); 	/* TM1 enable */
 	msr.lo |= (1 << 13);	/* TM2 enable */
 	msr.lo |= (1 << 17);	/* Bidirectional PROCHOT# */
@@ -124,8 +201,8 @@
 
 	// TODO: Only if  IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
 	msr.lo |= (1 << 16);	/* Enhanced SpeedStep Enable */
+	msr.lo |= (1 << 0);	/* Fast String Enable */
 
-	// TODO Do we want Deep C4 and  Dynamic L2 shrinking?
 	wrmsr(IA32_MISC_ENABLE, msr);
 
 	msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
@@ -189,11 +266,13 @@
 
 static struct cpu_device_id cpu_table[] = {
 	{ X86_VENDOR_INTEL, 0x106c0 }, /* Intel Atom 230 */
+	{ X86_VENDOR_INTEL, 0x106ca }, /* Intel Pineview */
 	{ 0, 0 },
 };
 
 static const struct cpu_driver driver __cpu_driver = {
 	.ops      = &cpu_dev_ops,
 	.id_table = cpu_table,
+	.cstates  = cstate_map,
 };
 
diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig
new file mode 100644
index 0000000..55948a4
--- /dev/null
+++ b/src/cpu/intel/model_206ax/Kconfig
@@ -0,0 +1,24 @@
+config CPU_INTEL_MODEL_206AX
+	bool
+	select SMP
+	select SSE2
+	select UDELAY_LAPIC
+	select SMM_TSEG
+	#select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_MODEL_206AX
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/model_206ax/bootblock.c"
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	int
+	default 0x800000
+
+endif
+
diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc
new file mode 100644
index 0000000..e9b8e6d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/Makefile.inc
@@ -0,0 +1,8 @@
+driver-y += model_206ax_init.c
+subdirs-y += ../../x86/name
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_206ax/acpi.c b/src/cpu/intel/model_206ax/acpi.c
new file mode 100644
index 0000000..9a70bd4
--- /dev/null
+++ b/src/cpu/intel/model_206ax/acpi.c
@@ -0,0 +1,357 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/acpi.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "model_206ax.h"
+#include "chip.h"
+
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	switch (c.x86_model) {
+	case 0x2a: /* SandyBridge */
+		result = cpuid_ext(0xb, 1);
+		cores = result.ebx & 0xff;
+		break;
+	default:
+		cores = (cpuid_ebx(1) >> 16) & 0xff;
+		break;
+	}
+
+	return cores;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0)
+		length += acpigen_write_CST_package(1, &cstates[c1]);
+	if (c2 > 0)
+		length += acpigen_write_CST_package(2, &cstates[c2]);
+	if (c3 > 0)
+		length += acpigen_write_CST_package(3, &cstates[c3]);
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_C_state_entries(void)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+	device_t lapic;
+	struct cpu_intel_model_206ax_config *conf = NULL;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic)
+		return 0;
+	conf = lapic->chip_info;
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+static acpi_tstate_t tss_table_fine[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 94, 940, 0, 0x1f, 0 },
+	{ 88, 880, 0, 0x1e, 0 },
+	{ 82, 820, 0, 0x1d, 0 },
+	{ 75, 760, 0, 0x1c, 0 },
+	{ 69, 700, 0, 0x1b, 0 },
+	{ 63, 640, 0, 0x1a, 0 },
+	{ 57, 580, 0, 0x19, 0 },
+	{ 50, 520, 0, 0x18, 0 },
+	{ 44, 460, 0, 0x17, 0 },
+	{ 38, 400, 0, 0x16, 0 },
+	{ 32, 340, 0, 0x15, 0 },
+	{ 25, 280, 0, 0x14, 0 },
+	{ 19, 220, 0, 0x13, 0 },
+	{ 13, 160, 0, 0x12, 0 },
+};
+
+static acpi_tstate_t tss_table_coarse[] = {
+	{ 100, 1000, 0, 0x00, 0 },
+	{ 88, 875, 0, 0x1f, 0 },
+	{ 75, 750, 0, 0x1e, 0 },
+	{ 63, 625, 0, 0x1d, 0 },
+	{ 50, 500, 0, 0x1c, 0 },
+	{ 38, 375, 0, 0x1b, 0 },
+	{ 25, 250, 0, 0x1a, 0 },
+	{ 13, 125, 0, 0x19, 0 },
+};
+
+static int generate_T_state_entries(int core, int cores_per_package)
+{
+	int len;
+
+	/* Indicate SW_ALL coordination for T-states */
+	len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL);
+
+	/* Indicate FFixedHW so OS will use MSR */
+	len += acpigen_write_empty_PTC();
+
+	/* Set a T-state limit that can be modified in NVS */
+	len += acpigen_write_TPC("\\TLVL");
+
+	/*
+	 * CPUID.(EAX=6):EAX[5] indicates support
+	 * for extended throttle levels.
+	 */
+	if (cpuid_eax(6) & (1 << 5))
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_fine), tss_table_fine);
+	else
+		len += acpigen_write_TSS_package(
+			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
+
+	return len;
+}
+
+static int calculate_power(int tdp, int p1_ratio, int ratio)
+{
+	u32 m;
+	u32 power;
+
+	/*
+	 * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2
+	 *
+	 * Power = (ratio / p1_ratio) * m * tdp
+	 */
+
+	m = (110000 - ((p1_ratio - ratio) * 625)) / 11;
+	m = (m * m) / 1000;
+
+	power = ((ratio * 100000 / p1_ratio) / 100);
+	power *= (m / 100) * (tdp / 1000);
+	power /= 1000;
+
+	return (int)power;
+}
+
+static int generate_P_state_entries(int core, int cores_per_package)
+{
+	int len, len_pss;
+	int ratio_min, ratio_max, ratio_turbo, ratio_step;
+	int coord_type, power_max, power_unit, num_entries;
+	int ratio, power, clock, clock_max;
+	msr_t msr;
+
+	/* Determine P-state coordination type from MISC_PWR_MGMT[0] */
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS)
+		coord_type = SW_ANY;
+	else
+		coord_type = HW_ALL;
+
+	/* Get bus ratio limits and calculate clock speeds */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */
+	ratio_max = (msr.lo >> 8) & 0xff;       /* Max Non-Turbo Ratio */
+	clock_max = ratio_max * SANDYBRIDGE_BCLK;
+
+	/* Calculate CPU TDP in mW */
+	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+	msr = rdmsr(MSR_PKG_POWER_SKU);
+	power_max = ((msr.lo & 0x7fff) / power_unit) * 1000;
+
+	/* Write _PCT indicating use of FFixedHW */
+	len = acpigen_write_empty_PCT();
+
+	/* Write _PPC with no limit on supported P-state */
+	len += acpigen_write_PPC(0);
+
+	/* Write PSD indicating configured coordination type */
+	len += acpigen_write_PSD_package(core, cores_per_package, coord_type);
+
+	/* Add P-state entries in _PSS table */
+	len += acpigen_write_name("_PSS");
+
+	/* Determine ratio points */
+	ratio_step = PSS_RATIO_STEP;
+	num_entries = (ratio_max - ratio_min) / ratio_step;
+	while (num_entries > PSS_MAX_ENTRIES-1) {
+		ratio_step <<= 1;
+		num_entries >>= 1;
+	}
+
+	/* P[T] is Turbo state if enabled */
+	if (get_turbo_state() == TURBO_ENABLED) {
+		/* _PSS package count including Turbo */
+		len_pss = acpigen_write_package(num_entries + 2);
+
+		msr = rdmsr(MSR_TURBO_RATIO_LIMIT);
+		ratio_turbo = msr.lo & 0xff;
+
+		/* Add entry for Turbo ratio */
+		len_pss += acpigen_write_PSS_package(
+			clock_max + 1,		/*MHz*/
+			power_max,		/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio_turbo << 8,	/*control*/
+			ratio_turbo << 8);	/*status*/
+	} else {
+		/* _PSS package count without Turbo */
+		len_pss = acpigen_write_package(num_entries + 1);
+	}
+
+	/* First regular entry is max non-turbo ratio */
+	len_pss += acpigen_write_PSS_package(
+		clock_max,		/*MHz*/
+		power_max,		/*mW*/
+		PSS_LATENCY_TRANSITION,	/*lat1*/
+		PSS_LATENCY_BUSMASTER,	/*lat2*/
+		ratio_max << 8,		/*control*/
+		ratio_max << 8);	/*status*/
+
+	/* Generate the remaining entries */
+	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
+	     ratio >= ratio_min; ratio -= ratio_step) {
+
+		/* Calculate power at this ratio */
+		power = calculate_power(power_max, ratio_max, ratio);
+		clock = ratio * SANDYBRIDGE_BCLK;
+
+		len_pss += acpigen_write_PSS_package(
+			clock,			/*MHz*/
+			power,			/*mW*/
+			PSS_LATENCY_TRANSITION,	/*lat1*/
+			PSS_LATENCY_BUSMASTER,	/*lat2*/
+			ratio << 8,		/*control*/
+			ratio << 8);		/*status*/
+	}
+
+	/* Fix package length */
+	len_pss--;
+	acpigen_patch_len(len_pss);
+
+	return len + len_pss;
+}
+
+void generate_cpu_entries(void)
+{
+	int len_pr;
+	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+	int totalcores = dev_count_cpu();
+	int cores_per_package = get_cores_per_package();
+	int numcpus = totalcores/cores_per_package;
+
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+	       numcpus, cores_per_package);
+
+	for (cpuID=1; cpuID <=numcpus; cpuID++) {
+		for (coreID=1; coreID<=cores_per_package; coreID++) {
+			if (coreID>1) {
+				pcontrol_blk = 0;
+				plen = 0;
+			}
+
+			/* Generate processor \_PR.CPUx */
+			len_pr = acpigen_write_processor(
+				(cpuID-1)*cores_per_package+coreID-1,
+				pcontrol_blk, plen);
+
+			/* Generate P-state tables */
+			len_pr += generate_P_state_entries(
+				cpuID-1, cores_per_package);
+
+			/* Generate C-state tables */
+			len_pr += generate_C_state_entries();
+
+			/* Generate T-state tables */
+			len_pr += generate_T_state_entries(
+				cpuID-1, cores_per_package);
+
+			len_pr--;
+			acpigen_patch_len(len_pr);
+		}
+	}
+}
+
+struct chip_operations cpu_intel_model_206ax_ops = {
+	CHIP_NAME("Intel SandyBridge CPU")
+};
diff --git a/src/cpu/intel/model_206ax/acpi/cpu.asl b/src/cpu/intel/model_206ax/acpi/cpu.asl
new file mode 100644
index 0000000..a9d5eeb
--- /dev/null
+++ b/src/cpu/intel/model_206ax/acpi/cpu.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* These devices are created at runtime */
+External (\_PR.CPU0, DeviceObj)
+External (\_PR.CPU1, DeviceObj)
+External (\_PR.CPU2, DeviceObj)
+External (\_PR.CPU3, DeviceObj)
+External (\_PR.CPU4, DeviceObj)
+External (\_PR.CPU5, DeviceObj)
+External (\_PR.CPU6, DeviceObj)
+External (\_PR.CPU7, DeviceObj)
+
+/* Notify OS to re-read CPU tables, assuming ^2 CPU count */
+Method (PNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CPU0, 0x80)  // _PPC
+		Notify (\_PR.CPU0, 0x81)  // _CST
+		Notify (\_PR.CPU1, 0x80)  // _PPC
+		Notify (\_PR.CPU1, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CPU2, 0x80)  // _PPC
+		Notify (\_PR.CPU2, 0x81)  // _CST
+		Notify (\_PR.CPU3, 0x80)  // _PPC
+		Notify (\_PR.CPU3, 0x81)  // _CST
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CPU4, 0x80)  // _PPC
+		Notify (\_PR.CPU4, 0x81)  // _CST
+		Notify (\_PR.CPU5, 0x80)  // _PPC
+		Notify (\_PR.CPU5, 0x81)  // _CST
+		Notify (\_PR.CPU6, 0x80)  // _PPC
+		Notify (\_PR.CPU6, 0x81)  // _CST
+		Notify (\_PR.CPU7, 0x80)  // _PPC
+		Notify (\_PR.CPU7, 0x81)  // _CST
+	}
+}
+
+/* Notify OS to re-read Throttle Limit tables, assuming ^2 CPU count */
+Method (TNOT)
+{
+	If (LGreaterEqual (\PCNT, 2)) {
+		Notify (\_PR.CPU0, 0x82)  // _TPC
+		Notify (\_PR.CPU1, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 4)) {
+		Notify (\_PR.CPU2, 0x82)  // _TPC
+		Notify (\_PR.CPU3, 0x82)  // _TPC
+	}
+	If (LGreaterEqual (\PCNT, 8)) {
+		Notify (\_PR.CPU4, 0x82)  // _TPC
+		Notify (\_PR.CPU5, 0x82)  // _TPC
+		Notify (\_PR.CPU6, 0x82)  // _TPC
+		Notify (\_PR.CPU7, 0x82)  // _TPC
+	}
+}
+
+/* Return a package containing enabled processor entries */
+Method (PPKG)
+{
+	If (LGreaterEqual (\PCNT, 8)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3,
+				   \_PR.CPU4, \_PR.CPU5, \_PR.CPU6, \_PR.CPU7})
+	} ElseIf (LGreaterEqual (\PCNT, 4)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1, \_PR.CPU2, \_PR.CPU3})
+	} ElseIf (LGreaterEqual (\PCNT, 2)) {
+		Return (Package() {\_PR.CPU0, \_PR.CPU1})
+	} Else {
+		Return (Package() {\_PR.CPU0})
+	}
+}
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c
new file mode 100644
index 0000000..8d91126
--- /dev/null
+++ b/src/cpu/intel/model_206ax/bootblock.c
@@ -0,0 +1,158 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/mtrr.h>
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_00000025.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+struct microcode {
+	u32 hdrver;	/* Header Version */
+	u32 rev;	/* Patch ID       */
+	u32 date;	/* DATE           */
+	u32 sig;	/* CPUID          */
+
+	u32 cksum;	/* Checksum       */
+	u32 ldrver;	/* Loader Version */
+	u32 pf;		/* Platform ID    */
+
+	u32 data_size;	/* Data size      */
+	u32 total_size;	/* Total size     */
+
+	u32 reserved[3];
+	u32 bits[1012];
+};
+
+static inline u32 read_microcode_rev(void)
+{
+	/* Some Intel Cpus can be very finicky about the
+	 * CPUID sequence used.  So this is implemented in
+	 * assembly so that it works reliably.
+	 */
+	msr_t msr;
+	__asm__ volatile (
+		"wrmsr\n\t"
+		"xorl %%eax, %%eax\n\t"
+		"xorl %%edx, %%edx\n\t"
+		"movl $0x8b, %%ecx\n\t"
+		"wrmsr\n\t"
+		"movl $0x01, %%eax\n\t"
+		"cpuid\n\t"
+		"movl $0x08b, %%ecx\n\t"
+		"rdmsr \n\t"
+		: /* outputs */
+		"=a" (msr.lo), "=d" (msr.hi)
+		: /* inputs */
+		: /* trashed */
+		 "ecx"
+	);
+	return msr.hi;
+}
+
+void intel_update_microcode(const void *microcode_updates)
+{
+	unsigned int eax;
+	unsigned int pf, rev, sig;
+	unsigned int x86_model, x86_family;
+	const struct microcode *m;
+	const char *c;
+	msr_t msr;
+
+	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(0x8B, msr);
+	eax = cpuid_eax(1);
+	msr = rdmsr(0x8B);
+	rev = msr.hi;
+	x86_model = (eax >>4) & 0x0f;
+	x86_family = (eax >>8) & 0x0f;
+	sig = eax;
+
+	pf = 0;
+	if ((x86_model >= 5)||(x86_family>6)) {
+		msr = rdmsr(0x17);
+		pf = 1 << ((msr.hi >> 18) & 7);
+	}
+
+	m = microcode_updates;
+	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
+		if ((m->sig == sig) && (m->pf & pf)) {
+			unsigned int new_rev;
+			msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
+			msr.hi = 0;
+			wrmsr(0x79, msr);
+
+			/* Read back the new microcode version */
+			new_rev = read_microcode_rev();
+			break;
+		}
+		if (m->total_size) {
+			c += m->total_size;
+		} else {
+			c += 2048;
+		}
+	}
+}
+
+static void set_var_mtrr(
+	unsigned reg, unsigned base, unsigned size, unsigned type)
+
+{
+	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
+	/* FIXME: It only support 4G less range */
+	msr_t basem, maskm;
+	basem.lo = base | type;
+	basem.hi = 0;
+	wrmsr(MTRRphysBase_MSR(reg), basem);
+	maskm.lo = ~(size - 1) | MTRRphysMaskValid;
+	maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1;
+	wrmsr(MTRRphysMask_MSR(reg), maskm);
+}
+
+static void enable_rom_caching(void)
+{
+	msr_t msr;
+
+	disable_cache();
+	set_var_mtrr(1, 0xffc00000, 4*1024*1024, MTRR_TYPE_WRPROT);
+	enable_cache();
+
+	/* Enable Variable MTRRs */
+	msr.hi = 0x00000000;
+	msr.lo = 0x00000800;
+	wrmsr(MTRRdefType_MSR, msr);
+}
+
+static void bootblock_cpu_init(void)
+{
+	enable_rom_caching();
+	intel_update_microcode(microcode_updates);
+}
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
new file mode 100644
index 0000000..d5f1d7d
--- /dev/null
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -0,0 +1,348 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <cpu/x86/stack.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
+
+cache_as_ram:
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
+
+	/* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+	movl	(%esi), %eax
+	bt	$12, %eax
+	jc	wait_for_sipi
+
+	post_code(0x21)
+	/* Zero out all fixed range and variable range MTRRs. */
+	movl	$mtrr_table, %esi
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+clear_mtrrs:
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	post_code(0x22)
+	/* Configure the default memory type to uncacheable. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	post_code(0x23)
+	/* Set Cache-as-RAM base address. */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	post_code(0x24)
+	/* Set Cache-as-RAM mask. */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x25)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+        movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* enable the 'no eviction' mode */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $1, %eax
+	andl    $~2, %eax
+	wrmsr
+
+       /* Clear the cache memory region. This will also fill up the cache */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	// movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+
+	/* enable the 'no eviction run' state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	orl     $3, %eax
+	wrmsr
+
+	post_code(0x26)
+	/* Enable Cache-as-RAM mode by disabling cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
+#if CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$0x0000000f, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	wrmsr
+
+	post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for ram init code to run faster */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+#endif
+
+	post_code(0x28)
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0
+
+	/* Set up the stack pointer below MRC variable space. */
+	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
+		  CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+before_romstage:
+	post_code(0x29)
+	/* Call romstage.c main function. */
+	call	main
+
+	post_code(0x2f)
+
+	/* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+	cld
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	$24, %ecx
+	rep	movsb
+#endif
+
+	post_code(0x30)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x31)
+
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~MTRRdefTypeEn), %eax
+	wrmsr
+
+	post_code(0x31)
+
+	/* Disable the no eviction run state */
+	movl    $NoEvictMod_MSR, %ecx
+	rdmsr
+	andl    $~2, %eax
+	wrmsr
+
+	invd
+
+	/* Disable the no eviction mode */
+	rdmsr
+	andl    $~1, %eax
+	wrmsr
+
+#if CONFIG_CACHE_MRC_BIN
+	/* Clear MTRR that was used to cache MRC */
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	movl	$MTRRphysBase_MSR(2), %ecx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	wrmsr
+#endif
+
+	post_code(0x33)
+
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x36)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x38)
+
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
+	movl	$MTRRphysBase_MSR(0), %ecx
+	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(0), %ecx
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx	// 36bit address space
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+	post_code(0x3c)
+
+#if CONFIG_HAVE_ACPI_RESUME
+	movl	CBMEM_BOOT_MODE, %eax
+	cmpl	$0x2, %eax // Resume?
+	jne	__acpi_resume_backup_done
+
+	/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+	 * through stage 2. We could keep stuff like stack and heap in high
+	 * tables memory completely, but that's a wonderful clean up task for
+	 * another day.
+	 */
+	cld
+	movl	$CONFIG_RAMBASE, %esi
+	movl	CBMEM_RESUME_BACKUP, %edi
+	movl	$HIGH_MEMORY_SAVE / 4, %ecx
+	rep	movsl
+
+__acpi_resume_backup_done:
+#endif
+
+	post_code(0x3d)
+
+	/* Clear boot_complete flag. */
+	xorl	%ebp, %ebp
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+
+	movl	%ebp, %esi
+
+	movl	$ROMSTAGE_STACK, %esp
+	movl	%esp, %ebp
+	pushl	%esi
+	call	copy_and_run
+
+.Lhlt:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.Lhlt
+
+mtrr_table:
+	/* Fixed MTRRs */
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
+	/* Variable MTRRs */
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
+
diff --git a/src/cpu/intel/model_206ax/chip.h b/src/cpu/intel/model_206ax/chip.h
new file mode 100644
index 0000000..48e0c89
--- /dev/null
+++ b/src/cpu/intel/model_206ax/chip.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_model_206ax_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_model_206ax_config {
+	u8 disable_acpi;	/* Do not generate CPU ACPI tables */
+
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* ACPI C1 on Battery Power */
+	int c2_battery;		/* ACPI C2 on Battery Power */
+	int c3_battery;		/* ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* ACPI C1 on AC Power */
+	int c2_acpower;		/* ACPI C2 on AC Power */
+	int c3_acpower;		/* ACPI C3 on AC Power */
+};
diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c
new file mode 100644
index 0000000..9de94c4
--- /dev/null
+++ b/src/cpu/intel/model_206ax/finalize.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include "model_206ax.h"
+
+static void msr_set_bit(unsigned reg, unsigned bit)
+{
+	msr_t msr = rdmsr(reg);
+
+	if (bit < 32) {
+		if (msr.lo & (1 << bit))
+			return;
+		msr.lo |= 1 << bit;
+	} else {
+		if (msr.hi & (1 << (bit - 32)))
+			return;
+		msr.hi |= 1 << (bit - 32);
+	}
+
+	wrmsr(reg, msr);
+}
+
+void intel_model_206ax_finalize_smm(void)
+{
+	msr_set_bit(IA32_FEATURE_CONTROL, 0);
+	msr_set_bit(MSR_PMG_CST_CONFIG_CONTROL, 15);
+
+	/* Lock AES-NI only if supported */
+	if (cpuid_ecx(1) & (1 << 25))
+		msr_set_bit(MSR_FEATURE_CONFIG, 0);
+
+	msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31);
+	msr_set_bit(MSR_PKG_POWER_LIMIT, 63);
+	msr_set_bit(MSR_PP0_POWER_LIMIT, 31);
+	msr_set_bit(MSR_PP1_POWER_LIMIT, 31);
+	msr_set_bit(MSR_MISC_PWR_MGMT, 22);
+	msr_set_bit(MSR_LT_LOCK_MEMORY, 0);
+}
diff --git a/src/cpu/intel/model_206ax/microcode-M12206A7_00000025.h b/src/cpu/intel/model_206ax/microcode-M12206A7_00000025.h
new file mode 100644
index 0000000..2b9e59a
--- /dev/null
+++ b/src/cpu/intel/model_206ax/microcode-M12206A7_00000025.h
@@ -0,0 +1,578 @@
+/* Intel Copyrighted material. Do not distribute */
+
+0x00000001,	0x00000025,	0x10112011,	0x000206a7,
+0x6aa14554,	0x00000001,	0x00000012,	0x000023d0,
+0x00002400,	0x00000000,	0x00000000,	0x00000000,
+0x00000000,	0x000000a1,	0x00020001,	0x00000025,
+0x00000000,	0x00000000,	0x20111011,	0x000008d1,
+0x00000001,	0x000206a7,	0x00000000,	0x00000000,
+0x00000000,	0x00000000,	0x00000000,	0x00000000,
+0x00000000,	0x000008d1,	0x00000000,	0x00000000,
+0x00000000,	0x00000000,	0x00000000,	0x00000000,
+0x9d225b45,	0x6ab4c3b0,	0xebba1c32,	0x469a230a,
+0x8a7d6315,	0x2fc24d3e,	0x82506f79,	0x18dbb9d6,
+0x1a7bbeb1,	0x355a1d62,	0x2e7eb594,	0x09f8dea9,
+0x432a49e4,	0xbf520253,	0xdafa4010,	0x893a858a,
+0x766e0efb,	0xd91e196d,	0x838bd2ef,	0xe5146494,
+0xd515f413,	0x29704828,	0xe85598b6,	0xdcbe6c51,
+0x88eabbfa,	0xa1e8909f,	0xd8931721,	0x35386554,
+0x089a78a7,	0xd9914775,	0xd4644748,	0x1556a4dc,
+0xf44448f6,	0xd054d7db,	0xf30f2b7d,	0x5ae223d0,
+0xcbbb48b0,	0x5c8b0383,	0x177de157,	0x9c1e5f73,
+0x2ec28289,	0xd72a7b6c,	0x823b6eb2,	0x35e02171,
+0xba8deae4,	0x06f4d468,	0x13dbafaa,	0x72b419f1,
+0x033385b5,	0x05806920,	0x4c6034cf,	0x9bd117dc,
+0x976e2d04,	0x250330f0,	0x7250b5e1,	0x184980c2,
+0x12a9d7d6,	0x1bc808f9,	0xae79994f,	0xc6f87901,
+0xc0e3132f,	0x671491c5,	0x236cad39,	0x37889d9c,
+0x67f7c3f3,	0x964a6be5,	0xbcced7da,	0x57eeaa6e,
+0x7bca1522,	0x654fee4c,	0x2a1ca5d9,	0xa1803cf3,
+0x00000011,	0x3f96e33b,	0xbcc97e7d,	0xfecb5781,
+0x24a87ac3,	0x281fad3d,	0x6c5d0169,	0x406f3d4b,
+0x1bedf9bf,	0x514f3332,	0xb33e1926,	0x539139d4,
+0x0b5a03bb,	0x7948224c,	0x403919aa,	0xd30c64b2,
+0xb1df420a,	0xbc62cb65,	0x8b036cd8,	0x662064a0,
+0x7381ae61,	0xfb070274,	0x9a3978d9,	0x051c1cbd,
+0x7bcfb857,	0x2c94fcc0,	0x25f643f1,	0xda3d4463,
+0x8aad6318,	0xabd2966c,	0x663d015a,	0x9fe4c504,
+0x43786fce,	0xa1b3dfdc,	0x435783a4,	0x1e44e90a,
+0x85ae6018,	0x9402a6c9,	0x709f4d13,	0x1bdec841,
+0x4840a539,	0xaa446221,	0x27401d2d,	0x1e0d39c6,
+0x6ae8973f,	0xc8b603b8,	0x8044340d,	0x9a4846e1,
+0xf7e68ad9,	0xd2a0cbd1,	0xc64bf2bf,	0x51286697,
+0xf3110b6f,	0x1562e9dc,	0xc682712e,	0x5cfbda8f,
+0x0d575c4f,	0x929f8530,	0x69abd158,	0x41c783e1,
+0xbfe313de,	0x33cbec29,	0xbcbddb8a,	0xe0861b12,
+0x866f3884,	0xf3b79ad6,	0x3415ad37,	0x3a17893c,
+0xb29694df,	0xecd242ce,	0x5d8231ef,	0x5b208f8f,
+0xc781cb94,	0xeb8dc8b8,	0x9d04fd73,	0x4639b3f9,
+0x543fbc28,	0x3957879c,	0xc7f0d4a1,	0x29ac4965,
+0x10f47a96,	0xf7d5b5ce,	0x8ed0c39f,	0x5a36d20f,
+0xff5bd157,	0xf4a3152e,	0xfa9087b4,	0xe4021354,
+0x2b394395,	0x118d8abd,	0xa6ef26da,	0xe47688e5,
+0x15352ccd,	0xa2a1120c,	0xf86a3b13,	0x3453d233,
+0x74d464e9,	0x28cb0910,	0x1c0d9908,	0xf7a672c4,
+0xa725013d,	0xfd618f4a,	0x2035f826,	0x2544d00b,
+0xe6bd2f30,	0xd6e3992f,	0xf7f39f5e,	0x282a3593,
+0x00de27bf,	0x5d0470c2,	0x14473c88,	0xc763ad23,
+0x2ccd5c60,	0x71f0d333,	0x09e8b8cd,	0x716fd1e1,
+0x2dfd1003,	0x006b819f,	0x7b157ad2,	0xa6305470,
+0xcde50f1a,	0x955bc9c8,	0xbe464835,	0xf67f9b33,
+0x21ab56ea,	0xc133d4c6,	0x77d754bf,	0x130877e0,
+0xbd1b247a,	0x7840690d,	0xe6174dd0,	0x61d13bfd,
+0x675ae943,	0x9149e21b,	0xce8ddf65,	0xe06ca163,
+0x33ee3750,	0xa89318e4,	0xa5476a0f,	0x72d15429,
+0x1442d6e5,	0x13f70d65,	0x81923d22,	0x4eefbbc5,
+0x1af2cbf1,	0x052ae881,	0x2fcb621a,	0x44e6c1f6,
+0x10c0c127,	0x6132dbfc,	0x0b3e5d38,	0x18379c7c,
+0x24848ccf,	0xb929cddf,	0xbd0c9549,	0x68d44ac1,
+0xf1a4967b,	0x60d466f9,	0x60a12700,	0x6bdf875f,
+0x2d8255a9,	0x464c149d,	0x32c047ee,	0x5d744d6c,
+0xdf44c2b2,	0xda41f152,	0xb83bd853,	0x3f612ed9,
+0xcecd3f95,	0xde938fc5,	0x2120712d,	0x6e895650,
+0xa5d34947,	0xb5d7459d,	0x13df64d9,	0xf8d40e55,
+0x7f590e01,	0x1724e7cf,	0x5843ee08,	0xdce43dd9,
+0x574cae1c,	0x5ec349e6,	0x56ab1066,	0x7d518ee9,
+0x1f83b1fe,	0xac633b58,	0xcef8a5fd,	0xacf35357,
+0xa93932b1,	0x64e73ca0,	0xb824e2b0,	0xb6c68da4,
+0x287ee847,	0xec1dbf97,	0xd313d2fa,	0x9fe37eec,
+0x281d8559,	0x2fd0c6c7,	0x15e9a89a,	0x273e9932,
+0xf081dec8,	0xa04d5e16,	0x8a3ac66a,	0xe5b25b5c,
+0x4138b7b3,	0xace013c4,	0xe5bee1c8,	0xd9daafd4,
+0x952af837,	0xf28c36bf,	0xcdff2a71,	0xa1cf3b94,
+0x8821440c,	0x3693fab8,	0xd6d2d0d0,	0xa2ccd66d,
+0xe8736467,	0x8a8952f8,	0xe32db4d9,	0x47b71bdf,
+0x620f3c22,	0xdb2922a7,	0x98e5cc6b,	0x905be886,
+0x822feb82,	0xf722cf0c,	0x7a356d80,	0x9c6b3ab6,
+0x19a3cc17,	0x08dfaf09,	0x4c99a23d,	0x0926d99e,
+0xa81577e5,	0xc684495a,	0x359aa743,	0xbc7aa166,
+0xaac2e24d,	0x16110785,	0x8ccc6fbc,	0xfd90cf70,
+0xb34be19c,	0xf57fef0d,	0x9c29c8a7,	0x022c249d,
+0x946cef68,	0xe07b7779,	0x4f6ea6b4,	0xe3a4eef4,
+0xfed31061,	0x96e78ae9,	0x220c0f91,	0x30aca707,
+0xa081c7b9,	0x159dc936,	0x4cbaa290,	0x447910e2,
+0x6ec95f93,	0x3cc3fde8,	0xce2c17a1,	0x4f18c4cb,
+0x025605b1,	0xbce02471,	0x21656693,	0x9368f6cd,
+0x0c19760f,	0xcc35da81,	0x4c5edab1,	0x85a0890e,
+0xbc5b861e,	0x203a23a6,	0xddc7d7ed,	0x0b585825,
+0xec9e7ab2,	0x1f1ad49a,	0xa7444b1f,	0xe77976b4,
+0x99e8c05e,	0x8b04c7c2,	0xb1aeb88b,	0x416d07ac,
+0x5a5689be,	0xe4094686,	0xe048c8e6,	0x2e0259dd,
+0xd2fe1113,	0x6190504b,	0xa0352318,	0x6f0cae7c,
+0x040da641,	0x29fab483,	0x2e354a07,	0xab62c485,
+0xbd787e0a,	0xc345308c,	0xc8ab8568,	0xf75adc1d,
+0x82b55654,	0x6cf29bbf,	0x8786a46e,	0x433c20d2,
+0x9229c1ee,	0x5e8eedf5,	0xab9bb981,	0x1a1a5419,
+0x97994816,	0x010eef10,	0x0172fd65,	0x975b8297,
+0xff6c4377,	0x6fca39f8,	0x13accf88,	0x94f05a02,
+0x5a772f20,	0xfbf97bca,	0x60801139,	0x64cbd0a6,
+0x72512821,	0x0830cb9a,	0x402f033c,	0xd0e2a50d,
+0x7ac45ee3,	0xbae23515,	0xd213695d,	0x72016572,
+0x20651143,	0x3552bc4d,	0xf014ebb1,	0x9aeebedf,
+0xee65d90f,	0x53abd424,	0x841f5383,	0xa43a2e44,
+0xee379480,	0x1638e568,	0x2573aad0,	0x2e935090,
+0xb9dcbe13,	0x9cdc4e30,	0xce8d170c,	0xbc546d14,
+0x18b77a7b,	0x3b652642,	0x79ae26c2,	0x5ab240c2,
+0xf74cfe35,	0x30be64cf,	0x3b5e7456,	0x81be84d1,
+0x12bb10db,	0x573da6b3,	0x83e28efe,	0x395c1512,
+0xf11928ee,	0xe64d50b5,	0x6f714c8b,	0xb3393f61,
+0x13b6b2f4,	0x0ab3b2aa,	0x5cada4c7,	0x19dfb423,
+0xe7b1c195,	0x47ee32d7,	0x03ab86bd,	0x08b8a8c6,
+0xdc7a6cdf,	0x3e5b4f68,	0x9ea0e297,	0x13193f7e,
+0x8fe31f30,	0x6118a11c,	0xc0762196,	0x9fd26fc0,
+0x9f515662,	0x5a1abb55,	0x5e434855,	0x4c6af26a,
+0x163cf95d,	0xa54ee076,	0xb41a0c1a,	0xf8a8affb,
+0x69db8391,	0xa7204db3,	0x86dc9909,	0x25ba82c5,
+0x04154f7a,	0xa191c23a,	0x6f3ee8ed,	0x55162d2b,
+0x14f9478d,	0xc717fb1c,	0x91408cdd,	0x7a87a50d,
+0x44d10ceb,	0xd04b5347,	0x82a3b3ce,	0x07e3998e,
+0x1dafee6f,	0x77c24219,	0x4ff885ef,	0xd994194a,
+0xfeff078a,	0x20f4b18a,	0x529676bd,	0x17738de7,
+0x01f8491b,	0xe31d2728,	0x34e5155b,	0x87120d79,
+0xb96f615c,	0xd6d15cd2,	0x4a1f66a8,	0xa0b37474,
+0x0713a36e,	0x70df574c,	0xe6015de6,	0x5f50f282,
+0xbd828397,	0xda75bb9f,	0x13e35581,	0x5bb84a7f,
+0xf66216ca,	0xac35d098,	0xff3a8f78,	0xb43a2d55,
+0xcb820994,	0x74f97ab1,	0x0ebb37aa,	0x5457d670,
+0xc7617908,	0x5f0ad21e,	0xeb8a4b9f,	0x0c678bc7,
+0x705cb6ce,	0xc2b3ef2a,	0x89c0c723,	0xab4399a9,
+0xc2216b3e,	0x9adda9ee,	0x82c7bfa0,	0x9d56f661,
+0x0f715ee5,	0x627d8182,	0x306a00b9,	0x2d9c259c,
+0x251b933c,	0x67fbe9e7,	0x103e2322,	0x29d1c68a,
+0x8f019d2f,	0x077e80b4,	0xbbbd9c2a,	0x266f4f74,
+0x96b32213,	0x5019c61d,	0x4a59782c,	0x8810efb7,
+0xfa55eaae,	0xbabe0b82,	0x956cae7f,	0xf016453c,
+0x255e2b2a,	0x1b805b17,	0x9c9b51cb,	0x0eaafa33,
+0x45fb3835,	0x2c2070d2,	0x70005da8,	0xf39c43b4,
+0x78c372ac,	0xa6fe8b80,	0x473ab824,	0x758cf1c0,
+0x8d012210,	0x8e26dc51,	0xf8f88450,	0xd1ffe2b8,
+0xa36a40ff,	0xbed11609,	0xaaa32039,	0xbc6ee3b5,
+0x36f84b62,	0xbacf3880,	0x26af8917,	0x9c6cb47f,
+0xa2a70b0b,	0x4b003af3,	0x83d9d354,	0x7aa355ce,
+0x75ec5db9,	0xa4384855,	0x0e8ac979,	0xa55a370e,
+0xbb3af0dd,	0x42153802,	0x32531de8,	0xe57570a8,
+0xe490a98c,	0xa9a910ee,	0x453953a6,	0x1348535e,
+0xb73595c5,	0x89bcd5dd,	0x0c68cc61,	0x5e880831,
+0x65cf0e50,	0xa4ccd3ac,	0xe61f9f5f,	0x01b610b0,
+0x7387c5aa,	0x6458654f,	0x35bbb16c,	0x90e9e91c,
+0xc56957f2,	0xaadb7f70,	0x07732d08,	0xce4ad932,
+0x7fa3e135,	0x31a83cad,	0x43271bcf,	0xa74b4eab,
+0x4f483674,	0x9cc84d3c,	0x7562feb5,	0x0b445b18,
+0xc1b1b769,	0xcfd31f23,	0xdf6f0843,	0x56789e7b,
+0x0ed7daf8,	0xe28e3610,	0x0b516cac,	0x5d805128,
+0xe430861d,	0x993bc596,	0xd85434cb,	0x740f7d13,
+0xe91e0d47,	0xe518a80f,	0xf729e13a,	0xd7fde910,
+0x838697c0,	0xf25c49b6,	0x7b9a6956,	0x70c8cb88,
+0xe5befc43,	0x84e0cd72,	0x2799a866,	0x62f8241e,
+0xa13dd267,	0x675404c0,	0x107995e6,	0xd5a44abb,
+0xe8b14bc2,	0x299705c4,	0xe691d679,	0x2a72edfa,
+0x353adfa6,	0x89aa4a58,	0x22247d90,	0x5a97fc14,
+0x09843de7,	0x4537f188,	0x7cd7cb9c,	0x7395900f,
+0xa178c352,	0x96fff660,	0x3b1d36a9,	0x7872cd2c,
+0x4e8e86ac,	0x6d0d129e,	0x366d1810,	0x84e4869f,
+0x9d73317d,	0xfc92685c,	0x6b3ba9cf,	0x573d9a1f,
+0xa5e5a1bd,	0x29620cbd,	0xd7a53209,	0x156f5151,
+0x58a48a3b,	0x91e00b57,	0xf68f1270,	0xb0911b95,
+0xf33c953b,	0x7402498a,	0x7cd9d9b5,	0x7f306060,
+0x08de3b88,	0x4e1b3dfa,	0xb7f0044f,	0x1e215ef7,
+0xaa6a9016,	0xdc45a3f7,	0x6a5266f9,	0x44f25fa1,
+0x64d10347,	0xf518fca6,	0x0043e846,	0x9f768875,
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+0xadb81dfc,	0x3770a8b2,	0x473d8f26,	0x1e775e35,
+0x259f5ad7,	0x13fef5c5,	0x3aa92640,	0x5a76c79b,
+0xdfa3ff6b,	0x43d6bba4,	0xae2a900e,	0x8c698a3e,
+0x51ce5a96,	0x66908c24,	0x0911f46e,	0x70d619f7,
+0x972efb65,	0xb5c23792,	0x1b3ee153,	0x909746c1,
+0x8370fa25,	0xbcde8c5c,	0x1aa4f41d,	0x373a398a,
+0x3c8559a2,	0x4b528ba2,	0x54019afe,	0xe409c632,
+0x160581e2,	0x7e30d7d4,	0xf841f0a0,	0xdc1d200a,
+0x46ed47de,	0x0f77093c,	0xac835c24,	0x2ce29974,
+0xc031bfe9,	0xe879d971,	0xa67200ee,	0x3fe62089,
+0x90a38599,	0xcf7107d2,	0x45b49b01,	0xebb5ad89,
+0x8f42d795,	0x77b19427,	0x800e71fa,	0x6bc93b64,
+0xc0cdf4d6,	0x97dc9d9f,	0x7cf2edd3,	0xcb482372,
+0x6221fd9e,	0x84492515,	0xbd2b7283,	0xfc15f19e,
+0x547a79ae,	0x73337e65,	0xec64a1de,	0x822bf271,
+0x65c6b44a,	0x6d3246ea,	0x464aa85a,	0xd5110102,
+0x2578e4ef,	0xb5c4273f,	0xef03fde4,	0x1c5358fd,
+0x9b30fb66,	0x214b5514,	0xc7c50eb5,	0x76372928,
+0x5ec235f3,	0x20df4fbc,	0x12c684c5,	0x141308c1,
+0x1ffda6ae,	0x1a64f972,	0xad2f29b8,	0x4de7315a,
+0xd0fa953d,	0x8c55fe93,	0xa375129d,	0xd120f9b8,
+0xbb20cb19,	0x535d873d,	0x1fa8e047,	0x6dd4c1f5,
+0xd456632c,	0xa388867b,	0x762656d5,	0x00812012,
+0x1225a049,	0xf7900f05,	0x5b50f75d,	0xf720a919,
+0xbb8dcb70,	0xa6d48d13,	0xf750522c,	0x8ad277b3,
+0x334daf09,	0x5f882b42,	0x38a53713,	0xe9bbeef7,
+0xcc7fd1d6,	0xda484573,	0x4b3e2894,	0xbc0ef5ab,
+0xb2be1128,	0x88f27a64,	0x84ccdf55,	0x93aca22b,
+0x80b9641e,	0xa2bc2354,	0x5d78ca97,	0xb36ab105,
+0xdeb4d233,	0xe7e653bc,	0x7a29de17,	0x950c7ece,
+0xca5e997c,	0x5b8d4b6c,	0xaa5b0c7f,	0x2048cacf,
+0x71bd96bf,	0x580520f9,	0xc4da2129,	0xa3f0d78e,
+0x5235e085,	0x30c220c3,	0x2edbb5eb,	0xd12227ed,
+0x67f8faf5,	0x0d5f8ef1,	0xd8176ac6,	0x1ee955f7,
+0x13b75133,	0xb935ee9d,	0xdfe2d54f,	0x43ff1de9,
+0x6e848017,	0x4011e255,	0x5180f71b,	0x72ed0330,
+0xc737adbd,	0x7f6839a6,	0x142bd2d2,	0x66d6143b,
+0x69cf3cd0,	0x9b492cb9,	0x3266f995,	0x8ce763fe,
+0xdf8493e0,	0x8a981e31,	0xe6351c8e,	0xb0fd34fe,
+0xdc236978,	0x385f0118,	0x1c44fcdb,	0xcf70bb77,
+0x6046d066,	0x2d9475af,	0x3799ac4b,	0xe9efc39c,
+0x90d0450c,	0xa40a5fc6,	0xcfb5ef83,	0x049854c0,
+0x7215e231,	0x0424cc7e,	0x56ad0075,	0xff0a28a0,
+0x7488be97,	0xe1f82798,	0xc445794d,	0xeb7dd129,
+0x631403b5,	0xfcfd85de,	0xbf795cac,	0x00aafac9,
+0x6a2fe3ec,	0x294c2bde,	0x12861212,	0xddff6bfb,
+0xb0b29b5a,	0x46387e2d,	0x4a5a42a2,	0x4549f462,
+0x4f20df9b,	0xd189a190,	0x0ef70bb7,	0xa544ce4b,
+0x44a69377,	0x5e8c0f35,	0x2ecf5b5c,	0x0c1b08be,
+0x7f054c31,	0x73ed91a2,	0x82cd81c4,	0xf693111c,
+0x1ce7be10,	0x55d7acf8,	0x015c32a7,	0x5a3d7795,
+0x1372ac6d,	0x038755f6,	0xd1ed8be2,	0xe1b2bd04,
+0x20f3c81c,	0x326ffd81,	0x658c1e11,	0x37f74017,
+0x0a8388b2,	0xa8e74512,	0xcb9f97ab,	0x3588376e,
+0x483048d2,	0xe3ee2145,	0x029eba71,	0x2a6efdb8,
+0x7e629d7c,	0xe7458f31,	0xd2edd71b,	0xa265588c,
+0xee3a7a3d,	0xc3f6a74d,	0xb55fbbb2,	0xac3dc469,
+0x350e24ac,	0xfdfb094c,	0xc6760d93,	0x014aad92,
+0x4bf74e51,	0x9ab932af,	0xc600d00f,	0x5dd0c96d,
+0x6b081fbe,	0xecba3e1c,	0x19abcf55,	0x46905ea0,
+0x41ff2a8f,	0x9305e1c0,	0xdbfa1df1,	0x8100370e,
+0x0df9b3df,	0x09763efc,	0x60447b79,	0xb64eb88a,
+0xe4c706de,	0x2dadc973,	0xf6bc6357,	0x7395486a,
+0xf15aae31,	0x1daca268,	0xa5b8395f,	0x127bcb11,
+0xe84c9715,	0xe0417152,	0xc3d8520e,	0x0bdcbb00,
+0xf3daba82,	0xe1925ffb,	0x3526a2e8,	0xda189c78,
+0xa32bf2fc,	0xe7de02ab,	0x2f344593,	0x07b916dd,
+0xe2d46b57,	0x83921885,	0x6f066626,	0x7ce5ab67,
+0xebcaf5de,	0xbb0f6b00,	0x6d1faffb,	0x1eff0018,
+0x2debe6bc,	0x57d003b3,	0x3a3f5f80,	0xec6b7c0e,
+0x9f1dd663,	0xbebdbf56,	0x98e5774e,	0xb7a29504,
+0x5166a8c5,	0xaf7ce332,	0xca5e70c5,	0xfe235309,
+0x9c23f707,	0x99b08cc4,	0x2fe1edd1,	0xba36918f,
+0x262dd395,	0x423edc8c,	0x801e8f1f,	0x5b4cc6c5,
+0x3fcdf7f4,	0x5a490992,	0xd4006978,	0x977e2f86,
+0x6311af7b,	0x06bb2412,	0x2be72eb1,	0x5706b252,
+0xa000c75b,	0xe3ea5cff,	0xc9208730,	0xd9e369fb,
+0x1aed50e2,	0x8916d70d,	0x87f01eb6,	0x663b8f67,
+0x3dc68ee3,	0x5197b72b,	0xddb19fb8,	0x6839be2a,
+0x99fcfc25,	0x5542f267,	0xa922eea9,	0xc9ae9d93,
+0xcf8a9d64,	0x76bfeec4,	0xacbcd4c6,	0x81960ab0,
+0x7b24eb81,	0x8e8cad81,	0xfb2c1362,	0x9ccf1224,
+0x16d2c962,	0x18f7d553,	0x2a7f9c1e,	0x3678f775,
+0x1210588a,	0xe1644769,	0x3dd29db7,	0xbe9daa2c,
+0xe9c4e13a,	0x8d9de528,	0x19c3075e,	0x68a336d4,
+0x0ba157f3,	0xe3780ca6,	0x69c54c28,	0x9f96bb00,
+0xa78204e9,	0x1c8627cf,	0x2fd52aa9,	0x957b15ed,
+0xd3d61e03,	0x658cea71,	0x42d77750,	0x0c0755bc,
+0xde372a0d,	0x0d3687d7,	0xc04c56f6,	0xc3882257,
+0x98fd462c,	0xb65fac1e,	0x01b5ecab,	0xd554413d,
+0xb4beec40,	0xb4caab5e,	0xdeee4085,	0xd1b0500c,
+0x6845de70,	0x5a06e889,	0xfc89a4a7,	0xedbfd435,
+0xac039058,	0x9c1acd2f,	0x876fbfac,	0x9d8b83f3,
+0x8aa71c5f,	0x2e0f12ef,	0x87ff0c68,	0x53a9d19a,
+0x0ee62d27,	0x5d93a3f4,	0x7f13dc77,	0xd4ec7c79,
+0xd72a35c8,	0xb84ba058,	0x21e1d1ad,	0xbcf9c0fe,
+0x106fb166,	0x84ff4a86,	0x3b2d960f,	0x4cf3ab0e,
+0x65d25f76,	0xdcda7e29,	0xc444ddc8,	0xe97096dc,
+0xbfe1815c,	0x25b9dec5,	0x7aed80de,	0x6cbb6f7a,
+0x2daf76b7,	0x249ee47f,	0xdc6e770d,	0xa5a02e7d,
+0xd019d0d7,	0x17feead1,	0xbf80c1f6,	0x83644ac0,
+0x412f1ce4,	0x59c1de41,	0x1a47db26,	0x8848ab89,
+0xc2c17745,	0x31183c80,	0x9bb13cc3,	0x6da9c349,
+0x414b378d,	0xd58df4ba,	0x41f5ca37,	0x02a5162f,
+0x2843bb24,	0xbd2bb85a,	0x0b2c6e81,	0x2d50fe1d,
+0xc67b2c07,	0x630ce2b3,	0x73274d84,	0x3b4ba900,
+0x5e672d3c,	0x7ef23846,	0x81036625,	0x380b3d3b,
+0x391470b1,	0x5b3dcbed,	0x63038751,	0xa0c7aed8,
+0xc185b677,	0x516b8170,	0xbf79f025,	0x2b4c9edb,
+0x29354139,	0x9deabe33,	0x2838f581,	0x0574281f,
+0xc1267da2,	0x0c070755,	0x6832a8b9,	0x57436eed,
+0xe604c645,	0x4f13172a,	0x3227ac12,	0xf6b78267,
+0xbbd5d003,	0x5f8ae7ed,	0x74b6682c,	0x356b9e81,
+0x82703c20,	0x8ccf1f78,	0xa6b79197,	0x434d5316,
+0x1ba0853a,	0xe6ae4829,	0x1193ed0a,	0xa2d171f0,
+0x4f565a15,	0xf78ea4af,	0xa9a27e39,	0x30a45316,
+0xc005a8f6,	0x79a23d86,	0x07edcbe3,	0x3b76806b,
+0x3df6268a,	0xb0f33186,	0x2fd51855,	0xb34efefe,
+0xa24ce423,	0x6c62d711,	0x335c7252,	0x0d2ddcff,
+0x64485539,	0x00c8a89e,	0x4827ad2d,	0x01de50f4,
+0x593a9a38,	0xee90b919,	0xf523cd40,	0x97ed7009,
+0x1038e6b0,	0x95931966,	0xaaac22b9,	0xef1b9915,
+0x23f6d33c,	0xe417a460,	0x4e9b59c2,	0x3fd38b75,
+0x7ceabd08,	0x8279d672,	0xf24936e8,	0x668630f8,
+0x3cb0ddc0,	0x56c56418,	0x91221ef8,	0xc8926c65,
+0x4d7436b6,	0xc06b5b1e,	0xdea496b1,	0x4fa4c971,
+0xeea15028,	0x7aead456,	0x1329b826,	0xcf9a4d4f,
+0xabd69aba,	0x9dd78c2e,	0x5e9782ff,	0x563f3cb0,
+0xfc2db55c,	0xb2d5f64b,	0x9478caeb,	0x7409ae76,
+0xc4690516,	0xb12bb352,	0xad5283c7,	0x608e7a23,
+0xc8b4b59a,	0x0da06391,	0x9a6ccd78,	0xe4af91ad,
+0xb156f74a,	0x790b21dd,	0x6ce9970b,	0x46e89ac1,
+0x07815d28,	0x1f2fc3ac,	0x690cd168,	0x6ae48bb4,
+0x1ed48c84,	0xe5f121a3,	0x49a762cf,	0xc5e8fd6a,
+0x75d45162,	0xf49c2c5e,	0xd161eb4a,	0xb6351b73,
+0xc2605562,	0xb097aa9d,	0x114421ee,	0xf93baf78,
+0x82b9b2ab,	0x0374be4d,	0xd715656b,	0x3524549f,
+0xb37dc283,	0xfa8308d0,	0x3f69f2be,	0x238bc31e,
+0x839f3f68,	0x0639b8d7,	0xa8cdbe8e,	0xd15c7cb3,
+0x0a31ec87,	0x39a57286,	0x7c3ffef5,	0x461d70b2,
+0x7d1e8a90,	0x629b803f,	0x351b6cb8,	0x255391c2,
+0x07215420,	0x5e1aef8c,	0xa3b48e74,	0x8fa78c73,
+0xb6fab65c,	0xb13cb77f,	0x5bd44236,	0x31cbeab2,
+0x9f68d29a,	0x207a2b05,	0x668ac8a7,	0xb6de6033,
+0x3d2a4173,	0x04a2543a,	0x559b1b7c,	0x5e9116d4,
+0x5cb3ee57,	0x4a47f644,	0x90be9381,	0xbccc9cd2,
+0x3160e0d5,	0xed791f87,	0xdd9da7a8,	0x3e6d398b,
+0x6a68ad78,	0x418974ef,	0xfd010940,	0x8bed7055,
+0xf21e4d13,	0xac8160b9,	0x85f10ecb,	0xd637b0e2,
+0x987dd54e,	0x9835f225,	0xdbee940c,	0x9a34e16d,
+0x15fcfb54,	0x6720e48c,	0x9a42e266,	0x31eb0270,
+0x714dee04,	0xbcd417d8,	0xedf7757e,	0x099c4e89,
+0xee3e6c2e,	0x6246d530,	0xfbdad1d6,	0xbbe301a3,
+0xe08f829c,	0xa3c7d9c4,	0xe753a1dd,	0xf1466da1,
+0xa1e353a7,	0x33828150,	0x267d4059,	0x458bd806,
+0xac0ed307,	0x2079bf7c,	0xb25200db,	0x9dfd338c,
+0x0b94573e,	0x8188fa16,	0x9e641b63,	0xafa2a60c,
+0x61e5f820,	0x63a38983,	0x172d3a6f,	0xc98a34b2,
+0x532b56f5,	0x1883cb1a,	0x93ba9692,	0x7d85d109,
+0xd20ffd1a,	0xcc6e9937,	0xb3813eb1,	0xea7e1b45,
+0xf1e09c71,	0x35aa1ab9,	0xbd2d43d7,	0xc53a07ef,
+0xf3fa3fd6,	0xf3cd1e20,	0x5e620481,	0xd7bec1b0,
+0xc7d3caf6,	0xe9eae29f,	0x19c5b2c1,	0x940e3186,
+0x200f0a30,	0xbaf511b1,	0x103cb39c,	0x3f46b067,
+0xba6c5e9a,	0xc32b5592,	0x393e8503,	0x7ea29847,
+0x04d4a493,	0x18fc67d5,	0xea4ff94e,	0xc0281d5e,
+0xaeeaae85,	0x13be6b70,	0xa1bc8be4,	0xa1edbe06,
+0x572b8b35,	0x3baca7c5,	0x06ac9591,	0x8309b11d,
+0x7f381b05,	0xb16dd9b2,	0xf9b5d898,	0xb2e04c3a,
+0xed89b7dd,	0xd30e7e33,	0x4ac6cb61,	0xd2c50800,
+0x6554ae61,	0xa263efe2,	0x666244c3,	0xb6aaa480,
+0xcb4344ee,	0x31cf3efa,	0x14a4a476,	0xf6804765,
+0xaca47c23,	0x7e15ae69,	0xaffade7d,	0x693a6ff9,
+0x3f0f22c0,	0xe6135bcb,	0xf0632009,	0x06fa2abb,
+0xad0c1085,	0x3ce130b3,	0x70001594,	0xd80c452b,
+0x486c9d1f,	0x93b94966,	0x81612f95,	0x7573faea,
+0x1568ddb9,	0x3c1d26e5,	0x0a5d7b45,	0x5ea78077,
+0x1c5491f9,	0x24363c4b,	0x54b8e62a,	0xb86697e6,
+0x18750c76,	0xa355cee8,	0x9c09de46,	0xb022ec2b,
+0xfa142272,	0xd1e1dcce,	0xc7c2f6c9,	0xd8e72fc1,
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
new file mode 100644
index 0000000..3343d11
--- /dev/null
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -0,0 +1,98 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_INTEL_MODEL_206AX_H
+#define _CPU_INTEL_MODEL_206AX_H
+
+/* SandyBridge bus clock is fixed at 100MHz */
+#define SANDYBRIDGE_BCLK		100
+
+#define IA32_FEATURE_CONTROL		0x3a
+#define  CPUID_VMX			(1 << 5)
+#define  CPUID_SMX			(1 << 6)
+#define MSR_FEATURE_CONFIG		0x13c
+#define IA32_PLATFORM_DCA_CAP		0x1f8
+#define IA32_MISC_ENABLE		0x1a0
+#define IA32_PERF_CTL 			0x199
+#define IA32_THERM_INTERRUPT		0x19b
+#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define  ENERGY_POLICY_PERFORMANCE	0
+#define  ENERGY_POLICY_NORMAL		6
+#define  ENERGY_POLICY_POWERSAVE	15
+#define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
+#define MSR_LT_LOCK_MEMORY		0x2e7
+#define IA32_MC0_STATUS 		0x401
+
+#define MSR_PIC_MSG_CONTROL		0x2e
+#define MSR_PLATFORM_INFO		0xce
+#define  PLATFORM_INFO_SET_TDP		(1 << 29)
+#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PMG_IO_CAPTURE_BASE		0xe4
+
+#define MSR_MISC_PWR_MGMT		0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS	(1 << 0)
+#define MSR_TURBO_RATIO_LIMIT		0x1ad
+#define MSR_POWER_CTL			0x1fc
+
+#define MSR_PKGC3_IRTL			0x60a
+#define MSR_PKGC6_IRTL			0x60b
+#define MSR_PKGC7_IRTL			0x60c
+#define  IRTL_VALID			(1 << 15)
+#define  IRTL_1_NS			(0 << 10)
+#define  IRTL_32_NS			(1 << 10)
+#define  IRTL_1024_NS			(2 << 10)
+#define  IRTL_32768_NS			(3 << 10)
+#define  IRTL_1048576_NS		(4 << 10)
+#define  IRTL_33554432_NS		(5 << 10)
+#define  IRTL_RESPONSE_MASK		(0x3ff)
+
+/* long duration in low dword, short duration in high dword */
+#define MSR_PKG_POWER_LIMIT		0x610
+#define  PKG_POWER_LIMIT_MASK		0x7fff
+#define  PKG_POWER_LIMIT_EN		(1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP		(1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT	17
+#define  PKG_POWER_LIMIT_TIME_MASK	0x7f
+
+#define MSR_PP0_CURRENT_CONFIG		0x601
+#define  PP0_CURRENT_LIMIT		(112 << 3) /* 112 A */
+#define MSR_PP1_CURRENT_CONFIG		0x602
+#define  PP1_CURRENT_LIMIT		(35 << 3) /* 35 A */
+#define MSR_PKG_POWER_SKU_UNIT		0x606
+#define MSR_PKG_POWER_SKU		0x614
+#define MSR_PP0_POWER_LIMIT		0x638
+#define MSR_PP1_POWER_LIMIT		0x640
+
+/* P-state configuration */
+#define PSS_MAX_ENTRIES			8
+#define PSS_RATIO_STEP			2
+#define PSS_LATENCY_TRANSITION		10
+#define PSS_LATENCY_BUSMASTER		10
+
+#ifdef __SMM__
+/* Lock MSRs */
+void intel_model_206ax_finalize_smm(void);
+#else
+/* Configure power limits for turbo mode */
+void set_power_limits(u8 power_limit_1_time);
+#endif
+
+#endif
diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c
new file mode 100644
index 0000000..dc78cee
--- /dev/null
+++ b/src/cpu/intel/model_206ax/model_206ax_init.c
@@ -0,0 +1,559 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/name.h>
+#include <pc80/mc146818rtc.h>
+#include <usbdebug.h>
+#include "model_206ax.h"
+
+/*
+ * List of suported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* MWAIT State 0 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C3 */
+		.latency = 63,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 4: C6 */
+		.latency = 87,
+		.power = 350,
+		.resource = {
+			.addrl = 0x20,	/* MWAIT State 2 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 5: C7 */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 6: C7S */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{ 0 }
+};
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_00000025.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+static void enable_vmx(void)
+{
+	struct cpuid_result regs;
+	msr_t msr;
+	int enable = 0;
+
+	if (get_option(&enable, "enable_vmx") < 0)
+		enable = 0;
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		/* VMX locked. If we set it again we get an illegal
+		 * instruction
+		 */
+		return;
+	}
+
+	regs = cpuid(1);
+	if (regs.ecx & CPUID_VMX) {
+		if (enable)
+			msr.lo |= (1 << 2);
+		else
+			msr.lo &= ~(1 << 2);
+
+		if (regs.ecx & CPUID_SMX) {
+			if (enable)
+				msr.lo |= (1 << 1);
+			else
+				msr.lo &= ~(1 << 1);
+		}
+	}
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+/* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
+static const u8 power_limit_time_sec_to_msr[] = {
+	[0]   = 0x00,
+	[1]   = 0x0a,
+	[2]   = 0x0b,
+	[3]   = 0x4b,
+	[4]   = 0x0c,
+	[5]   = 0x2c,
+	[6]   = 0x4c,
+	[7]   = 0x6c,
+	[8]   = 0x0d,
+	[10]  = 0x2d,
+	[12]  = 0x4d,
+	[14]  = 0x6d,
+	[16]  = 0x0e,
+	[20]  = 0x2e,
+	[24]  = 0x4e,
+	[28]  = 0x6e,
+	[32]  = 0x0f,
+	[40]  = 0x2f,
+	[48]  = 0x4f,
+	[56]  = 0x6f,
+	[64]  = 0x10,
+	[80]  = 0x30,
+	[96]  = 0x50,
+	[112] = 0x70,
+	[128] = 0x11,
+};
+
+/* Convert POWER_LIMIT_1_TIME MSR value to seconds */
+static const u8 power_limit_time_msr_to_sec[] = {
+	[0x00] = 0,
+	[0x0a] = 1,
+	[0x0b] = 2,
+	[0x4b] = 3,
+	[0x0c] = 4,
+	[0x2c] = 5,
+	[0x4c] = 6,
+	[0x6c] = 7,
+	[0x0d] = 8,
+	[0x2d] = 10,
+	[0x4d] = 12,
+	[0x6d] = 14,
+	[0x0e] = 16,
+	[0x2e] = 20,
+	[0x4e] = 24,
+	[0x6e] = 28,
+	[0x0f] = 32,
+	[0x2f] = 40,
+	[0x4f] = 48,
+	[0x6f] = 56,
+	[0x10] = 64,
+	[0x30] = 80,
+	[0x50] = 96,
+	[0x70] = 112,
+	[0x11] = 128,
+};
+
+/*
+ * Configure processor power limits if possible
+ * This must be done AFTER set of BIOS_RESET_CPL
+ */
+void set_power_limits(u8 power_limit_1_time)
+{
+	msr_t msr = rdmsr(MSR_PLATFORM_INFO);
+	msr_t limit;
+	unsigned power_unit;
+	unsigned tdp, min_power, max_power, max_time;
+	u8 power_limit_1_val;
+
+	if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
+		return;
+
+	if (!(msr.lo & PLATFORM_INFO_SET_TDP))
+		return;
+
+	/* Get units */
+	msr = rdmsr(MSR_PKG_POWER_SKU_UNIT);
+	power_unit = 2 << ((msr.lo & 0xf) - 1);
+
+	/* Get power defaults for this SKU */
+	msr = rdmsr(MSR_PKG_POWER_SKU);
+	tdp = msr.lo & 0x7fff;
+	min_power = (msr.lo >> 16) & 0x7fff;
+	max_power = msr.hi & 0x7fff;
+	max_time = (msr.hi >> 16) & 0x7f;
+
+	printk(BIOS_DEBUG, "CPU TDP: %u Watts\n", tdp / power_unit);
+
+	if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
+		power_limit_1_time = power_limit_time_msr_to_sec[max_time];
+
+	if (min_power > 0 && tdp < min_power)
+		tdp = min_power;
+
+	if (max_power > 0 && tdp > max_power)
+		tdp = max_power;
+
+	power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
+
+	/* Set long term power limit to TDP */
+	limit.lo = 0;
+	limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
+	limit.lo |= PKG_POWER_LIMIT_EN;
+	limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
+		PKG_POWER_LIMIT_TIME_SHIFT;
+
+	/* Set short term power limit to 1.25 * TDP */
+	limit.hi = 0;
+	limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
+	limit.hi |= PKG_POWER_LIMIT_EN;
+	/* Power limit 2 time is only programmable on SNB EP/EX */
+
+	wrmsr(MSR_PKG_POWER_LIMIT, limit);
+}
+
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 28);	// C1 Auto Undemotion Enable
+	msr.lo |= (1 << 27);	// C3 Auto Undemotion Enable
+	msr.lo |= (1 << 26);	// C1 Auto Demotion Enable
+	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
+	msr.lo &= ~(1 << 10);	// Disable IO MWAIT redirection
+	msr.lo |= 7;		// No package C-state limit
+	wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr);
+
+	msr = rdmsr(MSR_PMG_IO_CAPTURE_BASE);
+	msr.lo &= ~0x7ffff;
+	msr.lo |= (PMB0_BASE + 4);	// LVL_2 base address
+	msr.lo |= (2 << 16);		// CST Range: C7 is max C-state
+	wrmsr(MSR_PMG_IO_CAPTURE_BASE, msr);
+
+	msr = rdmsr(MSR_MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
+	wrmsr(MSR_MISC_PWR_MGMT, msr);
+
+	msr = rdmsr(MSR_POWER_CTL);
+	msr.lo |= (1 << 18);	// Enable Energy Perf Bias MSR 0x1b0
+	msr.lo |= (1 << 1);	// C1E Enable
+	msr.lo |= (1 << 0);	// Bi-directional PROCHOT#
+	wrmsr(MSR_POWER_CTL, msr);
+
+	/* C3 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+	wrmsr(MSR_PKGC3_IRTL, msr);
+
+	/* C6 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+	wrmsr(MSR_PKGC6_IRTL, msr);
+
+	/* C7 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+	wrmsr(MSR_PKGC7_IRTL, msr);
+
+	/* Primary Plane Current Limit */
+	msr = rdmsr(MSR_PP0_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= PP0_CURRENT_LIMIT;
+	wrmsr(MSR_PP0_CURRENT_CONFIG, msr);
+
+	/* Secondary Plane Current Limit */
+	msr = rdmsr(MSR_PP1_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= PP1_CURRENT_LIMIT;
+	wrmsr(MSR_PP1_CURRENT_CONFIG, msr);
+}
+
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+static void configure_dca_cap(void)
+{
+	struct cpuid_result cpuid_regs;
+	msr_t msr;
+
+	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.ecx & (1 << 18)) {
+		msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+		msr.lo |= 1;
+		wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+	}
+}
+
+static void set_max_ratio(void)
+{
+	msr_t msr;
+
+	/* Platform Info bits 15:8 give max ratio */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	msr.hi = 0;
+	msr.lo &= 0xff00;
+	wrmsr(IA32_PERF_CTL, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: frequency set to %d\n",
+	       ((msr.lo >> 8) & 0xff) * 100);
+}
+
+static void set_energy_perf_bias(u8 policy)
+{
+	msr_t msr;
+
+	/* Energy Policy is bits 3:0 */
+	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: energy policy set to %u\n",
+	       policy);
+}
+
+static void configure_mca(void)
+{
+	msr_t msr;
+	int i;
+
+	msr.lo = msr.hi = 0;
+	/* This should only be done on a cold boot */
+	for (i = 0; i < 7; i++)
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static void intel_cores_init(device_t cpu)
+{
+	struct cpuid_result result;
+	unsigned cores, threads, i;
+
+	result = cpuid_ext(0xb, 0); /* Threads per core */
+	threads = result.ebx & 0xff;
+
+	result = cpuid_ext(0xb, 1); /* Cores per package */
+	cores = result.ebx & 0xff;
+
+	/* Only initialize extra cores from BSP */
+	if (cpu->path.apic.apic_id)
+		return;
+
+	printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n",
+	       cpu->path.apic.apic_id, cores, threads);
+
+	for (i = 1; i < cores; ++i) {
+		struct device_path cpu_path;
+		device_t new;
+
+		/* Build the cpu device path */
+		cpu_path.type = DEVICE_PATH_APIC;
+		cpu_path.apic.apic_id =
+			cpu->path.apic.apic_id + i;
+
+		/* Update APIC ID if no hyperthreading */
+		if (threads == 1)
+			cpu_path.apic.apic_id <<= 1;
+
+		/* Allocate the new cpu device structure */
+		new = alloc_dev(cpu->bus, &cpu_path);
+		if (!new)
+			continue;
+
+		printk(BIOS_DEBUG, "CPU: %u has core %u\n",
+		       cpu->path.apic.apic_id,
+		       new->path.apic.apic_id);
+
+		/* Start the new cpu */
+		if (!start_cpu(new)) {
+			/* Record the error in cpu? */
+			printk(BIOS_ERR, "CPU %u would not start!\n",
+			       new->path.apic.apic_id);
+		}
+	}
+}
+
+static void model_206ax_init(device_t cpu)
+{
+	char processor_name[49];
+	struct cpuid_result cpuid_regs;
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG
+	// Is this caution really needed?
+	if(!ehci_debug_addr)
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs based on physical address size */
+	cpuid_regs = cpuid(0x80000008);
+	x86_setup_fixed_mtrrs();
+	x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
+	x86_mtrr_check();
+
+	/* Setup Page Attribute Tables (PAT) */
+	// TODO set up PAT
+
+#if CONFIG_USBDEBUG
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+	setup_lapic();
+
+	/* Enable virtualization if enabled in CMOS */
+	enable_vmx();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Set Max Ratio */
+	set_max_ratio();
+
+	/* Enable Turbo */
+	enable_turbo();
+
+	/* Start up extra cores */
+	intel_cores_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_206ax_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */
+	{ X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */
+	{ X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+	.cstates  = cstate_map,
+};
+
diff --git a/src/cpu/intel/model_306ax/Kconfig b/src/cpu/intel/model_306ax/Kconfig
new file mode 100644
index 0000000..1954d75
--- /dev/null
+++ b/src/cpu/intel/model_306ax/Kconfig
@@ -0,0 +1,19 @@
+config CPU_INTEL_MODEL_206AX
+	bool
+	select SMP
+	select SSE2
+	select UDELAY_LAPIC
+	select AP_IN_SIPI_WAIT
+
+if CPU_INTEL_MODEL_206AX
+
+config BOOTBLOCK_CPU_INIT
+	string
+	default "cpu/intel/model_206ax/bootblock.c"
+
+config SERIAL_CPU_INIT
+	bool
+	default n
+
+endif
+
diff --git a/src/cpu/intel/model_306ax/Makefile.inc b/src/cpu/intel/model_306ax/Makefile.inc
new file mode 100644
index 0000000..67ead07
--- /dev/null
+++ b/src/cpu/intel/model_306ax/Makefile.inc
@@ -0,0 +1,6 @@
+driver-y += model_206ax_init.c
+subdirs-y += ../../x86/name
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+cpu_incs += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
diff --git a/src/cpu/intel/model_306ax/acpi.c b/src/cpu/intel/model_306ax/acpi.c
new file mode 100644
index 0000000..5160a64
--- /dev/null
+++ b/src/cpu/intel/model_306ax/acpi.c
@@ -0,0 +1,255 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+#include <cpu/intel/acpi.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "chip.h"
+
+#define MIN_POWER 16000
+#define MAX_POWER 35000
+
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	switch (c.x86_model) {
+	case 0x2a: /* SandyBridge */
+		result = cpuid_ext(0xb, 1);
+		cores = result.ebx & 0xff;
+		break;
+	default:
+		cores = (cpuid_ebx(1) >> 16) & 0xff;
+		break;
+	}
+
+	return cores;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0)
+		length += acpigen_write_CST_package(1, &cstates[c1]);
+	if (c2 > 0)
+		length += acpigen_write_CST_package(2, &cstates[c2]);
+	if (c3 > 0)
+		length += acpigen_write_CST_package(3, &cstates[c3]);
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_CST_table(struct cpu_intel_model_206ax_config *conf)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa1);		/* ElseOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					 conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	acpigen_patch_len(len - 1);
+	return len;
+}
+
+void generate_cpu_entries(void)
+{
+	int len_pr, len_ps;
+	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
+	msr_t msr;
+	int totalcores = dev_count_cpu();
+	int cores_per_package = get_cores_per_package();
+	int numcpus = totalcores/cores_per_package;
+	int fsb = 100; /* BCLK fixed at 100MHz for SandyBridge */
+	struct cpu_intel_model_206ax_config *conf = NULL;
+	u8 coord_type = HW_ALL;
+	device_t cpu;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	cpu = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!cpu)
+		return;
+	conf = cpu->chip_info;
+	coord_type = conf->pstate_coord_type;
+
+	if (conf->disable_acpi) {
+		printk(BIOS_DEBUG, "ACPI: P-state and C-state tables "
+		       "disabled by devicetree\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n",
+	       numcpus, cores_per_package);
+
+	for (cpuID=1; cpuID <=numcpus; cpuID++) {
+		for (coreID=1; coreID<=cores_per_package; coreID++) {
+			if (coreID>1) {
+				pcontrol_blk = 0;
+				plen = 0;
+			}
+			len_pr = acpigen_write_processor(
+				(cpuID-1)*cores_per_package+coreID-1,
+				pcontrol_blk, plen);
+			len_pr += acpigen_write_empty_PCT();
+			len_pr += acpigen_write_PSD_package(
+				cpuID-1,cores_per_package,coord_type);
+			len_pr += acpigen_write_name("_PSS");
+
+			int max_states=8;
+			int bus_step=2;
+			msr = rdmsr(0xce);
+			int bus_min=(msr.hi >> (40-32)) & 0xff;
+			int bus_max=(msr.lo >> 8) & 0xff;
+			int clock_max=fsb*bus_max;
+			int clock_min=fsb*bus_min;
+			printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n",
+			       clock_min, clock_max);
+			int power_max=MAX_POWER;
+			int power_min=MIN_POWER;
+			int num_states=(bus_max-bus_min)/bus_step;
+			while (num_states > max_states-1) {
+				bus_step <<= 1;
+				num_states >>= 1;
+			}
+			printk(BIOS_DEBUG, "adding %x P-States between "
+			       "busratio %x and %x, incl. P0\n",
+			       num_states+1, bus_min, bus_max);
+			int power_step=(power_max-power_min)/num_states;
+			int clock_step=(clock_max-clock_min)/num_states;
+
+			/* P[0] is Turbo if enabled */
+			if (get_turbo_state() == TURBO_ENABLED) {
+				len_ps = acpigen_write_package(num_states+2);
+				msr = rdmsr(0x1ad);
+				int bus_turbo = msr.lo & 0xff;
+				len_ps += acpigen_write_PSS_package(
+					clock_max+1 /*mhz*/,
+					power_max+1 /*mW*/,
+					10 /*lat1*/,
+					10 /*lat2*/,
+					bus_turbo<<8 /*control*/,
+					bus_turbo<<8 /*status*/);
+			} else {
+				len_ps = acpigen_write_package(num_states+1);
+			}
+
+			len_ps += acpigen_write_PSS_package(
+				clock_max /*mhz*/,
+				power_max /*mW*/,
+				10 /*lat1*/,
+				10 /*lat2*/,
+				bus_max<<8 /*control*/,
+				bus_max<<8 /*status*/);
+			int current_bus=bus_min+((num_states-1)*bus_step);
+			int current_power=power_min+((num_states-1)*power_step);
+			int current_clock=clock_min+((num_states-1)*clock_step);
+			int i;
+			for (i=0;i<num_states; i++) {
+				len_ps += acpigen_write_PSS_package(
+					current_clock /*mhz*/,
+					current_power /*mW*/,
+					10 /*lat1*/,
+					10 /*lat2*/,
+					current_bus<<8 /*control*/,
+					current_bus<<8 /*status*/);
+				current_bus -= bus_step;
+				current_power -= power_step;
+				current_clock -= clock_step;
+			}
+			len_ps--;
+			acpigen_patch_len(len_ps);
+			len_pr += acpigen_write_PPC(0);
+			/* Generate C-state tables */
+			len_pr += generate_CST_table(conf);
+		len_pr += len_ps;
+		len_pr--;
+		acpigen_patch_len(len_pr);
+		}
+	}
+}
+
+struct chip_operations cpu_intel_model_206ax_ops = {
+	CHIP_NAME("Intel SandyBridge CPU")
+};
diff --git a/src/cpu/intel/model_306ax/bootblock.c b/src/cpu/intel/model_306ax/bootblock.c
new file mode 100644
index 0000000..6b12b89
--- /dev/null
+++ b/src/cpu/intel/model_306ax/bootblock.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <cpu/x86/msr.h>
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_0000001A.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+struct microcode {
+	u32 hdrver;	/* Header Version */
+	u32 rev;	/* Patch ID       */
+	u32 date;	/* DATE           */
+	u32 sig;	/* CPUID          */
+
+	u32 cksum;	/* Checksum       */
+	u32 ldrver;	/* Loader Version */
+	u32 pf;		/* Platform ID    */
+
+	u32 data_size;	/* Data size      */
+	u32 total_size;	/* Total size     */
+
+	u32 reserved[3];
+	u32 bits[1012];
+};
+
+static inline u32 read_microcode_rev(void)
+{
+	/* Some Intel Cpus can be very finicky about the
+	 * CPUID sequence used.  So this is implemented in
+	 * assembly so that it works reliably.
+	 */
+	msr_t msr;
+	__asm__ volatile (
+		"wrmsr\n\t"
+		"xorl %%eax, %%eax\n\t"
+		"xorl %%edx, %%edx\n\t"
+		"movl $0x8b, %%ecx\n\t"
+		"wrmsr\n\t"
+		"movl $0x01, %%eax\n\t"
+		"cpuid\n\t"
+		"movl $0x08b, %%ecx\n\t"
+		"rdmsr \n\t"
+		: /* outputs */
+		"=a" (msr.lo), "=d" (msr.hi)
+		: /* inputs */
+		: /* trashed */
+		 "ecx"
+	);
+	return msr.hi;
+}
+
+void intel_update_microcode(const void *microcode_updates)
+{
+	unsigned int eax;
+	unsigned int pf, rev, sig;
+	unsigned int x86_model, x86_family;
+	const struct microcode *m;
+	const char *c;
+	msr_t msr;
+
+	/* cpuid sets msr 0x8B iff a microcode update has been loaded. */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(0x8B, msr);
+	eax = cpuid_eax(1);
+	msr = rdmsr(0x8B);
+	rev = msr.hi;
+	x86_model = (eax >>4) & 0x0f;
+	x86_family = (eax >>8) & 0x0f;
+	sig = eax;
+
+	pf = 0;
+	if ((x86_model >= 5)||(x86_family>6)) {
+		msr = rdmsr(0x17);
+		pf = 1 << ((msr.hi >> 18) & 7);
+	}
+
+	m = microcode_updates;
+	for(c = microcode_updates; m->hdrver;  m = (const struct microcode *)c) {
+		if ((m->sig == sig) && (m->pf & pf)) {
+			unsigned int new_rev;
+			msr.lo = (unsigned long)(&m->bits) & 0xffffffff;
+			msr.hi = 0;
+			wrmsr(0x79, msr);
+
+			/* Read back the new microcode version */
+			new_rev = read_microcode_rev();
+			break;
+		}
+		if (m->total_size) {
+			c += m->total_size;
+		} else {
+			c += 2048;
+		}
+	}
+}
+
+static void bootblock_cpu_init(void)
+{
+	intel_update_microcode(microcode_updates);
+}
diff --git a/src/cpu/intel/model_306ax/cache_as_ram.inc b/src/cpu/intel/model_306ax/cache_as_ram.inc
new file mode 100644
index 0000000..9d9a5ab
--- /dev/null
+++ b/src/cpu/intel/model_306ax/cache_as_ram.inc
@@ -0,0 +1,323 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich@gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <cpu/x86/stack.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/post_code.h>
+#include <cbmem.h>
+
+#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
+#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
+
+/* Cache 4GB - MRC_SIZE_KB for MRC */
+#define CACHE_MRC_BYTES   ((CONFIG_CACHE_MRC_SIZE_KB << 10) - 1)
+#define CACHE_MRC_BASE    (0xFFFFFFFF - CACHE_MRC_BYTES)
+#define CACHE_MRC_MASK    (~CACHE_MRC_BYTES)
+
+	/* Save the BIST result. */
+	movl	%eax, %ebp
+
+cache_as_ram:
+	post_code(0x20)
+
+	/* Send INIT IPI to all excluding ourself. */
+	movl	$0x000C4500, %eax
+	movl	$0xFEE00300, %esi
+	movl	%eax, (%esi)
+
+	/* All CPUs need to be in Wait for SIPI state */
+wait_for_sipi:
+	movl	(%esi), %eax
+	bt	$12, %eax
+	jc	wait_for_sipi
+
+	post_code(0x21)
+	/* Zero out all fixed range and variable range MTRRs. */
+	movl	$mtrr_table, %esi
+	movl	$((mtrr_table_end - mtrr_table) / 2), %edi
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+clear_mtrrs:
+	movw	(%esi), %bx
+	movzx	%bx, %ecx
+	wrmsr
+	add	$2, %esi
+	dec	%edi
+	jnz	clear_mtrrs
+
+	post_code(0x22)
+	/* Configure the default memory type to uncacheable. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~0x00000cff), %eax
+	wrmsr
+
+	post_code(0x23)
+	/* Set Cache-as-RAM base address. */
+	movl	$(MTRRphysBase_MSR(0)), %ecx
+	movl	$(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	post_code(0x24)
+	/* Set Cache-as-RAM mask. */
+	movl	$(MTRRphysMask_MSR(0)), %ecx
+	movl	$(~(CACHE_AS_RAM_SIZE - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x25)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
+        movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	invd
+	movl	%eax, %cr0
+
+	/* Clear the cache memory reagion. */
+	movl	$CACHE_AS_RAM_BASE, %esi
+	movl	%esi, %edi
+	movl	$(CACHE_AS_RAM_SIZE / 4), %ecx
+	// movl	$0x23322332, %eax
+	xorl	%eax, %eax
+	rep	stosl
+
+	post_code(0x26)
+	/* Enable Cache-as-RAM mode by disabling cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	/* Enable cache for our code in Flash because we do XIP here */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	xorl	%edx, %edx
+#if CONFIG_TINY_BOOTBLOCK
+#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
+#else
+#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
+#endif
+	/*
+	 * IMPORTANT: The two lines below can _not_ be written like this:
+	 *   movl $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 */
+	movl	$REAL_XIP_ROM_BASE, %eax
+	orl	$MTRR_TYPE_WRPROT, %eax
+	wrmsr
+
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$0x0000000f, %edx
+	movl	$(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
+	wrmsr
+
+	post_code(0x27)
+#if CONFIG_CACHE_MRC_BIN
+	/* Enable caching for ram init code to run faster */
+	movl	$MTRRphysBase_MSR(2), %ecx
+	movl	$(CACHE_MRC_BASE | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	movl	$(CACHE_MRC_MASK | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+#endif
+
+	post_code(0x28)
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$(~((1 << 30) | (1 << 29))), %eax
+	movl	%eax, %cr0
+
+	/* Set up the stack pointer below MRC variable space. */
+	movl	$(CACHE_AS_RAM_SIZE + CACHE_AS_RAM_BASE - \
+		  CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 4), %eax
+	movl	%eax, %esp
+
+	/* Restore the BIST result. */
+	movl	%ebp, %eax
+	movl	%esp, %ebp
+	pushl	%eax
+
+before_romstage:
+	post_code(0x29)
+	/* Call romstage.c main function. */
+	call	main
+
+	post_code(0x2f)
+
+	/* Copy global variable space (for USBDEBUG) to memory */
+#if CONFIG_USBDEBUG
+	cld
+	movl	$(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
+	movl	$(CONFIG_RAMTOP - 24), %edi
+	movl	$24, %ecx
+	rep	movsb
+#endif
+
+	post_code(0x30)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x31)
+
+	/* Disable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	andl	$(~MTRRdefTypeEn), %eax
+	wrmsr
+
+	post_code(0x31)
+
+	invd
+#if CONFIG_CACHE_MRC_BIN
+	/* Clear MTRR that was used to cache MRC */
+	xorl	%eax, %eax
+	xorl	%edx, %edx
+	movl	$MTRRphysBase_MSR(2), %ecx
+	wrmsr
+	movl	$MTRRphysMask_MSR(2), %ecx
+	wrmsr
+#endif
+
+	post_code(0x33)
+
+	/* Enable cache. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x36)
+
+	/* Disable cache. */
+	movl	%cr0, %eax
+	orl	$(1 << 30), %eax
+	movl	%eax, %cr0
+
+	post_code(0x38)
+
+	/* Enable Write Back and Speculative Reads for the first MB
+	 * and coreboot_ram.
+	 */
+	movl	$MTRRphysBase_MSR(0), %ecx
+	movl	$(0x00000000 | MTRR_TYPE_WRBACK), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(0), %ecx
+	movl	$(~(CONFIG_RAMTOP - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx	// 36bit address space
+	wrmsr
+
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	movl	$MTRRphysBase_MSR(1), %ecx
+	movl	$(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+	xorl	%edx, %edx
+	wrmsr
+	movl	$MTRRphysMask_MSR(1), %ecx
+	movl	$(~(4*1024*1024 - 1) | MTRRphysMaskValid), %eax
+	movl	$0x0000000f, %edx
+	wrmsr
+
+	post_code(0x39)
+
+	/* And enable cache again after setting MTRRs. */
+	movl	%cr0, %eax
+	andl	$~((1 << 30) | (1 << 29)), %eax
+	movl	%eax, %cr0
+
+	post_code(0x3a)
+
+	/* Enable MTRR. */
+	movl	$MTRRdefType_MSR, %ecx
+	rdmsr
+	orl	$MTRRdefTypeEn, %eax
+	wrmsr
+
+	post_code(0x3b)
+
+	/* Invalidate the cache again. */
+	invd
+
+	post_code(0x3c)
+
+#if CONFIG_HAVE_ACPI_RESUME
+	movl	CBMEM_BOOT_MODE, %eax
+	cmpl	$0x2, %eax // Resume?
+	jne	__acpi_resume_backup_done
+
+	/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+	 * through stage 2. We could keep stuff like stack and heap in high
+	 * tables memory completely, but that's a wonderful clean up task for
+	 * another day.
+	 */
+	cld
+	movl	$CONFIG_RAMBASE, %esi
+	movl	CBMEM_RESUME_BACKUP, %edi
+	movl	$HIGH_MEMORY_SAVE / 4, %ecx
+	rep	movsl
+
+__acpi_resume_backup_done:
+#endif
+
+	post_code(0x3d)
+
+	/* Clear boot_complete flag. */
+	xorl	%ebp, %ebp
+__main:
+	post_code(POST_PREPARE_RAMSTAGE)
+	cld			/* Clear direction flag. */
+
+	movl	%ebp, %esi
+
+	movl	$ROMSTAGE_STACK, %esp
+	movl	%esp, %ebp
+	pushl	%esi
+	call	copy_and_run
+
+.Lhlt:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.Lhlt
+
+mtrr_table:
+	/* Fixed MTRRs */
+	.word 0x250, 0x258, 0x259
+	.word 0x268, 0x269, 0x26A
+	.word 0x26B, 0x26C, 0x26D
+	.word 0x26E, 0x26F
+	/* Variable MTRRs */
+	.word 0x200, 0x201, 0x202, 0x203
+	.word 0x204, 0x205, 0x206, 0x207
+	.word 0x208, 0x209, 0x20A, 0x20B
+	.word 0x20C, 0x20D, 0x20E, 0x20F
+	.word 0x210, 0x211, 0x212, 0x213
+mtrr_table_end:
+
diff --git a/src/cpu/intel/model_306ax/chip.h b/src/cpu/intel/model_306ax/chip.h
new file mode 100644
index 0000000..48e0c89
--- /dev/null
+++ b/src/cpu/intel/model_306ax/chip.h
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_model_206ax_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_model_206ax_config {
+	u8 disable_acpi;	/* Do not generate CPU ACPI tables */
+
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* ACPI C1 on Battery Power */
+	int c2_battery;		/* ACPI C2 on Battery Power */
+	int c3_battery;		/* ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* ACPI C1 on AC Power */
+	int c2_acpower;		/* ACPI C2 on AC Power */
+	int c3_acpower;		/* ACPI C3 on AC Power */
+};
diff --git a/src/cpu/intel/model_306ax/model_306ax_init.c b/src/cpu/intel/model_306ax/model_306ax_init.c
new file mode 100644
index 0000000..b9c484f
--- /dev/null
+++ b/src/cpu/intel/model_306ax/model_306ax_init.c
@@ -0,0 +1,474 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/speedstep.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/name.h>
+#include <usbdebug.h>
+
+/*
+ * List of suported C-states in this processor
+ *
+ * Latencies are typical worst-case package exit time in uS
+ * taken from the SandyBridge BIOS specification.
+ */
+static acpi_cstate_t cstate_map[] = {
+	{	/* 0: C0 */
+	},{	/* 1: C1 */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x00,	/* MWAIT State 0 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 2: C1E */
+		.latency = 1,
+		.power = 1000,
+		.resource = {
+			.addrl = 0x01,	/* MWAIT State 0 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD,
+		}
+	},
+	{	/* 3: C3 */
+		.latency = 63,
+		.power = 500,
+		.resource = {
+			.addrl = 0x10,	/* MWAIT State 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{	/* 4: C6 */
+		.latency = 87,
+		.power = 350,
+		.resource = {
+			.addrl = 0x20,	/* MWAIT State 2 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{	/* 5: C7 */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x30,	/* MWAIT State 3 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{	/* 6: C7S */
+		.latency = 90,
+		.power = 200,
+		.resource = {
+			.addrl = 0x31,	/* MWAIT State 3 Sub-state 1 */
+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+			.resv = ACPI_FFIXEDHW_FLAG_HW_COORD |
+				ACPI_FFIXEDHW_FLAG_BM_STS,
+		}
+	},
+	{ 0 }
+};
+
+static const uint32_t microcode_updates[] = {
+	#include "microcode-M12206A7_0000001A.h"
+
+	/*  Dummy terminator  */
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+        0x0, 0x0, 0x0, 0x0,
+};
+
+#define IA32_FEATURE_CONTROL 0x003a
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+static void enable_vmx(void)
+{
+	struct cpuid_result regs;
+	msr_t msr;
+
+	msr = rdmsr(IA32_FEATURE_CONTROL);
+
+	if (msr.lo & (1 << 0)) {
+		/* VMX locked. If we set it again we get an illegal
+		 * instruction
+		 */
+		return;
+	}
+
+	regs = cpuid(1);
+	if (regs.ecx & CPUID_VMX) {
+		msr.lo |= (1 << 2);
+		if (regs.ecx & CPUID_SMX)
+			msr.lo |= (1 << 1);
+	}
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+
+	msr.lo |= (1 << 0); /* Set lock bit */
+
+	wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+#define PMG_CST_CONFIG_CONTROL	0xe2
+#define PMG_IO_CAPTURE_BASE	0xe4
+#define MISC_PWR_MGMT		0x1aa
+#define POWER_CTL		0x1fc
+#define PP0_CURRENT_CONFIG	0x601
+#define PP1_CURRENT_CONFIG	0x602
+#define PKGC3_IRTL		0x60a
+#define PKGC6_IRTL		0x60b
+#define PKGC7_IRTL		0x60c
+#define  IRTL_VALID		(1 << 15)
+#define  IRTL_1_NS		(0 << 10)
+#define  IRTL_32_NS		(1 << 10)
+#define  IRTL_1024_NS		(2 << 10)
+#define  IRTL_32768_NS		(3 << 10)
+#define  IRTL_1048576_NS	(4 << 10)
+#define  IRTL_33554432_NS	(5 << 10)
+#define  IRTL_RESPONSE_MASK	(0x3ff)
+
+static void configure_c_states(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+	msr.lo |= (1 << 28);	// C1 Auto Undemotion Enable
+	msr.lo |= (1 << 27);	// C3 Auto Undemotion Enable
+	msr.lo |= (1 << 26);	// C1 Auto Demotion Enable
+	msr.lo |= (1 << 25);	// C3 Auto Demotion Enable
+	msr.lo |= (1 << 15);	// config lock until next reset
+	msr.lo |= (1 << 10);	// Enable IO MWAIT redirection
+	msr.lo |= 7;		// No package C-state limit
+	wrmsr(PMG_CST_CONFIG_CONTROL, msr);
+
+	msr = rdmsr(PMG_IO_CAPTURE_BASE);
+	msr.lo &= ~0x7ffff;
+	msr.lo |= (PMB0_BASE + 4);	// LVL_2 base address
+	msr.lo |= (2 << 16);		// CST Range: C7 is max C-state
+	wrmsr(PMG_IO_CAPTURE_BASE, msr);
+
+	msr = rdmsr(MISC_PWR_MGMT);
+	msr.lo &= ~(1 << 0);	// Enable P-state HW_ALL coordination
+	msr.lo |= (1 << 22);	// Lock TM interrupt
+	wrmsr(MISC_PWR_MGMT, msr);
+
+	msr = rdmsr(POWER_CTL);
+	msr.lo |= (1 << 18);	// Enable Energy Perf Bias MSR 0x1b0
+	msr.lo |= (1 << 1);	// C1E Enable
+	msr.lo |= (1 << 0);	// Bi-directional PROCHOT#
+	wrmsr(POWER_CTL, msr);
+
+	/* C3 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
+	wrmsr(PKGC3_IRTL, msr);
+
+	/* C6 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
+	wrmsr(PKGC6_IRTL, msr);
+
+	/* C7 Interrupt Response Time Limit */
+	msr.hi = 0;
+	msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
+	wrmsr(PKGC7_IRTL, msr);
+
+	/* Primary Plane Current Limit */
+	msr = rdmsr(PP0_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= 1000;
+	wrmsr(PP0_CURRENT_CONFIG, msr);
+
+	/* Secondary Plane Current Limit */
+	msr = rdmsr(PP1_CURRENT_CONFIG);
+	msr.lo &= ~0x1fff;
+	msr.lo |= 300;
+	wrmsr(PP1_CURRENT_CONFIG, msr);
+}
+
+#define IA32_MISC_ENABLE	0x1a0
+#define IA32_THERM_INTERRUPT		0x19b
+#define IA32_PACKAGE_THERM_INTERRUPT	0x1b2
+static void configure_misc(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(IA32_MISC_ENABLE);
+	msr.lo |= (1 << 0);	  /* Fast String enable */
+	msr.lo |= (1 << 3); 	  /* TM1/TM2/EMTTM enable */
+	msr.lo |= (1 << 16);	  /* Enhanced SpeedStep Enable */
+	wrmsr(IA32_MISC_ENABLE, msr);
+
+	/* Disable Thermal interrupts */
+	msr.lo = 0;
+	msr.hi = 0;
+	wrmsr(IA32_THERM_INTERRUPT, msr);
+
+	/* Enable package critical interrupt only */
+	msr.lo = 1 << 4;
+	msr.hi = 0;
+	wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr);
+}
+
+#define MSR_PIC_MSG_CONTROL	0x2e
+static void enable_lapic_tpr(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MSR_PIC_MSG_CONTROL);
+	msr.lo &= ~(1 << 10);	/* Enable APIC TPR updates */
+	wrmsr(MSR_PIC_MSG_CONTROL, msr);
+}
+
+#define IA32_PLATFORM_DCA_CAP	0x1f8
+static void configure_dca_cap(void)
+{
+	struct cpuid_result cpuid_regs;
+	msr_t msr;
+
+	/* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
+	cpuid_regs = cpuid(1);
+	if (cpuid_regs.ecx & (1 << 18)) {
+		msr = rdmsr(IA32_PLATFORM_DCA_CAP);
+		msr.lo |= 1;
+		wrmsr(IA32_PLATFORM_DCA_CAP, msr);
+	}
+}
+
+#define MSR_PLATFORM_INFO	0xce
+#define IA32_PERF_CTL 		0x199
+
+static void set_max_ratio(void)
+{
+	msr_t msr;
+
+	/* Platform Info bits 15:8 give max ratio */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	msr.hi = 0;
+	msr.lo &= 0xff00;
+	wrmsr(IA32_PERF_CTL, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: frequency set to %d\n",
+	       ((msr.lo >> 8) & 0xff) * 100);
+}
+
+#define IA32_ENERGY_PERFORMANCE_BIAS	0x1b0
+#define ENERGY_POLICY_PERFORMANCE	0
+#define ENERGY_POLICY_NORMAL		6
+#define ENERGY_POLICY_POWERSAVE		15
+
+static void set_energy_perf_bias(u8 policy)
+{
+	msr_t msr;
+
+	/* Energy Policy is bits 3:0 */
+	msr = rdmsr(IA32_ENERGY_PERFORMANCE_BIAS);
+	msr.lo &= ~0xf;
+	msr.lo |= policy & 0xf;
+	wrmsr(IA32_ENERGY_PERFORMANCE_BIAS, msr);
+
+	printk(BIOS_DEBUG, "model_206ax: energy policy set to %u\n",
+	       policy);
+}
+
+#define IA32_MC0_STATUS 0x401
+static void configure_mca(void)
+{
+	msr_t msr;
+	int i;
+
+	msr.lo = msr.hi = 0;
+	/* This should only be done on a cold boot */
+	for (i = 0; i < 7; i++)
+		wrmsr(IA32_MC0_STATUS + (i * 4), msr);
+}
+
+#if CONFIG_USBDEBUG
+static unsigned ehci_debug_addr;
+#endif
+
+/*
+ * Initialize any extra cores/threads in this package.
+ */
+static void intel_cores_init(device_t cpu)
+{
+	struct cpuid_result result;
+	unsigned cores, threads, i;
+
+	result = cpuid_ext(0xb, 0); /* Threads per core */
+	threads = result.ebx & 0xff;
+
+	result = cpuid_ext(0xb, 1); /* Cores per package */
+	cores = result.ebx & 0xff;
+
+	/* Only initialize extra cores from BSP */
+	if (cpu->path.apic.apic_id)
+		return;
+
+	printk(BIOS_DEBUG, "CPU: %u has %u cores %u threads\n",
+	       cpu->path.apic.apic_id, cores, threads);
+
+	for (i = 1; i < cores; ++i) {
+		struct device_path cpu_path;
+		device_t new;
+
+		/* Build the cpu device path */
+		cpu_path.type = DEVICE_PATH_APIC;
+		cpu_path.apic.apic_id =
+			cpu->path.apic.apic_id + i;
+
+		/* Update APIC ID if no hyperthreading */
+		if (threads == 1)
+			cpu_path.apic.apic_id <<= 1;
+
+		/* Allocate the new cpu device structure */
+		new = alloc_dev(cpu->bus, &cpu_path);
+		if (!new)
+			continue;
+
+		printk(BIOS_DEBUG, "CPU: %u has core %u\n",
+		       cpu->path.apic.apic_id,
+		       new->path.apic.apic_id);
+
+		/* Start the new cpu */
+		if (!start_cpu(new)) {
+			/* Record the error in cpu? */
+			printk(BIOS_ERR, "CPU %u would not start!\n",
+			       new->path.apic.apic_id);
+		}
+	}
+}
+
+static void model_206ax_init(device_t cpu)
+{
+	char processor_name[49];
+	struct cpuid_result cpuid_regs;
+
+	/* Turn on caching if we haven't already */
+	x86_enable_cache();
+
+	/* Update the microcode */
+	intel_update_microcode(microcode_updates);
+
+	/* Clear out pending MCEs */
+	configure_mca();
+
+	/* Print processor name */
+	fill_processor_name(processor_name);
+	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG
+	// Is this caution really needed?
+	if(!ehci_debug_addr)
+		ehci_debug_addr = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+
+	/* Setup MTRRs based on physical address size */
+	cpuid_regs = cpuid(0x80000008);
+	x86_setup_mtrrs(cpuid_regs.eax & 0xff);
+	x86_mtrr_check();
+
+	/* Setup Page Attribute Tables (PAT) */
+	// TODO set up PAT
+
+#if CONFIG_USBDEBUG
+	set_ehci_debug(ehci_debug_addr);
+#endif
+
+	/* Enable the local cpu apics */
+	enable_lapic_tpr();
+	setup_lapic();
+
+	/* Enable virtualization */
+	enable_vmx();
+
+	/* Configure C States */
+	configure_c_states();
+
+	/* Configure Enhanced SpeedStep and Thermal Sensors */
+	configure_misc();
+
+	/* Enable Direct Cache Access */
+	configure_dca_cap();
+
+	/* Set energy policy */
+	set_energy_perf_bias(ENERGY_POLICY_NORMAL);
+
+	/* Set Max Ratio */
+	set_max_ratio();
+
+	/* Enable Turbo */
+	enable_turbo();
+
+	/* Start up extra cores */
+	intel_cores_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+	.init     = model_206ax_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, 0x206a0 }, /* Intel Sandybridge */
+	{ X86_VENDOR_INTEL, 0x206a6 }, /* Intel Sandybridge D1 */
+	{ X86_VENDOR_INTEL, 0x206a7 }, /* Intel Sandybridge D2/J1 */
+	{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+	.ops      = &cpu_dev_ops,
+	.id_table = cpu_table,
+	.cstates  = cstate_map,
+};
+
diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig
index f73c8a9..fb6bdc6 100644
--- a/src/cpu/intel/socket_441/Kconfig
+++ b/src/cpu/intel/socket_441/Kconfig
@@ -8,6 +8,7 @@
 	select CPU_INTEL_MODEL_106CX
 	select MMX
 	select SSE
+	select SSE2
 	select CACHE_AS_RAM
 
 config DCACHE_RAM_BASE
diff --git a/src/cpu/intel/socket_rPGA989/Kconfig b/src/cpu/intel/socket_rPGA989/Kconfig
new file mode 100644
index 0000000..b0bdeb46
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/Kconfig
@@ -0,0 +1,37 @@
+config CPU_INTEL_SOCKET_RPGA989
+	bool
+
+if CPU_INTEL_SOCKET_RPGA989
+
+config SOCKET_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select CPU_INTEL_MODEL_206AX
+	select MMX
+	select SSE
+	select CACHE_AS_RAM
+
+config CACHE_MRC_BIN
+	bool
+	default n
+
+config CACHE_MRC_SIZE_KB
+	int "MRC Cache Size in KB"
+	default 256
+
+config DCACHE_MRC_BASE
+	hex
+	default 0xfffd0000
+
+config DCACHE_RAM_BASE
+	hex
+	default 0xff7f0000
+
+config DCACHE_RAM_SIZE
+	hex
+	default 0x10000
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	hex
+	default 0x4000
+
+endif
diff --git a/src/cpu/intel/socket_rPGA989/Makefile.inc b/src/cpu/intel/socket_rPGA989/Makefile.inc
new file mode 100644
index 0000000..cef0606
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/Makefile.inc
@@ -0,0 +1,9 @@
+ramstage-y += socket_rPGA989.c
+subdirs-y += ../model_206ax
+subdirs-y += ../../x86/tsc
+subdirs-y += ../../x86/mtrr
+subdirs-y += ../../x86/lapic
+subdirs-y += ../../x86/cache
+subdirs-y += ../../x86/smm
+subdirs-y += ../microcode
+subdirs-y += ../turbo
diff --git a/src/cpu/intel/socket_rPGA989/chip.h b/src/cpu/intel/socket_rPGA989/chip.h
new file mode 100644
index 0000000..f843e74
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/chip.h
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_intel_socket_rPGA989_ops;
+
+struct cpu_intel_socket_rPGA989_config {
+};
diff --git a/src/cpu/intel/socket_rPGA989/socket_rPGA989.c b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c
new file mode 100644
index 0000000..2484571
--- /dev/null
+++ b/src/cpu/intel/socket_rPGA989/socket_rPGA989.c
@@ -0,0 +1,6 @@
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_intel_socket_rPGA989_ops = {
+	CHIP_NAME("Socket rPGA989 CPU")
+};
diff --git a/src/cpu/intel/speedstep/Makefile.inc b/src/cpu/intel/speedstep/Makefile.inc
index c717a33..753dbcd 100644
--- a/src/cpu/intel/speedstep/Makefile.inc
+++ b/src/cpu/intel/speedstep/Makefile.inc
@@ -1 +1 @@
-ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c speedstep.c
diff --git a/src/cpu/intel/speedstep/acpi.c b/src/cpu/intel/speedstep/acpi.c
index 48e1a3c..64d9bc6 100644
--- a/src/cpu/intel/speedstep/acpi.c
+++ b/src/cpu/intel/speedstep/acpi.c
@@ -28,6 +28,8 @@
 #include <cpu/intel/acpi.h>
 #include <cpu/intel/speedstep.h>
 #include <device/device.h>
+#include <device/pci.h>
+#include "chip.h"
 
 // XXX: PSS table values for power consumption are for Merom only
 
@@ -48,18 +50,122 @@
 	return count;
 }
 
+static int get_cores_per_package(void)
+{
+	struct cpuinfo_x86 c;
+	struct cpuid_result result;
+	int cores = 1;
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return 1;
+
+	switch (c.x86_model) {
+	case 0x2a: /* SandyBridge */
+		result = cpuid_ext(0xb, 1);
+		cores = result.ebx & 0xff;
+		break;
+	default:
+		cores = (cpuid_ebx(1) >> 16) & 0xff;
+		break;
+	}
+
+	return cores;
+}
+
 static int get_fsb(void)
 {
-	u32 fsbcode=(rdmsr(0xcd).lo >> 4) & 7;
-	switch (fsbcode) {
-		case 0: return 266;
-		case 1: return 133;
-		case 2: return 200;
-		case 3: return 166;
-		case 5: return 100;
+	struct cpuinfo_x86 c;
+	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
+	int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 };
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return -1;
+
+	switch (c.x86_model) {
+	case 0xe:  /* Core Solo/Duo */
+	case 0x1c: /* Atom */
+		return core_fsb[rdmsr(0xcd).lo & 7];
+	case 0xf:  /* Core 2*/
+	case 0x17: /* Enhanced Core */
+		return core2_fsb[rdmsr(0xcd).lo & 7];
+	case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+		return 0; // DISABLED
 	}
-	printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
-	return 200;
+
+	printk(BIOS_DEBUG, "Warning: No supported FSB frequency\n");
+	return -1;
+}
+
+static int generate_cstate_entries(acpi_cstate_t *cstates,
+				   int c1, int c2, int c3)
+{
+	int length, cstate_count = 0;
+
+	/* Count number of active C-states */
+	if (c1 > 0)
+		++cstate_count;
+	if (c2 > 0)
+		++cstate_count;
+	if (c3 > 0)
+		++cstate_count;
+	if (!cstate_count)
+		return 0;
+
+	length = acpigen_write_package(cstate_count + 1);
+	length += acpigen_write_byte(cstate_count);
+
+	/* Add an entry if the level is enabled */
+	if (c1 > 0)
+		length += acpigen_write_CST_package(1, &cstates[c1]);
+	if (c2 > 0)
+		length += acpigen_write_CST_package(2, &cstates[c2]);
+	if (c3 > 0)
+		length += acpigen_write_CST_package(3, &cstates[c3]);
+
+	acpigen_patch_len(length - 1);
+	return length;
+}
+
+static int generate_CST_table(struct cpu_intel_speedstep_config *conf)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	int len, lenif;
+
+	if (!conf)
+		return 0;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return 0;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return 0;
+
+	len = acpigen_emit_byte(0x14);		/* MethodOp */
+	len += acpigen_write_len_f();		/* PkgLength */
+	len += acpigen_emit_namestring("_CST");
+	len += acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	len += acpigen_emit_byte(0xa0);		/* IfOp */
+	lenif = acpigen_write_len_f();		/* PkgLength */
+	lenif += acpigen_emit_namestring("PWRS");
+	lenif += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	lenif += generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_patch_len(lenif - 1);
+	len += lenif;
+
+	/* Else on battery power */
+	len += acpigen_emit_byte(0xa4);	/* ReturnOp */
+	len += generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_patch_len(len - 1);
+	return len;
 }
 
 void generate_cpu_entries(void)
@@ -68,8 +174,23 @@
 	int coreID, cpuID, pcontrol_blk = PMB0_BASE, plen = 6;
 	msr_t msr;
 	int totalcores = determine_total_number_of_cores();
-	int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
+	int cores_per_package = get_cores_per_package();
 	int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
+	int fsb = get_fsb();
+	struct cpu_intel_speedstep_config *conf = NULL;
+	u8 coord_type = SW_ANY;
+	device_t cpu;
+
+	if (fsb <= 0)
+		return;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	cpu = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (cpu) {
+		conf = cpu->chip_info;
+		coord_type = conf->pstate_coord_type;
+	}
+
 	printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
 
 	for (cpuID=1; cpuID <=numcpus; cpuID++) {
@@ -80,7 +201,8 @@
 		}
 		len_pr = acpigen_write_processor((cpuID-1)*cores_per_package+coreID-1, pcontrol_blk, plen);
 			len_pr += acpigen_write_empty_PCT();
-			len_pr += acpigen_write_PSD_package(cpuID-1,cores_per_package,SW_ANY);
+			len_pr += acpigen_write_PSD_package(
+				cpuID-1,cores_per_package,coord_type);
 			len_pr += acpigen_write_name("_PSS");
 
 			int max_states=8;
@@ -91,8 +213,8 @@
 			int vid_min=msr.lo & 0x3f;
 			msr = rdmsr(IA32_PLATFORM_ID);
 			int vid_max=msr.lo & 0x3f;
-			int clock_max=get_fsb()*busratio_max;
-			int clock_min=get_fsb()*busratio_min;
+			int clock_max=fsb*busratio_max;
+			int clock_min=fsb*busratio_min;
 			printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
 #define MEROM_MIN_POWER 16000
 #define MEROM_MAX_POWER 35000
@@ -125,6 +247,8 @@
 			len_ps--;
 			acpigen_patch_len(len_ps);
 			len_pr += acpigen_write_PPC(0);
+			/* Generate C-state tables */
+			len_pr += generate_CST_table(conf);
 		len_pr += len_ps;
 		len_pr--;
 		acpigen_patch_len(len_pr);
diff --git a/src/cpu/intel/speedstep/chip.h b/src/cpu/intel/speedstep/chip.h
new file mode 100644
index 0000000..44f336a
--- /dev/null
+++ b/src/cpu/intel/speedstep/chip.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+extern struct chip_operations cpu_intel_speedstep_ops;
+
+/* Magic value used to locate this chip in the device tree */
+#define SPEEDSTEP_APIC_MAGIC 0xACAC
+
+struct cpu_intel_speedstep_config {
+	u8 pstate_coord_type;	/* Processor Coordination Type */
+
+	int c1_battery;		/* CPU C-state for ACPI C1 on Battery Power */
+	int c2_battery;		/* CPU C-state for ACPI C2 on Battery Power */
+	int c3_battery;		/* CPU C-state for ACPI C3 on Battery Power */
+
+	int c1_acpower;		/* CPU C-state for ACPI C1 on AC Power */
+	int c2_acpower;		/* CPU C-state for ACPI C2 on AC Power */
+	int c3_acpower;		/* CPU C-state for ACPI C3 on AC Power */
+};
diff --git a/src/cpu/x86/mmx_disable.inc b/src/cpu/intel/speedstep/speedstep.c
similarity index 77%
copy from src/cpu/x86/mmx_disable.inc
copy to src/cpu/intel/speedstep/speedstep.c
index 1a4e70f..ff285c6 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/cpu/intel/speedstep/speedstep.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The Chromium OS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#include <device/device.h>
+#include "chip.h"
 
+struct chip_operations cpu_intel_speedstep_ops = {
+	CHIP_NAME("Intel SpeedStep CPU")
+};
diff --git a/src/cpu/intel/turbo/Makefile.inc b/src/cpu/intel/turbo/Makefile.inc
new file mode 100644
index 0000000..48ec55d
--- /dev/null
+++ b/src/cpu/intel/turbo/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += turbo.c
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
new file mode 100644
index 0000000..779550e
--- /dev/null
+++ b/src/cpu/intel/turbo/turbo.c
@@ -0,0 +1,90 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/intel/turbo.h>
+#include <cpu/x86/msr.h>
+#include <arch/cpu.h>
+
+static int turbo_state = TURBO_UNKNOWN;
+
+static const char *turbo_state_desc[] = {
+	[TURBO_UNKNOWN]		= "unknown",
+	[TURBO_UNAVAILABLE]	= "unavailable",
+	[TURBO_DISABLED]	= "available but hidden",
+	[TURBO_ENABLED]		= "available and visible"
+};
+
+/*
+ * Determine the current state of Turbo and cache it for later.
+ * Turbo is a package level config so it does not need to be
+ * enabled on every core.
+ */
+int get_turbo_state(void)
+{
+	struct cpuid_result cpuid_regs;
+	int turbo_en, turbo_cap;
+	msr_t msr;
+
+	/* Return cached state if available */
+	if (turbo_state != TURBO_UNKNOWN)
+		return turbo_state;
+
+	cpuid_regs = cpuid(CPUID_LEAF_PM);
+	turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
+
+	msr = rdmsr(MSR_IA32_MISC_ENABLES);
+	turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
+
+	if (!turbo_cap && turbo_en) {
+		/* Unavailable */
+		turbo_state = TURBO_UNAVAILABLE;
+	} else if (!turbo_cap && !turbo_en) {
+		/* Available but disabled */
+		turbo_state = TURBO_DISABLED;
+	} else if (turbo_cap && turbo_en) {
+		/* Available */
+		turbo_state = TURBO_ENABLED;
+	}
+
+	printk(BIOS_INFO, "Turbo is %s\n", turbo_state_desc[turbo_state]);
+	return turbo_state;
+}
+
+/*
+ * Try to enable Turbo mode.
+ */
+void enable_turbo(void)
+{
+	msr_t msr;
+
+	/* Only possible if turbo is available but hidden */
+	if (get_turbo_state() == TURBO_DISABLED) {
+		/* Clear Turbo Disable bit in Misc Enables */
+		msr = rdmsr(MSR_IA32_MISC_ENABLES);
+		msr.hi &= ~H_MISC_DISABLE_TURBO;
+		wrmsr(MSR_IA32_MISC_ENABLES, msr);
+
+		/* Update cached turbo state */
+		turbo_state = TURBO_ENABLED;
+		printk(BIOS_INFO, "Turbo has been enabled\n");
+	}
+}
diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc
index 1eb92c8..9f4c0e3 100644
--- a/src/cpu/x86/16bit/entry16.inc
+++ b/src/cpu/x86/16bit/entry16.inc
@@ -45,7 +45,6 @@
 	xorl	%eax, %eax
 	movl	%eax, %cr3    /* Invalidate TLB*/
 
-
 	/* Invalidating the cache here seems to be a bad idea on
 	 * modern processors.  Don't.
 	 * If we are hyperthreaded or we have multiple cores it is bad,
@@ -55,6 +54,13 @@
 	 * entry16.inc.
 	 */
 
+	/* Load an IDT with NULL limit to prevent the 16bit IDT being used
+	 * in protected mode before c_start.S sets up a 32bit IDT when entering
+	 * ram stage.
+	 */
+	movw $nullidt_offset, %bx
+	lidt %cs:(%bx)
+
 	/* Note: gas handles memory addresses in 16 bit code very poorly.
 	 * In particular it doesn't appear to have a directive allowing you
 	 * associate a section or even an absolute offset with a segment register.
@@ -118,6 +124,13 @@
 	.word	gdt_end - gdt -1 /* compute the table limit */
 	.long	gdt		 /* we know the offset */
 
+.align	4
+.globl nullidt
+nullidt:
+	.word	0	/* limit */
+	.long	0
+	.word	0
+
 .globl _estart
 _estart:
 	.code32
diff --git a/src/cpu/x86/16bit/entry16.lds b/src/cpu/x86/16bit/entry16.lds
index 0580f0e..112d429 100644
--- a/src/cpu/x86/16bit/entry16.lds
+++ b/src/cpu/x86/16bit/entry16.lds
@@ -1 +1,2 @@
 	gdtptr16_offset = gdtptr16 & 0xffff;
+	nullidt_offset = nullidt & 0xffff;
diff --git a/src/cpu/x86/16bit/reset16.inc b/src/cpu/x86/16bit/reset16.inc
index 1be0e3a..8dba3c8 100644
--- a/src/cpu/x86/16bit/reset16.inc
+++ b/src/cpu/x86/16bit/reset16.inc
@@ -2,6 +2,7 @@
 	.code16
 .globl	reset_vector
 reset_vector:
+	wbinvd
 	.byte  0xe9
 	.int   _start - ( . + 2 )
 	/* Note: The above jump is hand coded to work around bugs in binutils.
diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index ec559b5..19efb00 100644
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -39,4 +39,14 @@
 	bool
 	default y
 
+config CACHE_ROM
+	bool
+	default n
 
+config SMM_TSEG
+	bool
+	default n
+
+config SMM_TSEG_SIZE
+	hex
+	default 0
diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956..f3fcadc 100644
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c
diff --git a/src/cpu/x86/lapic/apic_timer.c b/src/cpu/x86/lapic/apic_timer.c
index a4737b3..f51fe21 100644
--- a/src/cpu/x86/lapic/apic_timer.c
+++ b/src/cpu/x86/lapic/apic_timer.c
@@ -20,6 +20,7 @@
 
 #include <stdint.h>
 #include <delay.h>
+#include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/x86/lapic.h>
 
@@ -27,14 +28,40 @@
  * memory init.
  */
 
-#define FSB_CLOCK_STS 0xcd
+static u32 timer_fsb = 0;
 
-static u32 timer_fsb = 200; // default to 200MHz
+static int set_timer_fsb(void)
+{
+	struct cpuinfo_x86 c;
+	int core_fsb[8] = { -1, 133, -1, 166, -1, 100, -1, -1 };
+	int core2_fsb[8] = { 266, 133, 200, 166, -1, 100, -1, -1 };
+
+	get_fms(&c, cpuid_eax(1));
+	if (c.x86 != 6)
+		return -1;
+
+	switch (c.x86_model) {
+	case 0xe:  /* Core Solo/Duo */
+	case 0x1c: /* Atom */
+		timer_fsb = core_fsb[rdmsr(0xcd).lo & 7];
+		break;
+	case 0xf:  /* Core 2*/
+	case 0x17: /* Enhanced Core */
+		timer_fsb = core2_fsb[rdmsr(0xcd).lo & 7];
+		break;
+	case 0x2a: /* SandyBridge BCLK fixed at 100MHz*/
+		timer_fsb = 100;
+		break;
+	default:
+		timer_fsb = 200;
+		break;
+	}
+
+	return 0;
+}
 
 void init_timer(void)
 {
-	msr_t fsb_clock_sts;
-
 	/* Set the apic timer to no interrupts and periodic mode */
 	lapic_write(LAPIC_LVTT, (1 << 17) | (1<< 16) | (0 << 12) | (0 << 0));
 
@@ -45,19 +72,16 @@
 	lapic_write(LAPIC_TMICT, 0xffffffff);
 
 	/* Set FSB frequency to a reasonable value */
-	fsb_clock_sts = rdmsr(FSB_CLOCK_STS);
-	switch ((fsb_clock_sts.lo >> 4) & 0x07) {
-	case 0: timer_fsb = 266; break;
-	case 1: timer_fsb = 133; break;
-	case 2: timer_fsb = 200; break;
-	case 3: timer_fsb = 166; break;
-	case 5: timer_fsb = 100; break;
-	}
+	set_timer_fsb();
 }
 
 void udelay(u32 usecs)
 {
 	u32 start, value, ticks;
+
+	if (!timer_fsb)
+		init_timer();
+
 	/* Calculate the number of ticks to run, our FSB runs at timer_fsb Mhz */
 	ticks = usecs * timer_fsb;
 	start = lapic_read(LAPIC_TMCCT);
diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index bca73e1..50dc0bf 100644
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,6 +1,7 @@
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 
-static int boot_cpu(void)
+int boot_cpu(void)
 {
 	int bsp;
 	msr_t msr;
diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 53bbe79..232fe35 100644
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -14,6 +14,7 @@
 #include <smp/atomic.h>
 #include <smp/spinlock.h>
 #include <cpu/cpu.h>
+#include <cpu/intel/speedstep/chip.h>
 
 #if CONFIG_SMP == 1
 /* This is a lot more paranoid now, since Linux can NOT handle
@@ -108,7 +109,7 @@
 		}
 		return 0;
 	}
-#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
+#if !CONFIG_CPU_AMD_MODEL_10XXX && !CONFIG_CPU_INTEL_MODEL_206AX
 	mdelay(10);
 #endif
 
@@ -136,7 +137,7 @@
 
 	start_eip = get_valid_start_eip((unsigned long)_secondary_start);
 
-#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
+#if !CONFIG_CPU_AMD_MODEL_10XXX
 	num_starts = 2;
 #else
 	num_starts = 1;
@@ -400,6 +401,8 @@
 {
 	device_t cpu;
 	int old_active_count, active_count;
+	long loopcount = 0;
+
 	/* Now loop until the other cpus have finished initializing */
 	old_active_count = 1;
 	active_count = atomic_read(&active_cpus);
@@ -410,17 +413,21 @@
 		}
 		udelay(10);
 		active_count = atomic_read(&active_cpus);
+		loopcount++;
 	}
 	for(cpu = cpu_bus->children; cpu; cpu = cpu->sibling) {
 		if (cpu->path.type != DEVICE_PATH_APIC) {
 			continue;
 		}
+		if (cpu->path.apic.apic_id == SPEEDSTEP_APIC_MAGIC) {
+			continue;
+		}
 		if (!cpu->initialized) {
 			printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
 				cpu->path.apic.apic_id);
 		}
 	}
-	printk(BIOS_DEBUG, "All AP CPUs stopped\n");
+	printk(BIOS_DEBUG, "All AP CPUs stopped (%ld loops)\n", loopcount);
 }
 
 #else /* CONFIG_SMP */
@@ -475,9 +482,9 @@
 	#if CONFIG_SERIAL_CPU_INIT == 1
 	start_other_cpus(cpu_bus, info->cpu);
 	#endif
+#endif
 
 	/* Now wait the rest of the cpus stop*/
 	wait_other_cpus_stop(cpu_bus);
-#endif
 }
 
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e7beea..43c21ec 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,6 +36,8 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
+#include <arch/acpi.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -47,6 +49,23 @@
 	MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 
+/* 2 MTRRS are reserved for the operating system */
+#define BIOS_MTRRS 6
+#define OS_MTRRS   2
+#define MTRRS      (BIOS_MTRRS + OS_MTRRS)
+
+static int total_mtrrs = MTRRS;
+static int bios_mtrrs = BIOS_MTRRS;
+
+static void detect_var_mtrrs(void)
+{
+	msr_t msr;
+
+	msr = rdmsr(MTRRcap_MSR);
+
+	total_mtrrs = msr.lo & 0xff;
+	bios_mtrrs = total_mtrrs - 2;
+}
 
 void enable_fixed_mtrr(void)
 {
@@ -74,8 +93,8 @@
 	msr_t base, mask;
 	unsigned address_mask_high;
 
-        if (reg >= 8)
-                return;
+        if (reg >= total_mtrrs)
+               return;
 
         // it is recommended that we disable and enable cache when we
         // do this.
@@ -167,16 +186,6 @@
  * or a 156MB (128MB + 32MB - 4MB SMA) example:
  *	ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB)
  */
-/* 2 MTRRS are reserved for the operating system */
-#if 1
-#define BIOS_MTRRS 6
-#define OS_MTRRS   2
-#else
-#define BIOS_MTRRS 8
-#define OS_MTRRS   0
-#endif
-#define MTRRS        (BIOS_MTRRS + OS_MTRRS)
-
 
 static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type)
 {
@@ -233,6 +242,8 @@
 	unsigned long next_range_startk, unsigned char type,
 	unsigned int address_bits, unsigned int above4gb)
 {
+	unsigned long hole_startk = 0, hole_sizek = 0;
+
 	if (!range_sizek) {
 		/* If there's no MTRR hole, this function will bail out
 		 * here when called for the hole.
@@ -241,7 +252,7 @@
 		return reg;
 	}
 
-	if (reg >= BIOS_MTRRS) {
+	if (reg >= bios_mtrrs) {
 		printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
 				range_startk >>10, range_sizek >> 10,
 				(type==MTRR_TYPE_UNCACHEABLE)?"UC":
@@ -249,6 +260,19 @@
 		return reg;
 	}
 
+#define MIN_ALIGN 0x10000 /* 64MB */
+
+	if (above4gb == 2 && type == MTRR_TYPE_WRBACK &&
+	    range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) {
+		/*
+		 * If this range is not divisible then instead
+		 * make a larger range and carve out an uncached hole.
+		 */
+		hole_startk = range_startk + range_sizek;
+		hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN);
+		range_sizek += hole_sizek;
+	}
+
 	while(range_sizek) {
 		unsigned long max_align, align;
 		unsigned long sizek;
@@ -272,11 +296,20 @@
 			set_var_mtrr(reg++, range_startk, sizek, type, address_bits);
 		range_startk += sizek;
 		range_sizek -= sizek;
-		if (reg >= BIOS_MTRRS) {
+		if (reg >= bios_mtrrs) {
 			printk(BIOS_ERR, "Running out of variable MTRRs!\n");
 			break;
 		}
 	}
+
+	if (hole_sizek) {
+		printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n",
+		       hole_startk >> 10, (hole_startk + hole_sizek) >> 10);
+		reg = range_to_mtrr(reg, hole_startk, hole_sizek,
+			      next_range_startk, MTRR_TYPE_UNCACHEABLE,
+			      address_bits, above4gb);
+	}
+
 	return reg;
 }
 
@@ -323,7 +356,7 @@
 {
 	struct var_mtrr_state *state = gp;
 	unsigned long basek, sizek;
-	if (state->reg >= BIOS_MTRRS)
+	if (state->reg >= bios_mtrrs)
 		return;
 	basek = resk(res->base);
 	sizek = resk(res->size);
@@ -339,7 +372,7 @@
 	/* Write the range mtrrs */
 	if (state->range_sizek != 0) {
 #if CONFIG_VAR_MTRR_HOLE
-		if (state->hole_sizek == 0) {
+		if (state->hole_sizek == 0 && state->above4gb != 2) {
 			/* We need to put that on to hole */
 			unsigned long endk = basek + sizek;
 			state->hole_startk = state->range_startk + state->range_sizek;
@@ -422,6 +455,10 @@
 	var_state.address_bits = address_bits;
 	var_state.above4gb = above4gb;
 
+	/* Detect number of variable MTRRs */
+	if (above4gb == 2)
+		detect_var_mtrrs();
+
 	search_global_resources(
 		IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
 		set_var_mtrr_resource, &var_state);
@@ -433,7 +470,8 @@
 	} else {
 #if CONFIG_VAR_MTRR_HOLE
 		// Increase the base range and set up UMA as an UC hole instead
-		var_state.range_sizek += (uma_memory_size >> 10);
+		if (above4gb != 2)
+			var_state.range_sizek += (uma_memory_size >> 10);
 
 		var_state.hole_startk = (uma_memory_base >> 10);
 		var_state.hole_sizek = (uma_memory_size >> 10);
@@ -452,9 +490,20 @@
 	printk(BIOS_DEBUG, "DONE variable MTRRs\n");
 	printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
 	/* Clear out the extra MTRR's */
-	while(var_state.reg < MTRRS) {
+	while(var_state.reg < total_mtrrs) {
 		set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
 	}
+
+#if CONFIG_CACHE_ROM
+	/* Enable Caching and speculative Reads for the
+	 * complete ROM now that we actually have RAM.
+	 */
+	if (boot_cpu() && (acpi_slp_type != 3)) {
+		set_var_mtrr(total_mtrrs-1, (4096-8)*1024, 8*1024,
+			MTRR_TYPE_WRPROT, address_bits);
+	}
+#endif
+
 	printk(BIOS_SPEW, "call enable_var_mtrr()\n");
 	enable_var_mtrr();
 	printk(BIOS_SPEW, "Leave %s\n", __func__);
diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc
index 85bb454..108f8f9 100644
--- a/src/cpu/x86/smm/Makefile.inc
+++ b/src/cpu/x86/smm/Makefile.inc
@@ -22,15 +22,25 @@
 ramstage-srcs += $(obj)/cpu/x86/smm/smm_wrap
 endif
 
+# Use TSEG specific entry point and linker script
+ifeq ($(CONFIG_SMM_TSEG),y)
+smm-y += smmhandler_tseg.S
+SMM_LDFLAGS  := $(LDFLAGS) -pie
+SMM_LDSCRIPT := smm_tseg.ld
+else
 smm-y += smmhandler.S
+SMM_LDFLAGS  := $(LDFLAGFS)
+SMM_LDSCRIPT := smm.ld
+endif
+
 smm-y += smihandler.c
 smm-y += smiutil.c
 
 $(obj)/cpu/x86/smm/smm.o: $$(smm-objs)
 	$(CC) $(LDFLAGS) -nostdlib -r -o $@ $^
 
-$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld $(obj)/ldoptions
-	$(CC) $(LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o
+$(obj)/cpu/x86/smm/smm_wrap: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/ldoptions
+	$(CC) $(SMM_LDFLAGS) -nostdlib -nostartfiles -static -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/$(SMM_LDSCRIPT) $(obj)/cpu/x86/smm/smm.o
 	$(NM) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map
 	$(OBJCOPY) -O binary $(obj)/cpu/x86/smm/smm.elf $(obj)/cpu/x86/smm/smm
 
diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c
index bdaedf8..a971d81 100644
--- a/src/cpu/x86/smm/smihandler.c
+++ b/src/cpu/x86/smm/smihandler.c
@@ -25,6 +25,7 @@
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
 
+#if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */
 typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore;
 
 /* SMI multiprocessing semaphore */
@@ -56,6 +57,7 @@
 		: "eax"
 	);
 }
+#endif
 
 #define LAPIC_ID 0xfee00020
 static inline __attribute__((always_inline)) unsigned long nodeid(void)
@@ -116,6 +118,7 @@
 	unsigned int node;
 	smm_state_save_area_t state_save;
 
+#if !CONFIG_SMM_TSEG
 	/* Are we ok to execute the handler? */
 	if (!smi_obtain_lock()) {
 		/* For security reasons we don't release the other CPUs
@@ -124,6 +127,7 @@
 		while (smi_handler_status == SMI_LOCKED) /* wait */ ;
 		return;
 	}
+#endif
 
 	smi_backup_pci_address();
 
@@ -141,6 +145,7 @@
 			(0xa8000 + 0x7e00 - (node * 0x400));
 		break;
 	case 0x00030100:
+	case 0x00030101: /* SandyBridge */
 		state_save.type = EM64T;
 		state_save.em64t_state_save = (em64t_smm_state_save_area_t *)
 			(0xa8000 + 0x7d00 - (node * 0x400));
@@ -169,7 +174,9 @@
 
 	smi_restore_pci_address();
 
+#if !CONFIG_SMM_TSEG
 	smi_release_lock();
+#endif
 
 	/* De-assert SMI# signal to allow another SMI */
 	smi_set_eos();
diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c
index d9057d8..9cd63ed 100644
--- a/src/cpu/x86/smm/smiutil.c
+++ b/src/cpu/x86/smm/smiutil.c
@@ -23,18 +23,8 @@
 #include <arch/romcc_io.h>
 #include <cpu/x86/cache.h>
 #include <cpu/x86/smm.h>
-
 #include <console/console.h>
 #include <console/vtxprintf.h>
-#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
-#include <uart8250.h>
-#endif
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-#if CONFIG_CONSOLE_NE2K
-#include <console/ne2k.h>
-#endif
 
 #if CONFIG_CONSOLE_SERIAL8250MEM
 static u32 serial8250mem_base_address = 0;
diff --git a/src/cpu/x86/smm/smm_tseg.ld b/src/cpu/x86/smm/smm_tseg.ld
new file mode 100644
index 0000000..f3a8dae
--- /dev/null
+++ b/src/cpu/x86/smm/smm_tseg.ld
@@ -0,0 +1,58 @@
+/* Maximum number of CPUs/cores */
+CPUS = 4;
+
+SECTIONS
+{
+	/* This is the actual SMM handler.
+	 *
+	 * We just put code, rodata, data and bss all in a row.
+	 */
+	.handler (.): {
+		/* Assembler stub */
+		*(.handler)
+
+		/* C code of the SMM handler */
+		*(.text);
+		*(.text.*);
+
+		/* C read-only data of the SMM handler */
+		. = ALIGN(16);
+		*(.rodata)
+		*(.rodata.*)
+		*(.data.rel.ro.*)
+
+		/* C read-write data of the SMM handler */
+		 . = ALIGN(4);
+		*(.data)
+
+		/* C uninitialized data of the SMM handler */
+		 . = ALIGN(4);
+		*(.bss)
+		*(.sbss)
+
+		/* What is this? */
+		*(COMMON)
+		 . = ALIGN(4);
+	}
+
+	/* We are using the TSEG interleaved to stuff the SMM handlers
+	 * for all CPU cores in there. The jump table redirects the execution
+	 * to the actual SMM handler
+	 */
+	. = 0x8000 - (( CPUS - 1) * 0x400);
+	.jumptable : {
+		*(.jumptable)
+	}
+
+	/* Data used in early SMM TSEG handler. */
+	. = 0x8400;
+	.earlydata : {
+		*(.earlydata)
+	}
+
+	/DISCARD/ : {
+		*(.comment)
+		*(.note)
+		*(.note.*)
+	}
+}
diff --git a/src/cpu/x86/smm/smmhandler_tseg.S b/src/cpu/x86/smm/smmhandler_tseg.S
new file mode 100644
index 0000000..0b41b37
--- /dev/null
+++ b/src/cpu/x86/smm/smmhandler_tseg.S
@@ -0,0 +1,264 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * +--------------------------------+ 0xffff
+ * |  Save State Map Node 0         |
+ * |  Save State Map Node 1         |
+ * |  Save State Map Node 2         |
+ * |  Save State Map Node 3         |
+ * |  ...                           |
+ * +--------------------------------+ 0xf000
+ * |                                |
+ * |                                |
+ * | EARLY DATA (lock, vectors)     |
+ * +--------------------------------+ 0x8400
+ * | SMM Entry Node 0 (+ stack)     |
+ * +--------------------------------+ 0x8000
+ * | SMM Entry Node 1 (+ stack)     |
+ * | SMM Entry Node 2 (+ stack)     |
+ * | SMM Entry Node 3 (+ stack)     |
+ * | ...                            |
+ * +--------------------------------+ 0x7400
+ * |                                |
+ * | SMM Handler                    |
+ * |                                |
+ * +--------------------------------+ TSEG
+ *
+ */
+
+#define LAPIC_ID	0xfee00020
+#define SMM_STACK_SIZE	(0x400 - 0x10)
+
+/* Values for the xchg lock */
+#define SMI_LOCKED	0
+#define SMI_UNLOCKED	1
+
+#define __PRE_RAM__
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
+#error "Northbridge must define TSEG_BAR."
+#endif
+
+/* initially SMM is some sort of real mode. Let gcc know
+ * how to treat the SMM handler stub
+ */
+
+.section ".handler", "a", @progbits
+
+.code16
+
+/**
+ * SMM code to enable protected mode and jump to the
+ * C-written function void smi_handler(u32 smm_revision)
+ *
+ * All the bad magic is not all that bad after all.
+ */
+smm_handler_start:
+	movl	$(TSEG_BAR), %eax	/* Get TSEG base from PCIE */
+	addr32	movl (%eax), %edx	/* Save TSEG_BAR in %edx */
+	andl	$~1, %edx		/* Remove lock bit */
+
+	/* Obtain lock */
+	movl	%edx, %ebx
+	addl	$(smm_lock), %ebx
+	movw	$SMI_LOCKED, %ax
+	addr32	xchg %ax, (%ebx)
+	cmpw	$SMI_UNLOCKED, %ax
+
+	/* Proceed if we got the lock */
+	je	smm_check_prot_vector
+
+	/* If we did not get the lock, wait for release */
+wait_for_unlock:
+	addr32	movw (%ebx), %ax
+	cmpw	$SMI_LOCKED, %ax
+	je	wait_for_unlock
+	rsm
+
+smm_check_prot_vector:
+	/* See if we need to adjust protected vector */
+	movl	%edx, %eax
+	addl	$(smm_prot_vector), %eax
+	addr32	movl (%eax), %ebx
+	cmpl	$(smm_prot_start), %ebx
+	jne	smm_check_gdt_vector
+
+	/* Adjust vector with TSEG offset */
+	addl	%edx, %ebx
+	addr32	movl %ebx, (%eax)
+
+smm_check_gdt_vector:
+	/* See if we need to adjust GDT vector */
+	movl	%edx, %eax
+	addl	$(smm_gdt_vector + 2), %eax
+	addr32	movl (%eax), %ebx
+	cmpl	$(smm_gdt - smm_handler_start), %ebx
+	jne	smm_load_gdt
+
+	/* Adjust vector with TSEG offset */
+	addl	%edx, %ebx
+	addr32	movl %ebx, (%eax)
+
+smm_load_gdt:
+	movl    $(smm_gdt_vector), %ebx
+	addl	%edx, %ebx        /* TSEG base in %edx */
+	data32  lgdt (%ebx)
+
+	movl    %cr0, %eax
+	andl    $0x1FFAFFD1, %eax /* CD,NW,PG,AM,WP,NE,TS,EM,MP = 0 */
+	orl     $0x1, %eax        /* PE = 1 */
+	movl    %eax, %cr0
+
+	/* Enable protected mode */
+	movl	$(smm_prot_vector), %eax
+	addl	%edx, %eax
+	data32	ljmp *(%eax)
+
+.code32
+smm_prot_start:
+	/* Use flat data segment */
+	movw    $0x10, %ax
+	movw    %ax, %ds
+	movw    %ax, %es
+	movw    %ax, %ss
+	movw    %ax, %fs
+	movw    %ax, %gs
+
+	/* Get this CPU's LAPIC ID */
+	movl	$LAPIC_ID, %esi
+	movl	(%esi), %ecx
+	shr	$24, %ecx
+
+	/* calculate stack offset by multiplying the APIC ID
+	 * by 1024 (0x400), and save that offset in ebp.
+	 */
+	shl	$10, %ecx
+	movl	%ecx, %ebp
+
+	/* We put the stack for each core right above
+	 * its SMM entry point. Core 0 starts at SMM_BASE + 0x8000,
+	 * we spare 0x10 bytes for the jump to be sure.
+	 */
+	movl	$0x8010, %eax	/* core 0 address */
+	addl	%edx, %eax	/* addjust for TSEG */
+	subl	%ecx, %eax	/* subtract offset, see above */
+	movl	%eax, %ebx	/* Save bottom of stack in ebx */
+
+	/* clear stack */
+	cld
+	movl	%eax, %edi
+	movl	$(SMM_STACK_SIZE >> 2), %ecx
+	xorl	%eax, %eax
+	rep	stosl
+
+	/* set new stack */
+	addl	$SMM_STACK_SIZE, %ebx
+	movl	%ebx, %esp
+
+	/* Get SMM revision */
+	movl	$0xfefc, %ebx	/* core 0 address */
+	addl	%edx, %ebx	/* addjust for TSEG */
+	subl	%ebp, %ebx	/* subtract core X offset */
+	movl	(%ebx), %eax
+	pushl	%eax
+
+	/* Call 32bit C handler */
+	call	smi_handler
+
+	/* Release lock */
+	movl	$(TSEG_BAR), %eax	/* Get TSEG base from PCIE */
+	movl	(%eax), %ebx		/* Save TSEG_BAR in %ebx */
+	andl	$~1, %ebx		/* Remove lock bit */
+	addl	$(smm_lock), %ebx
+	movw	$SMI_UNLOCKED, %ax
+	xchg	%ax, (%ebx)
+
+	/* To return, just do rsm. It will "clean up" protected mode */
+	rsm
+
+smm_gdt:
+	/* The first GDT entry can not be used. Keep it zero */
+	.long	0x00000000, 0x00000000
+
+	/* gdt selector 0x08, flat code segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */
+
+	/* gdt selector 0x10, flat data segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x93, 0xcf, 0x00
+
+smm_gdt_end:
+
+.section ".earlydata", "a", @progbits
+
+.code16
+
+.align	4, 0xff
+
+smm_lock:
+	.word	SMI_UNLOCKED
+
+.align	4, 0xff
+
+smm_prot_vector:
+	.long	smm_prot_start
+	.short	8
+
+.align	4, 0xff
+
+smm_gdt_vector:
+	.word	smm_gdt_end - smm_gdt - 1
+	.long	smm_gdt - smm_handler_start
+
+.section ".jumptable", "a", @progbits
+
+/* This is the SMM jump table. All cores use the same SMM handler
+ * for simplicity. But SMM Entry needs to be different due to the
+ * save state area. The jump table makes sure all CPUs jump into the
+ * real handler on SMM entry.
+ */
+
+/* This code currently supports up to 4 CPU cores. If more than 4 CPU cores
+ * shall be used, below table has to be updated, as well as smm.ld
+ */
+
+/* When using TSEG do a relative jump and fix up the CS later since we
+ * do not know what our TSEG base is yet.
+ */
+
+.code16
+jumptable:
+	/* core 3 */
+	jmp smm_handler_start
+.align 1024, 0x00
+	/* core 2 */
+	jmp smm_handler_start
+.align 1024, 0x00
+	/* core 1 */
+	jmp smm_handler_start
+.align 1024, 0x00
+	/* core 0 */
+	jmp smm_handler_start
+.align 1024, 0x00
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 7b38348..89834a5 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -35,10 +35,24 @@
 #include "../../../southbridge/intel/i82801dx/i82801dx.h"
 #elif CONFIG_SOUTHBRIDGE_INTEL_SCH
 #include "../../../southbridge/intel/sch/sch.h"
+#elif CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+#include "../../../southbridge/intel/bd82x6x/pch.h"
 #else
 #error "Southbridge needs SMM handler support."
 #endif
 
+#if CONFIG_SMM_TSEG
+
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#define TSEG_BAR (DEFAULT_PCIEXBAR | TSEG)
+#else
+#error "Northbridge must define TSEG_BAR."
+#endif
+#include <cpu/x86/mtrr.h>
+
+#endif /* CONFIG_SMM_TSEG */
+
 #define LAPIC_ID 0xfee00020
 
 .global smm_relocation_start
@@ -100,6 +114,7 @@
 	/* Check revision to see if AMD64 style SMM_BASE
 	 *   Intel Core Solo/Duo:  0x30007
 	 *   Intel Core2 Solo/Duo: 0x30100
+	 *   Intel SandyBridge:    0x30101
 	 *   AMD64:                0x3XX64
 	 * This check does not make much sense, unless someone ports
 	 * SMI handling to AMD64 CPUs.
@@ -127,11 +142,53 @@
 	movl %ecx, %edx
 	shl $10, %edx
 
+#if CONFIG_SMM_TSEG
+	movl	$(TSEG_BAR), %ecx	/* Get TSEG base from PCIE */
+	addr32	movl (%ecx), %eax	/* Save TSEG_BAR in %eax */
+	andl	$~1, %eax		/* Remove lock bit */
+#else
 	movl $0xa0000, %eax
+#endif
 	subl %edx, %eax	/* subtract offset, see above */
 
 	addr32 movl %eax, (%ebx)
 
+#if CONFIG_SMM_TSEG
+	/* Check for SMRR capability in MTRRCAP[11] */
+	movl	$MTRRcap_MSR, %ecx
+	rdmsr
+	bt	$11, %eax
+	jnc	skip_smrr
+
+	/* TSEG base */
+	movl	$(TSEG_BAR), %ecx	/* Get TSEG base from PCIE */
+	addr32	movl (%ecx), %eax	/* Save TSEG_BAR in %eax */
+	andl	$~1, %eax		/* Remove lock bit */
+	movl	%eax, %ebx
+
+	/* Set SMRR base address. */
+	movl	$SMRRphysBase_MSR, %ecx
+	orl	$MTRR_TYPE_WRBACK, %eax
+	xorl	%edx, %edx
+	wrmsr
+
+	/* Set SMRR mask. */
+	movl	$SMRRphysMask_MSR, %ecx
+	movl	$(~(CONFIG_SMM_TSEG_SIZE - 1) | MTRRphysMaskValid), %eax
+	xorl	%edx, %edx
+	wrmsr
+
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+	/*
+	 * IED base is top 4M of TSEG
+	 */
+	addl	$(CONFIG_SMM_TSEG_SIZE - IED_SIZE), %ebx
+	movl	$(0x30000 + 0x8000 + 0x7eec), %eax
+	addr32	movl %ebx, (%eax)
+#endif
+
+skip_smrr:
+#endif
 
 	/* The next section of code is potentially southbridge specific */
 
diff --git a/src/cpu/x86/sse_disable.inc b/src/cpu/x86/sse_disable.inc
deleted file mode 100644
index 37458c9..0000000
--- a/src/cpu/x86/sse_disable.inc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
- */
-
-	/*
-	 * Put the processor back into a reset state
-	 * with respect to the XMM registers.
-	 */
-	xorps %xmm0, %xmm0
-	xorps %xmm1, %xmm1
-	xorps %xmm2, %xmm2
-	xorps %xmm3, %xmm3
-	xorps %xmm4, %xmm4
-	xorps %xmm5, %xmm5
-	xorps %xmm6, %xmm6
-	xorps %xmm7, %xmm7
-
-	/*
-	 * Disable SSE instructions.
-	 *
-	 * Clear CR4[9] (OSFXSR) and CR4[10] (OSXMMEXCPT) so that the
-	 * processor can no longer execute SSE instructions, and unmasked
-	 * SIMD floating point exceptions will generate an invalid opcode
-	 * exception (#UD).
-	 */
-	movl	%cr4, %eax
-	andl	$~(3 << 9), %eax
-	movl	%eax, %cr4
-
diff --git a/src/devices/Kconfig b/src/devices/Kconfig
index 9e5ea6e..7429bda 100644
--- a/src/devices/Kconfig
+++ b/src/devices/Kconfig
@@ -33,6 +33,13 @@
 	  Execute VGA option ROMs, if found. This is required to enable
 	  PCI/AGP/PCI-E video cards.
 
+config S3_VGA_ROM_RUN
+	bool "Re-run VGA option ROMs on S3 resume"
+	default y
+	depends on VGA_ROM_RUN && HAVE_ACPI_RESUME
+	help
+	  Execute VGA option ROMs when coming out of an S3 resume.
+
 config PCI_ROM_RUN
 	bool "Run non-VGA option ROMs"
 	default y
@@ -42,6 +49,19 @@
 	  Examples include IDE/SATA controller option ROMs and option ROMs
 	  for network cards (NICs).
 
+config ON_DEVICE_ROM_RUN
+	bool "Run option ROMs on PCI devices"
+	default y
+	help
+	  Execute option ROMs that are stored on PCI/PCIe/AGP devices.
+
+	  If disabled, only option ROMs stored in CBFS will be executed. If
+	  you are concerned about security, you might want to disable this
+	  option, but it might leave your system in a state of degraded
+	  functionality.
+
+	  If unsure, say Y
+
 choice
 	prompt "Option ROM execution type"
 	default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86
@@ -143,3 +163,17 @@
 config CARDBUS_PLUGIN_SUPPORT
 	bool
 	default y
+
+config PCIEXP_COMMON_CLOCK
+	prompt "Enable PCIe Common Clock"
+	bool
+	default n
+	help
+	  Detect and enable Common Clock on PCIe links.
+
+config PCIEXP_ASPM
+	prompt "Enable PCIe ASPM"
+	bool
+	default n
+	help
+	  Detect and enable ASPM on PCIe links.
diff --git a/src/devices/device.c b/src/devices/device.c
index a2619bf..f559da5 100644
--- a/src/devices/device.c
+++ b/src/devices/device.c
@@ -41,6 +41,9 @@
 #include <stdlib.h>
 #include <string.h>
 #include <smp/spinlock.h>
+#if CONFIG_ARCH_X86
+#include <arch/ebda.h>
+#endif
 
 /** Linked list of ALL devices */
 struct device *all_devices = &dev_root;
@@ -1102,6 +1105,11 @@
 
 	printk(BIOS_INFO, "Initializing devices...\n");
 
+#if CONFIG_ARCH_X86
+	/* Ensure EBDA is prepared before Option ROMs. */
+	setup_default_ebda();
+#endif
+
 	/* First call the mainboard init. */
 	init_dev(&dev_root);
 
diff --git a/src/devices/device_util.c b/src/devices/device_util.c
index 9081a36..86124b4 100644
--- a/src/devices/device_util.c
+++ b/src/devices/device_util.c
@@ -110,6 +110,26 @@
 }
 
 /**
+ * Given a Local APIC ID, find the device structure.
+ *
+ * @param apic_id The Local APIC ID number.
+ * @return Pointer to the device structure (if found), 0 otherwise.
+ */
+device_t dev_find_lapic(unsigned apic_id)
+{
+	device_t dev, result = NULL;
+
+	for (dev = all_devices; dev; dev = dev->next) {
+		if (dev->path.type == DEVICE_PATH_APIC &&
+		    dev->path.apic.apic_id == apic_id) {
+			result = dev;
+			break;
+		}
+	}
+	return result;
+}
+
+/**
  * Find a device of a given vendor and type.
  *
  * @param vendor A PCI vendor ID (e.g. 0x8086 for Intel).
@@ -583,6 +603,8 @@
 					if (subbus->link_num
 					== IOINDEX_SUBTRACTIVE_LINK(res->index))
 						break;
+					if (!subbus) /* Why can subbus be NULL?  */
+						break;
 				search_bus_resources(subbus, type_mask, type,
 						     search, gp);
 				continue;
@@ -828,3 +850,21 @@
 
 	return tolm;
 }
+
+/* Count of enabled CPUs */
+int dev_count_cpu(void)
+{
+	device_t cpu;
+	int count = 0;
+
+	for (cpu = all_devices; cpu; cpu = cpu->next) {
+		if ((cpu->path.type != DEVICE_PATH_APIC) ||
+		    (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER))
+			continue;
+		if (!cpu->enabled)
+			continue;
+		count++;
+	}
+
+	return count;
+}
diff --git a/src/devices/oprom/include/vbe.h b/src/devices/oprom/include/vbe.h
new file mode 100644
index 0000000..f857b67
--- /dev/null
+++ b/src/devices/oprom/include/vbe.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+ * Copyright (c) 2004, 2008 IBM Corporation
+ * Copyright (c) 2009 Pattrick Hueper <phueper@hueper.net>
+ * All rights reserved.
+ * This program and the accompanying materials
+ * are made available under the terms of the BSD License
+ * which accompanies this distribution, and is available at
+ * http://www.opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     IBM Corporation - initial implementation
+ *****************************************************************************/
+
+// these structs are for input from and output to OF
+typedef struct {
+	u8 display_type;	// 0=NONE, 1= analog, 2=digital
+	u16 screen_width;
+	u16 screen_height;
+	u16 screen_linebytes;	// bytes per line in framebuffer, may be more than screen_width
+	u8 color_depth;	// color depth in bpp
+	u32 framebuffer_address;
+	u8 edid_block_zero[128];
+} __attribute__ ((__packed__)) screen_info_t;
+
+typedef struct {
+	u8 signature[4];
+	u16 size_reserved;
+	u8 monitor_number;
+	u16 max_screen_width;
+	u8 color_depth;
+} __attribute__ ((__packed__)) screen_info_input_t;
+
+// these structs only store a subset of the VBE defined fields
+// only those needed.
+typedef struct {
+	char signature[4];
+	u16 version;
+	u8 *oem_string_ptr;
+	u32 capabilities;
+	u16 video_mode_list[256];	// lets hope we never have more than 256 video modes...
+	u16 total_memory;
+} vbe_info_t;
+
+typedef struct {
+	u16 mode_attributes; // 00
+	u8 win_a_attributes; // 02
+	u8 win_b_attributes; // 03
+	u16 win_granularity; // 04
+	u16 win_size;        // 06
+	u16 win_a_segment;   // 08
+	u16 win_b_segment;   // 0a
+	u32 win_func_ptr;    // 0c
+	u16 bytes_per_scanline; // 10
+	u16 x_resolution;    // 12
+	u16 y_resolution;    // 14
+	u8 x_charsize;       // 16
+	u8 y_charsize;       // 17
+	u8 number_of_planes; // 18
+	u8 bits_per_pixel;   // 19
+	u8 number_of_banks;  // 20
+	u8 memory_model;     // 21
+	u8 bank_size;        // 22
+	u8 number_of_image_pages; // 23
+	u8 reserved_page;
+	u8 red_mask_size;
+	u8 red_mask_pos;
+	u8 green_mask_size;
+	u8 green_mask_pos;
+	u8 blue_mask_size;
+	u8 blue_mask_pos;
+	u8 reserved_mask_size;
+	u8 reserved_mask_pos;
+	u8 direct_color_mode_info;
+	u32 phys_base_ptr;
+	u32 offscreen_mem_offset;
+	u16 offscreen_mem_size;
+	u8 reserved[206];
+} __attribute__ ((__packed__)) vesa_mode_info_t;
+
+typedef struct {
+	u16 video_mode;
+	union {
+		vesa_mode_info_t vesa;
+		u8 mode_info_block[256];
+	};
+	// our crap
+	//u16 attributes;
+	//u16 linebytes;
+	//u16 x_resolution;
+	//u16 y_resolution;
+	//u8 x_charsize;
+	//u8 y_charsize;
+	//u8 bits_per_pixel;
+	//u8 memory_model;
+	//u32 framebuffer_address;
+} vbe_mode_info_t;
+
+typedef struct {
+	u8 port_number;	// i.e. monitor number
+	u8 edid_transfer_time;
+	u8 ddc_level;
+	u8 edid_block_zero[128];
+} vbe_ddc_info_t;
+
+struct lb_framebuffer;
+
+void vbe_set_graphics(void);
+void vbe_textmode_console(void);
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer);
+
+#define VESA_GET_INFO		0x4f00
+#define VESA_GET_MODE_INFO	0x4f01
+#define VESA_SET_MODE		0x4f02
+
diff --git a/src/devices/oprom/x86.c b/src/devices/oprom/x86.c
index 37b45e6..7e31cb4 100644
--- a/src/devices/oprom/x86.c
+++ b/src/devices/oprom/x86.c
@@ -25,42 +25,20 @@
 #include <arch/registers.h>
 #include <console/console.h>
 #include <arch/interrupt.h>
-
-#define REALMODE_BASE ((void *)0x600)
-
-struct realmode_idt {
-	u16 offset, cs;
-};
-
-void x86_exception(struct eregs *info);
-
-/* From x86_asm.S */
-extern unsigned char __idt_handler, __idt_handler_size;
-extern unsigned char __realmode_code, __realmode_code_size;
-extern unsigned char __realmode_call, __realmode_interrupt;
+#include <cbfs.h>
+#include <delay.h>
+#include <pc80/i8259.h>
+#include "x86.h"
+#include "vbe.h"
+#include "../../src/lib/jpeg.h"
 
 void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
-		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_call;
+		u32 esi, u32 edi) __attribute__((regparm(0))) =
+						(void *)&__realmode_call;
 
 void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
-		u32 esi, u32 edi) __attribute__((regparm(0))) = (void *)&__realmode_interrupt;
-
-#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB
-#define INITIAL_EBDA_SEGMENT 0xF600
-#define INITIAL_EBDA_SIZE 0x400
-
-static void setup_bda(void)
-{
-	/* clear BIOS DATA AREA */
-	memset((void *)0x400, 0, 0x200);
-
-	write16(0x413, FAKE_MEMORY_SIZE / 1024);
-	write16(0x40e, INITIAL_EBDA_SEGMENT);
-
-	/* Set up EBDA */
-	memset((void *)(INITIAL_EBDA_SEGMENT << 4), 0, INITIAL_EBDA_SIZE);
-	write16((INITIAL_EBDA_SEGMENT << 4) + 0x0, INITIAL_EBDA_SIZE / 1024);
-}
+		u32 esi, u32 edi) __attribute__((regparm(0))) =
+						(void *)&__realmode_interrupt;
 
 static void setup_rombios(void)
 {
@@ -80,14 +58,9 @@
 {
 	printk(BIOS_INFO, "Oops, exception %d while executing option rom\n",
 			regs->vector);
-#if 0
-	// Odd: The i945GM VGA oprom chokes on a pushl %eax and will
-	// die with an exception #6 if we run the coreboot exception 
-	// handler. Just continue, as it executes fine.
 	x86_exception(regs);	// Call coreboot exception handler
-#endif
 
-	return 0;		// Never returns?
+	return 0;		// Never really returns
 }
 
 static int intXX_unknown_handler(struct eregs *regs)
@@ -104,79 +77,6 @@
 	intXX_handler[intXX] = intXX_func;
 }
 
-static int int10_handler(struct eregs *regs)
-{
-	int res=-1;
-	static u8 cursor_row=0, cursor_col=0;
-	switch((regs->eax & 0xff00)>>8) {
-	case 0x01: // Set cursor shape
-		res = 0;
-		break;
-	case 0x02: // Set cursor position
-		if (cursor_row != ((regs->edx >> 8) & 0xff) ||
-		    cursor_col >= (regs->edx & 0xff)) {
-			printk(BIOS_INFO, "\n");
-		}
-		cursor_row = (regs->edx >> 8) & 0xff;
-		cursor_col = regs->edx & 0xff;
-		res = 0;
-		break;
-	case 0x03: // Get cursor position
-		regs->eax &= 0x00ff;
-		regs->ecx = 0x0607;
-		regs->edx = (cursor_row << 8) | cursor_col;
-		res = 0;
-		break;
-	case 0x06: // Scroll up
-		printk(BIOS_INFO, "\n");
-		res = 0;
-		break;
-	case 0x08: // Get Character and Mode at Cursor Position
-		regs->eax = 0x0f00 | 'A'; // White on black 'A'
-		res = 0;
-		break;
-	case 0x09: // Write Character and attribute
-	case 0x10: // Write Character
-		printk(BIOS_INFO, "%c", regs->eax & 0xff);
-		res = 0;
-		break;
-	case 0x0f: // Get video mode
-		regs->eax = 0x5002; //80x25
-		regs->ebx &= 0x00ff;
-		res = 0;
-		break;
-        default:
-		printk(BIOS_WARNING, "Unknown INT10 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-
-static int int16_handler(struct eregs *regs)
-{
-	int res=-1;
-	switch((regs->eax & 0xff00)>>8) {
-	case 0x00: // Check for Keystroke
-		regs->eax = 0x6120; // Space Bar, Space
-		res = 0;
-		break;
-	case 0x01: // Check for Keystroke
-		regs->eflags |= 1<<6; // Zero Flag set (no key available)
-		res = 0;
-		break;
-        default:
-		printk(BIOS_WARNING, "Unknown INT16 function %04x!\n",
-				regs->eax & 0xffff);
-		break;
-	}
-	return res;
-}
-
-int int12_handler(struct eregs *regs);
-int int15_handler(struct eregs *regs);
-int int1a_handler(struct eregs *regs);
-
 static void setup_interrupt_handlers(void)
 {
 	int i;
@@ -195,9 +95,9 @@
 		if(!intXX_handler[i])
 		{
 			/* Now set the default functions that are actually
-			 * needed to initialize the option roms. This is very
-			 * slick, as it allows us to implement mainboard specific
-			 * interrupt handlers, such as the int15
+			 * needed to initialize the option roms. This is
+			 * very slick, as it allows us to implement mainboard
+			 * specific interrupt handlers, such as the int15.
 			 */
 			switch (i) {
 			case 0x10:
@@ -206,9 +106,6 @@
 			case 0x12:
 				intXX_handler[0x12] = &int12_handler;
 				break;
-			case 0x15:
-				intXX_handler[0x15] = &int15_handler;
-				break;
 			case 0x16:
 				intXX_handler[0x16] = &int16_handler;
 				break;
@@ -269,12 +166,98 @@
 	write_idt_stub((void *)0xffe6e, 0x1a);
 }
 
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+static u8 vbe_get_mode_info(vbe_mode_info_t * mode_info)
+{
+	printk(BIOS_DEBUG, "Getting information about VESA mode %04x\n",
+		mode_info->video_mode);
+	char *buffer = (char *)&__buffer;
+	u16 buffer_seg = (((unsigned long)buffer) >> 4) & 0xff00;
+	u16 buffer_adr = ((unsigned long)buffer) & 0xffff;
+	realmode_interrupt(0x10, VESA_GET_MODE_INFO, 0x0000,
+			mode_info->video_mode, 0x0000, buffer_seg, buffer_adr);
+	memcpy(mode_info->mode_info_block, buffer, sizeof(vbe_mode_info_t));
+	return 0;
+}
+
+static u8 vbe_set_mode(vbe_mode_info_t * mode_info)
+{
+	printk(BIOS_DEBUG, "Setting VESA mode %04x\n", mode_info->video_mode);
+	// request linear framebuffer mode
+	mode_info->video_mode |= (1 << 14);
+	// request clearing of framebuffer
+	mode_info->video_mode &= ~(1 << 15);
+	realmode_interrupt(0x10, VESA_SET_MODE, mode_info->video_mode,
+			0x0000, 0x0000, 0x0000, 0x0000);
+	return 0;
+}
+
+vbe_mode_info_t mode_info;
+
+/* These two functions could probably even be generic between
+ * yabel and x86 native. TBD later.
+ */
+void vbe_set_graphics(void)
+{
+	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
+	vbe_get_mode_info(&mode_info);
+	unsigned char *framebuffer =
+		(unsigned char *)mode_info.vesa.phys_base_ptr;
+	printk(BIOS_DEBUG, "framebuffer: %p\n", framebuffer);
+	vbe_set_mode(&mode_info);
+#if CONFIG_BOOTSPLASH
+	struct jpeg_decdata *decdata;
+	decdata = malloc(sizeof(*decdata));
+	unsigned char *jpeg = cbfs_find_file("bootsplash.jpg",
+						CBFS_TYPE_BOOTSPLASH);
+	if (!jpeg) {
+		return;
+	}
+	int ret = 0;
+	ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata);
+#endif
+}
+
+void vbe_textmode_console(void)
+{
+	delay(2);
+	realmode_interrupt(0x10, 0x0003, 0x0000, 0x0000,
+				0x0000, 0x0000, 0x0000);
+}
+
+void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
+{
+	framebuffer->physical_address = mode_info.vesa.phys_base_ptr;
+
+	framebuffer->x_resolution = le16_to_cpu(mode_info.vesa.x_resolution);
+	framebuffer->y_resolution = le16_to_cpu(mode_info.vesa.y_resolution);
+	framebuffer->bytes_per_line =
+				le16_to_cpu(mode_info.vesa.bytes_per_scanline);
+	framebuffer->bits_per_pixel = mode_info.vesa.bits_per_pixel;
+
+	framebuffer->red_mask_pos = mode_info.vesa.red_mask_pos;
+	framebuffer->red_mask_size = mode_info.vesa.red_mask_size;
+
+	framebuffer->green_mask_pos = mode_info.vesa.green_mask_pos;
+	framebuffer->green_mask_size = mode_info.vesa.green_mask_size;
+
+	framebuffer->blue_mask_pos = mode_info.vesa.blue_mask_pos;
+	framebuffer->blue_mask_size = mode_info.vesa.blue_mask_size;
+
+	framebuffer->reserved_mask_pos = mode_info.vesa.reserved_mask_pos;
+	framebuffer->reserved_mask_size = mode_info.vesa.reserved_mask_size;
+}
+#endif
+
 void run_bios(struct device *dev, unsigned long addr)
 {
 	u32 num_dev = (dev->bus->secondary << 8) | dev->path.pci.devfn;
 
-	/* Set up BIOS Data Area */
-	setup_bda();
+	/* Setting up required hardware.
+	 * Removing this will cause random illegal instruction exceptions
+	 * in some option roms.
+	 */
+	setup_i8259();
 
 	/* Set up some legacy information in the F segment */
 	setup_rombios();
@@ -294,6 +277,10 @@
 	/* Option ROM entry point is at OPROM start + 3 */
 	realmode_call(addr + 0x0003, num_dev, 0xffff, 0x0000, 0xffff, 0x0, 0x0);
 	printk(BIOS_DEBUG, "... Option ROM returned.\n");
+
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
+	vbe_set_graphics();
+#endif
 }
 
 #if CONFIG_GEODE_VSA
diff --git a/src/devices/oprom/x86.h b/src/devices/oprom/x86.h
new file mode 100644
index 0000000..a4c740e
--- /dev/null
+++ b/src/devices/oprom/x86.h
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2009-2010 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#define REALMODE_BASE ((void *)0x600)
+
+struct realmode_idt {
+	u16 offset, cs;
+};
+
+void x86_exception(struct eregs *info);
+
+/* From x86_asm.S */
+extern unsigned char __idt_handler, __idt_handler_size;
+extern unsigned char __realmode_code, __realmode_code_size;
+extern unsigned char __realmode_call, __realmode_interrupt;
+extern unsigned char __buffer;
+
+extern void (*realmode_call)(u32 addr, u32 eax, u32 ebx, u32 ecx, u32 edx,
+		u32 esi, u32 edi) __attribute__((regparm(0)));
+
+extern void (*realmode_interrupt)(u32 intno, u32 eax, u32 ebx, u32 ecx, u32 edx, 
+		u32 esi, u32 edi) __attribute__((regparm(0)));
+
+#define FAKE_MEMORY_SIZE (1024*1024) // only 1MB
+#define INITIAL_EBDA_SEGMENT 0xF600
+#define INITIAL_EBDA_SIZE 0x400
+
+int int10_handler(struct eregs *regs);
+int int12_handler(struct eregs *regs);
+int int16_handler(struct eregs *regs);
+int int1a_handler(struct eregs *regs);
+
diff --git a/src/devices/oprom/x86_asm.S b/src/devices/oprom/x86_asm.S
index d5b5e18..57c5338 100644
--- a/src/devices/oprom/x86_asm.S
+++ b/src/devices/oprom/x86_asm.S
@@ -66,6 +66,11 @@
 	.long 0 /* 16 - ESI */
 	.long 0 /* 20 - EDI */
 
+/* 256 byte buffer, used by int10 */
+	.globl __buffer
+__buffer = RELOCATED(.)
+	.skip 256
+
 	.code32
 	.globl __realmode_call
 __realmode_call = RELOCATED(.)
diff --git a/src/devices/oprom/x86_interrupts.c b/src/devices/oprom/x86_interrupts.c
index 1dd645b..86d20d7 100644
--- a/src/devices/oprom/x86_interrupts.c
+++ b/src/devices/oprom/x86_interrupts.c
@@ -26,17 +26,7 @@
 #include <console/console.h>
 #include <arch/io.h>
 #include <arch/registers.h>
-
-enum {
-	PCIBIOS_CHECK = 0xb101,
-	PCIBIOS_FINDDEV = 0xb102,
-	PCIBIOS_READCONFBYTE = 0xb108,
-	PCIBIOS_READCONFWORD = 0xb109,
-	PCIBIOS_READCONFDWORD = 0xb10a,
-	PCIBIOS_WRITECONFBYTE = 0xb10b,
-	PCIBIOS_WRITECONFWORD = 0xb10c,
-	PCIBIOS_WRITECONFDWORD = 0xb10d
-};
+#include "x86.h"
 
 // errors go in AH. Just set these up so that word assigns
 // will work. KISS.
@@ -48,9 +38,54 @@
 	PCIBIOS_BADREG = 0x8700
 };
 
-int int12_handler(struct eregs *regs);
-int int1a_handler(struct eregs *regs);
-int int15_handler(struct eregs *regs);
+int int10_handler(struct eregs *regs)
+{
+	int res=-1;
+	static u8 cursor_row=0, cursor_col=0;
+	switch((regs->eax & 0xff00)>>8) {
+	case 0x01: // Set cursor shape
+		res = 0;
+		break;
+	case 0x02: // Set cursor position
+		if (cursor_row != ((regs->edx >> 8) & 0xff) ||
+		    cursor_col >= (regs->edx & 0xff)) {
+			printk(BIOS_INFO, "\n");
+		}
+		cursor_row = (regs->edx >> 8) & 0xff;
+		cursor_col = regs->edx & 0xff;
+		res = 0;
+		break;
+	case 0x03: // Get cursor position
+		regs->eax &= 0x00ff;
+		regs->ecx = 0x0607;
+		regs->edx = (cursor_row << 8) | cursor_col;
+		res = 0;
+		break;
+	case 0x06: // Scroll up
+		printk(BIOS_INFO, "\n");
+		res = 0;
+		break;
+	case 0x08: // Get Character and Mode at Cursor Position
+		regs->eax = 0x0f00 | 'A'; // White on black 'A'
+		res = 0;
+		break;
+	case 0x09: // Write Character and attribute
+	case 0x10: // Write Character
+		printk(BIOS_INFO, "%c", regs->eax & 0xff);
+		res = 0;
+		break;
+	case 0x0f: // Get video mode
+		regs->eax = 0x5002; //80x25
+		regs->ebx &= 0x00ff;
+		res = 0;
+		break;
+        default:
+		printk(BIOS_WARNING, "Unknown INT10 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
 
 int int12_handler(struct eregs *regs)
 {
@@ -58,6 +93,26 @@
 	return 0;
 }
 
+int int16_handler(struct eregs *regs)
+{
+	int res=-1;
+	switch((regs->eax & 0xff00)>>8) {
+	case 0x00: // Check for Keystroke
+		regs->eax = 0x6120; // Space Bar, Space
+		res = 0;
+		break;
+	case 0x01: // Check for Keystroke
+		regs->eflags |= 1<<6; // Zero Flag set (no key available)
+		res = 0;
+		break;
+        default:
+		printk(BIOS_WARNING, "Unknown INT16 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+
 #define PCI_CONFIG_SPACE_TYPE1	(1 << 0)
 #define PCI_CONFIG_SPACE_TYPE2	(1 << 1)
 #define PCI_SPECIAL_CYCLE_TYPE1	(1 << 4)
@@ -77,7 +132,7 @@
 	u8 byte, reg;
 
 	switch (func) {
-	case PCIBIOS_CHECK:
+	case 0xb101: /* PCIBIOS Check */
 		regs->edx = 0x20494350;	/* ' ICP' */
 		regs->eax &= 0xffff0000; /* Clear AH / AL */
 		regs->eax |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1;
@@ -87,7 +142,7 @@
 		regs->edi = 0x00000000;	/* protected mode entry */
 		retval = 0;
 		break;
-	case PCIBIOS_FINDDEV:
+	case 0xb102: /* Find Device */
 		devid = regs->ecx;
 		vendorid = regs->edx;
 		devindex = regs->esi;
@@ -114,12 +169,12 @@
 			retval = -1;
 		}
 		break;
-	case PCIBIOS_READCONFDWORD:
-	case PCIBIOS_READCONFWORD:
-	case PCIBIOS_READCONFBYTE:
-	case PCIBIOS_WRITECONFDWORD:
-	case PCIBIOS_WRITECONFWORD:
-	case PCIBIOS_WRITECONFBYTE:
+	case 0xb10a: /* Read Config Dword */
+	case 0xb109: /* Read Config Word */
+	case 0xb108: /* Read Config Byte */
+	case 0xb10d: /* Write Config Dword */
+	case 0xb10c: /* Write Config Word */
+	case 0xb10b: /* Write Config Byte */
 		devfn = regs->ebx & 0xff;
 		bus = regs->ebx >> 8;
 		reg = regs->edi;
@@ -133,27 +188,27 @@
 			return retval;
 		}
 		switch (func) {
-		case PCIBIOS_READCONFBYTE:
+		case 0xb108: /* Read Config Byte */
 			byte = pci_read_config8(dev, reg);
 			regs->ecx = byte;
 			break;
-		case PCIBIOS_READCONFWORD:
+		case 0xb109: /* Read Config Word */
 			word = pci_read_config16(dev, reg);
 			regs->ecx = word;
 			break;
-		case PCIBIOS_READCONFDWORD:
+		case 0xb10a: /* Read Config Dword */
 			dword = pci_read_config32(dev, reg);
 			regs->ecx = dword;
 			break;
-		case PCIBIOS_WRITECONFBYTE:
+		case 0xb10b: /* Write Config Byte */
 			byte = regs->ecx;
 			pci_write_config8(dev, reg, byte);
 			break;
-		case PCIBIOS_WRITECONFWORD:
+		case 0xb10c: /* Write Config Word */
 			word = regs->ecx;
 			pci_write_config16(dev, reg, word);
 			break;
-		case PCIBIOS_WRITECONFDWORD:
+		case 0xb10d: /* Write Config Dword */
 			dword = regs->ecx;
 			pci_write_config32(dev, reg, dword);
 			break;
@@ -178,42 +233,3 @@
 	return retval;
 }
 
-int int15_handler(struct eregs *regs)
-{
-	int res = -1;
-
-	/* This int15 handler is Intel IGD. specific. Other chipsets need other
-	 * handlers. The right way to do this is to move this handler code into
-	 * the mainboard or northbridge code.
-	 * TODO: completely move to mainboards / chipsets.
-	 */
-	switch (regs->eax & 0xffff) {
-	/* And now Intel IGD code */
-#define BOOT_DISPLAY_DEFAULT    0
-#define BOOT_DISPLAY_CRT        (1 << 0)
-#define BOOT_DISPLAY_TV         (1 << 1)
-#define BOOT_DISPLAY_EFP        (1 << 2)
-#define BOOT_DISPLAY_LCD        (1 << 3)
-#define BOOT_DISPLAY_CRT2       (1 << 4)
-#define BOOT_DISPLAY_TV2        (1 << 5)
-#define BOOT_DISPLAY_EFP2       (1 << 6)
-#define BOOT_DISPLAY_LCD2       (1 << 7)
-	case 0x5f35:
-		regs->eax = 0x5f;
-		regs->ecx = BOOT_DISPLAY_DEFAULT;
-		res = 0;
-		break;
-	case 0x5f40:
-		regs->eax = 0x5f;
-		regs->ecx = 3; // This is mainboard specific
-		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
-		res = 0;
-		break;
-	default:
-		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
-				regs->eax & 0xffff);
-	}
-
-	return res;
-}
-
diff --git a/src/devices/oprom/x86emu/debug.h b/src/devices/oprom/x86emu/debug.h
index ba180ba..1b2c3a3 100644
--- a/src/devices/oprom/x86emu/debug.h
+++ b/src/devices/oprom/x86emu/debug.h
@@ -198,6 +198,12 @@
 #define	DB(x)
 #endif
 
+#ifdef DEBUG
+#define X86EMU_DEBUG_ONLY(x) x
+#else
+#define X86EMU_DEBUG_ONLY(x) X86EMU_UNUSED(x)
+#endif
+
 /*-------------------------- Function Prototypes --------------------------*/
 
 #ifdef  __cplusplus
diff --git a/src/devices/oprom/x86emu/fpu.c b/src/devices/oprom/x86emu/fpu.c
index daa2ffa..7edebd4 100644
--- a/src/devices/oprom/x86emu/fpu.c
+++ b/src/devices/oprom/x86emu/fpu.c
@@ -50,6 +50,12 @@
     END_OF_INSTR_NO_TRACE();
 }
 
+#ifdef X86EMU_FPU_PRESENT
+#define X86EMU_FPU_ONLY(x) x
+#else
+#define X86EMU_FPU_ONLY(x) X86EMU_UNUSED(x)
+#endif
+
 #ifdef DEBUG
 
 static const char *x86emu_fpu_op_d9_tab[] = {
@@ -95,8 +101,8 @@
 void x86emuOp_esc_coprocess_d9(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -322,8 +328,8 @@
 void x86emuOp_esc_coprocess_da(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -403,7 +409,7 @@
 void x86emuOp_esc_coprocess_db(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
+    uint X86EMU_FPU_ONLY(destoffset);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -530,8 +536,8 @@
 void x86emuOp_esc_coprocess_dc(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -640,8 +646,8 @@
 void x86emuOp_esc_coprocess_dd(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -747,8 +753,8 @@
 void x86emuOp_esc_coprocess_de(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
@@ -866,8 +872,8 @@
 void x86emuOp_esc_coprocess_df(u8 X86EMU_UNUSED(op1))
 {
     int mod, rl, rh;
-    uint destoffset;
-    u8 stkelem;
+    uint X86EMU_FPU_ONLY(destoffset);
+    u8 X86EMU_FPU_ONLY(stkelem);
 
     START_OF_INSTR();
     FETCH_DECODE_MODRM(mod, rh, rl);
diff --git a/src/devices/oprom/x86emu/ops.c b/src/devices/oprom/x86emu/ops.c
index c66da95..70e048d 100644
--- a/src/devices/oprom/x86emu/ops.c
+++ b/src/devices/oprom/x86emu/ops.c
@@ -3562,7 +3562,7 @@
 ****************************************************************************/
 static void x86emuOp_int3(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
 
     START_OF_INSTR();
     DECODE_PRINTF("INT 3\n");
@@ -3590,7 +3590,7 @@
 ****************************************************************************/
 static void x86emuOp_int_IMM(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
     u8 intnum;
 
     START_OF_INSTR();
@@ -3620,7 +3620,7 @@
 ****************************************************************************/
 static void x86emuOp_into(u8 X86EMU_UNUSED(op1))
 {
-    u16 tmp;
+    u16 X86EMU_UNUSED(tmp);
 
     START_OF_INSTR();
     DECODE_PRINTF("INTO\n");
@@ -4034,7 +4034,7 @@
 ****************************************************************************/
 static void x86emuOp_aad(u8 X86EMU_UNUSED(op1))
 {
-    u8 a;
+    u8 X86EMU_UNUSED(a);
 
     START_OF_INSTR();
     DECODE_PRINTF("AAD\n");
diff --git a/src/devices/oprom/x86emu/ops2.c b/src/devices/oprom/x86emu/ops2.c
index 349a664..f559874 100644
--- a/src/devices/oprom/x86emu/ops2.c
+++ b/src/devices/oprom/x86emu/ops2.c
@@ -336,7 +336,7 @@
     int mod, rl, rh;
     uint destoffset;
     u8  *destreg;
-    const char *name = 0;
+    const char *X86EMU_DEBUG_ONLY(name) = 0;
     int cond = 0;
 
     START_OF_INSTR();
diff --git a/src/devices/oprom/yabel/compat/functions.c b/src/devices/oprom/yabel/compat/functions.c
index db37fbc..542c81f 100644
--- a/src/devices/oprom/yabel/compat/functions.c
+++ b/src/devices/oprom/yabel/compat/functions.c
@@ -38,7 +38,7 @@
 
 	biosemu(vmem, VMEM_SIZE, dev, addr);
 
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 	vbe_set_graphics();
 #endif
 }
diff --git a/src/devices/oprom/yabel/device.c b/src/devices/oprom/yabel/device.c
index 8259594..b09f50e 100644
--- a/src/devices/oprom/yabel/device.c
+++ b/src/devices/oprom/yabel/device.c
@@ -364,6 +364,7 @@
 		pci_ds.device_id = in16le(&pci_ds.device_id);
 		pci_ds.img_length = in16le(&pci_ds.img_length);
 		pci_ds.pci_ds_length = in16le(&pci_ds.pci_ds_length);
+#ifdef DO_THIS_TEST_TWICE
 		if (pci_ds.vendor_id != bios_device.pci_vendor_id) {
 			printf
 			    ("Image has invalid Vendor ID: %04x, expected: %04x\n",
@@ -376,6 +377,7 @@
 			     pci_ds.device_id, bios_device.pci_device_id);
 			break;
 		}
+#endif
 		DEBUG_PRINTF("Image Length: %d\n", pci_ds.img_length * 512);
 		DEBUG_PRINTF("Image Code Type: %d\n", pci_ds.code_type);
 		if (pci_ds.code_type == 0) {
diff --git a/src/devices/oprom/yabel/vbe.c b/src/devices/oprom/yabel/vbe.c
index 75e8f3e..b1d6984 100644
--- a/src/devices/oprom/yabel/vbe.c
+++ b/src/devices/oprom/yabel/vbe.c
@@ -13,7 +13,7 @@
 
 #include <string.h>
 #include <types.h>
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 #include <boot/coreboot_tables.h>
 #endif
 
@@ -31,13 +31,14 @@
 #include "mem.h"
 #include "interrupt.h"
 #include "device.h"
-#include "vbe.h"
 
 #include <cbfs.h>
 
 #include <delay.h>
 #include "../../src/lib/jpeg.h"
 
+#include <vbe.h>
+
 // pointer to VBEInfoBuffer, set by vbe_prepare
 u8 *vbe_info_buffer = 0;
 
@@ -45,97 +46,6 @@
 u8 *biosmem;
 u32 biosmem_size;
 
-// these structs are for input from and output to OF
-typedef struct {
-	u8 display_type;	// 0=NONE, 1= analog, 2=digital
-	u16 screen_width;
-	u16 screen_height;
-	u16 screen_linebytes;	// bytes per line in framebuffer, may be more than screen_width
-	u8 color_depth;	// color depth in bpp
-	u32 framebuffer_address;
-	u8 edid_block_zero[128];
-} __attribute__ ((__packed__)) screen_info_t;
-
-typedef struct {
-	u8 signature[4];
-	u16 size_reserved;
-	u8 monitor_number;
-	u16 max_screen_width;
-	u8 color_depth;
-} __attribute__ ((__packed__)) screen_info_input_t;
-
-// these structs only store a subset of the VBE defined fields
-// only those needed.
-typedef struct {
-	char signature[4];
-	u16 version;
-	u8 *oem_string_ptr;
-	u32 capabilities;
-	u16 video_mode_list[256];	// lets hope we never have more than 256 video modes...
-	u16 total_memory;
-} vbe_info_t;
-
-typedef struct {
-	u16 mode_attributes; // 00
-	u8 win_a_attributes; // 02
-	u8 win_b_attributes; // 03
-	u16 win_granularity; // 04
-	u16 win_size;        // 06
-	u16 win_a_segment;   // 08
-	u16 win_b_segment;   // 0a
-	u32 win_func_ptr;    // 0c
-	u16 bytes_per_scanline; // 10
-	u16 x_resolution;    // 12
-	u16 y_resolution;    // 14
-	u8 x_charsize;       // 16
-	u8 y_charsize;       // 17
-	u8 number_of_planes; // 18
-	u8 bits_per_pixel;   // 19
-	u8 number_of_banks;  // 20
-	u8 memory_model;     // 21
-	u8 bank_size;        // 22
-	u8 number_of_image_pages; // 23
-	u8 reserved_page;
-	u8 red_mask_size;
-	u8 red_mask_pos;
-	u8 green_mask_size;
-	u8 green_mask_pos;
-	u8 blue_mask_size;
-	u8 blue_mask_pos;
-	u8 reserved_mask_size;
-	u8 reserved_mask_pos;
-	u8 direct_color_mode_info;
-	u32 phys_base_ptr;
-	u32 offscreen_mem_offset;
-	u16 offscreen_mem_size;
-	u8 reserved[206];
-} __attribute__ ((__packed__)) vesa_mode_info_t;
-
-typedef struct {
-	u16 video_mode;
-	union {
-		vesa_mode_info_t vesa;
-		u8 mode_info_block[256];
-	};
-	// our crap
-	//u16 attributes;
-	//u16 linebytes;
-	//u16 x_resolution;
-	//u16 y_resolution;
-	//u8 x_charsize;
-	//u8 y_charsize;
-	//u8 bits_per_pixel;
-	//u8 memory_model;
-	//u32 framebuffer_address;
-} vbe_mode_info_t;
-
-typedef struct {
-	u8 port_number;	// i.e. monitor number
-	u8 edid_transfer_time;
-	u8 ddc_level;
-	u8 edid_block_zero[128];
-} vbe_ddc_info_t;
-
 static inline u8
 vbe_prepare(void)
 {
@@ -154,7 +64,7 @@
 	return 0;		// successfull init
 }
 
-#if CONFIG_BOOTSPLASH
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE
 // VBE Function 00h
 static u8
 vbe_info(vbe_info_t * info)
@@ -794,10 +704,12 @@
 
 	mode_info.video_mode = (1 << 14) | CONFIG_FRAMEBUFFER_VESA_MODE;
 	vbe_get_mode_info(&mode_info);
+	vbe_set_mode(&mode_info);
+
+#if CONFIG_BOOTSPLASH
 	unsigned char *framebuffer =
 		(unsigned char *) le32_to_cpu(mode_info.vesa.phys_base_ptr);
 	DEBUG_PRINTF_VBE("FRAMEBUFFER: 0x%p\n", framebuffer);
-	vbe_set_mode(&mode_info);
 
 	struct jpeg_decdata *decdata;
 	decdata = malloc(sizeof(*decdata));
@@ -818,6 +730,7 @@
 	DEBUG_PRINTF_VBE("Decompressing boot splash screen...\n");
 	ret = jpeg_decode(jpeg, framebuffer, 1024, 768, 16, decdata);
 	DEBUG_PRINTF_VBE("returns %x\n", ret);
+#endif
 }
 
 void fill_lb_framebuffer(struct lb_framebuffer *framebuffer)
diff --git a/src/devices/pci_device.c b/src/devices/pci_device.c
index 2ccb38a..e6c43170 100644
--- a/src/devices/pci_device.c
+++ b/src/devices/pci_device.c
@@ -51,6 +51,12 @@
 #if CONFIG_PC80_SYSTEM == 1
 #include <pc80/i8259.h>
 #endif
+#if CONFIG_HAVE_ACPI_RESUME && !CONFIG_S3_VGA_ROM_RUN
+#include <arch/acpi.h>
+#endif
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
 
 u8 pci_moving_config8(struct device *dev, unsigned int reg)
 {
@@ -664,6 +670,15 @@
 	    ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
 		return;
 
+#if CONFIG_CHROMEOS
+	/* In ChromeOS we want to boot blazingly fast. Therefore
+	 * we don't run (VGA) option ROMs, unless we have to print
+	 * something on the screen before the kernel is loaded.
+	 */
+	if (!developer_mode_enabled() && !recovery_mode_enabled())
+		return;
+#endif
+
 	rom = pci_rom_probe(dev);
 	if (rom == NULL)
 		return;
@@ -672,6 +687,14 @@
 	if (ram == NULL)
 		return;
 
+#if !CONFIG_S3_VGA_ROM_RUN
+	/* If S3_VGA_ROM_RUN is disabled, skip running VGA option
+	 * ROMs when coming out of an S3 resume.
+	 */
+	if ((acpi_slp_type == 3) &&
+		((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA))
+		return;
+#endif
 	run_bios(dev, (unsigned long)ram);
 #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */
 }
diff --git a/src/devices/pci_rom.c b/src/devices/pci_rom.c
index 56712df..1b6f1da 100644
--- a/src/devices/pci_rom.c
+++ b/src/devices/pci_rom.c
@@ -37,6 +37,19 @@
 	/* If it's in FLASH, then don't check device for ROM. */
 	rom_header = cbfs_load_optionrom(dev->vendor, dev->device, NULL);
 
+	u32 vendev = dev->vendor | (dev->device << 16);
+	u32 mapped_vendev = vendev;
+
+	if (map_oprom_vendev)
+		mapped_vendev = map_oprom_vendev(vendev);
+
+	if (!rom_header) {
+		if (vendev != mapped_vendev) {
+			rom_header = cbfs_load_optionrom(mapped_vendev &
+					0xffff, mapped_vendev >> 16, NULL);
+		}
+	}
+
 	if (rom_header) {
 		printk(BIOS_DEBUG, "In CBFS, ROM address for %s = %p\n",
 		       dev_path(dev), rom_header);
@@ -58,9 +71,15 @@
 					   rom_address|PCI_ROM_ADDRESS_ENABLE);
 		}
 
+#if CONFIG_ON_DEVICE_ROM_RUN
 		printk(BIOS_DEBUG, "On card, ROM address for %s = %lx\n",
 		       dev_path(dev), (unsigned long)rom_address);
 		rom_header = (struct rom_header *)rom_address;
+#else
+		printk(BIOS_DEBUG, "On card option ROM execution disabled "
+			"for %s\n", dev_path(dev));
+		return NULL;
+#endif
 	}
 
 	printk(BIOS_SPEW, "PCI expansion ROM, signature 0x%04x, "
@@ -78,8 +97,10 @@
 
 	printk(BIOS_SPEW, "PCI ROM image, vendor ID %04x, device ID %04x,\n",
 	       rom_data->vendor, rom_data->device);
-	if (dev->vendor != rom_data->vendor
-	    || dev->device != rom_data->device) {
+	/* If the device id is mapped, a mismatch is expected */
+	if ((dev->vendor != rom_data->vendor
+	    || dev->device != rom_data->device)
+	    && (vendev == mapped_vendev)) {
 		printk(BIOS_ERR, "ID mismatch: vendor ID %04x, "
 		       "device ID %04x\n", rom_data->vendor, rom_data->device);
 		return NULL;
diff --git a/src/devices/pciexp_device.c b/src/devices/pciexp_device.c
index 5d33942..36f3e6a 100644
--- a/src/devices/pciexp_device.c
+++ b/src/devices/pciexp_device.c
@@ -19,31 +19,197 @@
  */
 
 #include <console/console.h>
+#include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/pciexp.h>
 
+#if CONFIG_PCIEXP_COMMON_CLOCK
+/*
+ * Re-train a PCIe link
+ */
+#define PCIE_TRAIN_RETRY 10000
+static int pciexp_retrain_link(device_t dev, unsigned cap)
+{
+	unsigned try = PCIE_TRAIN_RETRY;
+	u16 lnk;
+
+	/* Start link retraining */
+	lnk = pci_read_config16(dev, cap + PCI_EXP_LNKCTL);
+	lnk |= PCI_EXP_LNKCTL_RL;
+	pci_write_config16(dev, cap + PCI_EXP_LNKCTL, lnk);
+
+	/* Wait for training to complete */
+	while (try--) {
+		lnk = pci_read_config16(dev, cap + PCI_EXP_LNKSTA);
+		if (!(lnk & PCI_EXP_LNKSTA_LT))
+			return 0;
+		udelay(100);
+	}
+
+	printk(BIOS_ERR, "%s: Link Retrain timeout\n", dev_path(dev));
+	return -1;
+}
+
+/*
+ * Check the Slot Clock Configuration for root port and endpoint
+ * and enable Common Clock Configuration if possible.  If CCC is
+ * enabled the link must be retrained.
+ */
+static void pciexp_enable_common_clock(device_t root, unsigned root_cap,
+				       device_t endp, unsigned endp_cap)
+{
+	u16 root_scc, endp_scc, lnkctl;
+
+	/* Get Slot Clock Configuration for root port */
+	root_scc = pci_read_config16(root, root_cap + PCI_EXP_LNKSTA);
+	root_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Get Slot Clock Configuration for endpoint */
+	endp_scc = pci_read_config16(endp, endp_cap + PCI_EXP_LNKSTA);
+	endp_scc &= PCI_EXP_LNKSTA_SLC;
+
+	/* Enable Common Clock Configuration and retrain */
+	if (root_scc && endp_scc) {
+		printk(BIOS_INFO, "Enabling Common Clock Configuration\n");
+
+		/* Set in endpoint */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set in root port */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= PCI_EXP_LNKCTL_CCC;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Retrain link if CCC was enabled */
+		pciexp_retrain_link(root, root_cap);
+	}
+}
+#endif /* CONFIG_PCIEXP_COMMON_CLOCK */
+
+#if CONFIG_PCIEXP_ASPM
+/*
+ * Determine the ASPM L0s or L1 exit latency for a link
+ * by checking both root port and endpoint and returning
+ * the highest latency value.
+ */
+static int pciexp_aspm_latency(device_t root, unsigned root_cap,
+			       device_t endp, unsigned endp_cap,
+			       enum aspm_type type)
+{
+	int root_lat = 0, endp_lat = 0;
+	u32 root_lnkcap, endp_lnkcap;
+
+	root_lnkcap = pci_read_config32(root, root_cap + PCI_EXP_LNKCAP);
+	endp_lnkcap = pci_read_config32(endp, endp_cap + PCI_EXP_LNKCAP);
+
+	/* Make sure the link supports this ASPM type by checking
+	 * capability bits 11:10 with aspm_type offset by 1 */
+	if (!(root_lnkcap & (1 << (type + 9))) ||
+	    !(endp_lnkcap & (1 << (type + 9))))
+		return -1;
+
+	/* Find the one with higher latency */
+	switch (type) {
+	case PCIE_ASPM_L0S:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
+		break;
+	case PCIE_ASPM_L1:
+		root_lat = (root_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		endp_lat = (endp_lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
+		break;
+	default:
+		return -1;
+	}
+
+	return (endp_lat > root_lat) ? endp_lat : root_lat;
+}
+
+/*
+ * Enable ASPM on PCIe root port and endpoint.
+ *
+ * Returns APMC value:
+ *   -1 = Error
+ *    0 = no ASPM
+ *    1 = L0s Enabled
+ *    2 = L1 Enabled
+ *    3 = L0s and L1 Enabled
+ */
+static enum aspm_type pciexp_enable_aspm(device_t root, unsigned root_cap,
+					 device_t endp, unsigned endp_cap)
+{
+	const char *aspm_type_str[] = { "None", "L0s", "L1", "L0s and L1" };
+	enum aspm_type apmc = PCIE_ASPM_NONE;
+	int exit_latency, ok_latency;
+	u16 lnkctl;
+	u32 devcap;
+
+	/* Get endpoint device capabilities for acceptable limits */
+	devcap = pci_read_config32(endp, endp_cap + PCI_EXP_DEVCAP);
+
+	/* Enable L0s if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L0S) >> 6;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L0S);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L0S;
+
+	/* Enable L1 if it is within endpoint acceptable limit */
+	ok_latency = (devcap & PCI_EXP_DEVCAP_L1) >> 9;
+	exit_latency = pciexp_aspm_latency(root, root_cap, endp, endp_cap,
+					   PCIE_ASPM_L1);
+	if (exit_latency >= 0 && exit_latency <= ok_latency)
+		apmc |= PCIE_ASPM_L1;
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Set APMC in root port first */
+		lnkctl = pci_read_config16(root, root_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(root, root_cap + PCI_EXP_LNKCTL, lnkctl);
+
+		/* Set APMC in endpoint device next */
+		lnkctl = pci_read_config16(endp, endp_cap + PCI_EXP_LNKCTL);
+		lnkctl |= apmc;
+		pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl);
+	}
+
+	printk(BIOS_INFO, "ASPM: Enabled %s\n", aspm_type_str[apmc]);
+	return apmc;
+}
+#endif /* CONFIG_PCIEXP_ASPM */
+
 static void pciexp_tune_dev(device_t dev)
 {
-	unsigned int cap;
-#if CONFIG_PCIE_TUNING
-	u32 reg32;
-#endif
+	device_t root = dev->bus->dev;
+	unsigned int root_cap, cap;
 
 	cap = pci_find_capability(dev, PCI_CAP_ID_PCIE);
 	if (!cap)
 		return;
 
-#if CONFIG_PCIE_TUNING
-	printk(BIOS_DEBUG, "PCIe: tuning %s\n", dev_path(dev));
+	root_cap = pci_find_capability(root, PCI_CAP_ID_PCIE);
+	if (!root_cap)
+		return;
 
-	// TODO make this depending on ASPM.
+#if CONFIG_PCIEXP_COMMON_CLOCK
+	/* Check for and enable Common Clock */
+	pciexp_enable_common_clock(root, root_cap, dev, cap);
+#endif
 
-	/* Enable ASPM role based error reporting. */
-	reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
-	reg32 |= PCI_EXP_DEVCAP_RBER;
-	pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+#if CONFIG_PCIEXP_ASPM
+	/* Check for and enable ASPM */
+	enum aspm_type apmc = pciexp_enable_aspm(root, root_cap, dev, cap);
+
+	if (apmc != PCIE_ASPM_NONE) {
+		/* Enable ASPM role based error reporting. */
+		u32 reg32 = pci_read_config32(dev, cap + PCI_EXP_DEVCAP);
+		reg32 |= PCI_EXP_DEVCAP_RBER;
+		pci_write_config32(dev, cap + PCI_EXP_DEVCAP, reg32);
+	}
 #endif
 }
 
diff --git a/src/drivers/generic/Makefile.inc b/src/drivers/generic/Makefile.inc
index 0700a0c..08e6cc5 100644
--- a/src/drivers/generic/Makefile.inc
+++ b/src/drivers/generic/Makefile.inc
@@ -1 +1,2 @@
 subdirs-y += debug
+subdirs-y += generic
diff --git a/src/drivers/generic/generic/Makefile.inc b/src/drivers/generic/generic/Makefile.inc
new file mode 100644
index 0000000..b7db254
--- /dev/null
+++ b/src/drivers/generic/generic/Makefile.inc
@@ -0,0 +1 @@
+# Empty
diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc
index 7d3a26f..7f4aa58 100644
--- a/src/drivers/oxford/oxpcie/Makefile.inc
+++ b/src/drivers/oxford/oxpcie/Makefile.inc
@@ -1,3 +1,5 @@
 driver-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie.c
 
+ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y)
 romstage-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie_early.c
+endif
diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c
index 94c5b64..8afdd1f 100644
--- a/src/drivers/oxford/oxpcie/oxpcie.c
+++ b/src/drivers/oxford/oxpcie/oxpcie.c
@@ -23,7 +23,6 @@
 #include <device/pci_ids.h>
 #include <console/console.h>
 #include <arch/io.h>
-#include <uart8250.h>
 
 static void oxford_oxpcie_enable(device_t dev)
 {
@@ -41,9 +40,20 @@
 			(read32(res->base + 4) & 3));
 }
 
+
+static void oxford_oxpcie_set_resources(struct device *dev)
+{
+	pci_dev_set_resources(dev);
+
+#if CONFIG_CONSOLE_SERIAL8250MEM
+	/* Re-initialize OXPCIe base address after set_resources */
+	uartmem_init();
+#endif
+}
+
 static struct device_operations oxford_oxpcie_ops = {
 	.read_resources   = pci_dev_read_resources,
-	.set_resources    = pci_dev_set_resources,
+	.set_resources    = oxford_oxpcie_set_resources,
 	.enable_resources = pci_dev_enable_resources,
 	.init             = oxford_oxpcie_enable,
 	.scan_bus         = 0,
@@ -54,3 +64,9 @@
 	.vendor = 0x1415,
 	.device = 0xc158,
 };
+
+static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = {
+	.ops    = &oxford_oxpcie_ops,
+	.vendor = 0x1415,
+	.device = 0xc11b,
+};
diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c
index 235c52c..52dae72 100644
--- a/src/drivers/oxford/oxpcie/oxpcie_early.c
+++ b/src/drivers/oxford/oxpcie/oxpcie_early.c
@@ -20,6 +20,8 @@
 #include <stdint.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
+#include <cpu/x86/car.h>
+#include <delay.h>
 #include <uart8250.h>
 #include <device/pci_def.h>
 
@@ -29,11 +31,18 @@
 		CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION)
 
 #define OXPCIE_DEVICE \
-	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) 
+	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0)
+
+#define OXPCIE_DEVICE_3 \
+	PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3)
+
+#if defined(__PRE_RAM__)
+int oxford_oxpcie_present CAR_GLOBAL;
 
 void oxford_init(void)
 {
 	u16 reg16;
+	oxford_oxpcie_present = 1;
 
 	/* First we reset the secondary bus */
 	reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL);
@@ -66,20 +75,44 @@
 	reg16 |= PCI_COMMAND_MEMORY;
 	pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16);
 
-	// FIXME Add a timeout or this will hang forever if 
-	// no device is in the slot.
+	u32 timeout = 20000; // Timeout in 10s of microseconds.
 	u32 id = 0;
-	while ((id == 0) || (id == 0xffffffff))
+	for (;;) {
 		id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID);
+		if (!timeout-- || (id != 0 && id != 0xffffffff))
+			break;
+		udelay(10);
+	}
+
+	u32 device = OXPCIE_DEVICE; /* unknown default */
+	switch (id) {
+	case 0xc1181415: /* e.g. Startech PEX1S1PMINI */
+		/* On this device function 0 is the parallel port, and
+		 * function 3 is the serial port. So let's go look for
+		 * the UART.
+		 */
+		id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID);
+		if (id != 0xc11b1415)
+			return;
+		device = OXPCIE_DEVICE_3;
+		break;
+	case 0xc1581415: /* e.g. Startech MPEX2S952 */
+		device = OXPCIE_DEVICE;
+		break;
+	default:
+		/* No UART here. */
+		oxford_oxpcie_present = 0;
+		return;
+	}
 
 	/* Setup base address on device */
-	pci_write_config32(OXPCIE_DEVICE, PCI_BASE_ADDRESS_0,
+	pci_write_config32(device, PCI_BASE_ADDRESS_0,
 				CONFIG_OXFORD_OXPCIE_BASE_ADDRESS);
 
 	/* Enable memory on device */
-	reg16 = pci_read_config16(OXPCIE_DEVICE, PCI_COMMAND);
+	reg16 = pci_read_config16(device, PCI_COMMAND);
 	reg16 |= PCI_COMMAND_MEMORY;
-	pci_write_config16(OXPCIE_DEVICE, PCI_COMMAND, reg16);
+	pci_write_config16(device, PCI_COMMAND, reg16);
 
 	/* Now the UART initialization */
 	u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000;
@@ -87,3 +120,4 @@
 	uart8250_mem_init(uart0_base, (4000000 / CONFIG_TTYS0_BAUD));
 }
 
+#endif
diff --git a/src/ec/Kconfig b/src/ec/Kconfig
index 2a36a32..935b40b 100644
--- a/src/ec/Kconfig
+++ b/src/ec/Kconfig
@@ -1,2 +1,3 @@
 source src/ec/acpi/Kconfig
 source src/ec/lenovo/Kconfig
+source src/ec/smsc/Kconfig
diff --git a/src/ec/Makefile.inc b/src/ec/Makefile.inc
index 69d0435..b334c1f 100644
--- a/src/ec/Makefile.inc
+++ b/src/ec/Makefile.inc
@@ -1,2 +1,2 @@
 subdirs-$(CONFIG_EC_ACPI) += acpi
-subdirs-y += lenovo
+subdirs-y += lenovo smsc
diff --git a/src/ec/smsc/Kconfig b/src/ec/smsc/Kconfig
new file mode 100644
index 0000000..afc6e4b
--- /dev/null
+++ b/src/ec/smsc/Kconfig
@@ -0,0 +1 @@
+source src/ec/smsc/mec1308/Kconfig
diff --git a/src/ec/smsc/Makefile.inc b/src/ec/smsc/Makefile.inc
new file mode 100644
index 0000000..3dd9cce
--- /dev/null
+++ b/src/ec/smsc/Makefile.inc
@@ -0,0 +1 @@
+subdirs-$(CONFIG_EC_SMSC_MEC1308) += mec1308
diff --git a/src/ec/smsc/mec1308/Kconfig b/src/ec/smsc/mec1308/Kconfig
new file mode 100644
index 0000000..0a0b04a
--- /dev/null
+++ b/src/ec/smsc/mec1308/Kconfig
@@ -0,0 +1,4 @@
+config EC_SMSC_MEC1308
+	bool
+	help
+	Shared memory mailbox interface to SMSC MEC1308 Embedded Controller.
diff --git a/src/ec/smsc/mec1308/Makefile.inc b/src/ec/smsc/mec1308/Makefile.inc
new file mode 100644
index 0000000..95c6c03
--- /dev/null
+++ b/src/ec/smsc/mec1308/Makefile.inc
@@ -0,0 +1,2 @@
+driver-y += ec.c
+smm-y += ec.c
diff --git a/src/ec/smsc/mec1308/acpi/ac.asl b/src/ec/smsc/mec1308/acpi/ac.asl
new file mode 100644
index 0000000..d14f3a4
--- /dev/null
+++ b/src/ec/smsc/mec1308/acpi/ac.asl
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Scope (EC0)
+
+Device (AC)
+{
+	Name (_HID, "ACPI0003")
+	Name (_PCL, Package () { \_SB })
+
+	Method (_PSR)
+	{
+		Return (ACEX)
+	}
+
+	Method (_STA)
+	{
+		Return (0x0F)
+	}
+}
diff --git a/src/ec/smsc/mec1308/acpi/battery.asl b/src/ec/smsc/mec1308/acpi/battery.asl
new file mode 100644
index 0000000..9b2f93b
--- /dev/null
+++ b/src/ec/smsc/mec1308/acpi/battery.asl
@@ -0,0 +1,196 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define strings in the root scope to
+ * report device-specific battery information to the OS.
+ *
+ *  BATM: Model
+ *  BATS: Serial
+ *  BATV: Vendor
+ */
+
+// Scope (EC0)
+
+Device (BAT0)
+{
+	Name (_HID, EISAID ("PNP0C0A"))
+	Name (_UID, 1)
+	Name (_PCL, Package () { \_SB })
+
+	Name (PBIF, Package () {
+		0x00000001,  // Power Unit: mAh
+		0xFFFFFFFF,  // Design Capacity
+		0xFFFFFFFF,  // Last Full Charge Capacity
+		0x00000001,  // Battery Technology: Rechargeable
+		0xFFFFFFFF,  // Design Voltage
+		0x00000003,  // Design Capacity of Warning
+		0xFFFFFFFF,  // Design Capacity of Low
+		0x00000001,  // Capacity Granularity 1
+		0x00000001,  // Capacity Granularity 2
+		"",          // Model Number
+		"",          // Serial Number
+		"LION",      // Battery Type
+		""           // OEM Information
+	})
+
+	Name (PBST, Package () {
+		0x00000000,  // Battery State
+		0xFFFFFFFF,  // Battery Present Rate
+		0xFFFFFFFF,  // Battery Remaining Capacity
+		0xFFFFFFFF,  // Battery Present Voltage
+	})
+	Name (BSTP, Zero)
+
+	// Workaround for full battery status, enabled by default
+	Name (BFWK, One)
+
+	// Method to enable full battery workaround
+	Method (BFWE)
+	{
+		Store (One, BFWK)
+	}
+
+	// Method to disable full battery workaround
+	Method (BFWD)
+	{
+		Store (Zero, BFWK)
+	}
+
+	// Swap bytes in a word
+	Method (SWAB, 1, NotSerialized)
+	{
+		ShiftRight (Arg0, 8, Local0)
+		ShiftLeft (Arg0, 8, Local1)
+		And (Local1, 0xFF00, Local1)
+		Or (Local0, Local1, Local0)
+		If (LEqual (Local0, 0xFFFF)) {
+			Store (0xFFFFFFFF, Local0)
+		}
+		Return (Local0)
+	}
+
+	Method (_STA, 0, Serialized)
+	{
+		If (BTEX) {
+			Return (0x1F)
+		} Else {
+			Return (0x0F)
+		}
+	}
+
+	Method (_BIF, 0, Serialized)
+	{
+		// Update fields from EC
+		Store (SWAB (BTDA), Index (PBIF, 1))
+		Store (SWAB (BTDF), Index (PBIF, 2))
+		Store (SWAB (BTDV), Index (PBIF, 4))
+		Store (SWAB (BTDL), Index (PBIF, 6))
+
+		// Get battery info from mainboard
+		Store (\BATM, Index (PBIF, 9))
+		Store (\BATS, Index (PBIF, 10))
+		Store (\BATV, Index (PBIF, 12))
+
+		Return (PBIF)
+	}
+
+	Method (_BST, 0, Serialized)
+	{
+		//
+		// 0: BATTERY STATE
+		//
+		// bit 0 = discharging
+		// bit 1 = charging
+		// bit 2 = critical level
+		//
+
+		// Get battery state from EC
+		Store (BTST, Local0)
+		Store (Zero, Local1)
+
+		// Check if AC is present
+		If (ACEX) {
+			// Set only charging/discharging bits
+			And (Local0, 0x03, Local1)
+		} Else {
+			// Always discharging when on battery power
+			Store (0x01, Local1)
+		}
+
+		// Flag if the battery level is critical
+		And (Local0, 0x04, Local4)
+		Or (Local1, Local4, Local1)
+		Store (Local1, Index (PBST, 0))
+
+		// Notify if battery state has changed since last time
+		If (LNotEqual (Local1, BSTP)) {
+			Store (Local1, BSTP)
+			Notify (BAT0, 0x80)
+		}
+
+		//
+		// 1: BATTERY PRESENT RATE
+		//
+
+		Store (SWAB (BTPR), Local1)
+		If (LAnd (LNotEqual (Local1, 0xFFFFFFFF),
+		          LGreaterEqual (Local1, 0x8000))) {
+			Xor (Local1, 0xFFFF, Local1)
+			Increment (Local1)
+		}
+		Store (Local1, Index (PBST, 1))
+
+		//
+		// 2: BATTERY REMAINING CAPACITY
+		//
+		Store (SWAB (BTRA), Local1)
+		If (LAnd (LNotEqual (Local1, 0xFFFFFFFF),
+		          LGreaterEqual (Local1, 0x8000))) {
+			Xor (Local1, 0xFFFF, Local1)
+			Increment (Local1)
+		}
+
+		If (LAnd (BFWK, LAnd (ACEX, LNot (Local0)))) {
+			// On AC power and battery is neither charging
+			// nor discharging.  Linux expects a full battery
+			// to report same capacity as last full charge.
+			// https://bugzilla.kernel.org/show_bug.cgi?id=12632
+			Store (SWAB (BTDF), Local2)
+
+			// See if within ~3% of full
+			ShiftRight (Local2, 5, Local3)
+			If (LAnd (LGreater (Local1, Subtract (Local2, Local3)),
+			          LLess (Local1, Add (Local2, Local3))))
+			{
+				Store (Local2, Local1)
+			}
+		}
+		Store (Local1, Index (PBST, 2))
+
+		//
+		// 3: BATTERY PRESENT VOLTAGE
+		//
+		Store (SWAB (BTVO), Index (PBST, 3))
+
+		Return (PBST)
+	}
+}
diff --git a/src/ec/smsc/mec1308/acpi/ec.asl b/src/ec/smsc/mec1308/acpi/ec.asl
new file mode 100644
index 0000000..f0b77c2
--- /dev/null
+++ b/src/ec/smsc/mec1308/acpi/ec.asl
@@ -0,0 +1,272 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The mainboard must define a PNOT method to handle power
+ * state notifications and Notify CPU device objects to
+ * re-evaluate their _PPC and _CST tables.
+ */
+
+Device (EC0)
+{
+	Name (_HID, EISAID ("PNP0C09"))
+	Name (_UID, 1)
+	Name (_GPE, EC_GPE)	// GPE for Runtime SCI
+
+	OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x80),
+		BTEX, 1,		// Battery Exists
+		, 1,
+		ACEX, 1,		// AC Exists
+		, 5,
+		Offset (0x83),
+		LIDS, 1,		// Lid Switch State
+		, 7,
+		BTST, 8,		// Battery State
+		Offset (0xA2),
+		BTRA, 16,		// Battery Remaining Capacity
+		BTPR, 16,		// Battery Present Rate
+		BTVO, 16,		// Battery Present Voltage
+		Offset (0xB0),
+		BTDA, 16,		// Battery Design Capacity
+		BTDF, 16,		// Battery Last Full Charge Capacity
+		BTDV, 16,		// Battery Design Voltage
+		BTDL, 16,		// Battery Design Low
+		Offset (0xC0),
+		CPUT, 8,		// CPU Temperature
+		Offset (0xCA),
+		FSL0, 1,		// Fan Speed Level 0
+		FSL1, 1,		// Fan Speed Level 1
+		FSL2, 1,		// Fan Speed Level 2
+		FSL3, 1,		// Fan Speed Level 3
+		FSL4, 1,		// Fan Speed Level 4
+		, 2,
+		FCOS, 1,		// Fan Speed OS Control
+	}
+
+	Method (_CRS, 0, NotSerialized)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 0, 1)
+			IO (Decode16, 0x66, 0x66, 0, 1)
+		})
+		Return (ECMD)
+	}
+
+	Method (_REG, 2, NotSerialized)
+	{
+		// Initialize AC power state
+		Store (ACEX, \PWRS)
+
+		// Initialize LID switch state
+		Store (LIDS, \LIDS)
+
+		// Enable OS control of fan speed
+		Store (One, FCOS)
+
+		// Force a read of CPU temperature
+		Store (CPUT, Local0)
+	}
+
+	PowerResource (FNP0, 0, 0)
+	{
+		Method (_STA) { Return (FSL0) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL0)
+				Store (0, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL0)
+				Store (1, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP1, 0, 0)
+	{
+		Method (_STA) { Return (FSL1) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL1)
+				Store (1, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL1)
+				Store (2, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP2, 0, 0)
+	{
+		Method (_STA) { Return (FSL2) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL2)
+				Store (2, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL2)
+				Store (3, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP3, 0, 0)
+	{
+		Method (_STA) { Return (FSL3) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL3)
+				Store (3, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL3)
+				Store (4, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	PowerResource (FNP4, 0, 0)
+	{
+		Method (_STA) { Return (FSL4) }
+		Method (_ON)  {
+			If (FCOS) {
+				Store (One, FSL4)
+				Store (4, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+		Method (_OFF) {
+			If (FCOS) {
+				Store (Zero, FSL4)
+				Store (5, \FLVL)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+	}
+
+	Device (FAN0)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 0)
+		Name (_PR0, Package () { FNP0 })
+	}
+
+	Device (FAN1)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 1)
+		Name (_PR0, Package () { FNP1 })
+	}
+
+	Device (FAN2)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 2)
+		Name (_PR0, Package () { FNP2 })
+	}
+
+	Device (FAN3)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 3)
+		Name (_PR0, Package () { FNP3 })
+	}
+
+	Device (FAN4)
+	{
+		Name (_HID, EISAID ("PNP0C0B"))
+		Name (_UID, 4)
+		Name (_PR0, Package () { FNP4 })
+	}
+
+	// AC Power Connected
+	Method (_Q51, 0, NotSerialized)
+	{
+		Store (One, \PWRS)
+		Notify (AC, 0x80)
+		\PNOT ()
+	}
+
+	// AC Power Removed
+	Method (_Q52, 0, NotSerialized)
+	{
+		Store (Zero, \PWRS)
+		Notify (AC, 0x80)
+		\PNOT ()
+	}
+
+	// Battery State Change
+	Method (_Q53, 0, NotSerialized)
+	{
+		Notify (BAT0, 0x80)
+		Notify (BAT0, 0x81)
+	}
+
+	// Battery State Change
+	Method (_Q54, 0, NotSerialized)
+	{
+		Notify (BAT0, 0x80)
+		Notify (BAT0, 0x81)
+	}
+
+	// Power State Change
+	Method (_Q55, 0, NotSerialized)
+	{
+		\PNOT ()
+	}
+
+	// Lid Switch Event
+	Method (_Q5E, 0, NotSerialized)
+	{
+		Store (LIDS, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	// Lid Switch Event
+	Method (_Q5F, 0, NotSerialized)
+	{
+		Store (LIDS, \LIDS)
+		Notify (\_SB.LID0, 0x80)
+	}
+
+	#include "ac.asl"
+	#include "battery.asl"
+}
diff --git a/src/ec/smsc/mec1308/chip.h b/src/ec/smsc/mec1308/chip.h
new file mode 100644
index 0000000..3a8eae8
--- /dev/null
+++ b/src/ec/smsc/mec1308/chip.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _EC_SMSC_MEC1308_CHIP_H
+#define _EC_SMSC_MEC1308_CHIP_H
+
+struct ec_smsc_mec1308_config
+{
+	u16 mailbox_port;
+};
+
+struct chip_operations;
+extern struct chip_operations ec_smsc_mec1308_ops;
+
+#endif /* _EC_SMSC_MEC1308_CHIP_H */
diff --git a/src/ec/smsc/mec1308/ec.c b/src/ec/smsc/mec1308/ec.c
new file mode 100644
index 0000000..bfd3c14
--- /dev/null
+++ b/src/ec/smsc/mec1308/ec.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "ec.h"
+#include "chip.h"
+
+static u16 ec_cmd_reg = 0;
+static u16 ec_data_reg = 0;
+
+static inline u8 __ec_read(u8 addr)
+{
+	outb(addr, ec_cmd_reg);
+	return inb(ec_data_reg);
+}
+
+static inline void __ec_write(u8 addr, u8 data)
+{
+	outb(addr, ec_cmd_reg);
+	outb(data, ec_data_reg);
+}
+
+static int ec_ready(void)
+{
+	u16 timeout = EC_TIMEOUT;
+
+	if (!ec_cmd_reg || !ec_data_reg) {
+		printk(BIOS_DEBUG, "Invalid ports: cmd=0x%x data=0x%x\n",
+		       ec_cmd_reg, ec_data_reg);
+		return -1;
+	}
+
+	while (__ec_read(EC_MAILBOX_COMMAND) != 0 && --timeout) {
+		udelay(10);
+		if ((timeout & 0xff) == 0)
+			printk(BIOS_SPEW, ".");
+	}
+	if (!timeout) {
+		printk(BIOS_DEBUG, "Timeout waiting for EC to be ready.\n");
+		return -1;
+	}
+	return 0;
+}
+
+int send_ec_command(u8 command)
+{
+	if (ec_ready() < 0)
+		return -1;
+	__ec_write(EC_MAILBOX_COMMAND, command);
+	return ec_ready();
+}
+
+int send_ec_command_data(u8 command, u8 data)
+{
+	if (ec_ready() < 0)
+		return -1;
+	__ec_write(EC_MAILBOX_DATA, data);
+	__ec_write(EC_MAILBOX_COMMAND, command);
+	return ec_ready();
+}
+
+u8 read_ec_command_byte(u8 command)
+{
+	send_ec_command(command);
+	return __ec_read(EC_MAILBOX_DATA);
+}
+
+u8 ec_read(u8 addr)
+{
+	if (send_ec_command_data(EC_RAM_READ, addr) < 0)
+		return 0;
+	return __ec_read(EC_MAILBOX_DATA);
+}
+
+int ec_write(u8 addr, u8 data)
+{
+	if (ec_ready() < 0)
+		return -1;
+	__ec_write(EC_MAILBOX_DATA, addr);
+	__ec_write(EC_MAILBOX_DATA_H, data);
+	__ec_write(EC_MAILBOX_COMMAND, EC_RAM_WRITE);
+	return ec_ready();
+}
+
+void ec_set_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) | (1 << bit));
+}
+
+void ec_clr_bit(u8 addr, u8 bit)
+{
+	ec_write(addr, ec_read(addr) &  ~(1 << bit));
+}
+
+void ec_set_ports(u16 cmd_reg, u16 data_reg)
+{
+	ec_cmd_reg = cmd_reg;
+	ec_data_reg = data_reg;
+}
+
+static void mec1308_enable(device_t dev)
+{
+	struct ec_smsc_mec1308_config *conf = dev->chip_info;
+
+	if (conf->mailbox_port) {
+		ec_cmd_reg = conf->mailbox_port;
+		ec_data_reg = conf->mailbox_port + 1;
+	}
+}
+
+struct chip_operations ec_smsc_mec1308_ops = {
+	CHIP_NAME("SMSC MEC1308 EC Mailbox Interface")
+	.enable_dev = mec1308_enable
+};
diff --git a/src/ec/smsc/mec1308/ec.h b/src/ec/smsc/mec1308/ec.h
new file mode 100644
index 0000000..07bfc4f
--- /dev/null
+++ b/src/ec/smsc/mec1308/ec.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ * Mailbox EC communication interface for SMSC MEC1308 Embedded Controller.
+ */
+
+#ifndef _EC_SMSC_MEC1308_EC_H
+#define _EC_SMSC_MEC1308_EC_H
+
+#define EC_TIMEOUT           0xfff
+#define EC_MAILBOX_COMMAND   0x82  // Send a command
+#define EC_MAILBOX_DATA      0x84  // Send data with a command
+#define EC_MAILBOX_DATA_H    0x85  // Send data with a command
+#define EC_RAM_READ          0x88  // Read from RAM
+#define EC_RAM_WRITE         0x89  // Write to RAM
+
+int send_ec_command(u8 command);
+int send_ec_command_data(u8 command, u8 data);
+u8 read_ec_command_byte(u8 command);
+u8 ec_read(u8 addr);
+int ec_write(u8 addr, u8 data);
+void ec_set_bit(u8 addr, u8 bit);
+void ec_clr_bit(u8 addr, u8 bit);
+void ec_set_ports(u16 cmd_reg, u16 data_reg);
+
+#endif /* _EC_SMSC_MEC1308_EC_H */
diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h
index 983b03f..bf59271 100644
--- a/src/include/boot/coreboot_tables.h
+++ b/src/include/boot/coreboot_tables.h
@@ -146,7 +146,10 @@
 struct lb_serial {
 	uint32_t tag;
 	uint32_t size;
-	uint16_t ioport;
+#define LB_SERIAL_TYPE_IO_MAPPED     1
+#define LB_SERIAL_TYPE_MEMORY_MAPPED 2
+	uint32_t type;
+	uint32_t baseaddr;
 	uint32_t baud;
 };
 
@@ -192,6 +195,59 @@
 	uint8_t reserved_mask_size;
 };
 
+#define LB_TAG_GPIO	0x0013
+
+struct lb_gpio {
+	uint32_t port;
+	uint32_t polarity;
+	uint32_t value;
+#define GPIO_MAX_NAME_LENGTH 16
+        uint8_t name[GPIO_MAX_NAME_LENGTH];
+};
+
+struct lb_gpios {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t count;
+	struct lb_gpio gpios[0];
+};
+
+#define LB_TAG_FDT	0x0014
+struct lb_fdt {
+	uint32_t tag;
+	uint32_t size;		     /* size of the entire entry */
+	/* the actual FDT gets placed here */
+};
+
+#define LB_TAG_VDAT	0x0015
+struct lb_vdat {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*vdat_addr;
+	uint32_t vdat_size;
+};
+
+#define LB_TAG_TIMESTAMPS	0x0016
+#define LB_TAG_CBMEM_CONSOLE	0x0017
+#define LB_TAG_MRC_CACHE	0x0018
+struct lb_cbmem_ref {
+	uint32_t tag;
+	uint32_t size;
+
+	void	*cbmem_addr;
+};
+
+#define LB_TAG_VBNV		0x0019
+struct lb_vbnv {
+	uint32_t tag;
+	uint32_t size;
+
+	uint32_t vbnv_start;
+	uint32_t vbnv_size;
+};
+
 /* The following structures are for the cmos definitions table */
 #define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */
diff --git a/src/include/cbfs.h b/src/include/cbfs.h
index c1c1e33..d517fe8 100644
--- a/src/include/cbfs.h
+++ b/src/include/cbfs.h
@@ -49,6 +49,7 @@
 #ifndef _CBFS_H_
 #define _CBFS_H_
 
+#include <arch/byteorder.h>
 #include <boot/coreboot_tables.h>
 /** These are standard values for the known compression
     alogrithms that coreboot knows about for stages and
@@ -72,17 +73,18 @@
 #define CBFS_TYPE_MBI        0x52
 #define CBFS_TYPE_MICROCODE  0x53
 #define CBFS_COMPONENT_CMOS_DEFAULT 0xaa
+#define CBFS_TYPE_FDT	     0xac
 #define CBFS_COMPONENT_CMOS_LAYOUT 0x01aa
 
 
 /** this is the master cbfs header - it need to be
     located somewhere in the bootblock.  Where it
     actually lives is up to coreboot. A pointer to
-    this header will live at 0xFFFFFFFc, so we can
+    this header will live at 0xfffffffc, so we can
     easily find it. */
 
-#define CBFS_HEADER_MAGIC  0x4F524243
-#define CBFS_HEADPTR_ADDR 0xFFFFFFFc
+#define CBFS_HEADER_MAGIC  0x4f524243
+#define CBFS_HEADPTR_ADDR 0xfffffffc
 #define VERSION1 0x31313131
 
 struct cbfs_header {
@@ -152,11 +154,11 @@
 	struct cbfs_payload_segment segments;
 };
 
-#define PAYLOAD_SEGMENT_CODE   0x45444F43
+#define PAYLOAD_SEGMENT_CODE   0x45444f43
 #define PAYLOAD_SEGMENT_DATA   0x41544144
 #define PAYLOAD_SEGMENT_BSS    0x20535342
 #define PAYLOAD_SEGMENT_PARAMS 0x41524150
-#define PAYLOAD_SEGMENT_ENTRY  0x52544E45
+#define PAYLOAD_SEGMENT_ENTRY  0x52544e45
 
 struct cbfs_optionrom {
 	u32 compression;
@@ -169,10 +171,12 @@
 void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name);
 void * cbfs_load_stage(const char *name);
 int cbfs_execute_stage(const char *name);
-void * cbfs_get_file(const char *name);
 void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest);
 int run_address(void *f);
 struct cbfs_file *cbfs_find(const char *name);
 void *cbfs_find_file(const char *name, int type);
+struct cbfs_header *get_cbfs_header(void);
+void *get_cbfs_base(void);
+u32 get_cbfs_size(void);
 #endif
 
diff --git a/src/include/cbmem.h b/src/include/cbmem.h
index d9ec93c..c55a7ca 100644
--- a/src/include/cbmem.h
+++ b/src/include/cbmem.h
@@ -20,13 +20,22 @@
 #ifndef _CBMEM_H_
 #define _CBMEM_H_
 
-/* Reserve 64k for ACPI and other tables */
-#define HIGH_MEMORY_DEF_SIZE	( 64 * 1024 )
-extern uint64_t high_tables_base, high_tables_size;
+/* Reserve 128k for ACPI and other tables */
+#if CONFIG_CONSOLE_CBMEM
+#define HIGH_MEMORY_DEF_SIZE	( 256 * 1024 )
+#else
+#define HIGH_MEMORY_DEF_SIZE	( 128 * 1024 )
+#endif
 
 #if CONFIG_HAVE_ACPI_RESUME
 #define HIGH_MEMORY_SIZE	((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_DEF_SIZE)
 #define HIGH_MEMORY_SAVE	( HIGH_MEMORY_SIZE - HIGH_MEMORY_DEF_SIZE )
+
+/* Delegation of resume backup memory so we don't have to
+ * (slowly) handle backing up OS memory in romstage.c
+ */
+#define CBMEM_BOOT_MODE		0x610
+#define CBMEM_RESUME_BACKUP	0x614
 #else
 #define HIGH_MEMORY_SIZE	HIGH_MEMORY_DEF_SIZE
 #endif
@@ -38,9 +47,18 @@
 #define CBMEM_ID_PIRQ		0x49525154
 #define CBMEM_ID_MPTABLE	0x534d5054
 #define CBMEM_ID_RESUME		0x5245534d
+#define CBMEM_ID_SMBIOS         0x534d4254
+#define CBMEM_ID_TIMESTAMP	0x54494d45
+#define CBMEM_ID_MRCDATA	0x4d524344
+#define CBMEM_ID_CONSOLE	0x434f4e53
 #define CBMEM_ID_NONE		0x00000000
 
-void cbmem_initialize(void);
+#ifndef __ASSEMBLER__
+#ifndef __PRE_RAM__
+extern uint64_t high_tables_base, high_tables_size;
+#endif
+
+int cbmem_initialize(void);
 
 void cbmem_init(u64 baseaddr, u64 size);
 int cbmem_reinit(u64 baseaddr);
@@ -55,3 +73,4 @@
 void set_cbmem_toc(struct cbmem_entry *);
 #endif
 #endif
+#endif
diff --git a/src/cpu/x86/mmx_disable.inc b/src/include/console/cbmem_console.h
similarity index 68%
copy from src/cpu/x86/mmx_disable.inc
copy to src/include/console/cbmem_console.h
index 1a4e70f..37ea4d8 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/include/console/cbmem_console.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,13 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
+#ifndef _CONSOLE_CBMEM_CONSOLE_H_
+#define _CONSOLE_CBMEM_CONSOLE_H_
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+void cbmemc_init(void);
+void cbmemc_reinit(void);
+void cbmemc_tx_byte(unsigned char data);
 
+#endif
diff --git a/src/include/console/console.h b/src/include/console/console.h
index 8283f66..3a8f47a 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -24,15 +24,24 @@
 #include <console/loglevel.h>
 #include <console/post_codes.h>
 
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
+#include <uart8250.h>
+#endif
+#ifdef CONFIG_USBDEBUG
+#include <usbdebug.h>
+#endif
+#if CONFIG_CONSOLE_NE2K
+#include <console/ne2k.h>
+#endif
+#if CONFIG_CONSOLE_CBMEM
+#include <console/cbmem_console.h>
+#endif
+
 #ifndef __PRE_RAM__
 void console_tx_byte(unsigned char byte);
 void console_tx_flush(void);
 unsigned char console_rx_byte(void);
 int console_tst_byte(void);
-#if CONFIG_USBDEBUG
-#include <usbdebug.h>
-#endif
-
 struct console_driver {
 	void (*init)(void);
 	void (*tx_byte)(unsigned char byte);
@@ -55,9 +64,6 @@
  * we could use the same code on all architectures.
  */
 #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-#if CONFIG_CONSOLE_SERIAL8250
-#include <uart8250.h>
-#endif
 #endif
 
 #ifndef __ROMCC__
diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h
new file mode 100644
index 0000000..b60c8cf
--- /dev/null
+++ b/src/include/cpu/intel/turbo.h
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _CPU_INTEL_TURBO_H
+#define _CPU_INTEL_TURBO_H
+
+#define CPUID_LEAF_PM		6
+#define PM_CAP_TURBO_MODE	(1 << 1)
+
+#define MSR_IA32_MISC_ENABLES	0x1a0
+#define H_MISC_DISABLE_TURBO	(1 << 6)
+
+enum {
+	TURBO_UNKNOWN,
+	TURBO_UNAVAILABLE,
+	TURBO_DISABLED,
+	TURBO_ENABLED,
+};
+
+/* Return current turbo state */
+int get_turbo_state(void);
+
+/* Enable turbo */
+void enable_turbo(void);
+
+#endif
diff --git a/src/cpu/x86/mmx_disable.inc b/src/include/cpu/x86/car.h
similarity index 61%
copy from src/cpu/x86/mmx_disable.inc
copy to src/include/cpu/x86/car.h
index 1a4e70f..2d2af03 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/include/cpu/x86/car.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,18 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef CPU_X86_CAR_H
+#define CPU_X86_CAR_H
 
+#ifdef __PRE_RAM__
+#define CAR_GLOBAL __attribute__((section(".car.global_data,\"w\",@nobits#")))
+#define CAR_CBMEM __attribute__((section(".car.cbmem_console,\"w\",@nobits#")))
+#else
+#define CAR_GLOBAL
+#define CAR_CBMEM
+#endif
+
+#endif
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 8b44a6c..2229a53 100644
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -1,9 +1,11 @@
 #ifndef CPU_X86_LAPIC_H
 #define CPU_X86_LAPIC_H
 
+#ifndef __ROMCC__
 #include <cpu/x86/lapic_def.h>
 #include <cpu/x86/msr.h>
 #include <arch/hlt.h>
+#include <delay.h>
 
 /* See if I need to initialize the local apic */
 #if CONFIG_SMP || CONFIG_IOAPIC
@@ -27,8 +29,6 @@
 	do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
 }
 
-
-
 static inline void enable_lapic(void)
 {
 
@@ -132,7 +132,7 @@
 	lapic_write_around(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
 	timeout = 0;
 	do {
-#if 0
+#if 1
 		udelay(100);
 #endif
 		status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
@@ -156,4 +156,7 @@
 
 #endif /* !__PRE_RAM__ */
 
+int boot_cpu(void);
+#endif
+
 #endif /* CPU_X86_LAPIC_H */
diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 44a2223..1a00cb0 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -17,6 +17,9 @@
 #define MTRRdefTypeEn		(1 << 11)
 #define MTRRdefTypeFixEn	(1 << 10)
 
+#define SMRRphysBase_MSR 0x1f2
+#define SMRRphysMask_MSR 0x1f3
+
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
@@ -35,6 +38,8 @@
 #define MTRRfix4K_F0000_MSR 0x26e
 #define MTRRfix4K_F8000_MSR 0x26f
 
+#define NoEvictMod_MSR 0x2e0
+
 #if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
 #include <device/device.h>
 void enable_fixed_mtrr(void);
@@ -67,7 +72,7 @@
 # error "CONFIG_RAMTOP must be a power of 2"
 #endif
 
-#if !defined (__ASSEMBLER__)
+#if !defined (__ASSEMBLER__) && !defined(__PRE_RAM__)
 #if defined(CONFIG_XIP_ROM_SIZE)
 # if CONFIG_TINY_BOOTBLOCK
    extern unsigned long AUTO_XIP_ROM_BASE;
diff --git a/src/include/cpu/x86/post_code.h b/src/include/cpu/x86/post_code.h
index 20b87c6..729f3c6 100644
--- a/src/include/cpu/x86/post_code.h
+++ b/src/include/cpu/x86/post_code.h
@@ -1,7 +1,6 @@
-
 #include <console/post_codes.h>
 
-#define post_code(value)        \
-	movb    $value, %al;    \
+#define post_code(value)     \
+	movb    $value, %al; \
 	outb    %al, $0x80
 
diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h
index ad0984ea..9e5ddc1 100644
--- a/src/include/cpu/x86/smm.h
+++ b/src/include/cpu/x86/smm.h
@@ -263,4 +263,5 @@
 void __attribute__((weak)) southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
 
 void __attribute__((weak)) mainboard_smi_gpi(u16 gpi_sts);
-
+void __attribute__((weak)) mainboard_smi_sleep(u8 slp_typ);
+void __attribute__((weak)) mainboard_smi_apmc(u8 apmc);
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 42b68f6..0aea1d6 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -16,6 +16,9 @@
 struct chip_operations {
 	void (*enable_dev)(struct device *dev);
 	const char *name;
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
+#endif
 };
 
 #define CHIP_NAME(X) .name = X,
@@ -31,6 +34,9 @@
 	void (*enable)(device_t dev);
 	void (*set_link)(device_t dev, unsigned int link);
 	void (*reset_bus)(struct bus *bus);
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
+#endif
 	const struct pci_operations *ops_pci;
 	const struct smbus_bus_operations *ops_smbus_bus;
 	const struct pci_bus_operations *ops_pci_bus;
@@ -126,6 +132,8 @@
 device_t dev_find_class (unsigned int class, device_t from);
 device_t dev_find_slot (unsigned int bus, unsigned int devfn);
 device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
+device_t dev_find_lapic(unsigned apic_id);
+int dev_count_cpu(void);
 
 /* Debug functions */
 void print_resource_tree(struct device * root, int debug_level,
diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h
index a5aa3a1..58a7321 100644
--- a/src/include/device/pci_def.h
+++ b/src/include/device/pci_def.h
@@ -371,8 +371,15 @@
 #define  PCI_EXP_DEVSTA_AUXPD	0x10	/* AUX Power Detected */
 #define  PCI_EXP_DEVSTA_TRPND	0x20	/* Transactions Pending */
 #define PCI_EXP_LNKCAP		12	/* Link Capabilities */
+#define  PCI_EXP_LNKCAP_ASPMS	0xc00	/* ASPM Support */
+#define  PCI_EXP_LNKCAP_L0SEL	0x7000	/* L0s Exit Latency */
+#define  PCI_EXP_LNKCAP_L1EL	0x38000	/* L1 Exit Latency */
 #define PCI_EXP_LNKCTL		16	/* Link Control */
+#define  PCI_EXP_LNKCTL_RL	0x20	/* Retrain Link */
+#define  PCI_EXP_LNKCTL_CCC	0x40	/* Common Clock COnfiguration */
 #define PCI_EXP_LNKSTA		18	/* Link Status */
+#define  PCI_EXP_LNKSTA_LT	0x800	/* Link Training */
+#define  PCI_EXP_LNKSTA_SLC	0x1000	/* Slot Clock Configuration */
 #define PCI_EXP_SLTCAP		20	/* Slot Capabilities */
 #define PCI_EXP_SLTCTL		24	/* Slot Control */
 #define PCI_EXP_SLTSTA		26	/* Slot Status */
diff --git a/src/include/device/pci_rom.h b/src/include/device/pci_rom.h
index f268341..fe77276 100644
--- a/src/include/device/pci_rom.h
+++ b/src/include/device/pci_rom.h
@@ -35,5 +35,6 @@
 
 struct rom_header *pci_rom_probe(struct device *dev);
 struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header);
+u32 __attribute__((weak)) map_oprom_vendev(u32 vendev);
 
 #endif
diff --git a/src/include/device/pciexp.h b/src/include/device/pciexp.h
index 409f211..87a5002 100644
--- a/src/include/device/pciexp.h
+++ b/src/include/device/pciexp.h
@@ -2,6 +2,13 @@
 #define DEVICE_PCIEXP_H
 /* (c) 2005 Linux Networx GPL see COPYING for details */
 
+enum aspm_type {
+	PCIE_ASPM_NONE = 0,
+	PCIE_ASPM_L0S  = 1,
+	PCIE_ASPM_L1   = 2,
+	PCIE_ASPM_BOTH = 3,
+};
+
 unsigned int pciexp_scan_bus(struct bus *bus, unsigned int min_devfn,
 			     unsigned int max_devfn, unsigned int max);
 unsigned int pciexp_scan_bridge(device_t dev, unsigned int max);
diff --git a/src/include/fdt/fdt.h b/src/include/fdt/fdt.h
new file mode 100644
index 0000000..14da287
--- /dev/null
+++ b/src/include/fdt/fdt.h
@@ -0,0 +1,64 @@
+#ifndef _FDT_H
+#define _FDT_H
+
+#include <types.h>
+#include <string.h>
+#ifndef __ASSEMBLY__
+
+struct fdt_header {
+	uint32_t magic;			 /* magic word FDT_MAGIC */
+	uint32_t totalsize;		 /* total size of DT block */
+	uint32_t off_dt_struct;		 /* offset to structure */
+	uint32_t off_dt_strings;	 /* offset to strings */
+	uint32_t off_mem_rsvmap;	 /* offset to memory reserve map */
+	uint32_t version;		 /* format version */
+	uint32_t last_comp_version;	 /* last compatible version */
+
+	/* version 2 fields below */
+	uint32_t boot_cpuid_phys;	 /* Which physical CPU id we're
+					    booting on */
+	/* version 3 fields below */
+	uint32_t size_dt_strings;	 /* size of the strings block */
+
+	/* version 17 fields below */
+	uint32_t size_dt_struct;	 /* size of the structure block */
+};
+
+struct fdt_reserve_entry {
+	uint64_t address;
+	uint64_t size;
+};
+
+struct fdt_node_header {
+	uint32_t tag;
+	char name[0];
+};
+
+struct fdt_property {
+	uint32_t tag;
+	uint32_t len;
+	uint32_t nameoff;
+	char data[0];
+};
+
+#endif /* !__ASSEMBLY */
+
+#define FDT_MAGIC	0xd00dfeed	/* 4: version, 4: total size */
+#define FDT_TAGSIZE	sizeof(uint32_t)
+
+#define FDT_BEGIN_NODE	0x1		/* Start node: full name */
+#define FDT_END_NODE	0x2		/* End node */
+#define FDT_PROP	0x3		/* Property: name off,
+					   size, content */
+#define FDT_NOP		0x4		/* nop */
+#define FDT_END		0x9
+
+#define FDT_V1_SIZE	(7*sizeof(uint32_t))
+#define FDT_V2_SIZE	(FDT_V1_SIZE + sizeof(uint32_t))
+#define FDT_V3_SIZE	(FDT_V2_SIZE + sizeof(uint32_t))
+#define FDT_V16_SIZE	FDT_V3_SIZE
+#define FDT_V17_SIZE	(FDT_V16_SIZE + sizeof(uint32_t))
+
+/* adding a ramdisk needs 0x44 bytes in version 2008.10 */
+#define FDT_RAMDISK_OVERHEAD	0x80
+#endif /* _FDT_H */
diff --git a/src/include/fdt/fdt_support.h b/src/include/fdt/fdt_support.h
new file mode 100644
index 0000000..863024f
--- /dev/null
+++ b/src/include/fdt/fdt_support.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2007
+ * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __FDT_SUPPORT_H
+#define __FDT_SUPPORT_H
+
+#ifdef CONFIG_OF_LIBFDT
+
+#include <fdt.h>
+
+u32 fdt_getprop_u32_default(void *fdt, const char *path, const char *prop,
+				const u32 dflt);
+int fdt_chosen(void *fdt, int force);
+int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
+void do_fixup_by_path(void *fdt, const char *path, const char *prop,
+		      const void *val, int len, int create);
+void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
+			  u32 val, int create);
+void do_fixup_by_prop(void *fdt,
+		      const char *pname, const void *pval, int plen,
+		      const char *prop, const void *val, int len,
+		      int create);
+void do_fixup_by_prop_u32(void *fdt,
+			  const char *pname, const void *pval, int plen,
+			  const char *prop, u32 val, int create);
+void do_fixup_by_compat(void *fdt, const char *compat,
+			const char *prop, const void *val, int len, int create);
+void do_fixup_by_compat_u32(void *fdt, const char *compat,
+			    const char *prop, u32 val, int create);
+int fdt_fixup_memory(void *blob, u64 start, u64 size);
+int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks);
+void fdt_fixup_ethernet(void *fdt);
+int fdt_find_and_setprop(void *fdt, const char *node, const char *prop,
+			 const void *val, int len, int create);
+void fdt_fixup_qe_firmware(void *fdt);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+void fdt_fixup_dr_usb(void *blob, bd_t *bd);
+#else
+static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
+#endif /* CONFIG_HAS_FSL_DR_USB */
+
+#if defined(CONFIG_SYS_FSL_SEC_COMPAT)
+void fdt_fixup_crypto_node(void *blob, int sec_rev);
+#else
+static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
+#endif
+
+#ifdef CONFIG_PCI
+#include <pci.h>
+int fdt_pci_dma_ranges(void *blob, int phb_off, struct pci_controller *hose);
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+void ft_board_setup(void *blob, bd_t *bd);
+void ft_cpu_setup(void *blob, bd_t *bd);
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+
+void set_working_fdt_addr(void *addr);
+int fdt_resize(void *blob);
+int fdt_increase_size(void *fdt, int add_len);
+
+int fdt_fixup_nor_flash_size(void *blob);
+
+void fdt_fixup_mtdparts(void *fdt, void *node_info, int node_info_size);
+void fdt_del_node_and_alias(void *blob, const char *alias);
+u64 fdt_translate_address(void *blob, int node_offset, const u32 *in_addr);
+int fdt_node_offset_by_compat_reg(void *blob, const char *compat,
+					phys_addr_t compat_off);
+int fdt_alloc_phandle(void *blob);
+int fdt_create_phandle(void *fdt, int nodeoffset, uint32_t phandle);
+int fdt_add_edid(void *blob, const char *compat, unsigned char *buf);
+
+int fdt_verify_alias_address(void *fdt, int anode, const char *alias,
+			      u64 addr);
+u64 fdt_get_base_address(void *fdt, int node);
+
+#endif /* ifdef CONFIG_OF_LIBFDT */
+#endif /* ifndef __FDT_SUPPORT_H */
diff --git a/src/include/fdt/libfdt.h b/src/include/fdt/libfdt.h
new file mode 100644
index 0000000..993a654
--- /dev/null
+++ b/src/include/fdt/libfdt.h
@@ -0,0 +1,1248 @@
+#ifndef _LIBFDT_H
+#define _LIBFDT_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <libfdt_env.h>
+#include <fdt.h>
+
+#define FDT_FIRST_SUPPORTED_VERSION	0x10
+#define FDT_LAST_SUPPORTED_VERSION	0x11
+
+/* Error codes: informative error codes */
+#define FDT_ERR_NOTFOUND	1
+	/* FDT_ERR_NOTFOUND: The requested node or property does not exist */
+#define FDT_ERR_EXISTS		2
+	/* FDT_ERR_EXISTS: Attemped to create a node or property which
+	 * already exists */
+#define FDT_ERR_NOSPACE		3
+	/* FDT_ERR_NOSPACE: Operation needed to expand the device
+	 * tree, but its buffer did not have sufficient space to
+	 * contain the expanded tree. Use fdt_open_into() to move the
+	 * device tree to a buffer with more space. */
+
+/* Error codes: codes for bad parameters */
+#define FDT_ERR_BADOFFSET	4
+	/* FDT_ERR_BADOFFSET: Function was passed a structure block
+	 * offset which is out-of-bounds, or which points to an
+	 * unsuitable part of the structure for the operation. */
+#define FDT_ERR_BADPATH		5
+	/* FDT_ERR_BADPATH: Function was passed a badly formatted path
+	 * (e.g. missing a leading / for a function which requires an
+	 * absolute path) */
+#define FDT_ERR_BADPHANDLE	6
+	/* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle
+	 * value.  phandle values of 0 and -1 are not permitted. */
+#define FDT_ERR_BADSTATE	7
+	/* FDT_ERR_BADSTATE: Function was passed an incomplete device
+	 * tree created by the sequential-write functions, which is
+	 * not sufficiently complete for the requested operation. */
+
+/* Error codes: codes for bad device tree blobs */
+#define FDT_ERR_TRUNCATED	8
+	/* FDT_ERR_TRUNCATED: Structure block of the given device tree
+	 * ends without an FDT_END tag. */
+#define FDT_ERR_BADMAGIC	9
+	/* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
+	 * device tree at all - it is missing the flattened device
+	 * tree magic number. */
+#define FDT_ERR_BADVERSION	10
+	/* FDT_ERR_BADVERSION: Given device tree has a version which
+	 * can't be handled by the requested operation.  For
+	 * read-write functions, this may mean that fdt_open_into() is
+	 * required to convert the tree to the expected version. */
+#define FDT_ERR_BADSTRUCTURE	11
+	/* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
+	 * structure block or other serious error (e.g. misnested
+	 * nodes, or subnodes preceding properties). */
+#define FDT_ERR_BADLAYOUT	12
+	/* FDT_ERR_BADLAYOUT: For read-write functions, the given
+	 * device tree has it's sub-blocks in an order that the
+	 * function can't handle (memory reserve map, then structure,
+	 * then strings).  Use fdt_open_into() to reorganize the tree
+	 * into a form suitable for the read-write operations. */
+
+/* "Can't happen" error indicating a bug in libfdt */
+#define FDT_ERR_INTERNAL	13
+	/* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
+	 * Should never be returned, if it is, it indicates a bug in
+	 * libfdt itself. */
+
+#define FDT_ERR_MAX		13
+
+/**********************************************************************/
+/* Low-level functions (you probably don't need these)                */
+/**********************************************************************/
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
+static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
+{
+	return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
+}
+
+uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
+
+/**********************************************************************/
+/* Traversal functions                                                */
+/**********************************************************************/
+
+int fdt_next_node(const void *fdt, int offset, int *depth);
+
+/**********************************************************************/
+/* General functions                                                  */
+/**********************************************************************/
+
+#define fdt_get_header(fdt, field) \
+	(fdt32_to_cpu(((const struct fdt_header *)(fdt))->field))
+#define fdt_magic(fdt)			(fdt_get_header(fdt, magic))
+#define fdt_totalsize(fdt)		(fdt_get_header(fdt, totalsize))
+#define fdt_off_dt_struct(fdt)		(fdt_get_header(fdt, off_dt_struct))
+#define fdt_off_dt_strings(fdt)		(fdt_get_header(fdt, off_dt_strings))
+#define fdt_off_mem_rsvmap(fdt)		(fdt_get_header(fdt, off_mem_rsvmap))
+#define fdt_version(fdt)		(fdt_get_header(fdt, version))
+#define fdt_last_comp_version(fdt)	(fdt_get_header(fdt, last_comp_version))
+#define fdt_boot_cpuid_phys(fdt)	(fdt_get_header(fdt, boot_cpuid_phys))
+#define fdt_size_dt_strings(fdt)	(fdt_get_header(fdt, size_dt_strings))
+#define fdt_size_dt_struct(fdt)		(fdt_get_header(fdt, size_dt_struct))
+
+#define __fdt_set_hdr(name) \
+	static inline void fdt_set_##name(void *fdt, uint32_t val) \
+	{ \
+		struct fdt_header *fdth = (struct fdt_header*)fdt; \
+		fdth->name = cpu_to_fdt32(val); \
+	}
+__fdt_set_hdr(magic);
+__fdt_set_hdr(totalsize);
+__fdt_set_hdr(off_dt_struct);
+__fdt_set_hdr(off_dt_strings);
+__fdt_set_hdr(off_mem_rsvmap);
+__fdt_set_hdr(version);
+__fdt_set_hdr(last_comp_version);
+__fdt_set_hdr(boot_cpuid_phys);
+__fdt_set_hdr(size_dt_strings);
+__fdt_set_hdr(size_dt_struct);
+#undef __fdt_set_hdr
+
+/**
+ * fdt_check_header - sanity check a device tree or possible device tree
+ * @fdt: pointer to data which might be a flattened device tree
+ *
+ * fdt_check_header() checks that the given buffer contains what
+ * appears to be a flattened device tree with sane information in its
+ * header.
+ *
+ * returns:
+ *     0, if the buffer appears to contain a valid device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings, as above
+ */
+int fdt_check_header(const void *fdt);
+
+/**
+ * fdt_move - move a device tree around in memory
+ * @fdt: pointer to the device tree to move
+ * @buf: pointer to memory where the device is to be moved
+ * @bufsize: size of the memory space at buf
+ *
+ * fdt_move() relocates, if possible, the device tree blob located at
+ * fdt to the buffer at buf of size bufsize.  The buffer may overlap
+ * with the existing device tree blob at fdt.  Therefore,
+ *     fdt_move(fdt, fdt, fdt_totalsize(fdt))
+ * should always succeed.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_move(const void *fdt, void *buf, int bufsize);
+
+/**********************************************************************/
+/* Read-only functions                                                */
+/**********************************************************************/
+
+/**
+ * fdt_string - retrieve a string from the strings block of a device tree
+ * @fdt: pointer to the device tree blob
+ * @stroffset: offset of the string within the strings block (native endian)
+ *
+ * fdt_string() retrieves a pointer to a single string from the
+ * strings block of the device tree blob at fdt.
+ *
+ * returns:
+ *     a pointer to the string, on success
+ *     NULL, if stroffset is out of bounds
+ */
+const char *fdt_string(const void *fdt, int stroffset);
+
+/**
+ * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
+ * @fdt: pointer to the device tree blob
+ *
+ * Returns the number of entries in the device tree blob's memory
+ * reservation map.  This does not include the terminating 0,0 entry
+ * or any other (0,0) entries reserved for expansion.
+ *
+ * returns:
+ *     the number of entries
+ */
+int fdt_num_mem_rsv(const void *fdt);
+
+/**
+ * fdt_get_mem_rsv - retrieve one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: pointers to 64-bit variables
+ *
+ * On success, *address and *size will contain the address and size of
+ * the n-th reserve map entry from the device tree blob, in
+ * native-endian format.
+ *
+ * returns:
+ *     0, on success
+ *     -FDT_ERR_BADMAGIC,
+ *     -FDT_ERR_BADVERSION,
+ *     -FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
+
+/**
+ * fdt_subnode_offset_namelen - find a subnode based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_subnode_offset(), but only examine the first
+ * namelen characters of name for matching the subnode name.  This is
+ * useful for finding subnodes based on a portion of a larger string,
+ * such as a full path.
+ */
+int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
+			       const char *name, int namelen);
+/**
+ * fdt_subnode_offset - find a subnode of a given node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_subnode_offset() finds a subnode of the node at structure block
+ * offset parentoffset with the given name.  name may include a unit
+ * address, in which case fdt_subnode_offset() will find the subnode
+ * with that unit address, or the unit address may be omitted, in
+ * which case fdt_subnode_offset() will find an arbitrary subnode
+ * whose name excluding unit address matches the given name.
+ *
+ * returns:
+ *	structure block offset of the requested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_path_offset - find a tree node by its full path
+ * @fdt: pointer to the device tree blob
+ * @path: full path of the node to locate
+ *
+ * fdt_path_offset() finds a node of a given path in the device tree.
+ * Each path component may omit the unit address portion, but the
+ * results of this are undefined if any such path component is
+ * ambiguous (that is if there are multiple nodes at the relevant
+ * level matching the given component, differentiated only by unit
+ * address).
+ *
+ * returns:
+ *	structure block offset of the node with the requested path (>=0), on success
+ *	-FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
+ *	-FDT_ERR_NOTFOUND, if the requested node does not exist
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_path_offset(const void *fdt, const char *path);
+
+/**
+ * fdt_get_name - retrieve the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the starting node
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_name() retrieves the name (including unit address) of the
+ * device tree node at structure block offset nodeoffset.  If lenp is
+ * non-NULL, the length of this name is also returned, in the integer
+ * pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the node's name, on success
+ *		If lenp is non-NULL, *lenp contains the length of that name (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE, standard meanings
+ */
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
+
+/**
+ * fdt_first_property_offset - find the offset of a node's first property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ *
+ * fdt_first_property_offset() finds the first property of the node at
+ * the given structure block offset.
+ *
+ * returns:
+ *	structure block offset of the property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested node has no properties
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_first_property_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_next_property_offset - step through a node's properties
+ * @fdt: pointer to the device tree blob
+ * @offset: structure block offset of a property
+ *
+ * fdt_next_property_offset() finds the property immediately after the
+ * one at the given structure block offset.  This will be a property
+ * of the same node as the given property.
+ *
+ * returns:
+ *	structure block offset of the next property (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the given property is the last in its node
+ *	-FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_next_property_offset(const void *fdt, int offset);
+
+/**
+ * fdt_get_property_by_offset - retrieve the property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @offset: offset of the property to retrieve
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property_by_offset() retrieves a pointer to the
+ * fdt_property structure within the device tree blob at the given
+ * offset.  If lenp is non-NULL, the length of the property value is
+ * also returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+						      int offset,
+						      int *lenp);
+
+/**
+ * fdt_get_property_namelen - find a property based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_get_property_namelen(), but only examine the first
+ * namelen characters of name for matching the property name.
+ */
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+						    int nodeoffset,
+						    const char *name,
+						    int namelen, int *lenp);
+
+/**
+ * fdt_get_property - find a given property in a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_get_property() retrieves a pointer to the fdt_property
+ * structure within the device tree blob corresponding to the property
+ * named 'name' of the node at offset nodeoffset.  If lenp is
+ * non-NULL, the length of the property value is also returned, in the
+ * integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the structure representing the property
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
+					    const char *name, int *lenp);
+static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
+						      const char *name,
+						      int *lenp)
+{
+	return (struct fdt_property *)(uintptr_t)
+		fdt_get_property(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_getprop_by_offset - retrieve the value of a property at a given offset
+ * @fdt: pointer to the device tree blob
+ * @ffset: offset of the property to read
+ * @namep: pointer to a string variable (will be overwritten) or NULL
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop_by_offset() retrieves a pointer to the value of the
+ * property at structure block offset 'offset' (this will be a pointer
+ * to within the device blob itself, not a copy of the value).  If
+ * lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.  If namep is non-NULL,
+ * the property's namne will also be returned in the char * pointed to
+ * by namep (this will be a pointer to within the device tree's string
+ * block, not a new copy of the name).
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *		if namep is non-NULL *namep contiains a pointer to the property
+ *		name.
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+				  const char **namep, int *lenp);
+
+/**
+ * fdt_getprop_namelen - get property value based on substring
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @namelen: number of characters of name to consider
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * Identical to fdt_getprop(), but only examine the first namelen
+ * characters of name for matching the property name.
+ */
+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
+				const char *name, int namelen, int *lenp);
+
+/**
+ * fdt_getprop - retrieve the value of a given property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to find
+ * @name: name of the property to find
+ * @lenp: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_getprop() retrieves a pointer to the value of the property
+ * named 'name' of the node at offset nodeoffset (this will be a
+ * pointer to within the device blob itself, not a copy of the value).
+ * If lenp is non-NULL, the length of the property value is also
+ * returned, in the integer pointed to by lenp.
+ *
+ * returns:
+ *	pointer to the property's value
+ *		if lenp is non-NULL, *lenp contains the length of the property
+ *		value (>=0)
+ *	NULL, on error
+ *		if lenp is non-NULL, *lenp contains an error code (<0):
+ *		-FDT_ERR_NOTFOUND, node does not have named property
+ *		-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *		-FDT_ERR_BADMAGIC,
+ *		-FDT_ERR_BADVERSION,
+ *		-FDT_ERR_BADSTATE,
+ *		-FDT_ERR_BADSTRUCTURE,
+ *		-FDT_ERR_TRUNCATED, standard meanings
+ */
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp);
+static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
+				  const char *name, int *lenp)
+{
+	return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
+}
+
+/**
+ * fdt_get_phandle - retrieve the phandle of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of the node
+ *
+ * fdt_get_phandle() retrieves the phandle of the device tree node at
+ * structure block offset nodeoffset.
+ *
+ * returns:
+ *	the phandle of the node at nodeoffset, on success (!= 0, != -1)
+ *	0, if the node has no phandle, or another error occurs
+ */
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_get_alias_namelen - get alias based on substring
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_get_alias(), but only examine the first namelen
+ * characters of name for matching the alias name.
+ */
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen);
+
+/**
+ * fdt_get_alias - retreive the path referenced by a given alias
+ * @fdt: pointer to the device tree blob
+ * @name: name of the alias th look up
+ *
+ * fdt_get_alias() retrieves the value of a given alias.  That is, the
+ * value of the property named 'name' in the node /aliases.
+ *
+ * returns:
+ *	a pointer to the expansion of the alias named 'name', of it exists
+ *	NULL, if the given alias or the /aliases node does not exist
+ */
+const char *fdt_get_alias(const void *fdt, const char *name);
+
+/**
+ * fdt_get_path - determine the full path of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose path to find
+ * @buf: character buffer to contain the returned path (will be overwritten)
+ * @buflen: size of the character buffer at buf
+ *
+ * fdt_get_path() computes the full path of the node at offset
+ * nodeoffset, and records that path in the buffer at buf.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	0, on success
+ *		buf contains the absolute path of the node at
+ *		nodeoffset, as a NUL-terminated string.
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
+ *		characters and will not fit in the given buffer.
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
+
+/**
+ * fdt_supernode_atdepth_offset - find a specific ancestor of a node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ * @supernodedepth: depth of the ancestor to find
+ * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
+ *
+ * fdt_supernode_atdepth_offset() finds an ancestor of the given node
+ * at a specific depth from the root (where the root itself has depth
+ * 0, its immediate subnodes depth 1 and so forth).  So
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
+ * will always return 0, the offset of the root node.  If the node at
+ * nodeoffset has depth D, then:
+ *	fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
+ * will return nodeoffset itself.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+
+ *	structure block offset of the node at node offset's ancestor
+ *		of depth supernodedepth (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+*	-FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of nodeoffset
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth);
+
+/**
+ * fdt_node_depth - find the depth of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_node_depth() finds the depth of a given node.  The root node
+ * has depth 0, its immediate subnodes depth 1 and so forth.
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset.
+ *
+ * returns:
+ *	depth of the node at nodeoffset (>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_depth(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_parent_offset - find the parent of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose parent to find
+ *
+ * fdt_parent_offset() locates the parent node of a given node (that
+ * is, it finds the offset of the node which contains the node at
+ * nodeoffset as a subnode).
+ *
+ * NOTE: This function is expensive, as it must scan the device tree
+ * structure from the start to nodeoffset, *twice*.
+ *
+ * returns:
+ *	structure block offset of the parent of the node at nodeoffset
+ *		(>=0), on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_parent_offset(const void *fdt, int nodeoffset);
+
+/**
+ * fdt_node_offset_by_prop_value - find nodes with a given property value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @propname: property name to check
+ * @propval: property value to search for
+ * @proplen: length of the value in propval
+ *
+ * fdt_node_offset_by_prop_value() returns the offset of the first
+ * node after startoffset, which has a property named propname whose
+ * value is of length proplen and has value equal to propval; or if
+ * startoffset is -1, the very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
+ *					       propval, proplen);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
+ *						       propval, proplen);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen);
+
+/**
+ * fdt_node_offset_by_phandle - find the node with a given phandle
+ * @fdt: pointer to the device tree blob
+ * @phandle: phandle value
+ *
+ * fdt_node_offset_by_phandle() returns the offset of the node
+ * which has the given phandle value.  If there is more than one node
+ * in the tree with the given phandle (an invalid tree), results are
+ * undefined.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0), on success
+ *	-FDT_ERR_NOTFOUND, no node with that phandle exists
+ *	-FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
+
+/**
+ * fdt_node_check_compatible: check a node's compatible property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of a tree node
+ * @compatible: string to match against
+ *
+ *
+ * fdt_node_check_compatible() returns 0 if the given node contains a
+ * 'compatible' property with the given string as one of its elements,
+ * it returns non-zero otherwise, or on error.
+ *
+ * returns:
+ *	0, if the node has a 'compatible' property listing the given string
+ *	1, if the node has a 'compatible' property, but it does not list
+ *		the given string
+ *	-FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
+ *	-FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible);
+
+/**
+ * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
+ * @fdt: pointer to the device tree blob
+ * @startoffset: only find nodes after this offset
+ * @compatible: 'compatible' string to match against
+ *
+ * fdt_node_offset_by_compatible() returns the offset of the first
+ * node after startoffset, which has a 'compatible' property which
+ * lists the given compatible string; or if startoffset is -1, the
+ * very first such node in the tree.
+ *
+ * To iterate through all nodes matching the criterion, the following
+ * idiom can be used:
+ *	offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
+ *	while (offset != -FDT_ERR_NOTFOUND) {
+ *		... other code here ...
+ *		offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
+ *	}
+ *
+ * Note the -1 in the first call to the function, if 0 is used here
+ * instead, the function will never locate the root node, even if it
+ * matches the criterion.
+ *
+ * returns:
+ *	structure block offset of the located node (>= 0, >startoffset),
+ *		 on success
+ *	-FDT_ERR_NOTFOUND, no node matching the criterion exists in the
+ *		tree after startoffset
+ *	-FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE, standard meanings
+ */
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible);
+
+/**********************************************************************/
+/* Write-in-place functions                                           */
+/**********************************************************************/
+
+/**
+ * fdt_setprop_inplace - change a property's value, but not its size
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to replace the property value with
+ * @len: length of the property value
+ *
+ * fdt_setprop_inplace() replaces the value of a given property with
+ * the data in val, of length len.  This function cannot change the
+ * size of a property, and so will only work if len is equal to the
+ * current length of the property.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if len is not equal to the property's current length
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len);
+
+/**
+ * fdt_setprop_inplace_cell - change the value of a single-cell property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: cell (32-bit integer) value to replace the property with
+ *
+ * fdt_setprop_inplace_cell() replaces the value of a given property
+ * with the 32-bit integer cell value in val, converting val to
+ * big-endian if necessary.  This function cannot change the size of a
+ * property, and so will only work if the property already exists and
+ * has length 4.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the given property value, and will not alter or move any other part
+ * of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, if the property's length is not equal to 4
+  *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
+					   const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop_inplace(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_nop_property - replace a property with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_nop_property() will replace a given property's representation
+ * in the blob with FDT_NOP tags, effectively removing it from the
+ * tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the property, and will not alter or move any other part of the
+ * tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_nop_node - replace a node (subtree) with nop tags
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_nop_node() will replace a given node's representation in the
+ * blob, including all its subnodes, if any, with FDT_NOP tags,
+ * effectively removing it from the tree.
+ *
+ * This function will alter only the bytes in the blob which contain
+ * the node and its properties and subnodes, and will not alter or
+ * move any other part of the tree.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_nop_node(void *fdt, int nodeoffset);
+
+/**********************************************************************/
+/* Sequential write functions                                         */
+/**********************************************************************/
+
+int fdt_create(void *buf, int bufsize);
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
+int fdt_finish_reservemap(void *fdt);
+int fdt_begin_node(void *fdt, const char *name);
+int fdt_property(void *fdt, const char *name, const void *val, int len);
+static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_property(fdt, name, &val, sizeof(val));
+}
+#define fdt_property_string(fdt, name, str) \
+	fdt_property(fdt, name, str, strlen(str)+1)
+int fdt_end_node(void *fdt);
+int fdt_finish(void *fdt);
+
+/**********************************************************************/
+/* Read-write functions                                               */
+/**********************************************************************/
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize);
+int fdt_pack(void *fdt);
+
+/**
+ * fdt_add_mem_rsv - add one memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @address, @size: 64-bit values (native endian)
+ *
+ * Adds a reserve map entry to the given blob reserving a region at
+ * address address of length size.
+ *
+ * This function will insert data into the reserve map and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new reservation entry
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
+
+/**
+ * fdt_del_mem_rsv - remove a memory reserve map entry
+ * @fdt: pointer to the device tree blob
+ * @n: entry to remove
+ *
+ * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
+ * the blob.
+ *
+ * This function will delete data from the reservation table and will
+ * therefore change the indexes of some entries in the table.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
+ *		are less than n+1 reserve map entries)
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_mem_rsv(void *fdt, int n);
+
+/**
+ * fdt_set_name - change the name of a given node
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: structure block offset of a node
+ * @name: name to give the node
+ *
+ * fdt_set_name() replaces the name (including unit address, if any)
+ * of the given node with the given string.  NOTE: this function can't
+ * efficiently check if the new name is unique amongst the given
+ * node's siblings; results are undefined if this function is invoked
+ * with a name equal to one of the given node's siblings.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob
+ *		to contain the new name
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE, standard meanings
+ */
+int fdt_set_name(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_setprop - create or change a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: pointer to data to set the property value to
+ * @len: length of the property value
+ *
+ * fdt_setprop() sets the value of the named property in the given
+ * node to the given value and length, creating the property if it
+ * does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len);
+
+/**
+ * fdt_setprop_cell - set a property to a single cell value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @val: 32-bit integer value for the property (native endian)
+ *
+ * fdt_setprop_cell() sets the value of the named property in the
+ * given node to the given cell value (converting to big-endian if
+ * necessary), or creates a new property with that value if it does
+ * not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
+				   uint32_t val)
+{
+	val = cpu_to_fdt32(val);
+	return fdt_setprop(fdt, nodeoffset, name, &val, sizeof(val));
+}
+
+/**
+ * fdt_setprop_string - set a property to a string value
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to change
+ * @name: name of the property to change
+ * @str: string value for the property
+ *
+ * fdt_setprop_string() sets the value of the named property in the
+ * given node to the given string value (using the length of the
+ * string to determine the new length of the property), or creates a
+ * new property with that value if it does not already exist.
+ *
+ * This function may insert or delete data from the blob, and will
+ * therefore change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOSPACE, there is insufficient free space in the blob to
+ *		contain the new property value
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+#define fdt_setprop_string(fdt, nodeoffset, name, str) \
+	fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
+
+/**
+ * fdt_delprop - delete a property
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node whose property to nop
+ * @name: name of the property to nop
+ *
+ * fdt_del_property() will delete the given property.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_NOTFOUND, node does not have the named property
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_delprop(void *fdt, int nodeoffset, const char *name);
+
+/**
+ * fdt_add_subnode_namelen - creates a new node based on substring
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ * @namelen: number of characters of name to consider
+ *
+ * Identical to fdt_add_subnode(), but use only the first namelen
+ * characters of name as the name of the new node.  This is useful for
+ * creating subnodes based on a portion of a larger string, such as a
+ * full path.
+ */
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen);
+
+/**
+ * fdt_add_subnode - creates a new node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_add_subnode() creates a new node as a subnode of the node at
+ * structure block offset parentoffset, with the given name (which
+ * should include the unit address, if any).
+ *
+ * This function will insert data into the blob, and will therefore
+ * change the offsets of some existing nodes.
+
+ * returns:
+ *	structure block offset of the created nodeequested subnode (>=0), on success
+ *	-FDT_ERR_NOTFOUND, if the requested subnode does not exist
+ *	-FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE tag
+ *	-FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
+ *		the given name
+ *	-FDT_ERR_NOSPACE, if there is insufficient free space in the
+ *		blob to contain the new node
+ *	-FDT_ERR_NOSPACE
+ *	-FDT_ERR_BADLAYOUT
+ *      -FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings.
+ */
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
+
+/**
+ * fdt_del_node - delete a node (subtree)
+ * @fdt: pointer to the device tree blob
+ * @nodeoffset: offset of the node to nop
+ *
+ * fdt_del_node() will remove the given node, including all its
+ * subnodes if any, from the blob.
+ *
+ * This function will delete data from the blob, and will therefore
+ * change the offsets of some existing nodes.
+ *
+ * returns:
+ *	0, on success
+ *	-FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
+ *	-FDT_ERR_BADLAYOUT,
+ *	-FDT_ERR_BADMAGIC,
+ *	-FDT_ERR_BADVERSION,
+ *	-FDT_ERR_BADSTATE,
+ *	-FDT_ERR_BADSTRUCTURE,
+ *	-FDT_ERR_TRUNCATED, standard meanings
+ */
+int fdt_del_node(void *fdt, int nodeoffset);
+
+/**
+ * fdt_get_base_addr - find base address of a node from its name
+ * @fdt: pointer to the device tree blob
+ * @offset: offset of the node to parse the name of
+ * @base_addr: pointer to place the node address retrieved from the name
+ *
+ * Retrieve base address from the string name of a node formatted as
+ * <name>@<base addr>.
+ *
+ * Return 0 on success, -1 on any errror.
+ */
+int fdt_get_base_addr(const void *fdt, int offset, u64 *base_addr);
+
+/**********************************************************************/
+/* Debugging / informational functions                                */
+/**********************************************************************/
+
+const char *fdt_strerror(int errval);
+
+#endif /* _LIBFDT_H */
diff --git a/src/include/fdt/libfdt_env.h b/src/include/fdt/libfdt_env.h
new file mode 100644
index 0000000..755a5a6
--- /dev/null
+++ b/src/include/fdt/libfdt_env.h
@@ -0,0 +1,31 @@
+/*
+ * libfdt - Flat Device Tree manipulation (build/run environment adaptation)
+ * Copyright (C) 2007 Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com
+ * Original version written by David Gibson, IBM Corporation.
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public License
+ * as published by the Free Software Foundation; either version 2.1 of
+ * the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _LIBFDT_ENV_H
+#define _LIBFDT_ENV_H
+
+#include <arch/byteorder.h>
+
+#define fdt32_to_cpu(x)		be32_to_cpu(x)
+#define cpu_to_fdt32(x)		cpu_to_be32(x)
+#define fdt64_to_cpu(x)		be64_to_cpu(x)
+#define cpu_to_fdt64(x)		cpu_to_be64(x)
+
+#endif /* _LIBFDT_ENV_H */
diff --git a/src/include/pc80/i8254.h b/src/include/pc80/i8254.h
index b0d3a93..4c5e703 100644
--- a/src/include/pc80/i8254.h
+++ b/src/include/pc80/i8254.h
@@ -58,4 +58,7 @@
 #define PPCB_SPKR       0x02    /* Bit 1 */
 #define PPCB_T2GATE     0x01    /* Bit 0 */
 
+#ifndef __ROMCC__
+void setup_i8254(void);
+#endif
 #endif
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 032e385..f51c371 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -104,6 +104,22 @@
 	outb(addr, RTC_BASE_PORT + offs + 0);
 	outb(val, RTC_BASE_PORT + offs + 1);
 }
+
+static inline u32 cmos_read32(u8 offset)
+{
+	u32 value = 0;
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		value |= cmos_read(offset + i) << (i << 3);
+	return value;
+}
+
+static inline void cmos_write32(u8 offset, u32 value)
+{
+	u8 i;
+	for (i = 0; i < sizeof(value); ++i)
+		cmos_write((value >> (i << 3)) & 0xff, offset + i);
+}
 #endif
 
 #if !defined(__ROMCC__)
diff --git a/src/cpu/x86/mmx_disable.inc b/src/include/pc80/tpm.h
similarity index 64%
copy from src/cpu/x86/mmx_disable.inc
copy to src/include/pc80/tpm.h
index 1a4e70f..2eff15a 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/include/pc80/tpm.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,16 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef TPM_H_
+#define TPM_H_
 
+int tis_init(void);
+int tis_open(void);
+int tis_close(void);
+int tis_sendrecv(const u8 *sendbuf, size_t send_size, u8 *recvbuf,
+			size_t *recv_len);
+
+#endif /* TPM_H_ */
diff --git a/src/include/smbios.h b/src/include/smbios.h
new file mode 100644
index 0000000..1210f0f
--- /dev/null
+++ b/src/include/smbios.h
@@ -0,0 +1,226 @@
+#ifndef SMBIOS_H
+#define SMBIOS_H
+
+#include <types.h>
+
+unsigned long smbios_write_tables(unsigned long start);
+int smbios_add_string(char *start, const char *str);
+int smbios_string_table_len(char *start);
+
+#define BIOS_CHARACTERISTICS_PCI_SUPPORTED  (1 << 7)
+#define BIOS_CHARACTERISTICS_PC_CARD  (1 << 8)
+#define BIOS_CHARACTERISTICS_PNP  (1 << 9)
+#define BIOS_CHARACTERISTICS_APM (1 << 10)
+#define BIOS_CHARACTERISTICS_UPGRADEABLE      (1 << 11)
+#define BIOS_CHARACTERISTICS_SHADOW           (1 << 12)
+#define BIOS_CHARACTERISTICS_BOOT_FROM_CD     (1 << 15)
+#define BIOS_CHARACTERISTICS_SELECTABLE_BOOT  (1 << 16)
+#define BIOS_CHARACTERISTICS_BIOS_SOCKETED    (1 << 17)
+
+#define BIOS_EXT1_CHARACTERISTICS_ACPI    (1 << 0)
+#define BIOS_EXT2_CHARACTERISTICS_TARGET  (1 << 2)
+
+#define SMBIOS_STATE_SAFE 3
+typedef enum {
+	SMBIOS_BIOS_INFORMATION=0,
+	SMBIOS_SYSTEM_INFORMATION=1,
+	SMBIOS_SYSTEM_ENCLOSURE=3,
+	SMBIOS_PROCESSOR_INFORMATION=4,
+	SMBIOS_CACHE_INFORMATION=7,
+	SMBIOS_SYSTEM_SLOTS=9,
+	SMBIOS_PHYS_MEMORY_ARRAY=16,
+	SMBIOS_MEMORY_DEVICE=17,
+	SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS=19,
+	SMBIOS_SYSTEM_BOOT_INFORMATION=32,
+	SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION=41,
+	SMBIOS_END_OF_TABLE=127,
+} smbios_struct_type_t;
+
+struct smbios_entry {
+	u8 anchor[4];
+	u8 checksum;
+	u8 length;
+	u8 major_version;
+	u8 minor_version;
+	u16 max_struct_size;
+	u8 entry_point_rev;
+	u8 formwatted_area[5];
+	u8 intermediate_anchor_string[5];
+	u8 intermediate_checksum;
+	u16 struct_table_length;
+	u32 struct_table_address;
+	u16 struct_count;
+	u8 smbios_bcd_revision;
+} __attribute__((packed));
+
+struct smbios_type0 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 vendor;
+	u8 bios_version;
+	u16 bios_start_segment;
+	u8 bios_release_date;
+	u8 bios_rom_size;
+	u64 bios_characteristics;
+	u8 bios_characteristics_ext1;
+	u8 bios_characteristics_ext2;
+	u8 system_bios_major_release;
+	u8 system_bios_minor_release;
+	u8 ec_major_release;
+	u8 ec_minor_release;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type1 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 manufacturer;
+	u8 product_name;
+	u8 version;
+	u8 serial_number;
+	u8 uuid[16];
+	u8 wakeup_type;
+	u8 sku;
+	u8 family;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type3 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 manufacturer;
+	u8 _type;
+	u8 version;
+	u8 serial_number;
+	u8 asset_tag_number;
+	u8 bootup_state;
+	u8 power_supply_state;
+	u8 thermal_state;
+	u8 security_status;
+	u32 oem_defined;
+	u8 height;
+	u8 number_of_power_cords;
+	u8 element_count;
+	u8 element_record_length;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type4 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 socket_designation;
+	u8 processor_type;
+	u8 processor_family;
+	u8 processor_manufacturer;
+	u32 processor_id[2];
+	u8 processor_version;
+	u8 voltage;
+	u16 external_clock;
+	u16 max_speed;
+	u16 current_speed;
+	u8 status;
+	u8 processor_upgrade;
+	u16 l1_cache_handle;
+	u16 l2_cache_handle;
+	u16 l3_cache_handle;
+	u8 serial_number;
+	u8 asset_tag;
+	u8 part_number;
+	u8 core_count;
+	u8 core_enabled;
+	u8 thread_count;
+	u16 processor_characteristics;
+	u16 processor_family2;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type16 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 location;
+	u8 use;
+	u8 memory_error_correction;
+	u32 maximum_capacity;
+	u16 memory_error_information_handle;
+	u16 number_of_memory_devices;
+	u64 extended_maximum_capacity;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type17 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u16 phys_memory_array_handle;
+	u16 memory_error_information_handle;
+	u16 total_width;
+	u16 data_width;
+	u16 size;
+	u8 form_factor;
+	u8 device_set;
+	u8 device_locator;
+	u8 bank_locator;
+	u8 memory_type;
+	u16 type_detail;
+	u16 speed;
+	u8 manufacturer;
+	u8 serial_number;
+	u8 asset_tag;
+	u8 part_number;
+	u8 attributes;
+	u16 extended_size;
+	u16 clock_speed;
+
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type32 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 reserved[6];
+	u8 boot_status;
+	u8 eos[2];
+} __attribute__((packed));
+
+typedef enum {
+	SMBIOS_DEVICE_TYPE_OTHER = 0x01,
+	SMBIOS_DEVICE_TYPE_UNKNOWN,
+	SMBIOS_DEVICE_TYPE_VIDEO,
+	SMBIOS_DEVICE_TYPE_SCSI,
+	SMBIOS_DEVICE_TYPE_ETHERNET,
+	SMBIOS_DEVICE_TYPE_TOKEN_RING,
+	SMBIOS_DEVICE_TYPE_SOUND,
+	SMBIOS_DEVICE_TYPE_PATA,
+	SMBIOS_DEVICE_TYPE_SATA,
+	SMBIOS_DEVICE_TYPE_SAS,
+} smbios_onboard_device_type;
+
+struct smbios_type41 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 reference_designation;
+	u8 device_type: 7;
+	u8 device_status: 1;
+	u8 device_type_instance;
+	u16 segment_group_number;
+	u8 bus_number;
+	u8 function_number: 3;
+	u8 device_number: 5;
+	char eos[2];
+} __attribute__((packed));
+
+struct smbios_type127 {
+	u8 type;
+	u8 length;
+	u16 handle;
+	u8 eos[2];
+} __attribute__((packed));
+
+#endif
diff --git a/src/include/stdlib.h b/src/include/stdlib.h
index 45420d7..5465c14 100644
--- a/src/include/stdlib.h
+++ b/src/include/stdlib.h
@@ -5,7 +5,7 @@
 
 #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
 
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1)
+#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1UL)
 #define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 
 #define MIN(a,b) ((a) < (b) ? (a) : (b))
diff --git a/src/include/string.h b/src/include/string.h
index 2168947..708961b 100644
--- a/src/include/string.h
+++ b/src/include/string.h
@@ -8,6 +8,7 @@
 void *memmove(void *dest, const void *src, size_t n);
 void *memset(void *s, int c, size_t n);
 int memcmp(const void *s1, const void *s2, size_t n);
+void *memchr(const void *s, int c, size_t n);
 #if !defined(__PRE_RAM__)
 int sprintf(char * buf, const char *fmt, ...);
 #endif
diff --git a/src/include/swab.h b/src/include/swab.h
index 3a16686..c5e4370 100644
--- a/src/include/swab.h
+++ b/src/include/swab.h
@@ -30,4 +30,15 @@
 		(((unsigned int)(x) & (unsigned int)0x00ff0000UL) >>  8) | \
 		(((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) ))
 
+#define swab64(x) \
+	((uint64_t)( \
+		(((uint64_t)(x) & (uint64_t)0x00000000000000ffULL) << 56) | \
+		(((uint64_t)(x) & (uint64_t)0x000000000000ff00ULL) << 40) | \
+		(((uint64_t)(x) & (uint64_t)0x0000000000ff0000ULL) << 24) | \
+		(((uint64_t)(x) & (uint64_t)0x00000000ff000000ULL) <<  8) | \
+		(((uint64_t)(x) & (uint64_t)0x000000ff00000000ULL) >>  8) | \
+		(((uint64_t)(x) & (uint64_t)0x0000ff0000000000ULL) >> 24) | \
+		(((uint64_t)(x) & (uint64_t)0x00ff000000000000ULL) >> 40) | \
+		(((uint64_t)(x) & (uint64_t)0xff00000000000000ULL) >> 56) ))
+
 #endif /* _SWAB_H */
diff --git a/src/include/timestamp.h b/src/include/timestamp.h
new file mode 100644
index 0000000..0bb323c
--- /dev/null
+++ b/src/include/timestamp.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#ifndef __TIMESTAMP_H__
+#define __TIMESTAMP_H__
+
+#include <cpu/x86/tsc.h>
+
+struct timestamp_entry {
+	uint32_t	entry_id;
+	uint64_t	entry_stamp;
+} __attribute__((packed));
+
+struct timestamp_table {
+	uint64_t	base_time;
+	uint32_t	max_entries;
+	uint32_t	num_entries;
+	struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+enum timestamp_id {
+	TS_START_ROMSTAGE = 1,
+	TS_BEFORE_INITRAM = 2,
+	TS_AFTER_INITRAM = 3,
+	TS_END_ROMSTAGE = 4,
+	TS_START_COPYRAM = 8,
+	TS_END_COPYRAM = 9,
+	TS_START_RAMSTAGE = 10,
+	TS_DEVICE_ENUMERATE = 30,
+	TS_DEVICE_CONFIGURE = 40,
+	TS_DEVICE_ENABLE = 50,
+	TS_DEVICE_INITIALIZE = 60,
+	TS_DEVICE_DONE = 70,
+	TS_WRITE_TABLES = 80,
+	TS_LOAD_PAYLOAD = 90,
+	TS_ACPI_WAKE_JUMP = 98,
+	TS_SELFBOOT_JUMP = 99,
+};
+
+#if CONFIG_COLLECT_TIMESTAMPS
+void timestamp_init(tsc_t base);
+void timestamp_add(enum timestamp_id id, tsc_t ts_time);
+void timestamp_add_now(enum timestamp_id id);
+#else
+#define timestamp_init(base)
+#define timestamp_add(id, time)
+#define timestamp_add_now(id)
+#endif
+
+#endif
diff --git a/src/include/uart8250.h b/src/include/uart8250.h
index bbf2d8c..14b28c8 100644
--- a/src/include/uart8250.h
+++ b/src/include/uart8250.h
@@ -20,26 +20,7 @@
 #ifndef UART8250_H
 #define UART8250_H
 
-/* Base Address */
-#ifndef CONFIG_TTYS0_BASE
-#define CONFIG_TTYS0_BASE 0x3f8
-#endif
-
-#ifndef CONFIG_TTYS0_BAUD
-#define CONFIG_TTYS0_BAUD 115200
-#endif
-#if ((115200%CONFIG_TTYS0_BAUD) != 0)
-#error Bad ttys0 baud rate
-#endif
-
-/* Line Control Settings */
-#ifndef CONFIG_TTYS0_LCS
-/* Set 8bit, 1 stop bit, no parity */
-#define CONFIG_TTYS0_LCS	0x3
-#endif
-
-#define UART_LCS	CONFIG_TTYS0_LCS
-
+#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM
 
 /* Data */
 #define UART_RBR 0x00
@@ -126,6 +107,12 @@
 #define UART_SCR 0x07
 #define UART_SPR 0x07
 
+#if ((115200 % CONFIG_TTYS0_BAUD) != 0)
+#error Bad ttyS0 baud rate
+#endif
+
+/* Line Control Settings */
+#define UART_LCS	CONFIG_TTYS0_LCS
 
 #ifndef __ROMCC__
 unsigned char uart8250_rx_byte(unsigned base_port);
@@ -144,10 +131,19 @@
 void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
 void uart8250_mem_init(unsigned base_port, unsigned divisor);
 u32 uart_mem_init(void);
+void uartmem_init(void);
+u32 uartmem_getbaseaddr(void);
 
+#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE && \
+	CONFIG_CONSOLE_SERIAL8250MEM
 /* and special init for OXPCIe based cards */
-void oxford_init(void);
+extern int oxford_oxpcie_present;
 
+void oxford_init(void);
 #endif
 
+#endif /* __ROMCC__ */
+
+#endif /* CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM */
+
 #endif /* UART8250_H */
diff --git a/src/include/usbdebug.h b/src/include/usbdebug.h
index 281ccde..c912f56 100644
--- a/src/include/usbdebug.h
+++ b/src/include/usbdebug.h
@@ -39,6 +39,7 @@
 unsigned get_ehci_debug(void);
 void set_debug_port(unsigned port);
 int early_usbdebug_init(void);
+void enable_usbdebug(unsigned int port); /* Implemented by southbridge */
 void usbdebug_tx_byte(unsigned char data);
 
 #endif
diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc
index 3817161..ba83fda 100644
--- a/src/lib/Makefile.inc
+++ b/src/lib/Makefile.inc
@@ -1,7 +1,12 @@
 
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 romstage-y += memset.c
+endif
+romstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 romstage-y += memcpy.c
+endif
 romstage-y += memcmp.c
 romstage-y += cbfs.c
 romstage-y += lzma.c
@@ -10,12 +15,20 @@
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+romstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 romstage-$(CONFIG_CONSOLE_NE2K) += ne2k.c
-romstage-$(CONFIG_CONSOLE_NE2K) += compute_ip_checksum.c
 romstage-$(CONFIG_USBDEBUG) += usbdebug.c
+romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
+romstage-y += compute_ip_checksum.c
+romstage-y += memmove.c
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y)
 ramstage-y += memset.c
+endif
+ramstage-y += memchr.c
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 ramstage-y += memcpy.c
+endif
 ramstage-y += memcmp.c
 ramstage-y += memmove.c
 ramstage-y += malloc.c
@@ -31,13 +44,28 @@
 ramstage-y += cbmem.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 ramstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c
 ramstage-$(CONFIG_USBDEBUG) += usbdebug.c
 ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c
+ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c
 
 driver-$(CONFIG_CONSOLE_NE2K) += ne2k.c
 
+ifneq ($(CONFIG_HAVE_ARCH_MEMCPY),y)
 smm-y += memcpy.c
+endif
 smm-$(CONFIG_CONSOLE_SERIAL8250) += uart8250.c
 smm-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart8250mem.c
+smm-$(CONFIG_USBDEBUG) += usbdebug.c
 
 $(obj)/lib/version.ramstage.o : $(obj)/build.h
+
+OPTION_TABLE_H:=
+ifeq ($(CONFIG_HAVE_OPTION_TABLE),y)
+OPTION_TABLE_H:=$(obj)/option_table.h
+endif
+
+$(obj)/lib/uart8250mem.smm.o : $(OPTION_TABLE_H)
+$(obj)/lib/uart8250.smm.o : $(OPTION_TABLE_H)
+
+subdirs-$(CONFIG_ADD_FDT) += libfdt
diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c
index 690033e..9573739 100644
--- a/src/lib/cbfs.c
+++ b/src/lib/cbfs.c
@@ -24,6 +24,11 @@
 #include <lib.h>
 #include <arch/byteorder.h>
 
+#if CONFIG_DEBUG_CBFS
+#define debug(x...) printk(BIOS_SPEW, x)
+#else
+#define debug(x...)
+#endif
 
 /**
  * Decompression wrapper for CBFS
@@ -48,7 +53,7 @@
 		return 0;
 
 	default:
-		printk(BIOS_INFO,  "CBFS:  Unknown compression type %d\n", algo);
+		printk(BIOS_INFO,  "CBFS: Unknown compression type %d\n", algo);
 		return -1;
 	}
 }
@@ -58,57 +63,98 @@
 	return !strcmp(file->magic, CBFS_FILE_MAGIC) ? 1 : 0;
 }
 
-static struct cbfs_header *cbfs_master_header(void)
+struct cbfs_header *get_cbfs_header(void)
 {
 	struct cbfs_header *header;
 
 	void *ptr = (void *)*((unsigned long *) CBFS_HEADPTR_ADDR);
-	printk(BIOS_SPEW, "Check CBFS header at %p\n", ptr);
+	debug("CBFS: Check master header at %p\n", ptr);
 	header = (struct cbfs_header *) ptr;
 
-	printk(BIOS_SPEW, "magic is %08x\n", ntohl(header->magic));
+	debug("magic is %08x\n", ntohl(header->magic));
 	if (ntohl(header->magic) != CBFS_HEADER_MAGIC) {
 		printk(BIOS_ERR, "ERROR: No valid CBFS header found!\n");
 		if (header->magic == 0xffffffff) {
-			printk(BIOS_ERR, "Maybe the ROM isn't entirely mapped yet?\n"
-				"See (and report to) http://www.coreboot.org/Infrastructure_Projects#CBFS\n");
+			printk(BIOS_ERR, "Maybe the ROM isn't entirely mapped "
+				"yet?\nSee (and report to) http://www.coreboot"
+				".org/Infrastructure_Projects#CBFS\n");
 		}
 		return NULL;
 	}
 
-	printk(BIOS_SPEW, "Found CBFS header at %p\n", ptr);
+	debug("CBFS: Found master header at %p\n", ptr);
 	return header;
 }
 
+u32 get_cbfs_size(void)
+{
+	struct cbfs_header *header = get_cbfs_header();
+
+	if (!header)
+		return 0;
+
+	return ntohl(header->romsize);
+}
+
+void *get_cbfs_base(void)
+{
+	u32 cbfs_size = get_cbfs_size();
+
+	if (cbfs_size)
+		return (void *)(unsigned long)(0x100000000ULL - cbfs_size);
+
+	return NULL;
+}
+
 struct cbfs_file *cbfs_find(const char *name)
 {
-	struct cbfs_header *header = cbfs_master_header();
+	struct cbfs_header *header = get_cbfs_header();
 	unsigned long offset;
+	u32 cbfs_size = get_cbfs_size();
+	u32 cbfs_base = (u32)get_cbfs_base();
 
 	if (header == NULL)
 		return NULL;
-	offset = 0 - ntohl(header->romsize) + ntohl(header->offset);
 
-	int align= ntohl(header->align);
+	offset = (unsigned long)(0x100000000ULL - ntohl(header->romsize) +
+			ntohl(header->offset));
 
+	if ((offset < cbfs_base) || (offset > (cbfs_base + cbfs_size - 1)))
+		printk(BIOS_WARNING, "WARNING: CBFS seems to live outside "
+			"of ROM\n");
+
+	int align = ntohl(header->align);
+
+	printk(BIOS_SPEW, "CBFS: Looking for '%s'\n", name);
 	while(1) {
 		struct cbfs_file *file = (struct cbfs_file *) offset;
 		if (!cbfs_check_magic(file)) return NULL;
-		printk(BIOS_SPEW, "Check %s\n", CBFS_NAME(file));
-		if (!strcmp(CBFS_NAME(file), name))
+		debug("CBFS: Check %s\n", CBFS_NAME(file));
+		if (!strcmp(CBFS_NAME(file), name)) {
+			printk(BIOS_SPEW, "CBFS: found.\n");
 			return file;
+		}
 
 		int flen = ntohl(file->len);
 		int foffset = ntohl(file->offset);
-		printk(BIOS_SPEW, "CBFS: follow chain: %p + %x + %x + align -> ", (void *)offset, foffset, flen);
+		debug("CBFS: follow chain: %p + %x + %x + align -> ",
+						(void *)offset, foffset, flen);
 
 		unsigned long oldoffset = offset;
 		offset = ALIGN(offset + foffset + flen, align);
-		printk(BIOS_SPEW, "%p\n", (void *)offset);
-		if (offset <= oldoffset) return NULL;
+		debug("%p\n", (void *)offset);
 
-		if (offset < 0xFFFFFFFF - ntohl(header->romsize))
+		/* The offset above will overflow when we hit 4GB,
+		 * at which point CBFS is done and did not find a
+		 * file.
+		 */
+		if (offset <= oldoffset)
 			return NULL;
+
+		if (offset < 0xFFFFFFFF - ntohl(header->romsize)) {
+			printk(BIOS_SPEW, "CBFS: not found.\n");
+			return NULL;
+		}
 	}
 }
 
@@ -117,13 +163,13 @@
 	struct cbfs_file *file = cbfs_find(name);
 
 	if (file == NULL) {
-		printk(BIOS_INFO,  "CBFS:  Could not find file %s\n",
+		printk(BIOS_INFO,  "CBFS: Could not find file %s\n",
 		       name);
 		return NULL;
 	}
 
 	if (ntohl(file->type) != type) {
-		printk(BIOS_INFO,  "CBFS:  File %s is of type %x instead of"
+		printk(BIOS_INFO,  "CBFS: File %s is of type %x instead of "
 		       "type %x\n", name, file->type, type);
 
 		return NULL;
@@ -134,25 +180,25 @@
 
 static inline int tohex4(unsigned int c)
 {
-	return (c<=9)?(c+'0'):(c-10+'a');
+	return (c <= 9) ? (c + '0') : (c - 10 + 'a');
 }
 
-static void tohex16(unsigned int val, char* dest)
+static void tohex16(unsigned int val, char *dest)
 {
-	dest[0]=tohex4(val>>12);
-	dest[1]=tohex4((val>>8) & 0xf);
-	dest[2]=tohex4((val>>4) & 0xf);
-	dest[3]=tohex4(val & 0xf);
+	dest[0] = tohex4(val >> 12);
+	dest[1] = tohex4((val >> 8) & 0xf);
+	dest[2] = tohex4((val >> 4) & 0xf);
+	dest[3] = tohex4(val & 0xf);
 }
 
-void *cbfs_load_optionrom(u16 vendor, u16 device, void * dest)
+void *cbfs_load_optionrom(u16 vendor, u16 device, void *dest)
 {
-	char name[17]="pciXXXX,XXXX.rom";
+	char name[17] = "pciXXXX,XXXX.rom";
 	struct cbfs_optionrom *orom;
 	u8 *src;
 
-	tohex16(vendor, name+3);
-	tohex16(device, name+8);
+	tohex16(vendor, name + 3);
+	tohex16(device, name + 8);
 
 	orom = (struct cbfs_optionrom *)
 		cbfs_find_file(name, CBFS_TYPE_OPTIONROM);
@@ -193,10 +239,10 @@
 	if (stage == NULL)
 		return (void *) -1;
 
-	printk(BIOS_INFO, "Stage: loading %s @ 0x%x (%d bytes), entry @ 0x%llx\n",
-			name,
-			(u32) stage->load, stage->memlen,
+	printk(BIOS_INFO, "CBFS: loading stage %s @ 0x%x (%d bytes), entry "
+			"@ 0x%llx\n", name, (u32) stage->load, stage->memlen,
 			stage->entry);
+
 	memset((void *) (u32) stage->load, 0, stage->memlen);
 
 	if (cbfs_decompress(stage->compression,
@@ -206,7 +252,7 @@
 			     stage->len))
 		return (void *) -1;
 
-	printk(BIOS_DEBUG, "Stage: done loading.\n");
+	printk(BIOS_DEBUG, "CBFS: stage loaded.\n");
 
 	entry = stage->entry;
 	// entry = ntohl((u32) stage->entry);
@@ -223,13 +269,13 @@
 		return 1;
 
 	if (ntohl(stage->compression) != CBFS_COMPRESS_NONE) {
-		printk(BIOS_INFO,  "CBFS:  Unable to run %s:  Compressed file"
+		printk(BIOS_INFO, "CBFS: Unable to run %s:  Compressed file"
 		       "Not supported for in-place execution\n", name);
 		return 1;
 	}
 
 	/* FIXME: This isn't right */
-	printk(BIOS_INFO,  "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
+	printk(BIOS_INFO, "CBFS: run @ %p\n", (void *) ntohl((u32) stage->entry));
 	return run_address((void *) ntohl((u32) stage->entry));
 }
 
diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c
index 5417ab8..8bc35d7 100644
--- a/src/lib/cbmem.c
+++ b/src/lib/cbmem.c
@@ -21,6 +21,9 @@
 #include <string.h>
 #include <cbmem.h>
 #include <console/console.h>
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+#include <arch/acpi.h>
+#endif
 
 // The CBMEM TOC reserves 512 bytes to keep
 // the other entries somewhat aligned.
@@ -118,6 +121,22 @@
 {
 	struct cbmem_entry *cbmem_toc;
 	int i;
+	void *p;
+
+	/*
+	 * This could be a restart, check if the section is there already. It
+	 * is remotely possible that the dram contents persisted over the
+	 * bootloader upgrade AND the same section now needs more room, but
+	 * this is quite a remote possibility and it is ignored here.
+	 */
+	p = cbmem_find(id);
+	if (p) {
+		printk(BIOS_NOTICE,
+		       "CBMEM section %x: using existing location at %p.\n",
+		       id, p);
+		return p;
+	}
+
 	cbmem_toc = get_cbmem_toc();
 
 	if (cbmem_toc == NULL) {
@@ -183,28 +202,33 @@
 	return (void *)NULL;
 }
 
-#ifndef __PRE_RAM__
-#if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
+#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)
+/* Returns True if it was not intialized before. */
+int cbmem_initialize(void)
+{
+	int rv = 0;
+
+#ifdef __PRE_RAM__
+	extern unsigned long get_top_of_ram(void);
+	uint64_t high_tables_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+	uint64_t high_tables_size = HIGH_MEMORY_SIZE;
 #endif
 
-void cbmem_initialize(void)
-{
-#if CONFIG_HAVE_ACPI_RESUME
-	if (acpi_slp_type == 3) {
-		if (!cbmem_reinit(high_tables_base)) {
-			/* Something went wrong, our high memory area got wiped */
+	/* We expect the romstage to always initialize it. */
+	if (!cbmem_reinit(high_tables_base)) {
+#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__)
+		if (acpi_slp_type == 3)
 			acpi_slp_type = 0;
-			cbmem_init(high_tables_base, high_tables_size);
-		}
-	} else {
-		cbmem_init(high_tables_base, high_tables_size);
-	}
-#else
-	cbmem_init(high_tables_base, high_tables_size);
 #endif
+		cbmem_init(high_tables_base, high_tables_size);
+		rv = 1;
+	}
+#ifndef __PRE_RAM__
 	cbmem_arch_init();
+#endif
+	return rv;
 }
+#endif
 
 #ifndef __PRE_RAM__
 void cbmem_list(void)
@@ -229,6 +253,10 @@
 		case CBMEM_ID_PIRQ:	 printk(BIOS_DEBUG, "IRQ TABLE  "); break;
 		case CBMEM_ID_MPTABLE:	 printk(BIOS_DEBUG, "SMP TABLE  "); break;
 		case CBMEM_ID_RESUME:	 printk(BIOS_DEBUG, "ACPI RESUME"); break;
+		case CBMEM_ID_SMBIOS:    printk(BIOS_DEBUG, "SMBIOS     "); break;
+		case CBMEM_ID_TIMESTAMP: printk(BIOS_DEBUG, "TIME STAMP "); break;
+		case CBMEM_ID_MRCDATA:   printk(BIOS_DEBUG, "MRC DATA   "); break;
+		case CBMEM_ID_CONSOLE:   printk(BIOS_DEBUG, "CONSOLE    "); break;
 		default: printk(BIOS_DEBUG, "%08x ", cbmem_toc[i].id);
 		}
 		printk(BIOS_DEBUG, "%08llx ", cbmem_toc[i].base);
@@ -237,5 +265,4 @@
 }
 #endif
 
-#endif
 
diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c
new file mode 100644
index 0000000..431ea1f
--- /dev/null
+++ b/src/lib/cbmem_console.c
@@ -0,0 +1,198 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cbmem.h>
+#include <cpu/x86/car.h>
+#include <string.h>
+
+/*
+ * Structure describing console buffer. It is overlaid on a flat memory area,
+ * whith buffer_body covering the extent of the memory. Once the buffer is
+ * full, the cursor keeps going but the data is dropped on the floor. This
+ * allows to tell how much data was lost in the process.
+ */
+struct cbmem_console {
+	u32 buffer_size;
+	u32 buffer_cursor;
+	u8  buffer_body[0];
+}  __attribute__ ((__packed__));
+
+#ifdef __PRE_RAM__
+/*
+ * While running from ROM, before DRAM is initialized, some area in cache as
+ * ram space is used for the console buffer storage. The size and location of
+ * the area are defined in the config.
+ */
+
+static struct cbmem_console car_cbmem_console CAR_CBMEM;
+#define cbmem_console_p (&car_cbmem_console)
+
+/*
+ * Once DRAM is initialized and the cache as ram mode is disabled, while still
+ * running from ROM, the console buffer in the cache as RAM area becomes
+ * unavailable.
+ *
+ * By this time the console log buffer is already available in
+ * CBMEM. The location at 0x600 is used as the redirect pointer allowing to
+ * find out where the actual console log buffer is.
+ */
+#define CBMEM_CONSOLE_REDIRECT (*((struct cbmem_console **)0x600))
+#else
+
+/*
+ * When running from RAM, a lot of console output is generated before CBMEM is
+ * reinitialized. This static buffer is used to store that output temporarily,
+ * to be concatenated with the CBMEM console buffer contents accumulated
+ * during the ROM stage, once CBMEM becomes avaiklable at RAM stage.
+ */
+static u8 static_console[40000];
+static struct cbmem_console *cbmem_console_p;
+#endif
+
+void cbmemc_init(void)
+{
+#ifdef __PRE_RAM__
+	cbmem_console_p->buffer_size = CONFIG_CONSOLE_CAR_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+#else
+	/*
+	 * Initializing before CBMEM is available, use static buffer to store
+	 * the log.
+	 */
+	cbmem_console_p = (struct cbmem_console *) static_console;
+	cbmem_console_p->buffer_size = sizeof(static_console) -
+		sizeof(struct cbmem_console);
+#endif
+	cbmem_console_p->buffer_cursor = 0;
+}
+
+void cbmemc_tx_byte(unsigned char data)
+{
+	struct cbmem_console *cbm_cons_p = cbmem_console_p;
+	u32 cursor;
+#ifdef __PRE_RAM__
+	/*
+	 * This check allows to tell if the cache as RAM mode has been exited
+	 * or not. If it has been exited, the real memory is being used
+	 * (resulting in the variable on the stack located below
+	 * DCACHE_RAM_BASE), use the redirect pointer to find out where the
+	 * actual console buffer is.
+	 */
+	if ((uintptr_t)&cursor < (uintptr_t)&car_cbmem_console)
+		cbm_cons_p = CBMEM_CONSOLE_REDIRECT;
+#endif
+	if (!cbm_cons_p)
+		return;
+
+	cursor = cbm_cons_p->buffer_cursor++;
+	if (cursor < cbm_cons_p->buffer_size)
+		cbm_cons_p->buffer_body[cursor] = data;
+}
+
+/*
+ * Copy the current console buffer (either from the cache as RAM area, or from
+ * the static buffer, pointed at by cbmem_console_p) into the CBMEM console
+ * buffer space (pointed at by new_cons_p), concatenating the copied data with
+ * the CBMEM console buffer contents.
+ *
+ * If there is overflow - add to the destination area a string, reporting the
+ * overflow and the number of dropped charactes.
+ */
+static void copy_console_buffer(struct cbmem_console *new_cons_p)
+{
+	u32 copy_size;
+	u32 cursor = new_cons_p->buffer_cursor;
+	int overflow = cbmem_console_p->buffer_cursor >
+		cbmem_console_p->buffer_size;
+
+	copy_size = overflow ?
+		cbmem_console_p->buffer_size : cbmem_console_p->buffer_cursor;
+
+	memcpy(new_cons_p->buffer_body + cursor,
+	       cbmem_console_p->buffer_body,
+	       copy_size);
+
+	cursor += copy_size;
+
+	if (overflow) {
+		const char loss_str1[] = "\n\n*** Log truncated, ";
+		const char loss_str2[] = " characters dropped. ***\n\n";
+		u32 dropped_chars = cbmem_console_p->buffer_cursor - copy_size;
+
+		/*
+		 * When running from ROM sprintf is not available, a simple
+		 * itoa implementation is used instead.
+		 */
+		int got_first_digit = 0;
+
+		/* Way more than possible number of dropped characters. */
+		u32 mult = 100000;
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str1);
+		cursor += sizeof(loss_str1) - 1;
+
+		while (mult) {
+			int digit = dropped_chars / mult;
+			if (got_first_digit || digit) {
+				new_cons_p->buffer_body[cursor++] = digit + '0';
+				dropped_chars %= mult;
+				/* Excessive, but keeps it simple */
+				got_first_digit = 1;
+			}
+			mult /= 10;
+		}
+
+		strcpy((char *)new_cons_p->buffer_body + cursor, loss_str2);
+		cursor += sizeof(loss_str2) - 1;
+	}
+	new_cons_p->buffer_cursor = cursor;
+}
+
+void cbmemc_reinit(void)
+{
+	struct cbmem_console *cbm_cons_p;
+
+#ifdef __PRE_RAM__
+	cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE,
+			       CONFIG_CONSOLE_CBMEM_BUFFER_SIZE);
+	if (!cbm_cons_p) {
+		CBMEM_CONSOLE_REDIRECT = NULL;
+		return;
+	}
+
+	cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE -
+		sizeof(struct cbmem_console);
+
+	cbm_cons_p->buffer_cursor = 0;
+
+	copy_console_buffer(cbm_cons_p);
+
+	CBMEM_CONSOLE_REDIRECT = cbm_cons_p;
+#else
+	cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE);
+
+	if (!cbm_cons_p)
+		return;
+
+	copy_console_buffer(cbm_cons_p);
+
+	cbmem_console_p = cbm_cons_p;
+#endif
+}
diff --git a/src/lib/fallback_boot.c b/src/lib/fallback_boot.c
index a8fe377..b5ec6c3 100644
--- a/src/lib/fallback_boot.c
+++ b/src/lib/fallback_boot.c
@@ -28,7 +28,7 @@
 
 void boot_successful(void)
 {
-#if CONFIG_BOOTSPLASH && !CONFIG_COREBOOT_KEEP_FRAMEBUFFER
+#if CONFIG_FRAMEBUFFER_SET_VESA_MODE && !CONFIG_FRAMEBUFFER_KEEP_VESA_MODE
 	void vbe_textmode_console(void);
 
 	vbe_textmode_console();
diff --git a/src/lib/libfdt/Makefile b/src/lib/libfdt/Makefile
new file mode 100644
index 0000000..c965577
--- /dev/null
+++ b/src/lib/libfdt/Makefile
@@ -0,0 +1,50 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)libfdt.o
+
+SOBJS	=
+
+COBJS-libfdt += fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_sw.o fdt_wip.o
+
+COBJS-$(CONFIG_OF_LIBFDT) += $(COBJS-libfdt)
+COBJS-$(CONFIG_FIT) += $(COBJS-libfdt)
+
+
+COBJS	:= $(sort $(COBJS-y))
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/src/lib/libfdt/Makefile.inc b/src/lib/libfdt/Makefile.inc
new file mode 100644
index 0000000..42e1736
--- /dev/null
+++ b/src/lib/libfdt/Makefile.inc
@@ -0,0 +1,10 @@
+ramstage-y += fdt.c
+ramstage-y += fdt_ro.c
+ramstage-y += fdt_rw.c
+ramstage-y += fdt_strerror.c
+ramstage-y += fdt_sw.c
+ramstage-y += fdt_wip.c
+
+romstage-y += fdt_ro.c
+romstage-y += fdt.c
+
diff --git a/src/lib/libfdt/README b/src/lib/libfdt/README
new file mode 100644
index 0000000..e059876
--- /dev/null
+++ b/src/lib/libfdt/README
@@ -0,0 +1,23 @@
+The libfdt functionality was written by David Gibson.  The original
+source came from the git repository:
+
+URL:		git://ozlabs.org/home/dgibson/git/libfdt.git
+
+author		David Gibson <dgibson@sneetch.(none)>
+		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
+committer	David Gibson <dgibson@sneetch.(none)>
+		Fri, 23 Mar 2007 04:16:54 +0000 (15:16 +1100)
+commit		857f54e79f74429af20c2b5ecc00ee98af6a3b8b
+tree		2f648f0f88225a51ded452968d28b4402df8ade0
+parent		07a12a08005f3b5cd9337900a6551e450c07b515
+
+To adapt for u-boot usage, only the applicable files were copied and
+imported into the u-boot git repository.
+Omitted:
+* GPL - u-boot comes with a copy of the GPL license
+* test subdirectory - not directly useful for u-boot
+
+After importing, other customizations were performed.  See the git log
+for details.
+
+Jerry Van Baren
diff --git a/src/lib/libfdt/fdt.c b/src/lib/libfdt/fdt.c
new file mode 100644
index 0000000..4157b21
--- /dev/null
+++ b/src/lib/libfdt/fdt.c
@@ -0,0 +1,226 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+int fdt_check_header(const void *fdt)
+{
+	if (fdt_magic(fdt) == FDT_MAGIC) {
+		/* Complete tree */
+		if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+		if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
+			return -FDT_ERR_BADVERSION;
+	} else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
+		/* Unfinished sequential-write blob */
+		if (fdt_size_dt_struct(fdt) == 0)
+			return -FDT_ERR_BADSTATE;
+	} else {
+		return -FDT_ERR_BADMAGIC;
+	}
+
+	return 0;
+}
+
+const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
+{
+	const char *p;
+
+	if (fdt_version(fdt) >= 0x11)
+		if (((offset + len) < offset)
+		    || ((offset + len) > fdt_size_dt_struct(fdt)))
+			return NULL;
+
+	p = _fdt_offset_ptr(fdt, offset);
+
+	if (p + len < p)
+		return NULL;
+	return p;
+}
+
+uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
+{
+	const uint32_t *tagp, *lenp;
+	uint32_t tag;
+	int offset = startoffset;
+	const char *p;
+
+	*nextoffset = -FDT_ERR_TRUNCATED;
+	tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
+	if (!tagp)
+		return FDT_END; /* premature end */
+	tag = fdt32_to_cpu(*tagp);
+	offset += FDT_TAGSIZE;
+
+	*nextoffset = -FDT_ERR_BADSTRUCTURE;
+	switch (tag) {
+	case FDT_BEGIN_NODE:
+		/* skip name */
+		do {
+			p = fdt_offset_ptr(fdt, offset++, 1);
+		} while (p && (*p != '\0'));
+		if (!p)
+			return FDT_END; /* premature end */
+		break;
+
+	case FDT_PROP:
+		lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
+		if (!lenp)
+			return FDT_END; /* premature end */
+		/* skip-name offset, length and value */
+		offset += sizeof(struct fdt_property) - FDT_TAGSIZE
+			+ fdt32_to_cpu(*lenp);
+		break;
+
+	case FDT_END:
+	case FDT_END_NODE:
+	case FDT_NOP:
+		break;
+
+	default:
+		return FDT_END;
+	}
+
+	if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset))
+		return FDT_END; /* premature end */
+
+	*nextoffset = FDT_TAGALIGN(offset);
+	return tag;
+}
+
+int _fdt_check_node_offset(const void *fdt, int offset)
+{
+	if ((offset < 0) || (offset % FDT_TAGSIZE)
+	    || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
+		return -FDT_ERR_BADOFFSET;
+
+	return offset;
+}
+
+int _fdt_check_prop_offset(const void *fdt, int offset)
+{
+	if ((offset < 0) || (offset % FDT_TAGSIZE)
+	    || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP))
+		return -FDT_ERR_BADOFFSET;
+
+	return offset;
+}
+
+int fdt_next_node(const void *fdt, int offset, int *depth)
+{
+	int nextoffset = 0;
+	uint32_t tag;
+
+	if (offset >= 0)
+		if ((nextoffset = _fdt_check_node_offset(fdt, offset)) < 0)
+			return nextoffset;
+
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_PROP:
+		case FDT_NOP:
+			break;
+
+		case FDT_BEGIN_NODE:
+			if (depth)
+				(*depth)++;
+			break;
+
+		case FDT_END_NODE:
+			if (depth && ((--(*depth)) < 0))
+				return nextoffset;
+			break;
+
+		case FDT_END:
+			if ((nextoffset >= 0)
+			    || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth))
+				return -FDT_ERR_NOTFOUND;
+			else
+				return nextoffset;
+		}
+	} while (tag != FDT_BEGIN_NODE);
+
+	return offset;
+}
+
+const char *_fdt_find_string(const char *strtab, int tabsize, const char *s)
+{
+	int len = strlen(s) + 1;
+	const char *last = strtab + tabsize - len;
+	const char *p;
+
+	for (p = strtab; p <= last; p++)
+		if (memcmp(p, s, len) == 0)
+			return p;
+	return NULL;
+}
+
+int fdt_move(const void *fdt, void *buf, int bufsize)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if (fdt_totalsize(fdt) > bufsize)
+		return -FDT_ERR_NOSPACE;
+
+	memmove(buf, fdt, fdt_totalsize(fdt));
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_ro.c b/src/lib/libfdt/fdt_ro.c
new file mode 100644
index 0000000..bcdc77d
--- /dev/null
+++ b/src/lib/libfdt/fdt_ro.c
@@ -0,0 +1,619 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+static int _fdt_nodename_eq(const void *fdt, int offset,
+			    const char *s, int len)
+{
+	const char *p = fdt_offset_ptr(fdt, offset + FDT_TAGSIZE, len+1);
+
+	if (! p)
+		/* short match */
+		return 0;
+
+	if (memcmp(p, s, len) != 0)
+		return 0;
+
+	if (p[len] == '\0')
+		return 1;
+	else if (!memchr(s, '@', len) && (p[len] == '@'))
+		return 1;
+	else
+		return 0;
+}
+
+const char *fdt_string(const void *fdt, int stroffset)
+{
+	return (const char *)fdt + fdt_off_dt_strings(fdt) + stroffset;
+}
+
+static int _fdt_string_eq(const void *fdt, int stroffset,
+			  const char *s, int len)
+{
+	const char *p = fdt_string(fdt, stroffset);
+
+	return (strlen(p) == len) && (memcmp(p, s, len) == 0);
+}
+
+int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
+{
+	FDT_CHECK_HEADER(fdt);
+	*address = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->address);
+	*size = fdt64_to_cpu(_fdt_mem_rsv(fdt, n)->size);
+	return 0;
+}
+
+int fdt_num_mem_rsv(const void *fdt)
+{
+	int i = 0;
+
+	while (fdt64_to_cpu(_fdt_mem_rsv(fdt, i)->size) != 0)
+		i++;
+	return i;
+}
+
+static int _nextprop(const void *fdt, int offset)
+{
+	uint32_t tag;
+	int nextoffset;
+
+	do {
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+
+		switch (tag) {
+		case FDT_END:
+			if (nextoffset >= 0)
+				return -FDT_ERR_BADSTRUCTURE;
+			else
+				return nextoffset;
+
+		case FDT_PROP:
+			return offset;
+		}
+		offset = nextoffset;
+	} while (tag == FDT_NOP);
+
+	return -FDT_ERR_NOTFOUND;
+}
+
+int fdt_subnode_offset_namelen(const void *fdt, int offset,
+			       const char *name, int namelen)
+{
+	int depth;
+
+	FDT_CHECK_HEADER(fdt);
+
+	for (depth = 0;
+	     (offset >= 0) && (depth >= 0);
+	     offset = fdt_next_node(fdt, offset, &depth))
+		if ((depth == 1)
+		    && _fdt_nodename_eq(fdt, offset, name, namelen))
+			return offset;
+
+	if (depth < 0)
+		return -FDT_ERR_NOTFOUND;
+	return offset; /* error */
+}
+
+int fdt_subnode_offset(const void *fdt, int parentoffset,
+		       const char *name)
+{
+	return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_path_offset(const void *fdt, const char *path)
+{
+	const char *end = path + strlen(path);
+	const char *p = path;
+	int offset = 0;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* see if we have an alias */
+	if (*path != '/') {
+		const char *q = strchr(path, '/');
+
+		if (!q)
+			q = end;
+
+		p = fdt_get_alias_namelen(fdt, p, q - p);
+		if (!p)
+			return -FDT_ERR_BADPATH;
+		offset = fdt_path_offset(fdt, p);
+
+		p = q;
+	}
+
+	while (*p) {
+		const char *q;
+
+		while (*p == '/')
+			p++;
+		if (! *p)
+			return offset;
+		q = strchr(p, '/');
+		if (! q)
+			q = end;
+
+		offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
+		if (offset < 0)
+			return offset;
+
+		p = q;
+	}
+
+	return offset;
+}
+
+const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
+{
+	const struct fdt_node_header *nh = _fdt_offset_ptr(fdt, nodeoffset);
+	int err;
+
+	if (((err = fdt_check_header(fdt)) != 0)
+	    || ((err = _fdt_check_node_offset(fdt, nodeoffset)) < 0))
+			goto fail;
+
+	if (len)
+		*len = strlen(nh->name);
+
+	return nh->name;
+
+ fail:
+	if (len)
+		*len = err;
+	return NULL;
+}
+
+int fdt_first_property_offset(const void *fdt, int nodeoffset)
+{
+	int offset;
+
+	if ((offset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+		return offset;
+
+	return _nextprop(fdt, offset);
+}
+
+int fdt_next_property_offset(const void *fdt, int offset)
+{
+	if ((offset = _fdt_check_prop_offset(fdt, offset)) < 0)
+		return offset;
+
+	return _nextprop(fdt, offset);
+}
+
+const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
+						      int offset,
+						      int *lenp)
+{
+	int err;
+	const struct fdt_property *prop;
+
+	if ((err = _fdt_check_prop_offset(fdt, offset)) < 0) {
+		if (lenp)
+			*lenp = err;
+		return NULL;
+	}
+
+	prop = _fdt_offset_ptr(fdt, offset);
+
+	if (lenp)
+		*lenp = fdt32_to_cpu(prop->len);
+
+	return prop;
+}
+
+const struct fdt_property *fdt_get_property_namelen(const void *fdt,
+						    int offset,
+						    const char *name,
+						    int namelen, int *lenp)
+{
+	for (offset = fdt_first_property_offset(fdt, offset);
+	     (offset >= 0);
+	     (offset = fdt_next_property_offset(fdt, offset))) {
+		const struct fdt_property *prop;
+
+		if (!(prop = fdt_get_property_by_offset(fdt, offset, lenp))) {
+			offset = -FDT_ERR_INTERNAL;
+			break;
+		}
+		if (_fdt_string_eq(fdt, fdt32_to_cpu(prop->nameoff),
+				   name, namelen))
+			return prop;
+	}
+
+	if (lenp)
+		*lenp = offset;
+	return NULL;
+}
+
+const struct fdt_property *fdt_get_property(const void *fdt,
+					    int nodeoffset,
+					    const char *name, int *lenp)
+{
+	return fdt_get_property_namelen(fdt, nodeoffset, name,
+					strlen(name), lenp);
+}
+
+const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
+				const char *name, int namelen, int *lenp)
+{
+	const struct fdt_property *prop;
+
+	prop = fdt_get_property_namelen(fdt, nodeoffset, name, namelen, lenp);
+	if (! prop)
+		return NULL;
+
+	return prop->data;
+}
+
+const void *fdt_getprop_by_offset(const void *fdt, int offset,
+				  const char **namep, int *lenp)
+{
+	const struct fdt_property *prop;
+
+	prop = fdt_get_property_by_offset(fdt, offset, lenp);
+	if (!prop)
+		return NULL;
+	if (namep)
+		*namep = fdt_string(fdt, fdt32_to_cpu(prop->nameoff));
+	return prop->data;
+}
+
+const void *fdt_getprop(const void *fdt, int nodeoffset,
+			const char *name, int *lenp)
+{
+	return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp);
+}
+
+uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
+{
+	const uint32_t *php;
+	int len;
+
+	/* FIXME: This is a bit sub-optimal, since we potentially scan
+	 * over all the properties twice. */
+	php = fdt_getprop(fdt, nodeoffset, "phandle", &len);
+	if (!php || (len != sizeof(*php))) {
+		php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
+		if (!php || (len != sizeof(*php)))
+			return 0;
+	}
+
+	return fdt32_to_cpu(*php);
+}
+
+const char *fdt_get_alias_namelen(const void *fdt,
+				  const char *name, int namelen)
+{
+	int aliasoffset;
+
+	aliasoffset = fdt_path_offset(fdt, "/aliases");
+	if (aliasoffset < 0)
+		return NULL;
+
+	return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
+}
+
+const char *fdt_get_alias(const void *fdt, const char *name)
+{
+	return fdt_get_alias_namelen(fdt, name, strlen(name));
+}
+
+int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
+{
+	int pdepth = 0, p = 0;
+	int offset, depth, namelen;
+	const char *name;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (buflen < 2)
+		return -FDT_ERR_NOSPACE;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		while (pdepth > depth) {
+			do {
+				p--;
+			} while (buf[p-1] != '/');
+			pdepth--;
+		}
+
+		if (pdepth >= depth) {
+			name = fdt_get_name(fdt, offset, &namelen);
+			if (!name)
+				return namelen;
+			if ((p + namelen + 1) <= buflen) {
+				memcpy(buf + p, name, namelen);
+				p += namelen;
+				buf[p++] = '/';
+				pdepth++;
+			}
+		}
+
+		if (offset == nodeoffset) {
+			if (pdepth < (depth + 1))
+				return -FDT_ERR_NOSPACE;
+
+			if (p > 1) /* special case so that root path is "/", not "" */
+				p--;
+			buf[p] = '\0';
+			return 0;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
+				 int supernodedepth, int *nodedepth)
+{
+	int offset, depth;
+	int supernodeoffset = -FDT_ERR_INTERNAL;
+
+	FDT_CHECK_HEADER(fdt);
+
+	if (supernodedepth < 0)
+		return -FDT_ERR_NOTFOUND;
+
+	for (offset = 0, depth = 0;
+	     (offset >= 0) && (offset <= nodeoffset);
+	     offset = fdt_next_node(fdt, offset, &depth)) {
+		if (depth == supernodedepth)
+			supernodeoffset = offset;
+
+		if (offset == nodeoffset) {
+			if (nodedepth)
+				*nodedepth = depth;
+
+			if (supernodedepth > depth)
+				return -FDT_ERR_NOTFOUND;
+			else
+				return supernodeoffset;
+		}
+	}
+
+	if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
+		return -FDT_ERR_BADOFFSET;
+	else if (offset == -FDT_ERR_BADOFFSET)
+		return -FDT_ERR_BADSTRUCTURE;
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_depth(const void *fdt, int nodeoffset)
+{
+	int nodedepth;
+	int err;
+
+	err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);
+	if (err)
+		return (err < 0) ? err : -FDT_ERR_INTERNAL;
+	return nodedepth;
+}
+
+int fdt_parent_offset(const void *fdt, int nodeoffset)
+{
+	int nodedepth = fdt_node_depth(fdt, nodeoffset);
+
+	if (nodedepth < 0)
+		return nodedepth;
+	return fdt_supernode_atdepth_offset(fdt, nodeoffset,
+					    nodedepth - 1, NULL);
+}
+
+int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
+				  const char *propname,
+				  const void *propval, int proplen)
+{
+	int offset;
+	const void *val;
+	int len;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_getprop(), then if that didn't
+	 * find what we want, we scan over them again making our way
+	 * to the next node.  Still it's the easiest to implement
+	 * approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		val = fdt_getprop(fdt, offset, propname, &len);
+		if (val && (len == proplen)
+		    && (memcmp(val, propval, len) == 0))
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
+{
+	int offset;
+
+	if ((phandle == 0) || (phandle == -1))
+		return -FDT_ERR_BADPHANDLE;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we
+	 * potentially scan each property of a node in
+	 * fdt_get_phandle(), then if that didn't find what
+	 * we want, we scan over them again making our way to the next
+	 * node.  Still it's the easiest to implement approach;
+	 * performance can come later. */
+	for (offset = fdt_next_node(fdt, -1, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		if (fdt_get_phandle(fdt, offset) == phandle)
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+static int _fdt_stringlist_contains(const char *strlist, int listlen,
+				    const char *str)
+{
+	int len = strlen(str);
+	const char *p;
+
+	while (listlen >= len) {
+		if (memcmp(str, strlist, len+1) == 0)
+			return 1;
+		p = memchr(strlist, '\0', listlen);
+		if (!p)
+			return 0; /* malformed strlist.. */
+		listlen -= (p-strlist) + 1;
+		strlist = p + 1;
+	}
+	return 0;
+}
+
+int fdt_node_check_compatible(const void *fdt, int nodeoffset,
+			      const char *compatible)
+{
+	const void *prop;
+	int len;
+
+	prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
+	if (!prop)
+		return len;
+	if (_fdt_stringlist_contains(prop, len, compatible))
+		return 0;
+	else
+		return 1;
+}
+
+int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
+				  const char *compatible)
+{
+	int offset, err;
+
+	FDT_CHECK_HEADER(fdt);
+
+	/* FIXME: The algorithm here is pretty horrible: we scan each
+	 * property of a node in fdt_node_check_compatible(), then if
+	 * that didn't find what we want, we scan over them again
+	 * making our way to the next node.  Still it's the easiest to
+	 * implement approach; performance can come later. */
+	for (offset = fdt_next_node(fdt, startoffset, NULL);
+	     offset >= 0;
+	     offset = fdt_next_node(fdt, offset, NULL)) {
+		err = fdt_node_check_compatible(fdt, offset, compatible);
+		if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
+			return err;
+		else if (err == 0)
+			return offset;
+	}
+
+	return offset; /* error from fdt_next_node() */
+}
+
+static int ascii_to_hex(char c)
+{
+	if ((c >= '0') && (c <= '9'))
+		return c - '0';
+
+	if (c > 'F')
+		c -= 'a' - 'A';
+
+	if ((c >= 'A') && (c <= 'F'))
+		return c - 'A' + 10;
+
+	return -1;
+}
+
+int fdt_get_base_addr(const void *fdt, int offset, u64 *base_addr)
+{
+	const char *fmap_node_name, *fmap_base_addr;
+	u64 addr = 0;
+	int len;
+
+	fmap_node_name = fdt_get_name(fdt, offset, &len);
+	if (!fmap_node_name)
+		return -1;
+
+	fmap_base_addr = memchr(fmap_node_name, '@', len);
+	if (!fmap_base_addr++)
+		return -1;
+
+	// get the address representnation length
+	len -= fmap_base_addr - fmap_node_name;
+	while (len--) {
+		int nibble = ascii_to_hex(*fmap_base_addr++);
+		if (nibble < 0)
+			return -1;
+		addr <<= 4;
+		addr += nibble;
+	}
+	*base_addr = addr;
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_rw.c b/src/lib/libfdt/fdt_rw.c
new file mode 100644
index 0000000..ca21059
--- /dev/null
+++ b/src/lib/libfdt/fdt_rw.c
@@ -0,0 +1,469 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+static int _fdt_blocks_misordered(const void *fdt,
+			      int mem_rsv_size, int struct_size)
+{
+	return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
+		|| (fdt_off_dt_struct(fdt) <
+		    (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
+		|| (fdt_off_dt_strings(fdt) <
+		    (fdt_off_dt_struct(fdt) + struct_size))
+		|| (fdt_totalsize(fdt) <
+		    (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
+}
+
+static int _fdt_rw_check_header(void *fdt)
+{
+	FDT_CHECK_HEADER(fdt);
+
+	if (fdt_version(fdt) < 17)
+		return -FDT_ERR_BADVERSION;
+	if (_fdt_blocks_misordered(fdt, sizeof(struct fdt_reserve_entry),
+				   fdt_size_dt_struct(fdt)))
+		return -FDT_ERR_BADLAYOUT;
+	if (fdt_version(fdt) > 17)
+		fdt_set_version(fdt, 17);
+
+	return 0;
+}
+
+#define FDT_RW_CHECK_HEADER(fdt) \
+	{ \
+		int _err; \
+		if ((_err = _fdt_rw_check_header(fdt)) != 0) \
+			return _err; \
+	}
+
+static inline int _fdt_data_size(void *fdt)
+{
+	return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+}
+
+static int _fdt_splice(void *fdt, void *splicepoint, int oldlen, int newlen)
+{
+	char *p = splicepoint;
+	char *end = (char *)fdt + _fdt_data_size(fdt);
+
+	if (((p + oldlen) < p) || ((p + oldlen) > end))
+		return -FDT_ERR_BADOFFSET;
+	if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
+		return -FDT_ERR_NOSPACE;
+	memmove(p + newlen, p + oldlen, end - p - oldlen);
+	return 0;
+}
+
+static int _fdt_splice_mem_rsv(void *fdt, struct fdt_reserve_entry *p,
+			       int oldn, int newn)
+{
+	int delta = (newn - oldn) * sizeof(*p);
+	int err;
+	err = _fdt_splice(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
+	if (err)
+		return err;
+	fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_struct(void *fdt, void *p,
+			      int oldlen, int newlen)
+{
+	int delta = newlen - oldlen;
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, oldlen, newlen)))
+		return err;
+
+	fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
+	fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
+	return 0;
+}
+
+static int _fdt_splice_string(void *fdt, int newlen)
+{
+	void *p = (char *)fdt
+		+ fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
+	int err;
+
+	if ((err = _fdt_splice(fdt, p, 0, newlen)))
+		return err;
+
+	fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
+	return 0;
+}
+
+static int _fdt_find_add_string(void *fdt, const char *s)
+{
+	char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
+	const char *p;
+	char *new;
+	int len = strlen(s) + 1;
+	int err;
+
+	p = _fdt_find_string(strtab, fdt_size_dt_strings(fdt), s);
+	if (p)
+		/* found it */
+		return (p - strtab);
+
+	new = strtab + fdt_size_dt_strings(fdt);
+	err = _fdt_splice_string(fdt, len);
+	if (err)
+		return err;
+
+	memcpy(new, s, len);
+	return (new - strtab);
+}
+
+int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)
+{
+	struct fdt_reserve_entry *re;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	re = _fdt_mem_rsv_w(fdt, fdt_num_mem_rsv(fdt));
+	err = _fdt_splice_mem_rsv(fdt, re, 0, 1);
+	if (err)
+		return err;
+
+	re->address = cpu_to_fdt64(address);
+	re->size = cpu_to_fdt64(size);
+	return 0;
+}
+
+int fdt_del_mem_rsv(void *fdt, int n)
+{
+	struct fdt_reserve_entry *re = _fdt_mem_rsv_w(fdt, n);
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	if (n >= fdt_num_mem_rsv(fdt))
+		return -FDT_ERR_NOTFOUND;
+
+	err = _fdt_splice_mem_rsv(fdt, re, 1, 0);
+	if (err)
+		return err;
+	return 0;
+}
+
+static int _fdt_resize_property(void *fdt, int nodeoffset, const char *name,
+				int len, struct fdt_property **prop)
+{
+	int oldlen;
+	int err;
+
+	*prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
+	if (! (*prop))
+		return oldlen;
+
+	if ((err = _fdt_splice_struct(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
+				      FDT_TAGALIGN(len))))
+		return err;
+
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+static int _fdt_add_property(void *fdt, int nodeoffset, const char *name,
+			     int len, struct fdt_property **prop)
+{
+	int proplen;
+	int nextoffset;
+	int namestroff;
+	int err;
+
+	if ((nextoffset = _fdt_check_node_offset(fdt, nodeoffset)) < 0)
+		return nextoffset;
+
+	namestroff = _fdt_find_add_string(fdt, name);
+	if (namestroff < 0)
+		return namestroff;
+
+	*prop = _fdt_offset_ptr_w(fdt, nextoffset);
+	proplen = sizeof(**prop) + FDT_TAGALIGN(len);
+
+	err = _fdt_splice_struct(fdt, *prop, 0, proplen);
+	if (err)
+		return err;
+
+	(*prop)->tag = cpu_to_fdt32(FDT_PROP);
+	(*prop)->nameoff = cpu_to_fdt32(namestroff);
+	(*prop)->len = cpu_to_fdt32(len);
+	return 0;
+}
+
+int fdt_set_name(void *fdt, int nodeoffset, const char *name)
+{
+	char *namep;
+	int oldlen, newlen;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
+	if (!namep)
+		return oldlen;
+
+	newlen = strlen(name);
+
+	err = _fdt_splice_struct(fdt, namep, FDT_TAGALIGN(oldlen+1),
+				 FDT_TAGALIGN(newlen+1));
+	if (err)
+		return err;
+
+	memcpy(namep, name, newlen+1);
+	return 0;
+}
+
+int fdt_setprop(void *fdt, int nodeoffset, const char *name,
+		const void *val, int len)
+{
+	struct fdt_property *prop;
+	int err;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	err = _fdt_resize_property(fdt, nodeoffset, name, len, &prop);
+	if (err == -FDT_ERR_NOTFOUND)
+		err = _fdt_add_property(fdt, nodeoffset, name, len, &prop);
+	if (err)
+		return err;
+
+	memcpy(prop->data, val, len);
+	return 0;
+}
+
+int fdt_delprop(void *fdt, int nodeoffset, const char *name)
+{
+	struct fdt_property *prop;
+	int len, proplen;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
+	if (! prop)
+		return len;
+
+	proplen = sizeof(*prop) + FDT_TAGALIGN(len);
+	return _fdt_splice_struct(fdt, prop, proplen, 0);
+}
+
+int fdt_add_subnode_namelen(void *fdt, int parentoffset,
+			    const char *name, int namelen)
+{
+	struct fdt_node_header *nh;
+	int offset, nextoffset;
+	int nodelen;
+	int err;
+	uint32_t tag;
+	uint32_t *endtag;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
+	if (offset >= 0)
+		return -FDT_ERR_EXISTS;
+	else if (offset != -FDT_ERR_NOTFOUND)
+		return offset;
+
+	/* Try to place the new node after the parent's properties */
+	fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
+	do {
+		offset = nextoffset;
+		tag = fdt_next_tag(fdt, offset, &nextoffset);
+	} while ((tag == FDT_PROP) || (tag == FDT_NOP));
+
+	nh = _fdt_offset_ptr_w(fdt, offset);
+	nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
+
+	err = _fdt_splice_struct(fdt, nh, 0, nodelen);
+	if (err)
+		return err;
+
+	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
+	memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
+	memcpy(nh->name, name, namelen);
+	endtag = (uint32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
+	*endtag = cpu_to_fdt32(FDT_END_NODE);
+
+	return offset;
+}
+
+int fdt_add_subnode(void *fdt, int parentoffset, const char *name)
+{
+	return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));
+}
+
+int fdt_del_node(void *fdt, int nodeoffset)
+{
+	int endoffset;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	endoffset = _fdt_node_end_offset(fdt, nodeoffset);
+	if (endoffset < 0)
+		return endoffset;
+
+	return _fdt_splice_struct(fdt, _fdt_offset_ptr_w(fdt, nodeoffset),
+				  endoffset - nodeoffset, 0);
+}
+
+static void _fdt_packblocks(const char *old, char *new,
+			    int mem_rsv_size, int struct_size)
+{
+	int mem_rsv_off, struct_off, strings_off;
+
+	mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
+	struct_off = mem_rsv_off + mem_rsv_size;
+	strings_off = struct_off + struct_size;
+
+	memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);
+	fdt_set_off_mem_rsvmap(new, mem_rsv_off);
+
+	memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);
+	fdt_set_off_dt_struct(new, struct_off);
+	fdt_set_size_dt_struct(new, struct_size);
+
+	memmove(new + strings_off, old + fdt_off_dt_strings(old),
+		fdt_size_dt_strings(old));
+	fdt_set_off_dt_strings(new, strings_off);
+	fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));
+}
+
+int fdt_open_into(const void *fdt, void *buf, int bufsize)
+{
+	int err;
+	int mem_rsv_size, struct_size;
+	int newsize;
+	const char *fdtstart = fdt;
+	const char *fdtend = fdtstart + fdt_totalsize(fdt);
+	char *tmp;
+
+	FDT_CHECK_HEADER(fdt);
+
+	mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
+		* sizeof(struct fdt_reserve_entry);
+
+	if (fdt_version(fdt) >= 17) {
+		struct_size = fdt_size_dt_struct(fdt);
+	} else {
+		struct_size = 0;
+		while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END)
+			;
+		if (struct_size < 0)
+			return struct_size;
+	}
+
+	if (!_fdt_blocks_misordered(fdt, mem_rsv_size, struct_size)) {
+		/* no further work necessary */
+		err = fdt_move(fdt, buf, bufsize);
+		if (err)
+			return err;
+		fdt_set_version(buf, 17);
+		fdt_set_size_dt_struct(buf, struct_size);
+		fdt_set_totalsize(buf, bufsize);
+		return 0;
+	}
+
+	/* Need to reorder */
+	newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
+		+ struct_size + fdt_size_dt_strings(fdt);
+
+	if (bufsize < newsize)
+		return -FDT_ERR_NOSPACE;
+
+	/* First attempt to build converted tree at beginning of buffer */
+	tmp = buf;
+	/* But if that overlaps with the old tree... */
+	if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) {
+		/* Try right after the old tree instead */
+		tmp = (char *)(uintptr_t)fdtend;
+		if ((tmp + newsize) > ((char *)buf + bufsize))
+			return -FDT_ERR_NOSPACE;
+	}
+
+	_fdt_packblocks(fdt, tmp, mem_rsv_size, struct_size);
+	memmove(buf, tmp, newsize);
+
+	fdt_set_magic(buf, FDT_MAGIC);
+	fdt_set_totalsize(buf, bufsize);
+	fdt_set_version(buf, 17);
+	fdt_set_last_comp_version(buf, 16);
+	fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt));
+
+	return 0;
+}
+
+int fdt_pack(void *fdt)
+{
+	int mem_rsv_size;
+
+	FDT_RW_CHECK_HEADER(fdt);
+
+	mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
+		* sizeof(struct fdt_reserve_entry);
+	_fdt_packblocks(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
+	fdt_set_totalsize(fdt, _fdt_data_size(fdt));
+
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_strerror.c b/src/lib/libfdt/fdt_strerror.c
new file mode 100644
index 0000000..9b00c3a
--- /dev/null
+++ b/src/lib/libfdt/fdt_strerror.c
@@ -0,0 +1,100 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+struct fdt_errtabent {
+	const char *str;
+};
+
+#define FDT_ERRTABENT(val) \
+	[(val)] = { .str = #val, }
+
+static struct fdt_errtabent fdt_errtable[] = {
+	FDT_ERRTABENT(FDT_ERR_NOTFOUND),
+	FDT_ERRTABENT(FDT_ERR_EXISTS),
+	FDT_ERRTABENT(FDT_ERR_NOSPACE),
+
+	FDT_ERRTABENT(FDT_ERR_BADOFFSET),
+	FDT_ERRTABENT(FDT_ERR_BADPATH),
+	FDT_ERRTABENT(FDT_ERR_BADSTATE),
+
+	FDT_ERRTABENT(FDT_ERR_TRUNCATED),
+	FDT_ERRTABENT(FDT_ERR_BADMAGIC),
+	FDT_ERRTABENT(FDT_ERR_BADVERSION),
+	FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
+	FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
+};
+#define FDT_ERRTABSIZE	(sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))
+
+const char *fdt_strerror(int errval)
+{
+	if (errval > 0)
+		return "<valid offset/length>";
+	else if (errval == 0)
+		return "<no error>";
+	else if (errval > -FDT_ERRTABSIZE) {
+		const char *s = fdt_errtable[-errval].str;
+
+		if (s)
+			return s;
+	}
+
+	return "<unknown error>";
+}
diff --git a/src/lib/libfdt/fdt_sw.c b/src/lib/libfdt/fdt_sw.c
new file mode 100644
index 0000000..55ebebf
--- /dev/null
+++ b/src/lib/libfdt/fdt_sw.c
@@ -0,0 +1,256 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#include <fdt.h>
+#include <libfdt.h>
+
+#include "libfdt_internal.h"
+
+static int _fdt_sw_check_header(void *fdt)
+{
+	if (fdt_magic(fdt) != FDT_SW_MAGIC)
+		return -FDT_ERR_BADMAGIC;
+	/* FIXME: should check more details about the header state */
+	return 0;
+}
+
+#define FDT_SW_CHECK_HEADER(fdt) \
+	{ \
+		int err; \
+		if ((err = _fdt_sw_check_header(fdt)) != 0) \
+			return err; \
+	}
+
+static void *_fdt_grab_space(void *fdt, size_t len)
+{
+	int offset = fdt_size_dt_struct(fdt);
+	int spaceleft;
+
+	spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt)
+		- fdt_size_dt_strings(fdt);
+
+	if ((offset + len < offset) || (offset + len > spaceleft))
+		return NULL;
+
+	fdt_set_size_dt_struct(fdt, offset + len);
+	return _fdt_offset_ptr_w(fdt, offset);
+}
+
+int fdt_create(void *buf, int bufsize)
+{
+	void *fdt = buf;
+
+	if (bufsize < sizeof(struct fdt_header))
+		return -FDT_ERR_NOSPACE;
+
+	memset(buf, 0, bufsize);
+
+	fdt_set_magic(fdt, FDT_SW_MAGIC);
+	fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION);
+	fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION);
+	fdt_set_totalsize(fdt,  bufsize);
+
+	fdt_set_off_mem_rsvmap(fdt, FDT_ALIGN(sizeof(struct fdt_header),
+					      sizeof(struct fdt_reserve_entry)));
+	fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt));
+	fdt_set_off_dt_strings(fdt, bufsize);
+
+	return 0;
+}
+
+int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size)
+{
+	struct fdt_reserve_entry *re;
+	int offset;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	if (fdt_size_dt_struct(fdt))
+		return -FDT_ERR_BADSTATE;
+
+	offset = fdt_off_dt_struct(fdt);
+	if ((offset + sizeof(*re)) > fdt_totalsize(fdt))
+		return -FDT_ERR_NOSPACE;
+
+	re = (struct fdt_reserve_entry *)((char *)fdt + offset);
+	re->address = cpu_to_fdt64(addr);
+	re->size = cpu_to_fdt64(size);
+
+	fdt_set_off_dt_struct(fdt, offset + sizeof(*re));
+
+	return 0;
+}
+
+int fdt_finish_reservemap(void *fdt)
+{
+	return fdt_add_reservemap_entry(fdt, 0, 0);
+}
+
+int fdt_begin_node(void *fdt, const char *name)
+{
+	struct fdt_node_header *nh;
+	int namelen = strlen(name) + 1;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	nh = _fdt_grab_space(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen));
+	if (! nh)
+		return -FDT_ERR_NOSPACE;
+
+	nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
+	memcpy(nh->name, name, namelen);
+	return 0;
+}
+
+int fdt_end_node(void *fdt)
+{
+	uint32_t *en;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	en = _fdt_grab_space(fdt, FDT_TAGSIZE);
+	if (! en)
+		return -FDT_ERR_NOSPACE;
+
+	*en = cpu_to_fdt32(FDT_END_NODE);
+	return 0;
+}
+
+static int _fdt_find_add_string(void *fdt, const char *s)
+{
+	char *strtab = (char *)fdt + fdt_totalsize(fdt);
+	const char *p;
+	int strtabsize = fdt_size_dt_strings(fdt);
+	int len = strlen(s) + 1;
+	int struct_top, offset;
+
+	p = _fdt_find_string(strtab - strtabsize, strtabsize, s);
+	if (p)
+		return p - strtab;
+
+	/* Add it */
+	offset = -strtabsize - len;
+	struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
+	if (fdt_totalsize(fdt) + offset < struct_top)
+		return 0; /* no more room :( */
+
+	memcpy(strtab + offset, s, len);
+	fdt_set_size_dt_strings(fdt, strtabsize + len);
+	return offset;
+}
+
+int fdt_property(void *fdt, const char *name, const void *val, int len)
+{
+	struct fdt_property *prop;
+	int nameoff;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	nameoff = _fdt_find_add_string(fdt, name);
+	if (nameoff == 0)
+		return -FDT_ERR_NOSPACE;
+
+	prop = _fdt_grab_space(fdt, sizeof(*prop) + FDT_TAGALIGN(len));
+	if (! prop)
+		return -FDT_ERR_NOSPACE;
+
+	prop->tag = cpu_to_fdt32(FDT_PROP);
+	prop->nameoff = cpu_to_fdt32(nameoff);
+	prop->len = cpu_to_fdt32(len);
+	memcpy(prop->data, val, len);
+	return 0;
+}
+
+int fdt_finish(void *fdt)
+{
+	char *p = (char *)fdt;
+	uint32_t *end;
+	int oldstroffset, newstroffset;
+	uint32_t tag;
+	int offset, nextoffset;
+
+	FDT_SW_CHECK_HEADER(fdt);
+
+	/* Add terminator */
+	end = _fdt_grab_space(fdt, sizeof(*end));
+	if (! end)
+		return -FDT_ERR_NOSPACE;
+	*end = cpu_to_fdt32(FDT_END);
+
+	/* Relocate the string table */
+	oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt);
+	newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
+	memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt));
+	fdt_set_off_dt_strings(fdt, newstroffset);
+
+	/* Walk the structure, correcting string offsets */
+	offset = 0;
+	while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) {
+		if (tag == FDT_PROP) {
+			struct fdt_property *prop =
+				_fdt_offset_ptr_w(fdt, offset);
+			int nameoff;
+
+			nameoff = fdt32_to_cpu(prop->nameoff);
+			nameoff += fdt_size_dt_strings(fdt);
+			prop->nameoff = cpu_to_fdt32(nameoff);
+		}
+		offset = nextoffset;
+	}
+	if (nextoffset < 0)
+		return nextoffset;
+
+	/* Finally, adjust the header */
+	fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt));
+	fdt_set_magic(fdt, FDT_MAGIC);
+	return 0;
+}
diff --git a/src/lib/libfdt/fdt_wip.c b/src/lib/libfdt/fdt_wip.c
new file mode 100644
index 0000000..e373677
--- /dev/null
+++ b/src/lib/libfdt/fdt_wip.c
@@ -0,0 +1,122 @@
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "libfdt_env.h"
+
+#ifndef USE_HOSTCC
+#include <fdt.h>
+#include <libfdt.h>
+#else
+#include "fdt_host.h"
+#endif
+
+#include "libfdt_internal.h"
+
+int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
+			const void *val, int len)
+{
+	void *propval;
+	int proplen;
+
+	propval = fdt_getprop_w(fdt, nodeoffset, name, &proplen);
+	if (! propval)
+		return proplen;
+
+	if (proplen != len)
+		return -FDT_ERR_NOSPACE;
+
+	memcpy(propval, val, len);
+	return 0;
+}
+
+static void _fdt_nop_region(void *start, int len)
+{
+	uint32_t *p;
+
+	for (p = start; (char *)p < ((char *)start + len); p++)
+		*p = cpu_to_fdt32(FDT_NOP);
+}
+
+int fdt_nop_property(void *fdt, int nodeoffset, const char *name)
+{
+	struct fdt_property *prop;
+	int len;
+
+	prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
+	if (! prop)
+		return len;
+
+	_fdt_nop_region(prop, len + sizeof(*prop));
+
+	return 0;
+}
+
+int _fdt_node_end_offset(void *fdt, int offset)
+{
+	int depth = 0;
+
+	while ((offset >= 0) && (depth >= 0))
+		offset = fdt_next_node(fdt, offset, &depth);
+
+	return offset;
+}
+
+int fdt_nop_node(void *fdt, int nodeoffset)
+{
+	int endoffset;
+
+	endoffset = _fdt_node_end_offset(fdt, nodeoffset);
+	if (endoffset < 0)
+		return endoffset;
+
+	_fdt_nop_region(fdt_offset_ptr_w(fdt, nodeoffset, 0),
+			endoffset - nodeoffset);
+	return 0;
+}
diff --git a/src/lib/libfdt/libfdt_internal.h b/src/lib/libfdt/libfdt_internal.h
new file mode 100644
index 0000000..e8358a2
--- /dev/null
+++ b/src/lib/libfdt/libfdt_internal.h
@@ -0,0 +1,95 @@
+#ifndef _LIBFDT_INTERNAL_H
+#define _LIBFDT_INTERNAL_H
+/*
+ * libfdt - Flat Device Tree manipulation
+ * Copyright (C) 2006 David Gibson, IBM Corporation.
+ *
+ * libfdt is dual licensed: you can use it either under the terms of
+ * the GPL, or the BSD license, at your option.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Alternatively,
+ *
+ *  b) Redistribution and use in source and binary forms, with or
+ *     without modification, are permitted provided that the following
+ *     conditions are met:
+ *
+ *     1. Redistributions of source code must retain the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer.
+ *     2. Redistributions in binary form must reproduce the above
+ *        copyright notice, this list of conditions and the following
+ *        disclaimer in the documentation and/or other materials
+ *        provided with the distribution.
+ *
+ *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
+ *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
+ *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <fdt.h>
+
+#define FDT_ALIGN(x, a)		(((x) + (a) - 1) & ~((a) - 1))
+#define FDT_TAGALIGN(x)		(FDT_ALIGN((x), FDT_TAGSIZE))
+
+#define FDT_CHECK_HEADER(fdt) \
+	{ \
+		int _err; \
+		if ((_err = fdt_check_header(fdt)) != 0) \
+			return _err; \
+	}
+
+int _fdt_check_node_offset(const void *fdt, int offset);
+int _fdt_check_prop_offset(const void *fdt, int offset);
+const char *_fdt_find_string(const char *strtab, int tabsize, const char *s);
+int _fdt_node_end_offset(void *fdt, int nodeoffset);
+
+static inline const void *_fdt_offset_ptr(const void *fdt, int offset)
+{
+	return (const char *)fdt + fdt_off_dt_struct(fdt) + offset;
+}
+
+static inline void *_fdt_offset_ptr_w(void *fdt, int offset)
+{
+	return (void *)(uintptr_t)_fdt_offset_ptr(fdt, offset);
+}
+
+static inline const struct fdt_reserve_entry *_fdt_mem_rsv(const void *fdt, int n)
+{
+	const struct fdt_reserve_entry *rsv_table =
+		(const struct fdt_reserve_entry *)
+		((const char *)fdt + fdt_off_mem_rsvmap(fdt));
+
+	return rsv_table + n;
+}
+static inline struct fdt_reserve_entry *_fdt_mem_rsv_w(void *fdt, int n)
+{
+	return (void *)(uintptr_t)_fdt_mem_rsv(fdt, n);
+}
+
+#define FDT_SW_MAGIC		(~FDT_MAGIC)
+
+#endif /* _LIBFDT_INTERNAL_H */
diff --git a/src/lib/memchr.c b/src/lib/memchr.c
new file mode 100644
index 0000000..a890dce
--- /dev/null
+++ b/src/lib/memchr.c
@@ -0,0 +1,11 @@
+#include <string.h>
+void *memchr(const void *s, int c, size_t n)
+{
+	const unsigned char *sc = s;
+	while (n--) {
+		if (*sc == (unsigned char)c)
+			return (void *)sc;
+		sc++;
+	}
+	return NULL;
+}
diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c
new file mode 100644
index 0000000..bbb8197d
--- /dev/null
+++ b/src/lib/timestamp.c
@@ -0,0 +1,74 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <cbmem.h>
+#include <timestamp.h>
+
+#define MAX_TIMESTAMPS 30
+
+#ifndef __PRE_RAM__
+static struct timestamp_table* ts_table;
+#endif
+
+static uint64_t tsc_to_uint64(tsc_t tstamp)
+{
+	return (((uint64_t)tstamp.hi) << 32) + tstamp.lo;
+}
+
+void timestamp_init(tsc_t base)
+{
+	struct timestamp_table* tst;
+
+	tst = cbmem_add(CBMEM_ID_TIMESTAMP,
+			sizeof(struct timestamp_table) +
+			MAX_TIMESTAMPS * sizeof(struct timestamp_entry));
+
+	if (!tst) {
+		printk(BIOS_ERR, "ERROR: failed to allocate timstamp table\n");
+		return;
+	}
+
+	tst->base_time = tsc_to_uint64(base);
+	tst->max_entries = MAX_TIMESTAMPS;
+	tst->num_entries = 0;
+}
+
+void timestamp_add(enum timestamp_id id, tsc_t ts_time)
+{
+	struct timestamp_entry *tse;
+#ifdef __PRE_RAM__
+	struct timestamp_table *ts_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+#else
+	if (!ts_table)
+		ts_table = cbmem_find(CBMEM_ID_TIMESTAMP);
+#endif
+	if (!ts_table || (ts_table->num_entries == ts_table->max_entries))
+		return;
+
+	tse = &ts_table->entries[ts_table->num_entries++];
+	tse->entry_id = id;
+	tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time;
+}
+
+void timestamp_add_now(enum timestamp_id id)
+{
+	timestamp_add(id, rdtsc());
+}
diff --git a/src/lib/uart8250mem.c b/src/lib/uart8250mem.c
index 918308e..0635a96 100644
--- a/src/lib/uart8250mem.c
+++ b/src/lib/uart8250mem.c
@@ -114,6 +114,8 @@
 
 #if defined(MORE_TESTING) && !defined(__SMM__) && !defined(__PRE_RAM__)
 	device_t dev = dev_find_device(0x1415, 0xc158, NULL);
+	if (!dev)
+		dev = dev_find_device(0x1415, 0xc11b, NULL);
 
 	if (dev) {
 		struct resource *res = find_resource(dev, 0x10);
diff --git a/src/lib/usbdebug.c b/src/lib/usbdebug.c
index d022d2f..175da36 100644
--- a/src/lib/usbdebug.c
+++ b/src/lib/usbdebug.c
@@ -575,17 +575,38 @@
 
 	return usbdebug_init(CONFIG_EHCI_BAR, CONFIG_EHCI_DEBUG_OFFSET, dbg_info);
 }
+#endif /* __PRE_RAM__ */
 
+#if defined(__PRE_RAM__) || defined(__SMM__)
 void usbdebug_tx_byte(unsigned char data)
 {
+	/* SMM needs some extra love. Define an empty function for now */
+#ifndef __SMM__
 	struct ehci_debug_info *dbg_info;
 
+#if CONFIG_ARCH_X86
+	/* XXX hack alert XXX */
+	/* XXX this should be done differently, or at least be moved */
+
 	/* "Find" dbg_info structure in Cache */
+	u32 esp = 0;
+	asm volatile ("movl %%esp, %%eax\n" : "=a" (esp) );
+
+	if (esp < CONFIG_RAMTOP) {
+		dbg_info = (struct ehci_debug_info *)((CONFIG_RAMTOP) - sizeof(struct ehci_debug_info));
+	} else {
+		dbg_info = (struct ehci_debug_info *)
+			(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info));
+	}
+#else
 	dbg_info = (struct ehci_debug_info *)
 	    (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - sizeof(struct ehci_debug_info));
 
+#endif
+
 	if (dbg_info->ehci_debug) {
 		dbgp_bulk_write_x(dbg_info, (char*)&data, 1);
 	}
+#endif
 }
 #endif
diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index 1a6f3941..444b50d 100644
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -44,10 +44,14 @@
 	bool "ECS"
 config VENDOR_EMULATION
 	bool "Emulation"
+config VENDOR_EVOC
+	bool "Evoc"
 config VENDOR_GETAC
 	bool "Getac"
 config VENDOR_GIGABYTE
 	bool "GIGABYTE"
+config VENDOR_GOOGLE
+	bool "Google"
 config VENDOR_HP
 	bool "HP"
 config VENDOR_IBASE
@@ -90,6 +94,8 @@
 	bool "RCA"
 config VENDOR_RODA
 	bool "Roda"
+config VENDOR_SAMSUNG
+	bool "SAMSUNG"
 config VENDOR_SOYO
 	bool "Soyo"
 config VENDOR_SUNW
@@ -137,6 +143,7 @@
 source "src/mainboard/eaglelion/Kconfig"
 source "src/mainboard/ecs/Kconfig"
 source "src/mainboard/emulation/Kconfig"
+source "src/mainboard/evoc/Kconfig"
 source "src/mainboard/getac/Kconfig"
 source "src/mainboard/gigabyte/Kconfig"
 source "src/mainboard/hp/Kconfig"
@@ -160,6 +167,7 @@
 source "src/mainboard/pcengines/Kconfig"
 source "src/mainboard/rca/Kconfig"
 source "src/mainboard/roda/Kconfig"
+source "src/mainboard/samsung/Kconfig"
 source "src/mainboard/soyo/Kconfig"
 source "src/mainboard/sunw/Kconfig"
 source "src/mainboard/supermicro/Kconfig"
diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index 1899648..3f22437 100644
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -9,6 +9,7 @@
 #include <bitops.h>
 #include "chip.h"
 #include <delay.h>
+#include <smbios.h>
 
 #if CONFIG_WRITE_HIGH_TABLES==1
 #include <cbmem.h>
@@ -19,18 +20,24 @@
 #define HIGH_RAM_ADDR 0x35
 #define LOW_RAM_ADDR 0x34
 
+static unsigned long qemu_get_memory_size(void)
+{
+	unsigned long tomk;
+	outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT);
+	tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
+	outb (LOW_RAM_ADDR, CMOS_ADDR_PORT);
+	tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
+	tomk += 16 * 1024;
+	return tomk;
+}
+
 static void cpu_pci_domain_set_resources(device_t dev)
 {
 	u32 pci_tolm = find_pci_tolm(dev->link_list);
 	unsigned long tomk = 0, tolmk;
 	int idx;
 
-	outb (HIGH_RAM_ADDR, CMOS_ADDR_PORT);
-	tomk = ((unsigned long) inb(CMOS_DATA_PORT)) << 14;
-	outb (LOW_RAM_ADDR, CMOS_ADDR_PORT);
-	tomk |= ((unsigned long) inb(CMOS_DATA_PORT)) << 6;
-	tomk += 16 * 1024;
-
+	tomk = qemu_get_memory_size();
 	printk(BIOS_DEBUG, "Detected %lu Kbytes (%lu MiB) RAM.\n",
 	       tomk, tomk / 1024);
 
@@ -80,12 +87,67 @@
 		     IORESOURCE_ASSIGNED;
 }
 
+#if CONFIG_GENERATE_SMBIOS_TABLES
+static int qemu_get_smbios_data16(int handle, unsigned long *current)
+{
+	struct smbios_type16 *t = (struct smbios_type16 *)*current;
+	int len = sizeof(struct smbios_type16);
+
+	memset(t, 0, sizeof(struct smbios_type16));
+	t->type = SMBIOS_PHYS_MEMORY_ARRAY;
+	t->handle = handle;
+	t->length = len - 2;
+	t->location = 3; /* Location: System Board */
+	t->use = 3; /* System memory */
+	t->memory_error_correction = 3; /* No error correction */
+	t->maximum_capacity = qemu_get_memory_size();
+	*current += len;
+	return len;
+}
+
+static int qemu_get_smbios_data17(int handle, int parent_handle, unsigned long *current)
+{
+	struct smbios_type17 *t = (struct smbios_type17 *)*current;
+	int len;
+
+	memset(t, 0, sizeof(struct smbios_type17));
+	t->type = SMBIOS_MEMORY_DEVICE;
+	t->handle = handle;
+	t->phys_memory_array_handle = parent_handle;
+	t->length = sizeof(struct smbios_type17) - 2;
+	t->size = qemu_get_memory_size() / 1024;
+	t->data_width = 64;
+	t->total_width = 64;
+	t->form_factor = 9; /* DIMM */
+	t->device_locator = smbios_add_string(t->eos, "Virtual");
+	t->memory_type = 0x12; /* DDR */
+	t->type_detail = 0x80; /* Synchronous */
+	t->speed = 200;
+	t->clock_speed = 200;
+	t->manufacturer = smbios_add_string(t->eos, CONFIG_MAINBOARD_VENDOR);
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	return len;
+}
+
+static int qemu_get_smbios_data(device_t dev, int *handle, unsigned long *current)
+{
+	int len;
+	len = qemu_get_smbios_data16(*handle, current);
+	len += qemu_get_smbios_data17(*handle+1, *handle, current);
+	*handle += 2;
+	return len;
+}
+#endif
 static struct device_operations pci_domain_ops = {
 	.read_resources		= cpu_pci_domain_read_resources,
 	.set_resources		= cpu_pci_domain_set_resources,
 	.enable_resources	= NULL,
 	.init			= NULL,
 	.scan_bus		= pci_domain_scan_bus,
+#if CONFIG_GENERATE_SMBIOS_TABLES
+	.get_smbios_data	= qemu_get_smbios_data,
+#endif
 };
 
 static void enable_dev(struct device *dev)
diff --git a/src/mainboard/evoc/Kconfig b/src/mainboard/evoc/Kconfig
new file mode 100644
index 0000000..89021a4
--- /dev/null
+++ b/src/mainboard/evoc/Kconfig
@@ -0,0 +1,17 @@
+if VENDOR_EVOC
+
+choice
+	prompt "Mainboard model"
+
+config BOARD_EVOC_MEC_7003
+	bool "MEC-7003"
+
+endchoice
+
+source "src/mainboard/evoc/mec-7003/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "Evoc"
+
+endif # VENDOR_EVOC
diff --git a/src/mainboard/evoc/mec-7003/Kconfig b/src/mainboard/evoc/mec-7003/Kconfig
new file mode 100644
index 0000000..14de9a8
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/Kconfig
@@ -0,0 +1,56 @@
+if BOARD_EVOC_MEC_7003
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_NUVOTON_NCT6776F
+	select SUPERIO_SMSC_FDC37N972
+	select BOARD_HAS_FADT
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select MMCONF_SUPPORT
+	select HAVE_SMI_HANDLER
+	select BOARD_ROMSIZE_KB_2048
+	select GFXUMA
+
+config MAINBOARD_DIR
+	string
+	default evoc/mec-7003
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "MEC-7003"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,a011.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0xc000
+
+endif # BOARD_EVOC_MEC_7003
diff --git a/src/mainboard/evoc/mec-7003/Makefile.inc b/src/mainboard/evoc/mec-7003/Makefile.inc
new file mode 100644
index 0000000..3fe4c11
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
diff --git a/src/mainboard/evoc/mec-7003/acpi/ec.asl b/src/mainboard/evoc/mec-7003/acpi/ec.asl
new file mode 100644
index 0000000..931d23c
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/acpi/ec.asl
@@ -0,0 +1,49 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device(EC0)
+{
+	Name (_HID, EISAID("PNP0C09"))
+	Name (_UID, 1)
+
+	Method (_CRS, 0)
+	{
+		Name (ECMD, ResourceTemplate()
+		{
+			IO (Decode16, 0x62, 0x62, 0, 1)
+			IO (Decode16, 0x66, 0x66, 0, 1)
+		})
+
+		Return (ECMD)
+	}
+
+	Method (_REG, 2)
+	{
+		// This method is needed by Windows XP/2000
+		// for EC initialization before a driver
+		// is loaded
+	}
+
+	Name (_GPE, 22)	// GPE22 -> Runtime SCI
+
+	// TODO EC Query methods
+
+	// TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/evoc/mec-7003/acpi/pch_pci_irqs.asl b/src/mainboard/evoc/mec-7003/acpi/pch_pci_irqs.asl
new file mode 100644
index 0000000..c108d3f
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/acpi/pch_pci_irqs.asl
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+If (PICM) {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, 0, 16},
+
+		Package() { 0x0001ffff, 0, 0, 20},
+		Package() { 0x0001ffff, 1, 0, 21},
+		Package() { 0x0001ffff, 2, 0, 22},
+		Package() { 0x0001ffff, 3, 0, 23},
+
+		Package() { 0x0002ffff, 0, 0, 21},
+		Package() { 0x0002ffff, 1, 0, 22},
+		Package() { 0x0002ffff, 2, 0, 23},
+		Package() { 0x0002ffff, 3, 0, 20},
+
+		Package() { 0x0003ffff, 0, 0, 22},
+		Package() { 0x0003ffff, 1, 0, 23},
+		Package() { 0x0003ffff, 2, 0, 20},
+		Package() { 0x0003ffff, 3, 0, 21},
+
+		Package() { 0x0004ffff, 0, 0, 23},
+		Package() { 0x0004ffff, 1, 0, 20},
+		Package() { 0x0004ffff, 2, 0, 21},
+		Package() { 0x0004ffff, 3, 0, 22},
+
+		Package() { 0x0005ffff, 0, 0, 19},
+		Package() { 0x0005ffff, 1, 0, 18},
+		Package() { 0x0005ffff, 2, 0, 17},
+		Package() { 0x0005ffff, 3, 0, 16},
+
+		Package() { 0x0006ffff, 0, 0, 18},
+		Package() { 0x0006ffff, 1, 0, 17},
+		Package() { 0x0006ffff, 2, 0, 16},
+		Package() { 0x0006ffff, 3, 0, 19},
+
+		Package() { 0x0009ffff, 0, 0, 21},
+		Package() { 0x0009ffff, 1, 0, 22},
+		Package() { 0x0009ffff, 2, 0, 23},
+		Package() { 0x0009ffff, 3, 0, 20},
+	})
+} Else {
+	Return (Package() {
+		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+
+		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKF, 0},
+
+		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKE, 0},
+		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKG, 0},
+
+		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
+		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+
+		Package() { 0x0006ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+		Package() { 0x0006ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+		Package() { 0x0006ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+		Package() { 0x0006ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+
+		Package() { 0x0009ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+		Package() { 0x0009ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+		Package() { 0x0009ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+		Package() { 0x0009ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+	})
+}
+
diff --git a/src/mainboard/evoc/mec-7003/acpi/platform.asl b/src/mainboard/evoc/mec-7003/acpi/platform.asl
new file mode 100644
index 0000000..2e4223c
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/acpi/platform.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	// Call a trap so SMI can prepare for Sleep as well.
+	// TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	// CPU specific part
+
+	// Notify PCI Express slots in case a card
+	// was inserted while a sleep state was active.
+
+	// Are we going to S3?
+	If (LEqual(Arg0, 3)) {
+		// ..
+	}
+
+	// Are we going to S4?
+	If (LEqual(Arg0, 4)) {
+		// ..
+	}
+
+	// TODO: Windows XP SP2 P-State restore
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/evoc/mec-7003/acpi/sandybridge_pci_irqs.asl b/src/mainboard/evoc/mec-7003/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..e466658
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, 0, 16 },
+			Package() { 0x0001ffff, 1, 0, 17 },
+			Package() { 0x0001ffff, 2, 0, 18 },
+			Package() { 0x0001ffff, 3, 0, 19 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 16 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 16 },
+			Package() { 0x001cffff, 1, 0, 17 },
+			Package() { 0x001cffff, 2, 0, 18 },
+			Package() { 0x001cffff, 3, 0, 19 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, 0, 23 },
+			Package() { 0x001dffff, 1, 0, 19 },
+			Package() { 0x001dffff, 2, 0, 18 },
+			Package() { 0x001dffff, 3, 0, 16 },
+			// AC97/IDE				0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, 0, 17 },
+			Package() { 0x001effff, 1, 0, 20 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, 0, 18 },
+			Package() { 0x001fffff, 1, 0, 19},
+		})
+	} Else {
+		Return (Package() {
+			// PCIe Graphics		0:1.0
+			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+			// USB and EHCI			0:1d.x
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+			// AC97/IDE			0:1e.2, 0:1e.3
+			Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+		})
+	}
+}
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/evoc/mec-7003/acpi/superio.asl
similarity index 74%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/evoc/mec-7003/acpi/superio.asl
index 1a4e70f..50f6fa3 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/evoc/mec-7003/acpi/superio.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,7 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
 
diff --git a/src/mainboard/evoc/mec-7003/acpi/thermal.asl b/src/mainboard/evoc/mec-7003/acpi/thermal.asl
new file mode 100644
index 0000000..d1774d4
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/acpi/thermal.asl
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+
+		// FIXME these could/should be read from the
+		// GNVS area, so they can be controlled by
+		// coreboot
+		Name(TC1V, 0x04)
+		Name(TC2V, 0x03)
+		Name(TSPV, 0x64)
+
+		// At which temperature should the OS start
+		// active cooling?
+		Method (_AC0, 0, Serialized)
+		{
+			Return (0xf5c) // Value for Rocky
+		}
+
+		// Method (_AC1, 0, Serialized)
+		// {
+		// 	Return (0xf5c)
+		// }
+
+		// Critical shutdown temperature
+		Method (_CRT, 0, Serialized)
+		{
+			Return (Add (0x0aac, 0x50)) // FIXME
+		}
+
+		// CPU throttling start temperature
+		Method (_PSV, 0, Serialized)
+		{
+			Return (0xaaf) // FIXME
+		}
+
+		// Get DTS Temperature
+		Method (_TMP, 0, Serialized)
+		{
+			Return (0xaac) // FIXME
+		}
+
+		// Processors used for active cooling
+		Method (_PSL, 0, Serialized)
+		{
+			If (MPEN) {
+				Return (Package() {\_PR.CPU1, \_PR.CPU2})
+			}
+			Return (Package() {\_PR.CPU1})
+		}
+
+		// TC1 value for passive cooling
+		Method (_TC1, 0, Serialized)
+		{
+			Return (TC1V)
+		}
+
+		// TC2 value for passive cooling
+		Method (_TC2, 0, Serialized)
+		{
+			Return (TC2V)
+		}
+
+		// Sampling period for passive cooling
+		Method (_TSP, 0, Serialized)
+		{
+			Return (TSPV)
+		}
+
+
+	}
+}
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/evoc/mec-7003/acpi/video.asl
similarity index 60%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/evoc/mec-7003/acpi/video.asl
index 1a4e70f..3ececa9 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/evoc/mec-7003/acpi/video.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,30 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
 
diff --git a/src/mainboard/evoc/mec-7003/acpi_tables.c b/src/mainboard/evoc/mec-7003/acpi_tables.c
new file mode 100644
index 0000000..2b0e440
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/acpi_tables.c
@@ -0,0 +1,262 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+
+	/* Enable both COM ports */
+	gnvs->cmap = 0x01;
+	gnvs->cmbp = 0x01;
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header = &(hpet->header);
+	acpi_addr_t *addr = &(hpet->addr);
+
+	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	addr->space_id = 0;	/* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = HPET_ADDR & 0xffffffff;
+	addr->addrh = HPET_ADDR >> 32;
+
+	hpet->id = 0x8086a201;	/* Intel */
+	hpet->number = 0x00;
+	hpet->min_tick = 0x0080;
+
+	header->checksum =
+	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	printk(BIOS_DEBUG, "ACPI:     * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	current += 0x100;
+	ALIGN_CURRENT;
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/evoc/mec-7003/chip.h
similarity index 74%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/evoc/mec-7003/chip.h
index 1a4e70f..831a973 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/evoc/mec-7003/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,8 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
-
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/evoc/mec-7003/cmos.layout b/src/mainboard/evoc/mec-7003/cmos.layout
new file mode 100644
index 0000000..6ee768b
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/cmos.layout
@@ -0,0 +1,145 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+416        512       s       0        boot_devices
+928          8       h       0        boot_default
+#936         32       r       0        unused
+
+# coreboot config options: mainboard specific options
+#968          16       r       0        unused
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# ram initialization internal data
+1024         8       r       0        C0WL0REOST
+1032         8       r       0        C1WL0REOST
+1040         8       r       0        RCVENMT
+1048         4       r       0        C0DRT1
+1052         4       r       0        C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
diff --git a/src/mainboard/evoc/mec-7003/devicetree.cb b/src/mainboard/evoc/mec-7003/devicetree.cb
new file mode 100644
index 0000000..1668c58
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/devicetree.cb
@@ -0,0 +1,110 @@
+chip northbridge/intel/sandybridge
+
+        device lapic_cluster 0 on
+                chip cpu/intel/socket_rPGA989
+                        device lapic 0 on end
+                end
+        end
+
+        device pci_domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+
+                chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi4_routing" = "2"
+			register "gpi5_routing" = "1"
+			register "gpi13_routing" = "2"
+
+                        register "ide_legacy_combined" = "0x1"
+                        register "sata_ahci" = "0x0"
+
+                	device pci 1b.0 on end # High Definition Audio
+                	device pci 1c.0 on end # PCIe
+                	device pci 1c.1 on end # PCIe
+                	device pci 1c.2 on end # PCIe
+			device pci 1c.3 on end # PCIe
+
+                	device pci 1d.0 on end # USB UHCI
+                	device pci 1d.1 on end # USB UHCI
+                	device pci 1d.2 on end # USB UHCI
+                	device pci 1d.3 on end # USB UHCI
+                	device pci 1d.7 on end # USB2 EHCI
+
+                	device pci 1e.0 on end # PCI bridge
+                        device pci 1f.0 on # LPC bridge
+                                chip superio/nuvoton/nct6776f
+					device pnp 2e.4 on # System Wake-Up Control
+						io 0x60 = 0x00
+						io 0x62 = 0x00
+						irq 0x70 = 0
+						irq 0x71 = 1
+					end
+					device pnp 2e.5 on # KBC/Mouse Interface
+						io 0x60 = 0x00
+						io 0x62 = 0x00
+						irq 0x70 = 12
+						irq 0x71 = 1
+					end
+                                        device pnp 2e.6 on # KBC/Keyboard Interface
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x71 = 1
+                                        end
+                                        device pnp 2e.f on # Shared Memory/Flash Interface
+						io 0x60 = 0x200
+                                        end
+                                        device pnp 2e.10 on # BRAM
+						io 0x62 = 0x700
+                                        end
+                                        device pnp 2e.11 on # Power Management I/F Channel 1
+						io 0x60 = 0x62
+						io 0x62 = 0x66
+						irq 0x70 = 1
+                                        end
+                                        device pnp 2e.12 on # Power Management I/F Channel 2
+						io 0x60 = 0x80
+						io 0x62 = 0x84
+						io 0x64 = 0x400
+						irq 0x70 = 2
+                                        end
+                                end
+                                chip superio/smsc/fdc37n972
+					device pnp 4e.0 off # Floppy
+					end
+					device pnp 4e.1 off # Power Management
+					end
+					device pnp 4e.3 off # Parallel Port
+					end
+					device pnp 4e.4 off # COM1
+					end
+					device pnp 4e.5 off # COM2
+					end
+					device pnp 4e.6 off # RTC
+					end
+					device pnp 4e.7 off # Keyboard
+					end
+					device pnp 4e.8 off # Embedded controller
+					end
+					device pnp 4e.9 off # Mailbox
+					end
+				end
+                        end
+                        device pci 1f.2 on end  # SATA
+                        device pci 1f.3 on end  # SMBus
+                end
+        end
+end
diff --git a/src/mainboard/evoc/mec-7003/dsdt.asl b/src/mainboard/evoc/mec-7003/dsdt.asl
new file mode 100644
index 0000000..eb7ecad
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/dsdt.asl
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20090419	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include "../../../southbridge/intel/bd82x6x/acpi/globalnvs.asl"
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	//#include "acpi/thermal.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include "../../../northbridge/intel/sandybridge/acpi/sandybridge.asl"
+			#include "../../../southbridge/intel/bd82x6x/acpi/pch.asl"
+		}
+	}
+
+	/* Chipset specific sleep states */
+	#include "../../../southbridge/intel/bd82x6x/acpi/sleepstates.asl"
+}
diff --git a/src/mainboard/evoc/mec-7003/fadt.c b/src/mainboard/evoc/mec-7003/fadt.c
new file mode 100644
index 0000000..12aeac0
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/fadt.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+ 	header->length = sizeof(acpi_fadt_t);
+ 	header->revision = 3;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+  	fadt->sci_int = 0x9;
+ 	fadt->smi_cmd = APM_CNT;
+ 	fadt->acpi_enable = ACPI_ENABLE;
+ 	fadt->acpi_disable = ACPI_DISABLE;
+  	fadt->s4bios_req = 0x0;
+ 	fadt->pstate_cnt = PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x20;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x28;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	// XXX: pm2_cnt_len is probably wrong. find out right value (hint: it's != 0)
+	fadt->pm2_cnt_len = 2;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 8;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+ 	fadt->cst_cnt = CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 85;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = 0x03;
+
+ 	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_RESET_REGISTER |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+ 	fadt->reset_reg.space_id = 1;
+ 	fadt->reset_reg.bit_width = 8;
+ 	fadt->reset_reg.bit_offset = 0;
+ 	fadt->reset_reg.resv = 0;
+ 	fadt->reset_reg.addrl = 0xcf9;
+ 	fadt->reset_reg.addrh = 0;
+
+ 	fadt->reset_value = 6;
+ 	fadt->x_firmware_ctl_l = (unsigned long)facs;
+ 	fadt->x_firmware_ctl_h = 0;
+ 	fadt->x_dsdt_l = (unsigned long)dsdt;
+ 	fadt->x_dsdt_h = 0;
+
+ 	fadt->x_pm1a_evt_blk.space_id = 1;
+ 	fadt->x_pm1a_evt_blk.bit_width = 32;
+ 	fadt->x_pm1a_evt_blk.bit_offset = 0;
+ 	fadt->x_pm1a_evt_blk.resv = 0;
+ 	fadt->x_pm1a_evt_blk.addrl = pmbase;
+ 	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ 	fadt->x_pm1b_evt_blk.space_id = 1;
+ 	fadt->x_pm1b_evt_blk.bit_width = 0;
+ 	fadt->x_pm1b_evt_blk.bit_offset = 0;
+ 	fadt->x_pm1b_evt_blk.resv = 0;
+ 	fadt->x_pm1b_evt_blk.addrl = 0x0;
+ 	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ 	fadt->x_pm1a_cnt_blk.space_id = 1;
+ 	fadt->x_pm1a_cnt_blk.bit_width = 16;
+ 	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ 	fadt->x_pm1a_cnt_blk.resv = 0;
+ 	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ 	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ 	fadt->x_pm1b_cnt_blk.space_id = 1;
+ 	fadt->x_pm1b_cnt_blk.bit_width = 0;
+ 	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ 	fadt->x_pm1b_cnt_blk.resv = 0;
+ 	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ 	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ 	fadt->x_pm2_cnt_blk.space_id = 1;
+ 	fadt->x_pm2_cnt_blk.bit_width = 8;
+ 	fadt->x_pm2_cnt_blk.bit_offset = 0;
+ 	fadt->x_pm2_cnt_blk.resv = 0;
+ 	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x20;
+ 	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ 	fadt->x_pm_tmr_blk.space_id = 1;
+ 	fadt->x_pm_tmr_blk.bit_width = 32;
+ 	fadt->x_pm_tmr_blk.bit_offset = 0;
+ 	fadt->x_pm_tmr_blk.resv = 0;
+ 	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ 	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ 	fadt->x_gpe0_blk.space_id = 1;
+ 	fadt->x_gpe0_blk.bit_width = 64;
+ 	fadt->x_gpe0_blk.bit_offset = 0;
+ 	fadt->x_gpe0_blk.resv = 0;
+ 	fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ 	fadt->x_gpe0_blk.addrh = 0x0;
+
+ 	fadt->x_gpe1_blk.space_id = 1;
+ 	fadt->x_gpe1_blk.bit_width = 0;
+ 	fadt->x_gpe1_blk.bit_offset = 0;
+ 	fadt->x_gpe1_blk.resv = 0;
+ 	fadt->x_gpe1_blk.addrl = 0x0;
+ 	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/evoc/mec-7003/hda_verb.h b/src/mainboard/evoc/mec-7003/hda_verb.h
new file mode 100644
index 0000000..2faf68c
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/hda_verb.h
@@ -0,0 +1,147 @@
+/*
+ * This file is part of the coreboot project.
+ * 
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10ec0272,	// Codec Vendor / Device ID: Realtek ALC262
+	0x11702786,	// Subsystem ID
+	0x00000014,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x11702786 */
+	0x00172086,
+	0x00172127,
+	0x00172270,
+	0x00172311,
+	
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x20) */
+	0x02050002,
+	0x0204A2A0,
+	0x02050003,
+	0x02044843,
+
+	/* Pin Complex (NID 0x01) */
+	0x0017FF00,
+	0x0017FF00,
+	0x0017FF00,
+	0x0017FF00,
+
+	/* Pin Complex (NID 0x11) */
+	0x01171CF0,
+	0x01171D11,
+	0x01171E11,
+	0x01171F41,
+
+	/* Pin Complex (NID 0x12) */
+	0x01271C30,
+	0x01271D09,
+	0x01271EA3,
+	0x01271F99,
+
+	/* Pin Complex (NID 0x13) */
+	0x01371CF0,
+	0x01371D11,
+	0x01371E11,
+	0x01371F41,
+
+	/* Pin Complex (NID 0x14) */
+	0x01471C10,
+	0x01471D01,
+	0x01471E13,
+	0x01471F99,
+
+	/* Pin Complex (NID 0x15) */
+	0x01571CF0,
+	0x01571D11,
+	0x01571E11,
+	0x01571F41,
+
+	/* Pin Complex (NID 0x16) */
+	0x01671CF0,
+	0x01671D11,
+	0x01671E11,
+	0x01671F41,
+
+	/* Pin Complex (NID 0x17) */
+	0x01771CF0,
+	0x01771D11,
+	0x01771E11,
+	0x01771F41,
+
+	/* Pin Complex (NID 0x18) */
+	0x01871C20,
+	0x01871D18,
+	0x01871EA1,
+	0x01871F01,
+
+	/* Pin Complex (NID 0x19) */
+	0x01971CF0,
+	0x01971D11,
+	0x01971E11,
+	0x01971F41,
+
+	/* Pin Complex (NID 0x1A) */
+	0x01A71CF0,
+	0x01A71D11,
+	0x01A71E11,
+	0x01A71F41,
+	
+	/* Pin Complex (NID 0x1B) */
+	0x01B71CF0,
+	0x01B71D11,
+	0x01B71E11,
+	0x01B71F41,
+	
+	/* Pin Complex (NID 0x1D) */
+	0x01D71C2D,
+	0x01D71D9A,
+	0x01D71E17,
+	0x01D71F40,
+	
+	/* Pin Complex (NID 0x1E) */
+	0x01E71CF0,
+	0x01E71D11,
+	0x01E71E11,
+	0x01E71F41,
+	
+	/* Pin Complex (NID 0x21) */
+	0x02171C1F,
+	0x02171D10,
+	0x02171E21,
+	0x02171F01,
+	
+	/* Pin Complex (NID 0x20) */
+	0x02050003,
+	0x02044003,
+	0x02050003,
+	0x02044003,
+
+	/* PC Speaker */
+	0x0205000D,
+	0x0205000D,
+	0x02042050,
+	0x00C37080,
+
+	0x00C37100,
+	0x014707C0,
+	0x0143B000,
+	0x00B37416
+};
+
diff --git a/src/mainboard/evoc/mec-7003/mainboard.c b/src/mainboard/evoc/mec-7003/mainboard.c
new file mode 100644
index 0000000..1bad02e
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/mainboard.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <device/device.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include "hda_verb.h"
+#include "chip.h"
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int evoc_mec_7003_int15_handler(struct eregs *regs)
+{
+	int res=-1;
+
+	printk(BIOS_DEBUG, "%s\n", __func__);
+
+	switch(regs->eax & 0xffff) {
+	case 0x5f21: /* Get Display Core Clock in MHz */
+		regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+		regs->ecx = (regs->ecx & 0xffff0000 ) | 167; // TODO read from HW
+		res=0;
+		break;
+	case 0x5f22: /* Get FSB in MHz */
+		regs->eax = (regs->eax & 0xffff0000 ) | 0x5f;
+		regs->ecx = (regs->ecx & 0xffff0000 ) | 800; // TODO read from HW
+		res=0;
+		break;
+        default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f21:
+		M.x86.R_AX = 0x005f; // Success
+		M.x86.R_CX = 167; // Display Core Clock in MHz
+		break;
+	case 0x5f22:
+		M.x86.R_AX = 0x005f; // Success
+		M.x86.R_CX = 800; // FSB in MHz
+		break;
+	default:
+		/* Interrupt was not handled */
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+
+static void int15_install(void)
+{
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	mainboard_interrupt_handlers(0x15, &evoc_mec_7003_int15_handler);
+#endif
+	verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Evoc MEC-7003 mainboard")
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/evoc/mec-7003/mainboard_smi.c b/src/mainboard/evoc/mec-7003/mainboard_smi.c
new file mode 100644
index 0000000..eef11b0
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/mainboard_smi.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include "southbridge/intel/bd82x6x/nvs.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		gnvs->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+
diff --git a/src/mainboard/evoc/mec-7003/romstage.c b/src/mainboard/evoc/mec-7003/romstage.c
new file mode 100644
index 0000000..9a850eb
--- /dev/null
+++ b/src/mainboard/evoc/mec-7003/romstage.c
@@ -0,0 +1,300 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2010 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include "option_table.h"
+#include <console/console.h>
+#include "superio/nuvoton/nct6776f/nct6776f.h"
+#include "superio/nuvoton/nct6776f/early_init.c"
+#include <cpu/x86/bist.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+
+void setup_pch_gpios(void)
+{
+	// printk(BIOS_DEBUG, " GPIOS...");
+	/* General Registers */
+	outl(0xffebf7ff, DEFAULT_GPIOBASE + 0x00);	/* GPIO_USE_SEL */
+	outl(0x00402862, DEFAULT_GPIOBASE + 0x04);	/* GP_IO_SEL */
+	outl(0x18002862, DEFAULT_GPIOBASE + 0x0c);	/* GP_LVL */
+	/* Output Control Registers */
+	outl(0x00000000, DEFAULT_GPIOBASE + 0x18);	/* GPO_BLINK */
+	/* Input Control Registers */
+	outl(0x000020c0, DEFAULT_GPIOBASE + 0x2c);	/* GPI_INV */
+	outl(0x000100fe, DEFAULT_GPIOBASE + 0x30);	/* GPIO_USE_SEL2 */
+	outl(0x00010000, DEFAULT_GPIOBASE + 0x34);	/* GP_IO_SEL2 */
+	outl(0x00000042, DEFAULT_GPIOBASE + 0x38);	/* GP_LVL2 */
+}
+
+static void pch_enable_lpc(void)
+{
+	// Enable Serial IRQ
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+	// Set COM1/COM2 decode range
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
+	// Enable COM1/COM2/KBD/SuperIO1+2
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f03);
+	// ??? Decode
+	// pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00040311);
+	// EC Mailbox Decode
+	//pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040701);
+	// Disable
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000);
+	// Disable
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000);
+}
+
+static void rcba_config(void)
+{
+	u32 reg32;
+
+	/* Set up virtual channel 0 */
+	//RCBA32(0x0014) = 0x80000001;
+	//RCBA32(0x001c) = 0x03128010;
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(0x3100) = 0x00042210;
+	RCBA32(0x3104) = 0x00002100;
+	RCBA32(0x3108) = 0x10004321;
+	RCBA32(0x310c) = 0x00214321;
+
+	/* dev irq route register (board specific) */
+	RCBA16(0x3140) = 0x3210;
+	RCBA16(0x3142) = 0x3210;
+	RCBA16(0x3144) = 0x3210;
+	RCBA16(0x3146) = 0x3210;
+	RCBA16(0x3148) = 0x3210;
+
+	/* Enable IOAPIC (generic) */
+	RCBA8(0x31ff) = 0x03;
+
+	/* Enable upper 128bytes of CMOS (generic) */
+	RCBA32(0x3400) = (1 << 2);
+
+	/* Disable unused devices (board specific) */
+	reg32 = 0x00300063; // FIXME put in the right defines
+	RCBA32(0x3418) = reg32;
+
+	/* Enable PCIe Root Port Clock Gate */
+	// RCBA32(0x341c) = 0x00000001;
+
+	// Disable PCI dynamic gating
+	RCBA32(0x341c) &= ~(1 << 16);
+	RCBA32(0x341c) = 0xcfa8000f; // for now just hard code the right value
+}
+
+// FIXME, this function is generic code that should go to sb/... or
+// nb/../early_init.c
+static void early_pch_init(void)
+{
+	uint8_t reg8;
+	uint32_t reg32;
+
+	// program secondary mlt XXX byte?
+	pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+	// usb transient disconnect
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+	reg8 |= (3 << 0);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+	// sata
+	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 2), 0x94);
+	reg8 |= (1 << 8) | (1 << 7);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x94, reg8);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+	reg32 |= (1 << 29) | (1 << 17);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+	reg32 |= (1 << 31) | (1 << 27);
+	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+	RCBA32(0x0088) = 0x0011d000;
+	RCBA16(0x01fc) = 0x060f;
+	RCBA32(0x01f4) = 0x86000040;
+	RCBA32(0x0214) = 0x10030509; // different from ich7
+	RCBA32(0x0218) = 0x00020504;
+	RCBA8(0x0220) = 0xc5;
+	reg32 = RCBA32(0x3410);
+	reg32 |= (1 << 6);
+	RCBA32(0x3410) = reg32;
+	reg32 = RCBA32(0x3430);
+	reg32 &= ~(3 << 0);
+	reg32 |= (1 << 0);
+	RCBA32(0x3430) = reg32;
+	RCBA32(0x3418) |= (1 << 0);
+	RCBA16(0x0200) = 0x2008;
+	RCBA8(0x2027) = 0x0d;
+	RCBA16(0x3e08) |= (1 << 7);
+	RCBA16(0x3e48) |= (1 << 7);
+	RCBA32(0x3e0e) |= (1 << 7);
+	RCBA32(0x3e4e) |= (1 << 7);
+	reg32 = RCBA32(0x2034);
+	reg32 &= ~(0x0f << 16);
+	reg32 |= (5 << 16);
+	RCBA32(0x2034) = reg32;
+	RCBA32(0x3418) |= (1 << 6) | (1 << 5) | (1 << 1);
+	// after pci enumeration:
+	//RCBA32(0x1d40) |= (1 << 0);
+}
+
+#include <cbmem.h>
+
+void main(unsigned long bist)
+{
+	u32 reg32;
+	int boot_mode = 0;
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10);	/* Enable GPIOs */
+	setup_pch_gpios();
+
+	/* Set up the console */
+#define SERIAL_DEV PNP_DEV(0x2e, NCT6776F_SP1)
+ 	nct6776f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+#if 1
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n");
+		outb(0x6, 0xcf9);
+		while (1) asm("hlt");
+	}
+#endif
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	sandybridge_early_initialization();
+
+	// Detect if we're coming from a warm reset.
+	if (MCHBAR32(0xf14) & (1 << 8)) {
+		printk(BIOS_DEBUG, "soft reset detected.\n");
+		boot_mode = 1;
+	}
+
+	/* Read PM1_CNT */
+	reg32 = inl(DEFAULT_PMBASE + 0x04);
+	printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
+	if (((reg32 >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+	post_code(0x38);
+
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	post_code(0x39);
+	sdram_initialize(boot_mode);
+
+	post_code(0x3a);
+	/* Perform some initialization that must run before stage2 */
+	early_pch_init();
+	post_code(0x3b);
+
+	/* This should probably go away. Until now it is required
+	 * and mainboard specific
+	 */
+	rcba_config();
+	post_code(0x3c);
+
+	/* Chipset Errata! */
+	//fixup_sandybridge_errata();
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	sandybridge_late_initialization();
+
+//#if !CONFIG_HAVE_ACPI_RESUME
+//#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+	post_code(0x3d);
+	// FIXME if these ramchecks are commented out, the CAR code will fail
+	// to copy the USBDEBUG data structure from cache to ram. Weird.
+	ram_check(0x00000000, 0x000a0000);
+	//ram_check(0x00100000, 0x3f800000);
+	ram_check(CONFIG_RAMBASE, CONFIG_RAMTOP);
+//#endif
+//#endif
+
+	post_code(0x3e);
+	quick_ram_check();
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* Start address of high memory tables */
+	unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE;
+
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+	if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+
+		/* copy 1MB - 64K to high tables ram_base to prevent memory corruption
+		 * through stage 2. We could keep stuff like stack and heap in high tables
+		 * memory completely, but that's a wonderful clean up task for another
+		 * day.
+		 */
+		if (resume_backup_memory)
+			memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE);
+
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+	post_code(0x3f);
+}
diff --git a/src/mainboard/getac/p470/acpi_tables.c b/src/mainboard/getac/p470/acpi_tables.c
index 649dff6..46e7b88 100644
--- a/src/mainboard/getac/p470/acpi_tables.c
+++ b/src/mainboard/getac/p470/acpi_tables.c
@@ -29,7 +29,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include "dmi.h"
 
 extern unsigned char AmlCode[];
 
@@ -355,15 +354,6 @@
 	ALIGN_CURRENT;
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
diff --git a/src/mainboard/getac/p470/dmi.h b/src/mainboard/getac/p470/dmi.h
deleted file mode 100644
index fde4d8a..0000000
--- a/src/mainboard/getac/p470/dmi.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static const u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
-	0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/mainboard/ibase/mb899/acpi_tables.c b/src/mainboard/ibase/mb899/acpi_tables.c
index 0089e21..dbe1e91 100644
--- a/src/mainboard/ibase/mb899/acpi_tables.c
+++ b/src/mainboard/ibase/mb899/acpi_tables.c
@@ -28,7 +28,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/x86/msr.h>
-#include "dmi.h"
 
 extern const unsigned char AmlCode[];
 #if CONFIG_HAVE_ACPI_SLIC
@@ -258,15 +257,6 @@
 	ALIGN_CURRENT;
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
diff --git a/src/mainboard/ibase/mb899/dmi.h b/src/mainboard/ibase/mb899/dmi.h
deleted file mode 100644
index 96b5873..0000000
--- a/src/mainboard/ibase/mb899/dmi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
-	0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/mainboard/intel/d945gclf/acpi_tables.c b/src/mainboard/intel/d945gclf/acpi_tables.c
index 1e8ea29..0600ec0 100644
--- a/src/mainboard/intel/d945gclf/acpi_tables.c
+++ b/src/mainboard/intel/d945gclf/acpi_tables.c
@@ -28,7 +28,6 @@
 #include <device/pci_ids.h>
 #include <cpu/x86/msr.h>
 #include <arch/ioapic.h>
-#include "dmi.h"
 
 #define OLD_ACPI 0
 
@@ -338,15 +337,6 @@
 	acpi_add_table(rsdp, ssdt);
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
diff --git a/src/mainboard/intel/d945gclf/dmi.h b/src/mainboard/intel/d945gclf/dmi.h
deleted file mode 100644
index 96b5873..0000000
--- a/src/mainboard/intel/d945gclf/dmi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
-	0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
index 92874bc..8c8e788 100644
--- a/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
+++ b/src/mainboard/iwave/iWRainbowG6/acpi_tables.c
@@ -28,7 +28,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/x86/msr.h>
-#include "dmi.h"
 
 extern const unsigned char AmlCode[];
 #if CONFIG_HAVE_ACPI_SLIC
@@ -264,15 +263,6 @@
 	ALIGN_CURRENT;
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
diff --git a/src/mainboard/iwave/iWRainbowG6/dmi.h b/src/mainboard/iwave/iWRainbowG6/dmi.h
deleted file mode 100644
index d076dff..0000000
--- a/src/mainboard/iwave/iWRainbowG6/dmi.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x2d, 0x1f, 0x02, 0x03, 0x51, 0x00, 0x00, 0x00,
-	    0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0xeb, 0xa8, 0x03, 0xa0, 0xff, 0x0f, 0x00,
-	    0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde,
-	    0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74,
-	    0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f,
-	    0x31, 0x33, 0x2f, 0x32,
-	0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/mainboard/kontron/986lcd-m/acpi_tables.c b/src/mainboard/kontron/986lcd-m/acpi_tables.c
index 0089e21..dbe1e91 100644
--- a/src/mainboard/kontron/986lcd-m/acpi_tables.c
+++ b/src/mainboard/kontron/986lcd-m/acpi_tables.c
@@ -28,7 +28,6 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <cpu/x86/msr.h>
-#include "dmi.h"
 
 extern const unsigned char AmlCode[];
 #if CONFIG_HAVE_ACPI_SLIC
@@ -258,15 +257,6 @@
 	ALIGN_CURRENT;
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
diff --git a/src/mainboard/kontron/986lcd-m/dmi.h b/src/mainboard/kontron/986lcd-m/dmi.h
deleted file mode 100644
index 96b5873..0000000
--- a/src/mainboard/kontron/986lcd-m/dmi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
-	0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/mainboard/kontron/986lcd-m/mainboard.c b/src/mainboard/kontron/986lcd-m/mainboard.c
index 1d0c494..d7b1f13 100644
--- a/src/mainboard/kontron/986lcd-m/mainboard.c
+++ b/src/mainboard/kontron/986lcd-m/mainboard.c
@@ -25,6 +25,7 @@
 #endif
 #include <pc80/mc146818rtc.h>
 #include <arch/io.h>
+#include <arch/interrupt.h>
 #include "chip.h"
 
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -70,6 +71,53 @@
 }
 #endif
 
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res = -1;
+
+	/* This int15 handler is Intel IGD. specific. Other chipsets need other
+	 * handlers. The right way to do this is to move this handler code into
+	 * the mainboard or northbridge code.
+	 * TODO: completely move to mainboards / chipsets.
+	 */
+	switch (regs->eax & 0xffff) {
+	/* And now Intel IGD code */
+#define BOOT_DISPLAY_DEFAULT    0
+#define BOOT_DISPLAY_CRT        (1 << 0)
+#define BOOT_DISPLAY_TV         (1 << 1)
+#define BOOT_DISPLAY_EFP        (1 << 2)
+#define BOOT_DISPLAY_LCD        (1 << 3)
+#define BOOT_DISPLAY_CRT2       (1 << 4)
+#define BOOT_DISPLAY_TV2        (1 << 5)
+#define BOOT_DISPLAY_EFP2       (1 << 6)
+#define BOOT_DISPLAY_LCD2       (1 << 7)
+	case 0x5f35:
+		regs->eax = 0x5f;
+		regs->ecx = BOOT_DISPLAY_DEFAULT;
+		res = 0;
+		break;
+	case 0x5f40:
+		regs->eax = 0x5f;
+		regs->ecx = 3; // This is mainboard specific
+		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
+		res = 0;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+	}
+
+	return res;
+}
+
+static void int15_install(void)
+{
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+}
+#endif
+
+
 /* Hardware Monitor */
 
 static u16 hwm_base = 0xa00;
@@ -221,7 +269,7 @@
 
 static void mainboard_enable(device_t dev)
 {
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 	/* Install custom int15 handler for VGA OPROM */
 	int15_install();
 #endif
diff --git a/src/mainboard/lenovo/t60/acpi_tables.c b/src/mainboard/lenovo/t60/acpi_tables.c
index d9275b5..cb0fe2a 100644
--- a/src/mainboard/lenovo/t60/acpi_tables.c
+++ b/src/mainboard/lenovo/t60/acpi_tables.c
@@ -29,7 +29,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include "dmi.h"
 
 extern const unsigned char AmlCode[];
 #if CONFIG_HAVE_ACPI_SLIC
@@ -349,15 +348,6 @@
 	ALIGN_CURRENT;
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 
 	/* Enable Dummy DCC ON# for DVI */
diff --git a/src/mainboard/lenovo/x60/acpi_tables.c b/src/mainboard/lenovo/x60/acpi_tables.c
index d9275b5..cb0fe2a 100644
--- a/src/mainboard/lenovo/x60/acpi_tables.c
+++ b/src/mainboard/lenovo/x60/acpi_tables.c
@@ -29,7 +29,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include "dmi.h"
 
 extern const unsigned char AmlCode[];
 #if CONFIG_HAVE_ACPI_SLIC
@@ -349,15 +348,6 @@
 	ALIGN_CURRENT;
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 
 	/* Enable Dummy DCC ON# for DVI */
diff --git a/src/mainboard/roda/rk886ex/acpi_tables.c b/src/mainboard/roda/rk886ex/acpi_tables.c
index d9275b5..cb0fe2a 100644
--- a/src/mainboard/roda/rk886ex/acpi_tables.c
+++ b/src/mainboard/roda/rk886ex/acpi_tables.c
@@ -29,7 +29,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include "dmi.h"
 
 extern const unsigned char AmlCode[];
 #if CONFIG_HAVE_ACPI_SLIC
@@ -349,15 +348,6 @@
 	ALIGN_CURRENT;
 
 	printk(BIOS_DEBUG, "current = %lx\n", current);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-#if CONFIG_WRITE_HIGH_TABLES == 1
-	memcpy((void *)current, dmi_table, DMI_TABLE_SIZE);
-	current += DMI_TABLE_SIZE;
-	ALIGN_CURRENT;
-#endif
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 
 	/* Enable Dummy DCC ON# for DVI */
diff --git a/src/mainboard/roda/rk886ex/dmi.h b/src/mainboard/roda/rk886ex/dmi.h
deleted file mode 100644
index 96b5873..0000000
--- a/src/mainboard/roda/rk886ex/dmi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
-	0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c
index 2c5b5e3..d87d712 100644
--- a/src/mainboard/roda/rk886ex/mainboard.c
+++ b/src/mainboard/roda/rk886ex/mainboard.c
@@ -22,6 +22,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <arch/io.h>
+#include <arch/interrupt.h>
 #include <boot/tables.h>
 #include <delay.h>
 #if CONFIG_PCI_OPTION_ROM_RUN_YABEL
@@ -99,6 +100,52 @@
 }
 #endif
 
+#if CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res = -1;
+
+	/* This int15 handler is Intel IGD. specific. Other chipsets need other
+	 * handlers. The right way to do this is to move this handler code into
+	 * the mainboard or northbridge code.
+	 * TODO: completely move to mainboards / chipsets.
+	 */
+	switch (regs->eax & 0xffff) {
+	/* And now Intel IGD code */
+#define BOOT_DISPLAY_DEFAULT    0
+#define BOOT_DISPLAY_CRT        (1 << 0)
+#define BOOT_DISPLAY_TV         (1 << 1)
+#define BOOT_DISPLAY_EFP        (1 << 2)
+#define BOOT_DISPLAY_LCD        (1 << 3)
+#define BOOT_DISPLAY_CRT2       (1 << 4)
+#define BOOT_DISPLAY_TV2        (1 << 5)
+#define BOOT_DISPLAY_EFP2       (1 << 6)
+#define BOOT_DISPLAY_LCD2       (1 << 7)
+	case 0x5f35:
+		regs->eax = 0x5f;
+		regs->ecx = BOOT_DISPLAY_DEFAULT;
+		res = 0;
+		break;
+	case 0x5f40:
+		regs->eax = 0x5f;
+		regs->ecx = 3; // This is mainboard specific
+		printk(BIOS_DEBUG, "DISPLAY=%x\n", regs->ecx);
+		res = 0;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+	}
+
+	return res;
+}
+
+static void int15_install(void)
+{
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+}
+#endif
+
 #if DUMP_RUNTIME_REGISTERS
 static void dump_runtime_registers(void)
 {
@@ -125,7 +172,7 @@
 	/* Disable Dummy DCC -> GP45 = 1 */
 	outb(inb(0x60f) | (1 << 5), 0x60f);
 
-#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
 	/* Install custom int15 handler for VGA OPROM */
 	int15_install();
 #endif
diff --git a/src/mainboard/samsung/Kconfig b/src/mainboard/samsung/Kconfig
new file mode 100644
index 0000000..d6992d9
--- /dev/null
+++ b/src/mainboard/samsung/Kconfig
@@ -0,0 +1,21 @@
+if VENDOR_SAMSUNG
+
+choice
+	prompt "Mainboard model"
+
+config BOARD_SAMSUNG_LUMPY
+	bool "Lumpy"
+
+config BOARD_SAMSUNG_STUMPY
+	bool "Stumpy"
+
+endchoice
+
+source "src/mainboard/samsung/lumpy/Kconfig"
+source "src/mainboard/samsung/stumpy/Kconfig"
+
+config MAINBOARD_VENDOR
+	string
+	default "SAMSUNG"
+
+endif # VENDOR_SAMSUNG
diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig
new file mode 100644
index 0000000..78d64f3
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/Kconfig
@@ -0,0 +1,62 @@
+if BOARD_SAMSUNG_LUMPY
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_SMSC_MEC1308
+	select EC_SMSC_MEC1308
+	select BOARD_HAS_FADT
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select HAVE_MAINBOARD_RESOURCES
+	select MMCONF_SUPPORT
+	select HAVE_SMI_HANDLER
+	select BOARD_ROMSIZE_KB_8192
+	select GFXUMA
+	select CHROMEOS
+
+config MAINBOARD_DIR
+	string
+	default samsung/lumpy
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Lumpy"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0xc000
+
+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+	bool
+	default n
+
+endif # BOARD_SAMSUNG_LUMPY
diff --git a/src/mainboard/samsung/lumpy/Makefile.inc b/src/mainboard/samsung/lumpy/Makefile.inc
new file mode 100644
index 0000000..e05c28b
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/Makefile.inc
@@ -0,0 +1,34 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ramstage-y += ec.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
+# Include spd rom data
+spd.bin:
+	xxd -rg1 $(src)/mainboard/samsung/lumpy/spd.hex >| $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := spd.bin
+spd.bin-type := 0xab
+spd.bin-position := 0xfffdc000
diff --git a/src/mainboard/samsung/lumpy/acpi/chromeos.asl b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
new file mode 100644
index 0000000..fc7be20
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/chromeos.asl
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (CRHW)
+{
+	Name(_HID, EISAID("GGL0001"))
+
+	Method(_STA, 0, Serialized)
+	{
+		Return (0xb)
+	}
+
+	Method(CHSW, 0, Serialized)
+	{
+		Name (WSHC, Package() { VBT3 })
+		Return (WSHC)
+	}
+
+	Method(FWID, 0, Serialized)
+	{
+		Name (DIW1, "")
+		ToString(VBT5, 63, DIW1)
+		Name (DIWF, Package() { DIW1 })
+		Return(DIWF)
+	}
+
+	Method(FRID, 0, Serialized)
+	{
+		Name (DIR1, "")
+		ToString(VBT6, 63, DIR1)
+		Name (DIRF, Package() { DIR1 })
+		Return (DIRF)
+	}
+
+	Method(HWID, 0, Serialized)
+	{
+		Name (DIW0, "")
+		ToString(VBT4, 255, DIW0)
+		Name (DIWH, Package() { DIW0 })
+		Return (DIWH)
+	}
+
+	Method(BINF, 0, Serialized)
+	{
+		Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+		Return (FNIB)
+	}
+
+	Method(GPIO, 0, Serialized)
+	{
+		Name(OIPG, Package() {
+			Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
+			Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
+			Package() { 0x003, 1, 24, "CougarPoint" }, // firmware write protect
+		})
+		Return (OIPG)
+
+	}
+
+	Method(VBNV, 0, Serialized)
+	{
+		Name(VNBV, Package() {
+			// See src/vendorcode/google/chromeos/Kconfig
+			// for the definition of these:
+			CONFIG_VBNV_OFFSET,
+			CONFIG_VBNV_SIZE
+		})
+		Return(VNBV)
+	}
+
+	Method(VDAT, 0, Serialized)
+	{
+		Name(TAD0,"")
+		ToBuffer(CHVD, TAD0)
+		Name (TADV, Package() { TAD0 })
+		Return (TADV)
+	}
+
+	Method(FMAP, 0, Serialized)
+	{
+		Name(PAMF, Package() { VBT9 })
+		Return(PAMF)
+	}
+
+	Method(MECK, 0, Serialized)
+	{
+		Name(HASH, Package() { MEHH })
+		Return(HASH)
+	}
+
+	Method(MLST, 0, Serialized)
+	{
+		Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+			   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+		})
+		Return (TSLM)
+	}
+}
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/samsung/lumpy/acpi/ec.asl
similarity index 71%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/samsung/lumpy/acpi/ec.asl
index 1a4e70f..21602c2 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/samsung/lumpy/acpi/ec.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,11 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+/* EC configuration */
+#define EC_GPE 23	// GPE23 -> Runtime SCI
+
+#include <ec/smsc/mec1308/acpi/ec.asl>
 
diff --git a/src/mainboard/samsung/lumpy/acpi/mainboard.asl b/src/mainboard/samsung/lumpy/acpi/mainboard.asl
new file mode 100644
index 0000000..b1ab678
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/mainboard.asl
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+	Device (LID0)
+	{
+		Name(_HID, EisaId("PNP0C0D"))
+		Method(_LID, 0)
+		{
+			Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+			Return (\LIDS)
+		}
+
+		// WAKE SCI# from EC is GPIO14
+		Name(_PRW, Package(){0x1e, 0x05})
+	}
+
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+	}
+
+	Device (TPAD)
+	{
+		// Report as a Sleep Button device so
+		// Linux will automatically enable for wake
+		Name(_HID, EisaId("PNP0C0E"))
+
+		// Trackpad Wake is GPIO11
+		Name(_PRW, Package(){0x1b, 0x03})
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQF -> GSI21
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {21}
+
+			// SMBUS Address 0x67
+			VendorShort (ADDR) {0x67}
+		})
+	}
+
+	Device (LITE)
+	{
+		// Generic ACPI Device Container
+		Name(_HID, EisaId("PNP0A05"))
+
+		Name(_CRS, ResourceTemplate()
+		{
+			// PIRQE -> GSI20
+			Interrupt (ResourceConsumer, Edge, ActiveLow) {20}
+
+			// SMBUS Address 0x44
+			VendorShort (ADDR) {0x44}
+		})
+	}
+}
+
+// Battery information
+Name (BATV, "SAMSUNG")
+Name (BATM, "LUMPY")
+Name (BATS, "BATTERY")
diff --git a/src/mainboard/samsung/lumpy/acpi/platform.asl b/src/mainboard/samsung/lumpy/acpi/platform.asl
new file mode 100644
index 0000000..39a29e7
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/platform.asl
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	Store (Zero, GP35)  // Disable WLAN
+	Store (Zero, GP38)  // Disable WWAN
+
+	If (S33G) {
+		Store (Zero, GP43)  // Enable HSPA
+	} Else {
+		Store (One, GP43)   // Disable HSPA
+	}
+
+	If (LEqual (Arg0, 3)) {
+		// NVS has a flag to determine USB policy in S3
+		If (S3U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S3
+		If (S3U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+	If (LEqual (Arg0, 5)) {
+		// NVS has a flag to determine USB policy in S5
+		If (S5U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S5
+		If (S5U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	/* Update in case state changed while asleep */
+	Store (\_SB.PCI0.LPCB.EC0.ACEX, \PWRS)
+
+	/* Enable OS control of fan */
+	Store (One, \_SB.PCI0.LPCB.EC0.FCOS)
+
+	Return(Package(){0,0})
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..179376e
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 16 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 17 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 16 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 17 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/samsung/lumpy/acpi/superio.asl b/src/mainboard/samsung/lumpy/acpi/superio.asl
new file mode 100644
index 0000000..465fa54
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/superio.asl
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#define SIO_ENABLE_SPM1          // pnp 2e.1: Enable ACPI PM1 Block
+#define SIO_SPM1_IO0      0xb00  // pnp 2e.1: io 0x60
+
+#undef SIO_ENABLE_SEC1           // pnp 2e.2: Disable EC 1
+
+#undef SIO_ENABLE_SEC2           // pnp 2e.3: Disable EC 2
+
+#undef SIO_ENABLE_SSP1           // pnp 2e.4: Disable UART
+
+#define SIO_ENABLE_SKBC          // pnp 2e.7: Enable Keyboard
+
+#undef SIO_ENABLE_SEC0           // pnp 2e.8: Already exported as EC
+
+#define SIO_ENABLE_SMBX          // pnp 2e.9: Enable Mailbox
+#define SIO_SMBX_IO0      0xa00  // pnp 2e.9: io 0xa00
+
+#include "../../../../superio/smsc/mec1308/acpi/superio.asl"
diff --git a/src/mainboard/samsung/lumpy/acpi/thermal.asl b/src/mainboard/samsung/lumpy/acpi/thermal.asl
new file mode 100644
index 0000000..b8fa750
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi/thermal.asl
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Ignore critical temps for the first few reads
+		// at boot to prevent unexpected shutdown
+		Name (IRDC, 4)
+		Name (CRDC, 0)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get CPU Temperature from the Embedded Controller
+			Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0)
+
+			// Re-read from EC if the temperature is very high to
+			// avoid OS shutdown if we got a bad reading.
+			If (LGreaterEqual (Local0, \TCRT)) {
+				Store (\_SB.PCI0.LPCB.EC0.CPUT, Local0)
+				If (LGreaterEqual (Local0, \TCRT)) {
+					// Check if this is an early read
+					If (LLess (CRDC, IRDC)) {
+						Store (0, Local0)
+					}
+				}
+			}
+
+			// Keep track of first few reads by the OS
+			If (LLess (CRDC, IRDC)) {
+				Increment (CRDC)
+			}
+
+			// Invalid reading, ensure fan is spinning
+			If (LGreaterEqual (Local0, 0x80)) {
+				Return (CTOK (\F4ON))
+			}
+
+			Return (CTOK (Local0))
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (\F0OF))
+			} Else {
+				Return (CTOK (\F0ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (\F1OF))
+			} Else {
+				Return (CTOK (\F1ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (\F2OF))
+			} Else {
+				Return (CTOK (\F2ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (\F3OF))
+			} Else {
+				Return (CTOK (\F3ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (\F4OF))
+			} Else {
+				Return (CTOK (\F4ON))
+			}
+		}
+
+		Name (_AL0, Package () { \_SB.PCI0.LPCB.EC0.FAN0 })
+		Name (_AL1, Package () { \_SB.PCI0.LPCB.EC0.FAN1 })
+		Name (_AL2, Package () { \_SB.PCI0.LPCB.EC0.FAN2 })
+		Name (_AL3, Package () { \_SB.PCI0.LPCB.EC0.FAN3 })
+		Name (_AL4, Package () { \_SB.PCI0.LPCB.EC0.FAN4 })
+	}
+}
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/samsung/lumpy/acpi/video.asl
similarity index 60%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/samsung/lumpy/acpi/video.asl
index 1a4e70f..3ececa9 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/samsung/lumpy/acpi/video.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,30 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
 
diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c
new file mode 100644
index 0000000..b5be2e1
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/acpi_tables.c
@@ -0,0 +1,323 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <ec/acpi/ec.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	gnvs->f4of = FAN4_THRESHOLD_OFF;
+	gnvs->f4on = FAN4_THRESHOLD_ON;
+
+	gnvs->f3of = FAN3_THRESHOLD_OFF;
+	gnvs->f3on = FAN3_THRESHOLD_ON;
+
+	gnvs->f2of = FAN2_THRESHOLD_OFF;
+	gnvs->f2on = FAN2_THRESHOLD_ON;
+
+	gnvs->f1of = FAN1_THRESHOLD_OFF;
+	gnvs->f1on = FAN1_THRESHOLD_ON;
+
+	gnvs->f0of = FAN0_THRESHOLD_OFF;
+	gnvs->f0on = FAN0_THRESHOLD_ON;
+
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tmax = MAX_TEMPERATURE;
+	gnvs->flvl = 5;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	gnvs_ = gnvs;
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+
+	/*
+	 * Disable 3G in suspend by default.
+	 * Provide option to enable for http://crosbug.com/p/7925
+	 */
+	gnvs->s33g = 0;
+
+	/* Disable USB ports in S3 by default */
+	gnvs->s3u0 = 0;
+	gnvs->s3u1 = 0;
+
+	/* Disable USB ports in S5 by default */
+	gnvs->s5u0 = 0;
+	gnvs->s5u1 = 0;
+
+	/* CBMEM TOC */
+	gnvs->cmem = (u32)get_cbmem_toc();
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+
+	// TODO(reinauer) this could move elsewhere?
+	chromeos_init_vboot(&(gnvs->chromeos));
+
+	acpi_update_thermal_table(gnvs);
+
+	gnvs->chromeos.vbt2 = ec_read(0xcb) ? ACTIVE_ECFW_RW : ACTIVE_ECFW_RO;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header = &(hpet->header);
+	acpi_addr_t *addr = &(hpet->addr);
+
+	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	addr->space_id = 0;	/* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = HPET_ADDR & 0xffffffff;
+	addr->addrh = HPET_ADDR >> 32;
+
+	hpet->id = 0x8086a201;	/* Intel */
+	hpet->number = 0x00;
+	hpet->min_tick = 0x0080;
+
+	header->checksum =
+	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+					const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	current += sizeof(global_nvs_t);
+	ALIGN_CURRENT;
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
+
+void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size)
+{
+	*vdat_addr = &gnvs_->chromeos.vdat;
+	*vdat_size = sizeof(gnvs_->chromeos.vdat);
+}
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/samsung/lumpy/chip.h
similarity index 74%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/samsung/lumpy/chip.h
index 1a4e70f..831a973 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/samsung/lumpy/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,8 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
-
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/samsung/lumpy/chromeos.c b/src/mainboard/samsung/lumpy/chromeos.c
new file mode 100644
index 0000000..6d93470
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/chromeos.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#define GPIO_SPI_WP	24
+#define GPIO_REC_MODE	42
+#define GPIO_DEV_MODE	17
+
+#define FLAG_SPI_WP	0
+#define FLAG_REC_MODE	1
+#define FLAG_DEV_MODE	2
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+#include "ec.h"
+#include <ec/smsc/mec1308/ec.h>
+
+#define GPIO_COUNT	5
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+	u8  lid = ec_read(0x83);
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	/* Write Protect: GPIO24 = KBC3_SPI_WP# */
+	gpios->gpios[0].port = GPIO_SPI_WP;
+	gpios->gpios[0].polarity = ACTIVE_HIGH;
+	gpios->gpios[0].value =
+		(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 2)),
+						 SATA_SP) >> FLAG_SPI_WP) & 1;
+	strncpy((char *)gpios->gpios[0].name,"write protect",
+							GPIO_MAX_NAME_LENGTH);
+
+	/* Recovery: GPIO42 = CHP3_REC_MODE# */
+	gpios->gpios[1].port = GPIO_REC_MODE;
+	gpios->gpios[1].polarity = ACTIVE_LOW;
+	gpios->gpios[1].value = !get_recovery_mode_switch();
+	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+	/* Developer: GPIO17 = KBC3_DVP_MODE */
+	gpios->gpios[2].port = GPIO_DEV_MODE;
+	gpios->gpios[2].polarity = ACTIVE_HIGH;
+	gpios->gpios[2].value = get_developer_mode_switch();
+	strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+	gpios->gpios[3].port = 100;
+	gpios->gpios[3].polarity = ACTIVE_HIGH;
+	gpios->gpios[3].value = lid & 1;
+	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+	/* Power Button */
+	gpios->gpios[4].port = 101;
+	gpios->gpios[4].polarity = ACTIVE_LOW;
+	gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
+	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+}
+
+#ifdef __PRE_RAM__
+void save_chromeos_gpios(void)
+{
+	u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
+	u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
+	u32 gp_lvl = inl(gpio_base + GP_LVL);
+	u32 flags = 0;
+
+	/* Write Protect: GPIO24 = KBC3_SPI_WP#, active high */
+	if (gp_lvl & (1 << GPIO_SPI_WP))
+		flags |= (1 << FLAG_SPI_WP);
+	/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
+	if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
+		flags |= (1 << FLAG_REC_MODE);
+	/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
+	if (gp_lvl & (1 << GPIO_DEV_MODE))
+		flags |= (1 << FLAG_DEV_MODE);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
+}
+#endif
diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout
new file mode 100644
index 0000000..9552021
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# coreboot config options: cpu
+400          1       e       2        hyper_threading
+#401          7       r       0        unused
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+#409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb
new file mode 100644
index 0000000..36af1ca
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/devicetree.cb
@@ -0,0 +1,111 @@
+chip northbridge/intel/sandybridge
+
+	# Enable DisplayPort Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Enable Panel as LVDS and configure power delays
+	register "gpu_panel_port_select" = "0"			# LVDS
+	register "gpu_panel_power_cycle_delay" = "5"		# T4: 400ms
+	register "gpu_panel_power_up_delay" = "400"		# T1+T2: 40ms
+	register "gpu_panel_power_down_delay" = "150"		# T3: 15ms
+	register "gpu_panel_power_backlight_on_delay" = "2100"	# T5: 210ms
+	register "gpu_panel_power_backlight_off_delay" = "2100"	# TD: 210ms
+
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			# Coordinate with HW_ALL
+			register "pstate_coord_type" = "0xfe"
+
+			register "c1_acpower" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_acpower" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
+
+			register "c1_battery" = "1"	# ACPI(C1) = MWAIT(C1)
+			register "c2_battery" = "3"	# ACPI(C2) = MWAIT(C3)
+			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "alt_gp_smi_en" = "0x0002"
+			register "gpi1_routing" = "1"
+			register "gpi7_routing" = "2"
+
+			register "ide_legacy_combined" = "0x0"
+			register "sata_ahci" = "0x1"
+			register "sata_port_map" = "0x1"
+
+			# EC range is 0xa00-0xa3f
+			register "gen1_dec" = "0x003c0a01"
+			register "gen2_dec" = "0x003c0b01"
+
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio
+			device pci 1c.0 on end # PCIe Port #1 (WLAN)
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 on end # PCIe Port #4 (LAN)
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on # LPC bridge
+				chip superio/smsc/mec1308
+					device pnp 2e.1 on		# PM1
+						io 0x60 = 0xb00
+					end
+					device pnp 2e.2 off end		# EC1
+					device pnp 2e.3 off end		# EC2
+					device pnp 2e.4 off end		# UART
+					device pnp 2e.7 on		# KBC
+						irq 0x70 = 1
+					end
+					device pnp 2e.8 on		# EC0
+						io 0x60 = 0x62
+					end
+					device pnp 2e.9 on		# MBX
+						io 0x60 = 0xa00
+					end
+				end
+				chip ec/smsc/mec1308
+					register "mailbox_port" = "0xa00"
+					device pnp ff.1 off end
+				end
+			end
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 on end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl
new file mode 100644
index 0000000..cfdabc8
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/dsdt.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include "../../../southbridge/intel/bd82x6x/acpi/globalnvs.asl"
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	// mainboard specific devices
+	#include "acpi/mainboard.asl"
+
+	#include "../../../cpu/intel/model_206ax/acpi/cpu.asl"
+
+	#include "acpi/thermal.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include "../../../northbridge/intel/sandybridge/acpi/sandybridge.asl"
+			#include "../../../southbridge/intel/bd82x6x/acpi/pch.asl"
+		}
+	}
+
+	#include "acpi/chromeos.asl"
+
+	/* Chipset specific sleep states */
+	#include "../../../southbridge/intel/bd82x6x/acpi/sleepstates.asl"
+}
diff --git a/src/mainboard/samsung/lumpy/ec.c b/src/mainboard/samsung/lumpy/ec.c
new file mode 100644
index 0000000..40d8319
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/ec.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/acpi.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "ec.h"
+
+void lumpy_ec_init(void)
+{
+	printk(BIOS_DEBUG, "lumpy_ec_init\n");
+
+	if (acpi_slp_type == 3)
+		return;
+
+	/*
+	 * Enable EC control of fan speed.
+	 *
+	 * This will be changed to OS control in ACPI EC _REG
+	 * method when the OS is ready to control the fan.
+	 */
+	ec_write(EC_FAN_SPEED, 0);
+
+	send_ec_command_data(EC_BATTERY_MODE, EC_BATTERY_MODE_NORMAL);
+	send_ec_command_data(EC_POWER_BUTTON_MODE, EC_POWER_BUTTON_MODE_OS);
+}
diff --git a/src/mainboard/samsung/lumpy/ec.h b/src/mainboard/samsung/lumpy/ec.h
new file mode 100644
index 0000000..3f90211
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/ec.h
@@ -0,0 +1,61 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_EC_H
+#define LUMPY_EC_H
+
+#define EC_MAILBOX_PORT               0xa00 /* Mailbox IO address */
+#define EC_SMI_GPI                    1     /* GPIO 1 is KBC3_EXTSMI# */
+
+/* Commands */
+#define EC_SMI_ENABLE                 0x74
+#define EC_SMI_DISABLE                0x75
+#define EC_ACPI_ENABLE                0x76 /* Enter ACPI mode */
+#define EC_ACPI_DISABLE               0x77 /* Exit ACPI mode */
+
+/* Commands with data */
+#define EC_AUX_PORT_MODE              0x64 /* PS/2 control mode */
+#define  EC_AUX_PORT_MODE_ENABLE       0x00
+#define  EC_AUX_PORT_MODE_DISABLE      0x01
+#define EC_POWER_BUTTON_MODE          0x63
+#define  EC_POWER_BUTTON_MODE_OS       0x00 /* OS control, 8 second override */
+#define  EC_POWER_BUTTON_MODE_EC       0x01 /* EC control */
+#define EC_BACKLIGHT_OFF              0x67  /* Turn Backlight Off */
+#define EC_BACKLIGHT_ON               0x68  /* Turn Backlight On */
+#define EC_BATTERY_MODE               0x13
+#define  EC_BATTERY_MODE_NORMAL        0x00 /* Normal mode */
+#define  EC_BATTERY_MODE_EXTEND        0x01 /* Battery Life Cycle Extension */
+#define EC_GET_SMI_CAUSE              0x72  /* Get cause of SMI */
+
+/* EC RAM */
+#define EC_FAN_SPEED                  0xca
+#define  EC_FAN_SPEED_LEVEL_0	       0x01 /* Level 0 is fastest */
+#define  EC_FAN_SPEED_LEVEL_1	       0x02 /* Level 1 is fast */
+#define  EC_FAN_SPEED_LEVEL_2	       0x04 /* Level 2 is slow */
+#define  EC_FAN_SPEED_LEVEL_3	       0x08 /* Level 3 is slowest */
+#define  EC_FAN_SPEED_LEVEL_4	       0x10 /* Level 4 is off */
+#define  EC_FAN_SPEED_FLAG_OS          0x80 /* OS control of fan speed */
+
+/* EC SMI */
+#define EC_LID_CLOSE                  0x9c  /* Lid close event */
+#define EC_LID_OPEN                   0x9d  /* Lid open event */
+
+extern void lumpy_ec_init(void);
+
+#endif // LUMPY_EC_H
diff --git a/src/mainboard/samsung/lumpy/fadt.c b/src/mainboard/samsung/lumpy/fadt.c
new file mode 100644
index 0000000..781c325
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/fadt.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+								0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_MOBILE;
+
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = ACPI_ENABLE;
+	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 16;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 87;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/samsung/lumpy/gpio.h b/src/mainboard/samsung/lumpy/gpio.h
new file mode 100644
index 0000000..af5f3e2
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/gpio.h
@@ -0,0 +1,336 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_GPIO_H
+#define LUMPY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+/*
+ * GPIO SET 1 includes GPIO0 to GPIO31
+ */
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0  = GPIO_MODE_GPIO,	/* CHP3_SERDBG */
+	.gpio1  = GPIO_MODE_GPIO,	/* KBC3_EXTSMI# */
+	.gpio2  = GPIO_MODE_NATIVE,	/* CHP3_ALSINT# (Light Sensor) */
+	.gpio3  = GPIO_MODE_NATIVE,	/* CHP3_TP_INT# (Trackpad) */
+	.gpio4  = GPIO_MODE_NONE,
+	.gpio5  = GPIO_MODE_GPIO,	/* SIM3_CARD_DET# */
+	.gpio6  = GPIO_MODE_NONE,
+	.gpio7  = GPIO_MODE_GPIO,	/* KBC3_RUNSCI# */
+	.gpio8  = GPIO_MODE_GPIO,	/* CHP3_INTELBT_OFF# */
+	.gpio9  = GPIO_MODE_NONE,
+	.gpio10 = GPIO_MODE_NONE,
+	.gpio11 = GPIO_MODE_GPIO,	/* CHP3_TP_INT# (Trackpad wake) */
+	.gpio12 = GPIO_MODE_NONE,
+	.gpio13 = GPIO_MODE_GPIO,	/* CHP3_DEBUG13 */
+	.gpio14 = GPIO_MODE_GPIO,	/* KBC3_WAKESCI# */
+	.gpio15 = GPIO_MODE_NONE,
+	.gpio16 = GPIO_MODE_NONE,
+	.gpio17 = GPIO_MODE_GPIO,	/* KBC3_DVP_MODE */
+	.gpio18 = GPIO_MODE_NATIVE,	/* MIN3_CLKREQ1# */
+	.gpio19 = GPIO_MODE_NONE,
+	.gpio20 = GPIO_MODE_NONE,
+	.gpio21 = GPIO_MODE_GPIO,	/* LCD3_SIZE */
+	.gpio22 = GPIO_MODE_GPIO,	/* CHP3_BIOS_CRISIS# */
+	.gpio23 = GPIO_MODE_NONE,
+	.gpio24 = GPIO_MODE_GPIO,	/* KBC3_SPI_WP# */
+	.gpio25 = GPIO_MODE_NONE,
+	.gpio26 = GPIO_MODE_NATIVE,	/* LAN3_CLKREQ# */
+	.gpio27 = GPIO_MODE_NONE,
+	.gpio28 = GPIO_MODE_NONE,
+	.gpio29 = GPIO_MODE_NONE,
+	.gpio30 = GPIO_MODE_NATIVE,	/* CHP3_SUSWARN# */
+	.gpio31 = GPIO_MODE_NATIVE,	/* KBC3_AC_PRESENT */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0  = GPIO_DIR_OUTPUT,
+	.gpio1  = GPIO_DIR_INPUT,
+	.gpio2  = GPIO_DIR_INPUT,
+	.gpio3  = GPIO_DIR_INPUT,
+	.gpio4  = GPIO_DIR_INPUT,
+	.gpio5  = GPIO_DIR_INPUT,
+	.gpio6  = GPIO_DIR_INPUT,
+	.gpio7  = GPIO_DIR_INPUT,
+	.gpio8  = GPIO_DIR_OUTPUT,
+	.gpio9  = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0  = GPIO_LEVEL_LOW,
+	.gpio1  = GPIO_LEVEL_LOW,
+	.gpio2  = GPIO_LEVEL_LOW,
+	.gpio3  = GPIO_LEVEL_LOW,
+	.gpio4  = GPIO_LEVEL_LOW,
+	.gpio5  = GPIO_LEVEL_LOW,
+	.gpio6  = GPIO_LEVEL_LOW,
+	.gpio7  = GPIO_LEVEL_LOW,
+	.gpio8  = GPIO_LEVEL_LOW,
+	.gpio9  = GPIO_LEVEL_LOW,
+	.gpio10 = GPIO_LEVEL_LOW,
+	.gpio11 = GPIO_LEVEL_LOW,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio13 = GPIO_LEVEL_LOW,
+	.gpio14 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio16 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_LOW,
+	.gpio18 = GPIO_LEVEL_LOW,
+	.gpio19 = GPIO_LEVEL_LOW,
+	.gpio20 = GPIO_LEVEL_LOW,
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio23 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio25 = GPIO_LEVEL_LOW,
+	.gpio26 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_LOW,
+	.gpio30 = GPIO_LEVEL_LOW,
+	.gpio31 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0  = GPIO_NO_INVERT,
+	.gpio1  = GPIO_INVERT,
+	.gpio2  = GPIO_INVERT,
+	.gpio3  = GPIO_INVERT,
+	.gpio4  = GPIO_NO_INVERT,
+	.gpio5  = GPIO_INVERT,
+	.gpio6  = GPIO_NO_INVERT,
+	.gpio7  = GPIO_INVERT,
+	.gpio8  = GPIO_NO_INVERT,
+	.gpio9  = GPIO_NO_INVERT,
+	.gpio10 = GPIO_NO_INVERT,
+	.gpio11 = GPIO_INVERT,
+	.gpio12 = GPIO_NO_INVERT,
+	.gpio13 = GPIO_NO_INVERT,
+	.gpio14 = GPIO_INVERT,
+	.gpio15 = GPIO_NO_INVERT,
+};
+
+/*
+ * GPIO SET 2 includes GPIO32 to GPIO63
+ */
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,	/* PCI3_CLKRUN# */
+	.gpio33 = GPIO_MODE_GPIO,	/* Onboard Memory Capacity */
+	.gpio34 = GPIO_MODE_NONE,
+	.gpio35 = GPIO_MODE_GPIO,	/* CHP3_WLAN_OFF# */
+	.gpio36 = GPIO_MODE_NONE,
+	.gpio37 = GPIO_MODE_GPIO,	/* CHP3_FDI_OVRVLTG */
+	.gpio38 = GPIO_MODE_GPIO,	/* CHP3_3G_OFF# */
+	.gpio39 = GPIO_MODE_NONE,
+	.gpio40 = GPIO_MODE_NATIVE,	/* USB3_OC1# */
+	.gpio41 = GPIO_MODE_GPIO,	/* Onboard Memory Revision */
+	.gpio42 = GPIO_MODE_GPIO,	/* CHP3_REC_MODE# */
+	.gpio43 = GPIO_MODE_GPIO,	/* CHP3_HSPA_PWRON# */
+	.gpio44 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG0_CTL2# */
+	.gpio45 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG0_CTL3# */
+	.gpio46 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG1_CTL2# */
+	.gpio47 = GPIO_MODE_GPIO,	/* CHP3_CHG_ENABLE0 */
+	.gpio48 = GPIO_MODE_GPIO,	/* CHP3_BT_OFF# */
+	.gpio49 = GPIO_MODE_GPIO,	/* Onboard Memory Vendor */
+	.gpio50 = GPIO_MODE_NONE,
+	.gpio51 = GPIO_MODE_NONE,
+	.gpio52 = GPIO_MODE_NONE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NONE,
+	.gpio55 = GPIO_MODE_GPIO,	/* STP_A16OVR */
+	.gpio56 = GPIO_MODE_GPIO,	/* CHP3_CHG_ENABLE1 */
+	.gpio57 = GPIO_MODE_GPIO,	/* CHP3_DEBUG10 */
+	.gpio58 = GPIO_MODE_NATIVE,	/* SIO3_THERM_SMCLK# */
+	.gpio59 = GPIO_MODE_NATIVE,	/* USB3_OC0# */
+	.gpio60 = GPIO_MODE_GPIO,	/* CHP3_DRAMRST_GATE */
+	.gpio61 = GPIO_MODE_NATIVE,	/* CHP3_SUSSTAT# */
+	.gpio62 = GPIO_MODE_NATIVE,	/* CHP3_SUSCLK */
+	.gpio63 = GPIO_MODE_NATIVE,	/* CHP3_SLPS5# */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_OUTPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_OUTPUT,
+	.gpio44 = GPIO_DIR_OUTPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio47 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio56 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+	.gpio62 = GPIO_DIR_INPUT,
+	.gpio63 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_LOW,
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_HIGH,	/* Enable WLAN */
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_HIGH,	/* Enable 3G */
+	.gpio39 = GPIO_LEVEL_LOW,
+	.gpio40 = GPIO_LEVEL_LOW,
+	.gpio41 = GPIO_LEVEL_LOW,
+	.gpio42 = GPIO_LEVEL_LOW,
+	.gpio43 = GPIO_LEVEL_LOW,
+	.gpio44 = GPIO_LEVEL_HIGH,	/* CTL2=1 for USB0 SDP */
+	.gpio45 = GPIO_LEVEL_LOW,	/* CTL3=0 for USB0 SDP */
+	.gpio46 = GPIO_LEVEL_HIGH,	/* CTL2=1 for USB1 SDP */
+	.gpio47 = GPIO_LEVEL_HIGH,	/* Enable USB0 */
+	.gpio48 = GPIO_LEVEL_LOW,	/* Disable Bluetooth */
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio50 = GPIO_LEVEL_LOW,
+	.gpio51 = GPIO_LEVEL_LOW,
+	.gpio52 = GPIO_LEVEL_LOW,
+	.gpio53 = GPIO_LEVEL_LOW,
+	.gpio54 = GPIO_LEVEL_LOW,
+	.gpio55 = GPIO_LEVEL_LOW,
+	.gpio56 = GPIO_LEVEL_HIGH,	/* Enable USB1 */
+	.gpio57 = GPIO_LEVEL_LOW,
+	.gpio58 = GPIO_LEVEL_LOW,
+	.gpio59 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_LOW,
+	.gpio62 = GPIO_LEVEL_LOW,
+	.gpio63 = GPIO_LEVEL_LOW,
+};
+
+/*
+ * GPIO SET 3 includes GPIO64 to GPIO75
+ */
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NONE,
+	.gpio65 = GPIO_MODE_NONE,
+	.gpio66 = GPIO_MODE_NONE,
+	.gpio67 = GPIO_MODE_NONE,
+	.gpio68 = GPIO_MODE_NONE,
+	.gpio69 = GPIO_MODE_GPIO,	/* PEX3_WWAN_DET# */
+	.gpio70 = GPIO_MODE_GPIO,	/* CHP3_WLAN_RST# */
+	.gpio71 = GPIO_MODE_GPIO,	/* CHP3_WLAN_PWRON */
+	.gpio72 = GPIO_MODE_NATIVE,	/* BATLOW# (pullup) */
+	.gpio73 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG1_CTL3# */
+	.gpio74 = GPIO_MODE_NONE,
+	.gpio75 = GPIO_MODE_NATIVE,	/* SIO3_THERM_SMDATA# */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_OUTPUT,
+	.gpio71 = GPIO_DIR_OUTPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio73 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+	.gpio75 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_LOW,
+	.gpio65 = GPIO_LEVEL_LOW,
+	.gpio66 = GPIO_LEVEL_LOW,
+	.gpio67 = GPIO_LEVEL_LOW,
+	.gpio68 = GPIO_LEVEL_LOW,
+	.gpio69 = GPIO_LEVEL_LOW,
+	.gpio70 = GPIO_LEVEL_HIGH,	/* WLAN out of reset */
+	.gpio71 = GPIO_LEVEL_HIGH,	/* WLAN power on */
+	.gpio72 = GPIO_LEVEL_LOW,
+	.gpio73 = GPIO_LEVEL_LOW,	/* USB1 CTL3=0 for SDP */
+	.gpio74 = GPIO_LEVEL_LOW,
+	.gpio75 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_reset = {
+	.gpio38 = GPIO_RESET_RSMRST,
+	.gpio43 = GPIO_RESET_RSMRST,
+};
+
+const struct pch_gpio_map lumpy_gpio_map = {
+	.set1 = {
+		.mode      = &pch_gpio_set1_mode,
+		.direction = &pch_gpio_set1_direction,
+		.level     = &pch_gpio_set1_level,
+		.invert    = &pch_gpio_set1_invert,
+	},
+	.set2 = {
+		.mode      = &pch_gpio_set2_mode,
+		.direction = &pch_gpio_set2_direction,
+		.level     = &pch_gpio_set2_level,
+		.reset     = &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode      = &pch_gpio_set3_mode,
+		.direction = &pch_gpio_set3_direction,
+		.level     = &pch_gpio_set3_level,
+	},
+};
+
+#endif
diff --git a/src/mainboard/samsung/lumpy/hda_verb.h b/src/mainboard/samsung/lumpy/hda_verb.h
new file mode 100644
index 0000000..732f0aa
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/hda_verb.h
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10134210,	// Codec Vendor / Device ID: Realtek ALC262
+	0x144db082,	// Subsystem ID
+	0x00000007,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144dc0c2 */
+	0x00172082,
+	0x001721b0,
+	0x0017224d,
+	0x00172314,
+
+	0x00170500,
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x05) */
+	0x00571cf0,
+	0x00571d10,
+	0x00571e21,
+	0x00571f02,
+
+	/* Pin Complex (NID 0x06) */
+	0x00671cf0,
+	0x00671d00,
+	0x00671e17,
+	0x00671f90,
+
+	/* Pin Complex (NID 0x07) */
+	0x00771cf0,
+	0x00771d10,
+	0x00771ea1,
+	0x00771f02,
+
+	/* Pin Complex (NID 0x08) */
+	0x00871c37,
+	0x00871d00,
+	0x00871ea7,
+	0x00871f77,
+
+	/* Pin Complex (NID 0x09) */
+	0x00971c3e,
+	0x00971d00,
+	0x00971ea6,
+	0x00971fb7,
+
+	/* Pin Complex (NID 0x0a) */
+	0x00a71cf0,
+	0x00a71d10,
+	0x00a71e45,
+	0x00a71f43
+};
diff --git a/src/mainboard/samsung/lumpy/mainboard.c b/src/mainboard/samsung/lumpy/mainboard.c
new file mode 100644
index 0000000..c5db0d3
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/mainboard.c
@@ -0,0 +1,332 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "hda_verb.h"
+#include "chip.h"
+#include "ec.h"
+#include "onboard.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <smbios.h>
+
+void mainboard_suspend_resume(void)
+{
+	/* Call SMM finalize() handlers before resume */
+	outb(0xcb, 0xb2);
+
+	/* Enable EC ACPI mode for the OS before resume */
+	send_ec_command(EC_SMI_DISABLE);
+	send_ec_command(EC_ACPI_ENABLE);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	return add_northbridge_resources(mem);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res=-1;
+
+	printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+			__func__, regs->eax & 0xffff);
+
+	switch(regs->eax & 0xffff) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffffff00;
+		regs->ecx |= 0x00;
+		res = 0;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0000;
+		res = 0;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0001;
+		res = 0;
+		break;
+	case 0x5f70:
+		switch ((regs->ecx >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 1:
+			/* Set Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				((regs->ecx >> 8) & 0xff));
+			return 0;
+		}
+		break;
+
+        default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CL = 0x00;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 1;
+		break;
+	case 0x5f70:
+		switch (M.x86.R_CH) {
+		case 0:
+			/* Get Mux */
+			printk(BIOS_DEBUG, "Get Mux\n");
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CL = 0;
+			break;
+		case 1:
+			printk(BIOS_DEBUG, "Set Mux\n");
+			/* Set Mux */
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CX = 0;
+			break;
+		case 2:
+			printk(BIOS_DEBUG, "Get SG Mode\n");
+			/* Get SG/Non-SG mode */
+			M.x86.R_AX = 0x005f;
+			M.x86.R_CX = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				M.x86.R_CH);
+			return 0;
+		}
+		break;
+	default:
+		/* Interrupt was not handled */
+		printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+			M.x86.R_AX);
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+static void mainboard_init(device_t dev)
+{
+	/* Initialize the Embedded Controller */
+	lumpy_ec_init();
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+	dev->ops->init = mainboard_init;
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
+	verb_setup();
+}
+
+static int lumpy_smbios_type41_irq(int *handle, unsigned long *current,
+				   const char *name, u8 irq, u8 addr)
+{
+	struct smbios_type41 *t = (struct smbios_type41 *)*current;
+	int len = sizeof(struct smbios_type41);
+
+	memset(t, 0, sizeof(struct smbios_type41));
+	t->type = SMBIOS_ONBOARD_DEVICES_EXTENDED_INFORMATION;
+	t->handle = *handle;
+	t->length = len - 2;
+	t->reference_designation = smbios_add_string(t->eos, name);
+	t->device_type = SMBIOS_DEVICE_TYPE_OTHER;
+	t->device_status = 1;
+	t->device_type_instance = irq;
+	t->segment_group_number = 0;
+	t->bus_number = addr;
+	t->function_number = 0;
+	t->device_number = 0;
+
+	len = t->length + smbios_string_table_len(t->eos);
+	*current += len;
+	*handle += 1;
+	return len;
+}
+
+
+static int lumpy_onboard_smbios_data(device_t dev, int *handle,
+				     unsigned long *current)
+{
+	int len = 0;
+
+	len += lumpy_smbios_type41_irq(handle, current,
+				       LUMPY_LIGHTSENSOR_NAME,
+				       LUMPY_LIGHTSENSOR_IRQ,
+				       LUMPY_LIGHTSENSOR_I2C_ADDR);
+
+	len += lumpy_smbios_type41_irq(handle, current,
+				       LUMPY_TRACKPAD_NAME,
+				       LUMPY_TRACKPAD_IRQ,
+				       LUMPY_TRACKPAD_I2C_ADDR);
+
+	return len;
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Samsung Lumpy ChromeBook")
+	.enable_dev = mainboard_enable,
+	.get_smbios_data = lumpy_onboard_smbios_data,
+};
+
diff --git a/src/mainboard/samsung/lumpy/mainboard_smi.c b/src/mainboard/samsung/lumpy/mainboard_smi.c
new file mode 100644
index 0000000..e19a185
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/mainboard_smi.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <ec/smsc/mec1308/ec.h>
+#include "ec.h"
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		gnvs->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+static u8 mainboard_smi_ec(void)
+{
+	u8 cmd;
+	u32 pm1_cnt;
+	extern u16 pmbase; /* Set in southbridge SMI handler */
+
+	cmd = read_ec_command_byte(EC_GET_SMI_CAUSE);
+
+	switch (cmd) {
+	case EC_LID_CLOSE:
+		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+		/* Go to S5 */
+		pm1_cnt = inl(pmbase + PM1_CNT);
+		pm1_cnt |= (0xf << 10);
+		outl(pm1_cnt, pmbase + PM1_CNT);
+		break;
+	}
+
+	return cmd;
+}
+
+void mainboard_smi_gpi(u16 gpi_sts)
+{
+	if (gpi_sts & (1 << EC_SMI_GPI)) {
+		/* Process all pending EC requests */
+		ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
+		while (mainboard_smi_ec() != 0xff);
+
+		/* The EC may keep asserting SMI# for some
+		 * period unless we kick it here.
+		 */
+		send_ec_command(EC_SMI_DISABLE);
+		send_ec_command(EC_SMI_ENABLE);
+	}
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+void mainboard_smi_apmc(u8 apmc)
+{
+	ec_set_ports(EC_MAILBOX_PORT, EC_MAILBOX_PORT+1);
+
+	switch (apmc) {
+	case 0xe1: /* ACPI ENABLE */
+		send_ec_command(EC_SMI_DISABLE);
+		send_ec_command(EC_ACPI_ENABLE);
+		break;
+
+	case 0x1e: /* ACPI DISABLE */
+		send_ec_command(EC_SMI_ENABLE);
+		send_ec_command(EC_ACPI_DISABLE);
+		break;
+
+	case APMC_FINALIZE:
+		if (mainboard_finalized) {
+			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+			return;
+		}
+
+		intel_me_finalize_smm();
+		intel_pch_finalize_smm();
+		intel_sandybridge_finalize_smm();
+		intel_model_206ax_finalize_smm();
+
+		mainboard_finalized = 1;
+		break;
+	}
+}
diff --git a/src/mainboard/samsung/lumpy/onboard.h b/src/mainboard/samsung/lumpy/onboard.h
new file mode 100644
index 0000000..6bdf057
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/onboard.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_ONBOARD_H
+#define LUMPY_ONBOARD_H
+
+#include <arch/smp/mpspec.h>
+
+#define LUMPY_LIGHTSENSOR_NAME      "lightsensor"
+#define LUMPY_LIGHTSENSOR_I2C_ADDR  0x44
+#define LUMPY_LIGHTSENSOR_IRQ       20
+
+#define LUMPY_TRACKPAD_NAME         "trackpad"
+#define LUMPY_TRACKPAD_I2C_ADDR     0x67
+#define LUMPY_TRACKPAD_IRQ          21
+
+#endif
diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c
new file mode 100644
index 0000000..b60f739
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/romstage.c
@@ -0,0 +1,383 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "option_table.h"
+#include "gpio.h"
+#if CONFIG_CONSOLE_SERIAL8250
+#include "superio/smsc/lpc47n207/lpc47n207.h"
+#include "superio/smsc/lpc47n207/early_serial.c"
+#endif
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+
+static void pch_enable_lpc(void)
+{
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+
+#if CONFIG_CONSOLE_SERIAL8250
+	/* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
+		KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+	try_enabling_LPC47N207_uart();
+#else
+	/* Enable SuperIO + EC + KBC */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN |
+		KBC_LPC_EN);
+#endif
+}
+
+static void rcba_config(void)
+{
+	u32 reg32;
+
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC (MSI)
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQB
+	 * D31IP_SIP   SATA   INTA -> PIRQA (MSI)
+	 * D31IP_SMIP  SMBUS  INTC -> PIRQH
+	 * D31IP_TTIP  THRT   INTB -> PIRQG
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 *
+	 * LIGHTSENSOR             -> PIRQE (Edge Triggered)
+	 * TRACKPAD                -> PIRQF (Edge Triggered)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTB << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTC << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQA, PIRQG, PIRQH, PIRQB);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQG, PIRQH);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQB, PIRQC, PIRQD, PIRQA);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA8(OIC) = 0x01;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA8(OIC);
+
+	/* Enable upper 128bytes of CMOS (generic) */
+	RCBA32(RC) = (1 << 2);
+
+	/* Disable unused devices (board specific) */
+	reg32 = RCBA32(FD);
+	reg32 |= PCH_DISABLE_ALWAYS;
+	RCBA32(FD) = reg32;
+}
+
+static void early_pch_init(void)
+{
+	u8 reg8;
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
+}
+
+void main(unsigned long bist)
+{
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	u32 pm1_cnt;
+	u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	tsc_t start_romstage_time;
+	tsc_t before_dram_time;
+	tsc_t after_dram_time;
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+#endif
+
+	struct pei_data pei_data = {
+		.mchbar = 0xfed10000,
+		.dmibar = 0xfed18000,
+		.epbar = 0xfed19000,
+		.pciexbar = 0xf0000000,
+		.smbusbar = 0x400,
+		.wdbbar = 0x4000000,
+		.wdbsize = 0x1000,
+		.hpet_address = 0xfed00000,
+		.rcba = 0xfed1c000,
+		.pmbase = 0x500,
+		.gpiobase = 0x480,
+		.thermalbase = 0xfed08000,
+		.system_type = 0, // 0 Mobile, 1 Desktop/Server
+		.tseg_size = CONFIG_SMM_TSEG_SIZE,
+		.spd_addresses = { 0x50, 0x00,0xf0,0x00 },
+		.ts_addresses = { 0x30, 0x00, 0x00, 0x00 },
+		.ec_present = 1,
+		// 0 = leave channel enabled
+		// 1 = disable dimm 0 on channel
+		// 2 = disable dimm 1 on channel
+		// 3 = disable dimm 0+1 on channel
+		.dimm_channel0_disabled = 2,
+		.dimm_channel1_disabled = 2,
+		.usb_port_config = {
+			{ 1, 0, 0x0080 }, /* P0: Port 0      (OC0) */
+			{ 1, 1, 0x0080 }, /* P1: Port 1      (OC1) */
+			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
+			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
+			{ 0, 0, 0x0000 }, /* P4: Empty */
+			{ 0, 0, 0x0000 }, /* P5: Empty */
+			{ 0, 0, 0x0000 }, /* P6: Empty */
+			{ 0, 0, 0x0000 }, /* P7: Empty */
+			{ 1, 4, 0x0040 }, /* P8: MINIPCIE2   (no OC) */
+			{ 0, 4, 0x0000 }, /* P9: Empty */
+			{ 0, 4, 0x0000 }, /* P10: Empty */
+			{ 1, 4, 0x0040 }, /* P11: Camera     (no OC) */
+			{ 0, 4, 0x0000 }, /* P12: Empty */
+			{ 0, 4, 0x0000 }, /* P13: Empty */
+		},
+		.spd_data = {
+		}
+	};
+
+	typedef const uint8_t spd_blob[256];
+	struct cbfs_file *spd_file;
+	spd_blob *spd_data;
+
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	start_romstage_time = rdtsc();
+#endif
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+	setup_pch_gpios(&lumpy_gpio_map);
+
+	console_init();
+
+#if CONFIG_CHROMEOS
+	save_chromeos_gpios();
+#endif
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected\n");
+		boot_mode = 1;
+
+		/* System is not happy after keyboard reset... */
+		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+		outb(0x6, 0xcf9);
+		hlt();
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+	/* Check PM1_STS[15] to see if we are waking from Sx */
+	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+	/* Read PM1_CNT[12:10] to determine which Sx state */
+	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	post_code(0x38);
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	/* Prepare USB controller early in S3 resume */
+	if (boot_mode == 2)
+		enable_usb_bar();
+
+	u32 gp_lvl2 = inl(DEFAULT_GPIOBASE + 0x38);
+	u8 gpio33, gpio41, gpio49;
+	gpio33 = (gp_lvl2 >> (33-32)) & 1;
+	gpio41 = (gp_lvl2 >> (41-32)) & 1;
+	gpio49 = (gp_lvl2 >> (49-32)) & 1;
+	printk(BIOS_DEBUG, "Memory Straps:\n");
+	printk(BIOS_DEBUG, " - memory capacity %dGB\n",
+		gpio33 ? 2 : 1);
+	printk(BIOS_DEBUG, " - die revision %d\n",
+		gpio41 ? 2 : 1);
+	printk(BIOS_DEBUG, " - vendor %s\n",
+		gpio49 ? "Samsung" : "Other");
+
+	int spd_index = 0;
+
+	switch ((gpio49 << 2) | (gpio41 << 1) | gpio33) {
+	case 0: // Other 1G Rev 1
+		spd_index = 0;
+		break;
+	case 2: // Other 1G Rev 2
+		spd_index = 1;
+		break;
+	case 1: // Other 2G Rev 1
+	case 3: // Other 2G Rev 2
+		spd_index = 2;
+		break;
+	case 4: // Samsung 1G Rev 1
+		spd_index = 3;
+		break;
+	case 6: // Samsung 1G Rev 2
+		spd_index = 4;
+		break;
+	case 5: // Samsung 2G Rev 1
+	case 7: // Samsung 2G Rev 2
+		spd_index = 5;
+		break;
+	}
+
+	spd_file = cbfs_find("spd.bin");
+	if (!spd_file)
+		die("SPD data not found.");
+	if (spd_file->len < (spd_index + 1) * 256)
+		die("Missing SPD data.");
+	spd_data = (spd_blob *)CBFS_SUBHEADER(spd_file);
+	// leave onboard dimm address at f0, and copy spd data there.
+	memcpy(pei_data.spd_data[0], spd_data[spd_index], 256);
+
+	post_code(0x39);
+	pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = rdtsc();
+#endif
+	sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = rdtsc();
+#endif
+	post_code(0x3a);
+	/* Perform some initialization that must run before stage2 */
+	early_pch_init();
+	post_code(0x3b);
+
+	rcba_config();
+	post_code(0x3c);
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	sandybridge_late_initialization();
+
+	post_code(0x3e);
+	quick_ram_check();
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+
+#if CONFIG_EARLY_CBMEM_INIT
+	cbmem_was_initted = !cbmem_initialize();
+#else
+	cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+						     - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+
+	*(u32 *)CBMEM_BOOT_MODE = 0;
+	*(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		if (resume_backup_memory) {
+			*(u32 *)CBMEM_BOOT_MODE = boot_mode;
+			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+		}
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else if (boot_mode == 2) {
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0x6, 0xcf9);
+		hlt();
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+	post_code(0x3f);
+#if CONFIG_CHROMEOS
+	init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/samsung/lumpy/spd.hex b/src/mainboard/samsung/lumpy/spd.hex
new file mode 100644
index 0000000..8690886
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/spd.hex
@@ -0,0 +1,96 @@
+0000000: 92 10 0b 03 02 11 00 01 03 52 01 08 0c 00 3e 00  .........R....>.
+0000010: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01  ixi0i. .p.<<....
+0000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000030: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00  ..............!.
+0000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000070: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 d3 0d  ................
+0000080: 4d 34 37 31 42 32 38 37 33 46 48 53 2d 43 48 39  M471B2873FHS-CH9
+0000090: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00    ..............
+00000a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00000f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000100: 92 10 0b 03 02 11 00 01 03 52 01 08 0f 00 1e 00  .........R......
+0000110: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01  ixi<i.,.p.<<.,..
+0000120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000130: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00  ..............!.
+0000140: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000150: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000160: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000170: 00 00 00 00 00 80 ce 02 10 31 81 1d 77 ce 91 a4  .........1..w...
+0000180: 4d 34 37 31 42 32 38 37 33 46 48 53 2d 43 46 38  M471B2873FHS-CF8
+0000190: 20 20 00 00 80 ce 00 00 00 53 47 30 44 35 31 31    .......SG0D511
+00001a0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001b0: 01 a0 04 38 20 06 57 31 00 00 00 00 00 00 00 00  ...8 .W1........
+00001c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00001f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000200: 92 10 0b 03 03 19 00 01 03 52 01 08 0c 00 7e 00  .........R....~.
+0000210: 69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 81  ixi0i. ...<<....
+0000220: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000230: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00  ..............A.
+0000240: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000250: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000260: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000270: 00 00 00 00 00 02 fe 00 00 00 00 00 00 00 29 2b  ..............)+
+0000280: 45 42 4a 32 30 55 46 38 42 44 55 30 2d 44 4a 2d  EBJ20UF8BDU0-DJ-
+0000290: 46 20 30 20 02 fe 00 00 00 00 00 00 00 00 00 00  F 0 ............
+00002a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00002f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000300: 92 11 0b 03 02 11 00 01 03 11 01 08 0c 00 3e 00  ..............>.
+0000310: 69 78 69 30 69 11 20 89 70 03 3c 3c 00 f0 83 01  ixi0i. .p.<<....
+0000320: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000330: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00  ..............A.
+0000340: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000350: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000360: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000370: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 cf 74  ...............t
+0000380: 4d 34 37 31 42 32 38 37 33 47 42 30 2d 43 48 39  M471B2873GB0-CH9
+0000390: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00    ..............
+00003a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00003f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000400: 92 11 0b 03 02 11 00 01 03 11 01 08 0f 00 1e 00  ................
+0000410: 69 78 69 3c 69 11 2c 95 70 03 3c 3c 01 2c 83 01  ixi<i.,.p.<<.,..
+0000420: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000430: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 41 00  ..............A.
+0000440: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000450: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000460: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000470: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 8d dd  ................
+0000480: 4d 34 37 31 42 32 38 37 33 47 42 30 2d 43 46 38  M471B2873GB0-CF8
+0000490: 20 20 00 00 80 ce 00 00 00 00 00 00 00 00 00 00    ..............
+00004a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004b0: 01 a0 04 38 20 06 57 31 00 00 00 00 00 00 00 00  ...8 .W1........
+00004c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00004f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000500: 92 10 0b 03 03 19 00 01 03 52 01 08 0c 00 3e 00  .........R....>.
+0000510: 69 78 69 30 69 11 20 89 00 05 3c 3c 00 f0 83 01  ixi0i. ...<<....
+0000520: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000530: 00 00 00 00 00 00 00 00 00 00 00 00 0f 11 21 00  ..............!.
+0000540: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000550: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000560: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+0000570: 00 00 00 00 00 80 ce 01 00 00 00 00 00 00 4c db  ..............L.
+0000580: 4d 34 37 31 42 35 37 37 33 43 48 53 2d 43 48 39  M471B5773CHS-CH9
+0000590: 20 20 00 00 80 ce 00 00 00 53 30 58 44 30 30 30    .......S0XD000
+00005a0: 01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
+00005f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
diff --git a/src/mainboard/samsung/lumpy/thermal.h b/src/mainboard/samsung/lumpy/thermal.h
new file mode 100644
index 0000000..82c413c
--- /dev/null
+++ b/src/mainboard/samsung/lumpy/thermal.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef LUMPY_THERMAL_H
+#define LUMPY_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF	0
+#define FAN4_THRESHOLD_ON	0
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF	44
+#define FAN3_THRESHOLD_ON	48
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF	48
+#define FAN2_THRESHOLD_ON	54
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF	60
+#define FAN1_THRESHOLD_ON	64
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF	66
+#define FAN0_THRESHOLD_ON	78
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE	100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE	90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE		100
+
+#endif
diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig
new file mode 100644
index 0000000..a49fe80
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/Kconfig
@@ -0,0 +1,61 @@
+if BOARD_SAMSUNG_STUMPY
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select ARCH_X86
+	select CPU_INTEL_SOCKET_RPGA989
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SOUTHBRIDGE_INTEL_BD82X6X
+	select SUPERIO_ITE_IT8772F
+	select BOARD_HAS_FADT
+	select HAVE_ACPI_TABLES
+	select HAVE_OPTION_TABLE
+	select HAVE_ACPI_RESUME
+	select HAVE_MAINBOARD_RESOURCES
+	select MMCONF_SUPPORT
+	select HAVE_SMI_HANDLER
+	select BOARD_ROMSIZE_KB_8192
+	select GFXUMA
+	select CHROMEOS
+
+config MAINBOARD_DIR
+	string
+	default samsung/stumpy
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "Stumpy"
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xf0000000
+
+config IRQ_SLOT_COUNT
+	int
+	default 18
+
+config MAX_CPUS
+	int
+	default 8
+
+config MAX_PHYSICAL_CPUS
+	int
+	default 2
+
+config VGA_BIOS_FILE
+	string
+	default "pci8086,0106.rom"
+
+config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+	hex
+	default 0x1ae0
+
+config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+	hex
+	default 0xc000
+
+config MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+	bool
+	default n
+
+endif # BOARD_SAMSUNG_STUMPY
diff --git a/src/mainboard/samsung/stumpy/Makefile.inc b/src/mainboard/samsung/stumpy/Makefile.inc
new file mode 100644
index 0000000..011df45
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
+
diff --git a/src/mainboard/samsung/stumpy/acpi/chromeos.asl b/src/mainboard/samsung/stumpy/acpi/chromeos.asl
new file mode 100644
index 0000000..65202cb
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/chromeos.asl
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+Device (CRHW)
+{
+	Name(_HID, EISAID("GGL0001"))
+
+	Method(_STA, 0, Serialized)
+	{
+		Return (0xb)
+	}
+
+	Method(CHSW, 0, Serialized)
+	{
+		Name (WSHC, Package() { VBT3 })
+		Return (WSHC)
+	}
+
+	Method(FWID, 0, Serialized)
+	{
+		Name (DIW1, "")
+		ToString(VBT5, 63, DIW1)
+		Name (DIWF, Package() { DIW1 })
+		Return(DIWF)
+	}
+
+	Method(FRID, 0, Serialized)
+	{
+		Name (DIR1, "")
+		ToString(VBT6, 63, DIR1)
+		Name (DIRF, Package() { DIR1 })
+		Return (DIRF)
+	}
+
+	Method(HWID, 0, Serialized)
+	{
+		Name (DIW0, "")
+		ToString(VBT4, 255, DIW0)
+		Name (DIWH, Package() { DIW0 })
+		Return (DIWH)
+	}
+
+	Method(BINF, 0, Serialized)
+	{
+		Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 })
+		Return (FNIB)
+	}
+
+	Method(GPIO, 0, Serialized)
+	{
+		Name(OIPG, Package() {
+			Package() { 0x001, 0, 42, "CougarPoint" }, // recovery button
+			Package() { 0x002, 1, 17, "CougarPoint" }, // developer switch
+			Package() { 0x003, 1, 68, "CougarPoint" }, // firmware write protect
+			Package() { 0x100, 0,  9, "CougarPoint" }, // debug header gpio
+			Package() { 0x101, 0, 10, "CougarPoint" }, // debug header gpio 1
+			Package() { 0x102, 0, 12, "CougarPoint" }, // debug header gpio 2
+			Package() { 0x103, 0, 13, "CougarPoint" }, // debug header gpio 3
+			Package() { 0x104, 0, 14, "CougarPoint" }, // debug header gpio 4
+			Package() { 0x105, 0, 15, "CougarPoint" }, // debug header gpio 5
+			Package() { 0x106, 0, 24, "CougarPoint" }, // debug header gpio 6
+			Package() { 0x107, 0, 26, "CougarPoint" }, // debug header gpio 7
+		})
+		Return (OIPG)
+
+	}
+
+	Method(VBNV, 0, Serialized)
+	{
+		Name(VNBV, Package() {
+			// See src/vendorcode/google/chromeos/Kconfig
+			// for the definition of these:
+			CONFIG_VBNV_OFFSET,
+			CONFIG_VBNV_SIZE
+		})
+		Return(VNBV)
+	}
+
+	Method(VDAT, 0, Serialized)
+	{
+		Name(TAD0,"")
+		ToBuffer(CHVD, TAD0)
+		Name (TADV, Package() { TAD0 })
+		Return (TADV)
+	}
+
+	Method(FMAP, 0, Serialized)
+	{
+		Name(PAMF, Package() { VBT9 })
+		Return(PAMF)
+	}
+
+	Method(MECK, 0, Serialized)
+	{
+		Name(HASH, Package() { MEHH })
+		Return(HASH)
+	}
+
+	Method(MLST, 0, Serialized)
+	{
+		Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF",
+			   "GPIO", "VBNV", "VDAT", "FMAP", "MECK"
+		})
+		Return (TSLM)
+	}
+}
diff --git a/src/mainboard/samsung/stumpy/acpi/ec.asl b/src/mainboard/samsung/stumpy/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/ec.asl
diff --git a/src/mainboard/samsung/stumpy/acpi/mainboard.asl b/src/mainboard/samsung/stumpy/acpi/mainboard.asl
new file mode 100644
index 0000000..151c13d
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Scope (\_SB) {
+	Device (PWRB)
+	{
+		Name(_HID, EisaId("PNP0C0C"))
+
+		// SIO3_WAKESCI# is GPIO14
+		Name(_PRW, Package(){0x1d, 0x05})
+	}
+}
diff --git a/src/mainboard/samsung/stumpy/acpi/platform.asl b/src/mainboard/samsung/stumpy/acpi/platform.asl
new file mode 100644
index 0000000..1887509
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/platform.asl
@@ -0,0 +1,125 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* The APM port can be used for generating software SMIs */
+
+OperationRegion (APMP, SystemIO, 0xb2, 2)
+Field (APMP, ByteAcc, NoLock, Preserve)
+{
+	APMC, 8,	// APM command
+	APMS, 8		// APM status
+}
+
+/* Port 80 POST */
+
+OperationRegion (POST, SystemIO, 0x80, 1)
+Field (POST, ByteAcc, Lock, Preserve)
+{
+	DBG0, 8
+}
+
+/* SMI I/O Trap */
+Method(TRAP, 1, Serialized)
+{
+	Store (Arg0, SMIF)	// SMI Function
+	Store (0, TRP0)		// Generate trap
+	Return (SMIF)		// Return value of SMI handler
+}
+
+/* The _PIC method is called by the OS to choose between interrupt
+ * routing via the i8259 interrupt controller or the APIC.
+ *
+ * _PIC is called with a parameter of 0 for i8259 configuration and
+ * with a parameter of 1 for Local Apic/IOAPIC configuration.
+ */
+
+Method(_PIC, 1)
+{
+	// Remember the OS' IRQ routing choice.
+	Store(Arg0, PICM)
+}
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+	Store (Zero, GP08)  // Disable Bluetooth
+
+	If (LEqual (Arg0, 3)) {
+		// NVS has a flag to determine USB policy in S3
+		If (S3U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S3
+		If (S3U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+	If (LEqual (Arg0, 5)) {
+		// NVS has a flag to determine USB policy in S5
+		If (S5U0) {
+			Store (One, GP47)   // Enable USB0
+		} Else {
+			Store (Zero, GP47)  // Disable USB0
+		}
+
+		// NVS has a flag to determine USB policy in S5
+		If (S5U1) {
+			Store (One, GP56)   // Enable USB1
+		} Else {
+			Store (Zero, GP56)  // Disable USB1
+		}
+	}
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
+/* CMOS Access */
+OperationRegion (CMOS, SystemIO, 0x70, 0x71)
+Field (CMOS, ByteAcc, NoLock, Preserve)
+{
+	NVRI, 8,
+	NVRD, 8,
+}
+
+IndexField (NVRI, NVRD, ByteAcc, NoLock, Preserve)
+{
+	Offset (0x32),
+	US3B, 8,	// USB Controller Reset S3 behavior
+}
+
+#define USB_RESET_DISABLE_MAGIC 0xdd
+
+/* Disable USB Controller Reset in S3 (defaults to enabled) */
+Method (USBR, 0, Serialized)
+{
+	Store (USB_RESET_DISABLE_MAGIC, US3B)
+}
diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
new file mode 100644
index 0000000..9963fbf
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is board specific information: IRQ routing for Sandybridge */
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+	If (PICM) {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, 0, 16 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, 0, 22 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, 0, 17 },
+			Package() { 0x001cffff, 1, 0, 18 },
+			Package() { 0x001cffff, 2, 0, 19 },
+			Package() { 0x001cffff, 3, 0, 20 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, 0, 19 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, 0, 20 },
+			// LPC devices			0:1f.0
+			Package() { 0x001fffff, 0, 0, 21 },
+			Package() { 0x001fffff, 1, 0, 22 },
+			Package() { 0x001fffff, 2, 0, 23 },
+			Package() { 0x001fffff, 3, 0, 16 },
+		})
+	} Else {
+		Return (Package() {
+			// Onboard graphics (IGD)	0:2.0
+			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+			// High Definition Audio	0:1b.0
+			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
+			// PCIe Root Ports		0:1c.x
+			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 },
+			// EHCI	#1			0:1d.0
+			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+			// EHCI	#2			0:1a.0
+			Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 },
+			// LPC device			0:1f.0
+			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 },
+			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 },
+			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 },
+			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 },
+		})
+	}
+}
+
diff --git a/src/mainboard/samsung/stumpy/acpi/superio.asl b/src/mainboard/samsung/stumpy/acpi/superio.asl
new file mode 100644
index 0000000..24bc8cf
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/superio.asl
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Values should match those defined in devicetree.cb */
+
+#undef SIO_ENABLE_FDC0           // pnp 2e.0: Disable Floppy Controller
+#undef SIO_ENABLE_INFR           // pnp 2e.a: Disable Consumer IR
+
+#define SIO_ENABLE_PS2K          // pnp 2e.5: Enable PS/2 Keyboard
+#define SIO_ENABLE_PS2M          // pnp 2e.6: Enable PS/2 Mouse
+#define SIO_ENABLE_COM1          // pnp 2e.1: Enable Serial Port 1
+#define SIO_ENABLE_ENVC          // pnp 2e.4: Enable Environmental Controller
+#define SIO_ENVC_IO0      0x700  // pnp 2e.4: io 0x60
+#define SIO_ENVC_IO1      0x710  // pnp 2e.4: io 0x62
+#define SIO_ENABLE_GPIO	  	 // pnp 2e.7: Enable GPIO
+#define SIO_GPIO_IO0      0x720  // pnp 2e.7: io 0x60
+#define SIO_GPIO_IO1      0x730  // pnp 2e.7: io 0x60
+
+#include "../../../../superio/ite/it8772f/acpi/superio.asl"
diff --git a/src/mainboard/samsung/stumpy/acpi/thermal.asl b/src/mainboard/samsung/stumpy/acpi/thermal.asl
new file mode 100644
index 0000000..d96d955
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi/thermal.asl
@@ -0,0 +1,274 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Thermal Zone
+
+Scope (\_TZ)
+{
+	ThermalZone (THRM)
+	{
+		Name (_TC1, 0x02)
+		Name (_TC2, 0x05)
+
+		// Thermal zone polling frequency: 10 seconds
+		Name (_TZP, 100)
+
+		// Thermal sampling period for passive cooling: 2 seconds
+		Name (_TSP, 20)
+
+		// Convert from Degrees C to 1/10 Kelvin for ACPI
+		Method (CTOK, 1) {
+			// 10th of Degrees C
+			Multiply (Arg0, 10, Local0)
+
+			// Convert to Kelvin
+			Add (Local0, 2732, Local0)
+
+			Return (Local0)
+		}
+
+		// Threshold for OS to shutdown
+		Method (_CRT, 0, Serialized)
+		{
+			Return (CTOK (\TCRT))
+		}
+
+		// Threshold for passive cooling
+		Method (_PSV, 0, Serialized)
+		{
+			Return (CTOK (\TPSV))
+		}
+
+		// Processors used for passive cooling
+		Method (_PSL, 0, Serialized)
+		{
+			Return (\PPKG ())
+		}
+
+		Method (_TMP, 0, Serialized)
+		{
+			// Get CPU Temperature from PECI via SuperIO TMPIN3
+			Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0)
+
+			// Check for invalid readings
+			If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) {
+				Return (CTOK (\F2ON))
+			}
+
+			// PECI raw value is an offset from Tj_max
+			Subtract (255, Local0, Local1)
+
+			// Handle values greater than Tj_max
+			If (LGreaterEqual (Local1, \TMAX)) {
+				Return (CTOK (\TMAX))
+			}
+
+			// Subtract from Tj_max to get temperature
+			Subtract (\TMAX, Local1, Local0)
+			Return (CTOK (Local0))
+		}
+
+		Method (_AC0) {
+			If (LLessEqual (\FLVL, 0)) {
+				Return (CTOK (\F0OF))
+			} Else {
+				Return (CTOK (\F0ON))
+			}
+		}
+
+		Method (_AC1) {
+			If (LLessEqual (\FLVL, 1)) {
+				Return (CTOK (\F1OF))
+			} Else {
+				Return (CTOK (\F1ON))
+			}
+		}
+
+		Method (_AC2) {
+			If (LLessEqual (\FLVL, 2)) {
+				Return (CTOK (\F2OF))
+			} Else {
+				Return (CTOK (\F2ON))
+			}
+		}
+
+		Method (_AC3) {
+			If (LLessEqual (\FLVL, 3)) {
+				Return (CTOK (\F3OF))
+			} Else {
+				Return (CTOK (\F3ON))
+			}
+		}
+
+		Method (_AC4) {
+			If (LLessEqual (\FLVL, 4)) {
+				Return (CTOK (\F4OF))
+			} Else {
+				Return (CTOK (\F4ON))
+			}
+		}
+
+		Name (_AL0, Package () { FAN0 })
+		Name (_AL1, Package () { FAN1 })
+		Name (_AL2, Package () { FAN2 })
+		Name (_AL3, Package () { FAN3 })
+		Name (_AL4, Package () { FAN4 })
+
+		PowerResource (FNP0, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 0)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (0, \FLVL)
+				Store (\F0PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (1, \FLVL)
+				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP1, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 1)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (1, \FLVL)
+				Store (\F1PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (2, \FLVL)
+				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP2, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 2)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (2, \FLVL)
+				Store (\F2PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (3, \FLVL)
+				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP3, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 3)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (3, \FLVL)
+				Store (\F3PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		PowerResource (FNP4, 0, 0)
+		{
+			Method (_STA) {
+				If (LLessEqual (\FLVL, 4)) {
+					Return (One)
+				} Else {
+					Return (Zero)
+				}
+			}
+			Method (_ON)  {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+			Method (_OFF) {
+				Store (4, \FLVL)
+				Store (\F4PW, \_SB.PCI0.LPCB.SIO.ENVC.F3PS)
+				Notify (\_TZ.THRM, 0x81)
+			}
+		}
+
+		Device (FAN0)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 0)
+			Name (_PR0, Package () { FNP0 })
+		}
+
+		Device (FAN1)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 1)
+			Name (_PR0, Package () { FNP1 })
+		}
+
+		Device (FAN2)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 2)
+			Name (_PR0, Package () { FNP2 })
+		}
+
+		Device (FAN3)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 3)
+			Name (_PR0, Package () { FNP3 })
+		}
+
+		Device (FAN4)
+		{
+			Name (_HID, EISAID ("PNP0C0B"))
+			Name (_UID, 4)
+			Name (_PR0, Package () { FNP4 })
+		}
+	}
+}
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/samsung/stumpy/acpi/video.asl
similarity index 60%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/samsung/stumpy/acpi/video.asl
index 1a4e70f..3ececa9 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/samsung/stumpy/acpi/video.asl
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2007-2009 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,30 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+	// TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+	// TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+	// TODO (no displays defined yet)
+}
 
diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c
new file mode 100644
index 0000000..80933df
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/acpi_tables.c
@@ -0,0 +1,330 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <vendorcode/google/chromeos/gnvs.h>
+
+extern const unsigned char AmlCode[];
+#if CONFIG_HAVE_ACPI_SLIC
+unsigned long acpi_create_slic(unsigned long current);
+#endif
+
+#include "southbridge/intel/bd82x6x/nvs.h"
+#include "thermal.h"
+
+static global_nvs_t *gnvs_;
+
+static void acpi_update_thermal_table(global_nvs_t *gnvs)
+{
+	gnvs->f4of = FAN4_THRESHOLD_OFF;
+	gnvs->f4on = FAN4_THRESHOLD_ON;
+	gnvs->f4pw = FAN4_PWM;
+
+	gnvs->f3of = FAN3_THRESHOLD_OFF;
+	gnvs->f3on = FAN3_THRESHOLD_ON;
+	gnvs->f3pw = FAN3_PWM;
+
+	gnvs->f2of = FAN2_THRESHOLD_OFF;
+	gnvs->f2on = FAN2_THRESHOLD_ON;
+	gnvs->f2pw = FAN2_PWM;
+
+	gnvs->f1of = FAN1_THRESHOLD_OFF;
+	gnvs->f1on = FAN1_THRESHOLD_ON;
+	gnvs->f1pw = FAN1_PWM;
+
+	gnvs->f0of = FAN0_THRESHOLD_OFF;
+	gnvs->f0on = FAN0_THRESHOLD_ON;
+	gnvs->f0pw = FAN0_PWM;
+
+	gnvs->tcrt = CRITICAL_TEMPERATURE;
+	gnvs->tpsv = PASSIVE_TEMPERATURE;
+	gnvs->tmax = MAX_TEMPERATURE;
+	gnvs->flvl = 5;
+}
+
+static void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+	gnvs_ = gnvs;
+	memset((void *)gnvs, 0, sizeof(*gnvs));
+	gnvs->apic = 1;
+	gnvs->mpen = 1; /* Enable Multi Processing */
+	gnvs->pcnt = dev_count_cpu();
+
+	/* Enable Front USB ports in S3 by default */
+	gnvs->s3u0 = 1;
+	gnvs->s3u1 = 1;
+
+	/*
+	 * Enable Front USB ports in S5 by default
+	 * to be consistent with back port behavior
+	 */
+	gnvs->s5u0 = 1;
+	gnvs->s5u1 = 1;
+
+	/* CBMEM TOC */
+	gnvs->cmem = (u32)get_cbmem_toc();
+
+	/* IGD Displays */
+	gnvs->ndid = 3;
+	gnvs->did[0] = 0x80000100;
+	gnvs->did[1] = 0x80000240;
+	gnvs->did[2] = 0x80000410;
+	gnvs->did[3] = 0x80000410;
+	gnvs->did[4] = 0x00000005;
+
+#if CONFIG_CHROMEOS
+	// TODO(reinauer) this could move elsewhere?
+	chromeos_init_vboot(&(gnvs->chromeos));
+#endif
+
+	acpi_update_thermal_table(gnvs);
+
+	// Stumpy has no arms^H^H^H^HEC.
+	gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+}
+
+static void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR  0xfed00000ULL
+	acpi_header_t *header = &(hpet->header);
+	acpi_addr_t *addr = &(hpet->addr);
+
+	memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+	/* fill out header fields */
+	memcpy(header->signature, "HPET", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->length = sizeof(acpi_hpet_t);
+	header->revision = 1;
+
+	/* fill out HPET address */
+	addr->space_id = 0;	/* Memory */
+	addr->bit_width = 64;
+	addr->bit_offset = 0;
+	addr->addrl = HPET_ADDR & 0xffffffff;
+	addr->addrh = HPET_ADDR >> 32;
+
+	hpet->id = 0x8086a201;	/* Intel */
+	hpet->number = 0x00;
+	hpet->min_tick = 0x0080;
+
+	header->checksum =
+	    acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+	/* Local APICs */
+	current = acpi_create_madt_lapics(current);
+
+	/* IOAPIC */
+	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+				2, IO_APIC_ADDR, 0);
+
+	/* INT_SRC_OVR */
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 0, 2, 0);
+	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
+		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
+
+	return current;
+}
+
+unsigned long acpi_fill_ssdt_generator(unsigned long current,
+					const char *oem_table_id)
+{
+	generate_cpu_entries();
+	return (unsigned long) (acpigen_get_current());
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+	// Not implemented
+	return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+	/* No NUMA, no SRAT */
+	return current;
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1);
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+	unsigned long current;
+	int i;
+	acpi_rsdp_t *rsdp;
+	acpi_rsdt_t *rsdt;
+	acpi_xsdt_t *xsdt;
+	acpi_hpet_t *hpet;
+	acpi_madt_t *madt;
+	acpi_mcfg_t *mcfg;
+	acpi_fadt_t *fadt;
+	acpi_facs_t *facs;
+#if CONFIG_HAVE_ACPI_SLIC
+	acpi_header_t *slic;
+#endif
+	acpi_header_t *ssdt;
+	acpi_header_t *dsdt;
+
+	current = start;
+
+	/* Align ACPI tables to 16byte */
+	ALIGN_CURRENT;
+
+	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start);
+
+	/* We need at least an RSDP and an RSDT Table */
+	rsdp = (acpi_rsdp_t *) current;
+	current += sizeof(acpi_rsdp_t);
+	ALIGN_CURRENT;
+	rsdt = (acpi_rsdt_t *) current;
+	current += sizeof(acpi_rsdt_t);
+	ALIGN_CURRENT;
+	xsdt = (acpi_xsdt_t *) current;
+	current += sizeof(acpi_xsdt_t);
+	ALIGN_CURRENT;
+
+	/* clear all table memory */
+	memset((void *) start, 0, current - start);
+
+	acpi_write_rsdp(rsdp, rsdt, xsdt);
+	acpi_write_rsdt(rsdt);
+	acpi_write_xsdt(xsdt);
+
+	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
+	facs = (acpi_facs_t *) current;
+	current += sizeof(acpi_facs_t);
+	ALIGN_CURRENT;
+	acpi_create_facs(facs);
+
+	printk(BIOS_DEBUG, "ACPI:    * DSDT\n");
+	dsdt = (acpi_header_t *) current;
+	memcpy(dsdt, &AmlCode, sizeof(acpi_header_t));
+	current += dsdt->length;
+	memcpy(dsdt, &AmlCode, dsdt->length);
+
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "ACPI:    * FADT\n");
+	fadt = (acpi_fadt_t *) current;
+	current += sizeof(acpi_fadt_t);
+	ALIGN_CURRENT;
+
+	acpi_create_fadt(fadt, facs, dsdt);
+	acpi_add_table(rsdp, fadt);
+
+	/*
+	 * We explicitly add these tables later on:
+	 */
+	printk(BIOS_DEBUG, "ACPI:    * HPET\n");
+
+	hpet = (acpi_hpet_t *) current;
+	current += sizeof(acpi_hpet_t);
+	ALIGN_CURRENT;
+	acpi_create_intel_hpet(hpet);
+	acpi_add_table(rsdp, hpet);
+
+	/* If we want to use HPET Timers Linux wants an MADT */
+	printk(BIOS_DEBUG, "ACPI:    * MADT\n");
+
+	madt = (acpi_madt_t *) current;
+	acpi_create_madt(madt);
+	current += madt->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, madt);
+
+	printk(BIOS_DEBUG, "ACPI:    * MCFG\n");
+	mcfg = (acpi_mcfg_t *) current;
+	acpi_create_mcfg(mcfg);
+	current += mcfg->header.length;
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, mcfg);
+
+	/* Pack GNVS into the ACPI table area */
+	for (i=0; i < dsdt->length; i++) {
+		if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) {
+			printk(BIOS_DEBUG, "ACPI: Patching up global NVS in "
+			     "DSDT at offset 0x%04x -> 0x%08lx\n", i, current);
+			*(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes
+			break;
+		}
+	}
+
+	/* And fill it */
+	acpi_create_gnvs((global_nvs_t *)current);
+
+	/* And tell SMI about it */
+	smm_setup_structures((void *)current, NULL, NULL);
+
+	current += sizeof(global_nvs_t);
+	ALIGN_CURRENT;
+
+	/* We patched up the DSDT, so we need to recalculate the checksum */
+	dsdt->checksum = 0;
+	dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length);
+
+	printk(BIOS_DEBUG, "ACPI:     * DSDT @ %p Length %x\n", dsdt,
+		     dsdt->length);
+
+#if CONFIG_HAVE_ACPI_SLIC
+	printk(BIOS_DEBUG, "ACPI:     * SLIC\n");
+	slic = (acpi_header_t *)current;
+	current += acpi_create_slic(current);
+	ALIGN_CURRENT;
+	acpi_add_table(rsdp, slic);
+#endif
+
+	printk(BIOS_DEBUG, "ACPI:     * SSDT\n");
+	ssdt = (acpi_header_t *)current;
+	acpi_create_ssdt_generator(ssdt, "COREBOOT");
+	current += ssdt->length;
+	acpi_add_table(rsdp, ssdt);
+	ALIGN_CURRENT;
+
+	printk(BIOS_DEBUG, "current = %lx\n", current);
+	printk(BIOS_INFO, "ACPI: done.\n");
+	return current;
+}
+
+#if CONFIG_CHROMEOS
+void acpi_get_vdat_info(void **vdat_addr, uint32_t *vdat_size)
+{
+	*vdat_addr = &gnvs_->chromeos.vdat;
+	*vdat_size = sizeof(gnvs_->chromeos.vdat);
+}
+#endif
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/mainboard/samsung/stumpy/chip.h
similarity index 74%
copy from src/cpu/x86/mmx_disable.inc
copy to src/mainboard/samsung/stumpy/chip.h
index 1a4e70f..831a973 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/mainboard/samsung/stumpy/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,8 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
-
+extern struct chip_operations mainboard_ops;
+struct mainboard_config {};
diff --git a/src/mainboard/samsung/stumpy/chromeos.c b/src/mainboard/samsung/stumpy/chromeos.c
new file mode 100644
index 0000000..510d737
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/chromeos.c
@@ -0,0 +1,133 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <arch/io.h>
+#ifdef __PRE_RAM__
+#include <arch/romcc_io.h>
+#else
+#include <device/device.h>
+#include <device/pci.h>
+#endif
+#include <southbridge/intel/bd82x6x/pch.h>
+
+#define GPIO_SPI_WP	68
+#define GPIO_REC_MODE	42
+#define GPIO_DEV_MODE	17
+
+#define FLAG_SPI_WP	0
+#define FLAG_REC_MODE	1
+#define FLAG_DEV_MODE	2
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+#include <arch/coreboot_tables.h>
+
+#define GPIO_COUNT	5
+#define ACTIVE_LOW	0
+#define ACTIVE_HIGH	1
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0));
+	u16 gen_pmcon_1 = pci_read_config32(dev, GEN_PMCON_1);
+
+	gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio));
+	gpios->count = GPIO_COUNT;
+
+	/* Write Protect: GPIO68 = CHP3_SPI_WP */
+	gpios->gpios[0].port = GPIO_SPI_WP;
+	gpios->gpios[0].polarity = ACTIVE_HIGH;
+	gpios->gpios[0].value =
+		(pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 2)),
+						 SATA_SP) >> FLAG_SPI_WP) & 1;
+	strncpy((char *)gpios->gpios[0].name,"write protect",
+							GPIO_MAX_NAME_LENGTH);
+
+	/* Recovery: GPIO42 = CHP3_REC_MODE# */
+	gpios->gpios[1].port = GPIO_REC_MODE;
+	gpios->gpios[1].polarity = ACTIVE_LOW;
+	gpios->gpios[1].value = !get_recovery_mode_switch();
+	strncpy((char *)gpios->gpios[1].name,"recovery", GPIO_MAX_NAME_LENGTH);
+
+	/* Developer: GPIO17 = KBC3_DVP_MODE */
+	gpios->gpios[2].port = GPIO_DEV_MODE;
+	gpios->gpios[2].polarity = ACTIVE_HIGH;
+	gpios->gpios[2].value = get_developer_mode_switch();
+	strncpy((char *)gpios->gpios[2].name,"developer", GPIO_MAX_NAME_LENGTH);
+
+	/* Hard code the lid switch GPIO to open. */
+	gpios->gpios[3].port = 100;
+	gpios->gpios[3].polarity = ACTIVE_HIGH;
+	gpios->gpios[3].value = 1;
+	strncpy((char *)gpios->gpios[3].name,"lid", GPIO_MAX_NAME_LENGTH);
+
+	/* Power Button */
+	gpios->gpios[4].port = 101;
+	gpios->gpios[4].polarity = ACTIVE_LOW;
+	gpios->gpios[4].value = (gen_pmcon_1 >> 9) & 1;
+	strncpy((char *)gpios->gpios[4].name,"power", GPIO_MAX_NAME_LENGTH);
+}
+#endif
+
+int get_developer_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_DEV_MODE) & 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	device_t dev;
+#ifdef __PRE_RAM__
+	dev = PCI_DEV(0, 0x1f, 2);
+#else
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2));
+#endif
+	return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1;
+}
+
+#ifdef __PRE_RAM__
+void save_chromeos_gpios(void)
+{
+	u16 gpio_base = pci_read_config32(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
+	u32 gp_lvl3 = inl(gpio_base + GP_LVL3);
+	u32 gp_lvl2 = inl(gpio_base + GP_LVL2);
+	u32 gp_lvl = inl(gpio_base + GP_LVL);
+	u32 flags = 0;
+
+	/* Write Protect: GPIO68 = CHP3_SPI_WP, active high */
+	if (gp_lvl3 & (1 << (GPIO_SPI_WP-64)))
+		flags |= (1 << FLAG_SPI_WP);
+	/* Recovery: GPIO42 = CHP3_REC_MODE#, active low */
+	if (!(gp_lvl2 & (1 << (GPIO_REC_MODE-32))))
+		flags |= (1 << FLAG_REC_MODE);
+	/* Developer: GPIO17 = KBC3_DVP_MODE, active high */
+	if (gp_lvl & (1 << GPIO_DEV_MODE))
+		flags |= (1 << FLAG_DEV_MODE);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
+}
+#endif
diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout
new file mode 100644
index 0000000..6d2ac45
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/cmos.layout
@@ -0,0 +1,139 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length  config config-ID    name
+#0            8       r       0        seconds
+#8            8       r       0        alarm_seconds
+#16           8       r       0        minutes
+#24           8       r       0        alarm_minutes
+#32           8       r       0        hours
+#40           8       r       0        alarm_hours
+#48           8       r       0        day_of_week
+#56           8       r       0        day_of_month
+#64           8       r       0        month
+#72           8       r       0        year
+# -----------------------------------------------------------------
+# Status Register A
+#80           4       r       0        rate_select
+#84           3       r       0        REF_Clock
+#87           1       r       0        UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88           1       r       0        auto_switch_DST
+#89           1       r       0        24_hour_mode
+#90           1       r       0        binary_values_enable
+#91           1       r       0        square-wave_out_enable
+#92           1       r       0        update_finished_enable
+#93           1       r       0        alarm_interrupt_enable
+#94           1       r       0        periodic_interrupt_enable
+#95           1       r       0        disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96           4       r       0        status_c_rsvd
+#100          1       r       0        uf_flag
+#101          1       r       0        af_flag
+#102          1       r       0        pf_flag
+#103          1       r       0        irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104          7       r       0        status_d_rsvd
+#111          1       r       0        valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112          8       r       0        diag_rsvd1
+
+# -----------------------------------------------------------------
+0          120       r       0        reserved_memory
+#120        264       r       0        unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384          1       e       4        boot_option
+385          1       e       4        last_boot
+388          4       r       0        reboot_bits
+#390          2       r       0        unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392          3       e       5        baud_rate
+395          4       e       6        debug_level
+#399          1       r       0        unused
+
+# Stumpy USB reset workaround disable
+400         8         r       0        stumpy_usb_reset_disable
+
+# coreboot config options: southbridge
+408          1       e       1        nmi
+409          2       e       7        power_on_after_fail
+#411          5       r       0        unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416        128       r        0        vbnv
+#544        440       r       0        unused
+
+# SandyBridge MRC Scrambler Seed values
+896         32        r       0        mrc_scrambler_seed
+928         32        r       0        mrc_scrambler_seed_s3
+960         16        r       0        mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984         16       h       0        check_sum
+#1000        24       r       0        amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value   text
+1     0     Disable
+1     1     Enable
+2     0     Enable
+2     1     Disable
+4     0     Fallback
+4     1     Normal
+5     0     115200
+5     1     57600
+5     2     38400
+5     3     19200
+5     4     9600
+5     5     4800
+5     6     2400
+5     7     1200
+6     1     Emergency
+6     2     Alert
+6     3     Critical
+6     4     Error
+6     5     Warning
+6     6     Notice
+6     7     Info
+6     8     Debug
+6     9     Spew
+7     0     Disable
+7     1     Enable
+7     2     Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
+
+
diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb
new file mode 100644
index 0000000..f10b283
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/devicetree.cb
@@ -0,0 +1,126 @@
+chip northbridge/intel/sandybridge
+
+	# Enable DisplayPort 1 Hotplug with 6ms pulse
+	register "gpu_dp_d_hotplug" = "0x06"
+
+	# Enable DisplayPort 0 Hotplug with 6ms pulse
+	register "gpu_dp_c_hotplug" = "0x06"
+
+	# Enable DVI Hotplug with 6ms pulse
+	register "gpu_dp_b_hotplug" = "0x06"
+
+	device lapic_cluster 0 on
+		chip cpu/intel/socket_rPGA989
+			device lapic 0 on end
+		end
+		chip cpu/intel/model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
+			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
+			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
+
+			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
+			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
+			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
+		end
+	end
+
+	device pci_domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 02.0 on end # vga controller
+
+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+			register "pirqa_routing" = "0x8b"
+			register "pirqb_routing" = "0x8a"
+			register "pirqc_routing" = "0x8b"
+			register "pirqd_routing" = "0x8b"
+			register "pirqe_routing" = "0x80"
+			register "pirqf_routing" = "0x80"
+			register "pirqg_routing" = "0x80"
+			register "pirqh_routing" = "0x80"
+
+			# GPI routing
+			#  0 No effect (default)
+			#  1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+			#  2 SCI (if corresponding GPIO_EN bit is also set)
+			register "gpi1_routing" = "0"
+			register "gpi14_routing" = "2"
+
+			register "ide_legacy_combined" = "0x0"
+			register "sata_ahci" = "0x1"
+			register "sata_port_map" = "0x3"
+
+			# SuperIO range is 0x700-0x73f
+			register "gen2_dec" = "0x003c0701"
+
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on end # USB2 EHCI #2
+			device pci 1b.0 on end # High Definition Audio
+			device pci 1c.0 on end # PCIe Port #1 (WLAN)
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 on end # PCIe Port #3 (Debug)
+			device pci 1c.3 on end # PCIe Port #4 (LAN)
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 off end # PCIe Port #6
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on # LPC bridge
+				chip superio/ite/it8772f
+					# Enable GPIO10 as USBPWRON12#
+					# Enable GPIO12 as USBPWRON13#
+					register "gpio_set1" = "0x05"
+					# Enable GPIO22 as SIO_WAEKSCI#
+					register "gpio_set2" = "0x04"
+					# Enable GPIO32 as SIO_EXTSMI#
+					register "gpio_set3" = "0x04"
+					# Enable GPIO45 as LED_POWER#
+					register "gpio_set4" = "0x20"
+					# Enable GPIO51 as USBPWRON8#
+					# Enable GPIO52 as USBPWRON1#
+					register "gpio_set5" = "0x06"
+					# Skip keyboard init
+					register "skip_keyboard" = "1"
+					# Enable PECI on TMPIN3
+					register "peci_tmpin" = "3"
+					# Enable FAN3
+					register "fan3_enable" = "1"
+
+					device pnp 2e.0 off end # FDC
+					device pnp 2e.1 on # Serial Port 1
+						io 0x60 = 0x2f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.4 on # Environment Controller
+						io 0x60 = 0x700
+						io 0x62 = 0x710
+					end
+					device pnp 2e.7 on # GPIO
+						io 0x60 = 0x720
+						io 0x62 = 0x730
+					end
+					device pnp 2e.5 on
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+					end # Keyboard
+					device pnp 2e.6 on
+						irq 0x70 = 12
+					end # Mouse
+					device pnp 2e.a off end # IR
+				end
+			end
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 on end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl
new file mode 100644
index 0000000..135b60f
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/dsdt.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",     // OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include "acpi/mainboard.asl"
+
+	// global NVS and variables
+	#include "../../../southbridge/intel/bd82x6x/acpi/globalnvs.asl"
+
+	// General Purpose Events
+	//#include "acpi/gpe.asl"
+
+	#include "acpi/thermal.asl"
+
+	#include "../../../cpu/intel/model_206ax/acpi/cpu.asl"
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include "../../../northbridge/intel/sandybridge/acpi/sandybridge.asl"
+			#include "../../../southbridge/intel/bd82x6x/acpi/pch.asl"
+		}
+	}
+
+	#include "acpi/chromeos.asl"
+
+	/* Chipset specific sleep states */
+	#include "../../../southbridge/intel/bd82x6x/acpi/sleepstates.asl"
+}
diff --git a/src/mainboard/samsung/stumpy/fadt.c b/src/mainboard/samsung/stumpy/fadt.c
new file mode 100644
index 0000000..8ec566b
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/fadt.c
@@ -0,0 +1,166 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+/* FIXME: This needs to go into a separate .h file
+ * to be included by the ich7 smi handler, ich7 smi init
+ * code and the mainboard fadt.
+ */
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+	acpi_header_t *header = &(fadt->header);
+	u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)),
+								0x40) & 0xfffe;
+
+	memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+	memcpy(header->signature, "FACP", 4);
+	header->length = sizeof(acpi_fadt_t);
+	header->revision = 3;
+	memcpy(header->oem_id, "CORE  ", 6);
+	memcpy(header->oem_table_id, "COREBOOT", 8);
+	memcpy(header->asl_compiler_id, "CORE", 4);
+	header->asl_compiler_revision = 1;
+
+	fadt->firmware_ctrl = (unsigned long) facs;
+	fadt->dsdt = (unsigned long) dsdt;
+	fadt->model = 1;
+	fadt->preferred_pm_profile = PM_DESKTOP;
+
+	fadt->sci_int = 0x9;
+	fadt->smi_cmd = APM_CNT;
+	fadt->acpi_enable = ACPI_ENABLE;
+	fadt->acpi_disable = ACPI_DISABLE;
+	fadt->s4bios_req = 0x0;
+	fadt->pstate_cnt = PST_CONTROL;
+
+	fadt->pm1a_evt_blk = pmbase;
+	fadt->pm1b_evt_blk = 0x0;
+	fadt->pm1a_cnt_blk = pmbase + 0x4;
+	fadt->pm1b_cnt_blk = 0x0;
+	fadt->pm2_cnt_blk = pmbase + 0x50;
+	fadt->pm_tmr_blk = pmbase + 0x8;
+	fadt->gpe0_blk = pmbase + 0x20;
+	fadt->gpe1_blk = 0;
+
+	fadt->pm1_evt_len = 4;
+	fadt->pm1_cnt_len = 2;
+	fadt->pm2_cnt_len = 1;
+	fadt->pm_tmr_len = 4;
+	fadt->gpe0_blk_len = 16;
+	fadt->gpe1_blk_len = 0;
+	fadt->gpe1_base = 0;
+	fadt->cst_cnt = CST_CONTROL;
+	fadt->p_lvl2_lat = 1;
+	fadt->p_lvl3_lat = 87;
+	fadt->flush_size = 1024;
+	fadt->flush_stride = 16;
+	fadt->duty_offset = 1;
+	fadt->duty_width = 0;
+	fadt->day_alrm = 0xd;
+	fadt->mon_alrm = 0x00;
+	fadt->century = 0x00;
+	fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042;
+
+	fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED |
+			ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON |
+			ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE |
+			ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK;
+
+	fadt->reset_reg.space_id = 1;
+	fadt->reset_reg.bit_width = 8;
+	fadt->reset_reg.bit_offset = 0;
+	fadt->reset_reg.resv = 0;
+	fadt->reset_reg.addrl = 0xcf9;
+	fadt->reset_reg.addrh = 0;
+
+	fadt->reset_value = 6;
+	fadt->x_firmware_ctl_l = (unsigned long)facs;
+	fadt->x_firmware_ctl_h = 0;
+	fadt->x_dsdt_l = (unsigned long)dsdt;
+	fadt->x_dsdt_h = 0;
+
+	fadt->x_pm1a_evt_blk.space_id = 1;
+	fadt->x_pm1a_evt_blk.bit_width = 32;
+	fadt->x_pm1a_evt_blk.bit_offset = 0;
+	fadt->x_pm1a_evt_blk.resv = 0;
+	fadt->x_pm1a_evt_blk.addrl = pmbase;
+	fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_evt_blk.space_id = 1;
+	fadt->x_pm1b_evt_blk.bit_width = 0;
+	fadt->x_pm1b_evt_blk.bit_offset = 0;
+	fadt->x_pm1b_evt_blk.resv = 0;
+	fadt->x_pm1b_evt_blk.addrl = 0x0;
+	fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+	fadt->x_pm1a_cnt_blk.space_id = 1;
+	fadt->x_pm1a_cnt_blk.bit_width = 16;
+	fadt->x_pm1a_cnt_blk.bit_offset = 0;
+	fadt->x_pm1a_cnt_blk.resv = 0;
+	fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+	fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm1b_cnt_blk.space_id = 1;
+	fadt->x_pm1b_cnt_blk.bit_width = 0;
+	fadt->x_pm1b_cnt_blk.bit_offset = 0;
+	fadt->x_pm1b_cnt_blk.resv = 0;
+	fadt->x_pm1b_cnt_blk.addrl = 0x0;
+	fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm2_cnt_blk.space_id = 1;
+	fadt->x_pm2_cnt_blk.bit_width = 8;
+	fadt->x_pm2_cnt_blk.bit_offset = 0;
+	fadt->x_pm2_cnt_blk.resv = 0;
+	fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50;
+	fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = 32;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.resv = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	fadt->x_gpe0_blk.space_id = 1;
+	fadt->x_gpe0_blk.bit_width = 64;
+	fadt->x_gpe0_blk.bit_offset = 0;
+	fadt->x_gpe0_blk.resv = 0;
+	fadt->x_gpe0_blk.addrl = pmbase + 0x20;
+	fadt->x_gpe0_blk.addrh = 0x0;
+
+	fadt->x_gpe1_blk.space_id = 1;
+	fadt->x_gpe1_blk.bit_width = 0;
+	fadt->x_gpe1_blk.bit_offset = 0;
+	fadt->x_gpe1_blk.resv = 0;
+	fadt->x_gpe1_blk.addrl = 0x0;
+	fadt->x_gpe1_blk.addrh = 0x0;
+
+	header->checksum =
+	    acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/samsung/stumpy/gpio.h b/src/mainboard/samsung/stumpy/gpio.h
new file mode 100644
index 0000000..c72548e
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/gpio.h
@@ -0,0 +1,310 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef STUMPY_GPIO_H
+#define STUMPY_GPIO_H
+
+#include "southbridge/intel/bd82x6x/gpio.h"
+
+/*
+ * GPIO SET 1 includes GPIO0 to GPIO31
+ */
+
+const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0  = GPIO_MODE_GPIO,	/* CHP3_SERDBG */
+	.gpio1  = GPIO_MODE_GPIO,	/* SIO3_EXTSMI# */
+	.gpio2  = GPIO_MODE_NONE,
+	.gpio3  = GPIO_MODE_NONE,
+	.gpio4  = GPIO_MODE_NONE,
+	.gpio5  = GPIO_MODE_NONE,
+	.gpio6  = GPIO_MODE_NONE,
+	.gpio7  = GPIO_MODE_NONE,
+	.gpio8  = GPIO_MODE_GPIO,	/* CHP3_INTELBT_OFF# */
+	.gpio9  = GPIO_MODE_NATIVE,	/* USB_OC13# */
+	.gpio10 = GPIO_MODE_NATIVE,	/* USB_OC12# */
+	.gpio11 = GPIO_MODE_NONE,
+	.gpio12 = GPIO_MODE_NONE,
+	.gpio13 = GPIO_MODE_GPIO,	/* CHP3_DEBUG13 */
+	.gpio14 = GPIO_MODE_GPIO,	/* SIO3_WAKESCI# */
+	.gpio15 = GPIO_MODE_NONE,
+	.gpio16 = GPIO_MODE_NONE,
+	.gpio17 = GPIO_MODE_GPIO,	/* KBC3_DVP_MODE */
+	.gpio18 = GPIO_MODE_NATIVE,	/* MIN3_CLKREQ1# */
+	.gpio19 = GPIO_MODE_NONE,
+	.gpio20 = GPIO_MODE_NONE,
+	.gpio21 = GPIO_MODE_NONE,
+	.gpio22 = GPIO_MODE_GPIO,	/* CHP3_BIOS_CRISIS# */
+	.gpio23 = GPIO_MODE_NONE,
+	.gpio24 = GPIO_MODE_NONE,
+	.gpio25 = GPIO_MODE_NATIVE,	/* MIN3_CLKREQ3# */
+	.gpio26 = GPIO_MODE_NATIVE,	/* LAN3_CLKREQ# */
+	.gpio27 = GPIO_MODE_NONE,
+	.gpio28 = GPIO_MODE_NONE,
+	.gpio29 = GPIO_MODE_NONE,
+	.gpio30 = GPIO_MODE_NATIVE,	/* CHP3_SUSWARN# */
+	.gpio31 = GPIO_MODE_NATIVE,	/* ACPRESENT (pullup) */
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0  = GPIO_DIR_OUTPUT,
+	.gpio1  = GPIO_DIR_INPUT,
+	.gpio2  = GPIO_DIR_INPUT,
+	.gpio3  = GPIO_DIR_INPUT,
+	.gpio4  = GPIO_DIR_INPUT,
+	.gpio5  = GPIO_DIR_INPUT,
+	.gpio6  = GPIO_DIR_INPUT,
+	.gpio7  = GPIO_DIR_INPUT,
+	.gpio8  = GPIO_DIR_OUTPUT,
+	.gpio9  = GPIO_DIR_INPUT,
+	.gpio10 = GPIO_DIR_INPUT,
+	.gpio11 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio18 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio20 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_OUTPUT,
+	.gpio23 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio25 = GPIO_DIR_INPUT,
+	.gpio26 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_INPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio0  = GPIO_LEVEL_LOW,
+	.gpio1  = GPIO_LEVEL_LOW,
+	.gpio2  = GPIO_LEVEL_LOW,
+	.gpio3  = GPIO_LEVEL_LOW,
+	.gpio4  = GPIO_LEVEL_LOW,
+	.gpio5  = GPIO_LEVEL_LOW,
+	.gpio6  = GPIO_LEVEL_LOW,
+	.gpio7  = GPIO_LEVEL_LOW,
+	.gpio8  = GPIO_LEVEL_HIGH,
+	.gpio9  = GPIO_LEVEL_LOW,
+	.gpio10 = GPIO_LEVEL_LOW,
+	.gpio11 = GPIO_LEVEL_LOW,
+	.gpio12 = GPIO_LEVEL_LOW,
+	.gpio13 = GPIO_LEVEL_LOW,
+	.gpio14 = GPIO_LEVEL_LOW,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio16 = GPIO_LEVEL_LOW,
+	.gpio17 = GPIO_LEVEL_LOW,
+	.gpio18 = GPIO_LEVEL_LOW,
+	.gpio19 = GPIO_LEVEL_LOW,
+	.gpio20 = GPIO_LEVEL_LOW,
+	.gpio21 = GPIO_LEVEL_LOW,
+	.gpio22 = GPIO_LEVEL_HIGH,
+	.gpio23 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio25 = GPIO_LEVEL_LOW,
+	.gpio26 = GPIO_LEVEL_LOW,
+	.gpio27 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_LOW,
+	.gpio30 = GPIO_LEVEL_LOW,
+	.gpio31 = GPIO_LEVEL_LOW,
+};
+
+/*
+ * GPIO SET 2 includes GPIO32 to GPIO63
+ */
+
+const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,	/* PCI3_CLKRUN# */
+	.gpio33 = GPIO_MODE_NONE,
+	.gpio34 = GPIO_MODE_NONE,
+	.gpio35 = GPIO_MODE_GPIO,	/* CHP3_WLAN_OFF# */
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,	/* CHP3_FDI_OVRVLTG */
+	.gpio38 = GPIO_MODE_NONE,
+	.gpio39 = GPIO_MODE_NONE,
+	.gpio40 = GPIO_MODE_NATIVE,	/* USB3_OC1# */
+	.gpio41 = GPIO_MODE_NATIVE,	/* USB3_OC4# */
+	.gpio42 = GPIO_MODE_GPIO,	/* CHP3_REC_MODE# */
+	.gpio43 = GPIO_MODE_NATIVE,	/* USB3_OC8# */
+	.gpio44 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG0_CTL2# */
+	.gpio45 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG0_CTL3# */
+	.gpio46 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG4_CTL2# */
+	.gpio47 = GPIO_MODE_GPIO,	/* CHP3_CHG_ENABLE0 */
+	.gpio48 = GPIO_MODE_GPIO,	/* CHP3_BT_OFF# */
+	.gpio49 = GPIO_MODE_NONE,
+	.gpio50 = GPIO_MODE_NONE,
+	.gpio51 = GPIO_MODE_NONE,
+	.gpio52 = GPIO_MODE_NONE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NONE,
+	.gpio55 = GPIO_MODE_GPIO,	/* STP_A16OVR */
+	.gpio56 = GPIO_MODE_GPIO,	/* CHP3_CHG_ENABLE4 */
+	.gpio57 = GPIO_MODE_GPIO,	/* CHP3_DEBUG10 */
+	.gpio58 = GPIO_MODE_NATIVE,	/* SIO3_THERM_SMCLK# */
+	.gpio59 = GPIO_MODE_NATIVE,	/* USB3_OC0# */
+	.gpio60 = GPIO_MODE_GPIO,	/* CHP3_DRAMRST_GATE */
+	.gpio61 = GPIO_MODE_NONE,
+	.gpio62 = GPIO_MODE_NATIVE,	/* CHP3_SUSCLK */
+	.gpio63 = GPIO_MODE_NATIVE,	/* CHP3_SLPS5# */
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_INPUT,
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_OUTPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio40 = GPIO_DIR_INPUT,
+	.gpio41 = GPIO_DIR_INPUT,
+	.gpio42 = GPIO_DIR_INPUT,
+	.gpio43 = GPIO_DIR_INPUT,
+	.gpio44 = GPIO_DIR_OUTPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio47 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_OUTPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_INPUT,
+	.gpio56 = GPIO_DIR_OUTPUT,
+	.gpio57 = GPIO_DIR_OUTPUT,
+	.gpio58 = GPIO_DIR_INPUT,
+	.gpio59 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+	.gpio61 = GPIO_DIR_INPUT,
+	.gpio62 = GPIO_DIR_INPUT,
+	.gpio63 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_LOW,
+	.gpio33 = GPIO_LEVEL_LOW,
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio35 = GPIO_LEVEL_HIGH,
+	.gpio36 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio38 = GPIO_LEVEL_LOW,
+	.gpio39 = GPIO_LEVEL_LOW,
+	.gpio40 = GPIO_LEVEL_LOW,
+	.gpio41 = GPIO_LEVEL_LOW,
+	.gpio42 = GPIO_LEVEL_LOW,
+	.gpio43 = GPIO_LEVEL_LOW,
+	.gpio44 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio47 = GPIO_LEVEL_HIGH,
+	.gpio48 = GPIO_LEVEL_HIGH,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio50 = GPIO_LEVEL_LOW,
+	.gpio51 = GPIO_LEVEL_LOW,
+	.gpio52 = GPIO_LEVEL_LOW,
+	.gpio53 = GPIO_LEVEL_LOW,
+	.gpio54 = GPIO_LEVEL_LOW,
+	.gpio55 = GPIO_LEVEL_LOW,
+	.gpio56 = GPIO_LEVEL_HIGH,
+	.gpio57 = GPIO_LEVEL_LOW,
+	.gpio58 = GPIO_LEVEL_LOW,
+	.gpio59 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+	.gpio61 = GPIO_LEVEL_LOW,
+	.gpio62 = GPIO_LEVEL_LOW,
+	.gpio63 = GPIO_LEVEL_LOW,
+};
+
+/*
+ * GPIO SET 3 includes GPIO64 to GPIO75
+ */
+
+const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,	/* CLK3_SIO48 */
+	.gpio65 = GPIO_MODE_NONE,
+	.gpio66 = GPIO_MODE_NONE,
+	.gpio67 = GPIO_MODE_NONE,
+	.gpio68 = GPIO_MODE_GPIO,	/* CHP3_SPI_WP */
+	.gpio69 = GPIO_MODE_NONE,
+	.gpio70 = GPIO_MODE_NONE,
+	.gpio71 = GPIO_MODE_NONE,
+	.gpio72 = GPIO_MODE_NATIVE,	/* BATLOW# (pullup) */
+	.gpio73 = GPIO_MODE_GPIO,	/* CHP3_SMRT_CHG4_CTL3# */
+	.gpio74 = GPIO_MODE_NONE,
+	.gpio75 = GPIO_MODE_NATIVE,	/* SIO3_THERM_SMDATA# */
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio64 = GPIO_DIR_INPUT,
+	.gpio65 = GPIO_DIR_INPUT,
+	.gpio66 = GPIO_DIR_INPUT,
+	.gpio67 = GPIO_DIR_INPUT,
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+	.gpio73 = GPIO_DIR_OUTPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+	.gpio75 = GPIO_DIR_INPUT,
+};
+
+const struct pch_gpio_set3 pch_gpio_set3_level = {
+	.gpio64 = GPIO_LEVEL_LOW,
+	.gpio65 = GPIO_LEVEL_LOW,
+	.gpio66 = GPIO_LEVEL_LOW,
+	.gpio67 = GPIO_LEVEL_LOW,
+	.gpio68 = GPIO_LEVEL_LOW,
+	.gpio69 = GPIO_LEVEL_LOW,
+	.gpio70 = GPIO_LEVEL_LOW,
+	.gpio71 = GPIO_LEVEL_LOW,
+	.gpio72 = GPIO_LEVEL_LOW,
+	.gpio73 = GPIO_LEVEL_LOW,
+	.gpio74 = GPIO_LEVEL_LOW,
+	.gpio75 = GPIO_LEVEL_LOW,
+};
+
+const struct pch_gpio_map stumpy_gpio_map = {
+	.set1 = {
+		.mode      = &pch_gpio_set1_mode,
+		.direction = &pch_gpio_set1_direction,
+		.level     = &pch_gpio_set1_level,
+	},
+	.set2 = {
+		.mode      = &pch_gpio_set2_mode,
+		.direction = &pch_gpio_set2_direction,
+		.level     = &pch_gpio_set2_level,
+	},
+	.set3 = {
+		.mode      = &pch_gpio_set3_mode,
+		.direction = &pch_gpio_set3_direction,
+		.level     = &pch_gpio_set3_level,
+	},
+};
+
+#endif
diff --git a/src/mainboard/samsung/stumpy/hda_verb.h b/src/mainboard/samsung/stumpy/hda_verb.h
new file mode 100644
index 0000000..9a4a740
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/hda_verb.h
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+static const u32 mainboard_cim_verb_data[] = {
+	/* coreboot specific header */
+	0x10134210,	// Codec Vendor / Device ID: Cirrus Logic CS4210
+	0x10134210,	// Subsystem ID
+	0x00000007,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10134210 */
+	0x00172010,
+	0x00172142,
+	0x00172213,
+	0x00172310,
+
+	/* Pin Widget Verb Table */
+
+	/* Pin Complex (NID 0x05)     1/8   Gray  HP Out at Ext Front */
+	0x00571cf0,
+	0x00571d20,
+	0x00571e21,
+	0x00571f02,
+
+	/* Pin Complex (NID 0x06)  Analog Unknown  Speaker at Int N/A */
+	0x00671c10,
+	0x00671d00,
+	0x00671e17,
+	0x00671f90,
+
+	/* Pin Complex (NID 0x07)     1/8    Grey  Line In at Ext Front */
+	0x00771cf0,
+	0x00771d20,
+	0x00771ea1,
+	0x00771f02,
+
+	/* Pin Complex (NID 0x08)  Analog Unknown  Mic at Oth Mobile-In */
+	0x00871c37,
+	0x00871d00,
+	0x00871ea7,
+	0x00871f77,
+
+	/* Pin Complex (NID 0x09) Digital Unknown  Mic at Oth Mobile-In */
+	0x00971c3e,
+	0x00971d00,
+	0x00971ea6,
+	0x00971f77,
+
+	/* Pin Complex (NID 0x0a) Optical   Black  SPDIF Out at Ext N/A */
+	0x00a71cf0,
+	0x00a71d10,
+	0x00a71e45,
+	0x00a71f43,
+
+	/* coreboot specific header */
+	0x80862805,	// Codec Vendor / Device ID: Intel CougarPoint HDMI
+	0x80860101,	// Subsystem ID
+	0x00000004,	// Number of jacks
+
+	/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
+	0x00172001,
+	0x00172101,
+	0x00172286,
+	0x00172380,
+
+	/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
+	0x30571c10,
+	0x30571d00,
+	0x30571e56,
+	0x30571f18,
+
+	/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
+	0x30671c20,
+	0x30671d00,
+	0x30671e56,
+	0x30671f18,
+
+	/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
+	0x30771c30,
+	0x30771d00,
+	0x30771e56,
+	0x30771f18
+};
+
diff --git a/src/mainboard/samsung/stumpy/mainboard.c b/src/mainboard/samsung/stumpy/mainboard.c
new file mode 100644
index 0000000..9152a3b
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/mainboard.c
@@ -0,0 +1,250 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <arch/coreboot_tables.h>
+#include "hda_verb.h"
+#include "chip.h"
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void mainboard_suspend_resume(void)
+{
+	/* Call SMM finalize() handlers before resume */
+	outb(0xcb, 0xb2);
+}
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+	return add_northbridge_resources(mem);
+}
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_REALMODE) && CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static int int15_handler(struct eregs *regs)
+{
+	int res=-1;
+
+	printk(BIOS_DEBUG, "%s: INT15 function %04x!\n",
+			__func__, regs->eax & 0xffff);
+
+	switch(regs->eax & 0xffff) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 *  0     = video bios default
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffffff00;
+		regs->ecx |= 0x01;
+		res = 0;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP) *
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP) *
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0000;
+		res = 0;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		regs->eax &= 0xffff0000;
+		regs->eax |= 0x005f;
+		regs->ecx &= 0xffff0000;
+		regs->ecx |= 0x0003;
+		res = 0;
+		break;
+	case 0x5f70:
+		switch ((regs->ecx >> 8) & 0xff) {
+		case 0:
+			/* Get Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 1:
+			/* Set Mux */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		case 2:
+			/* Get SG/Non-SG mode */
+			regs->eax &= 0xffff0000;
+			regs->eax |= 0x005f;
+			regs->ecx &= 0xffff0000;
+			regs->ecx |= 0x0000;
+			res = 0;
+			break;
+		default:
+			/* Interrupt was not handled */
+			printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n",
+				((regs->ecx >> 8) & 0xff));
+			return 0;
+		}
+		break;
+
+        default:
+		printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
+				regs->eax & 0xffff);
+		break;
+	}
+	return res;
+}
+#endif
+
+#if defined(CONFIG_PCI_OPTION_ROM_RUN_YABEL) && CONFIG_PCI_OPTION_ROM_RUN_YABEL
+static int int15_handler(void)
+{
+	printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+			  __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX);
+
+	switch (M.x86.R_AX) {
+	case 0x5f34:
+		/*
+		 * Set Panel Fitting Hook:
+		 *  bit 2 = Graphics Stretching
+		 *  bit 1 = Text Stretching
+		 *  bit 0 = Centering (do not set with bit1 or bit2)
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0001;
+		break;
+	case 0x5f35:
+		/*
+		 * Boot Display Device Hook:
+		 *  bit 0 = CRT
+		 *  bit 1 = TV (eDP) *
+		 *  bit 2 = EFP *
+		 *  bit 3 = LFP
+		 *  bit 4 = CRT2
+		 *  bit 5 = TV2 (eDP) *
+		 *  bit 6 = EFP2 *
+		 *  bit 7 = LFP2
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0x0000;
+		break;
+	case 0x5f51:
+		/*
+		 * Hook to select active LFP configuration:
+		 *  00h = No LVDS, VBIOS does not enable LVDS
+		 *  01h = Int-LVDS, LFP driven by integrated LVDS decoder
+		 *  02h = SVDO-LVDS, LFP driven by SVDO decoder
+		 *  03h = eDP, LFP Driven by Int-DisplayPort encoder
+		 */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 3;
+		break;
+	case 0x5f70:
+		/* Unknown */
+		M.x86.R_AX = 0x005f;
+		M.x86.R_CX = 0;
+		break;
+	default:
+		/* Interrupt was not handled */
+		printk(BIOS_DEBUG, "Unknown INT15 function: 0x%04x\n",
+			M.x86.R_AX);
+		return 0;
+	}
+
+	/* Interrupt handled */
+	return 1;
+}
+#endif
+
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+static void int15_install(void)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL
+	typedef int (* yabel_handleIntFunc)(void);
+	extern yabel_handleIntFunc yabel_intFuncArray[256];
+	yabel_intFuncArray[0x15] = int15_handler;
+#endif
+#ifdef CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+#endif
+
+/* Audio Setup */
+
+extern const u32 * cim_verb_data;
+extern u32 cim_verb_data_size;
+
+static void verb_setup(void)
+{
+	cim_verb_data = mainboard_cim_verb_data;
+	cim_verb_data_size = sizeof(mainboard_cim_verb_data);
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE
+	/* Install custom int15 handler for VGA OPROM */
+	int15_install();
+#endif
+	verb_setup();
+}
+
+struct chip_operations mainboard_ops = {
+	CHIP_NAME("Samsung Stumpy ChromeBox")
+	.enable_dev = mainboard_enable,
+};
+
diff --git a/src/mainboard/samsung/stumpy/mainboard_smi.c b/src/mainboard/samsung/stumpy/mainboard_smi.c
new file mode 100644
index 0000000..2fa6e23
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/mainboard_smi.c
@@ -0,0 +1,117 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <southbridge/intel/bd82x6x/nvs.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/me.h>
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+
+/* Include romstage serial for SIO helper functions */
+#include <superio/ite/it8772f/early_serial.c>
+
+/* The southbridge SMI handler checks whether gnvs has a
+ * valid pointer before calling the trap handler
+ */
+extern global_nvs_t *gnvs;
+
+int mainboard_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x99:
+		printk(BIOS_DEBUG, "Sample\n");
+		gnvs->smif = 0;
+		break;
+	default:
+		return 0;
+	}
+
+	/* On success, the IO Trap Handler returns 0
+	 * On failure, the IO Trap Handler returns a value != 0
+	 *
+	 * For now, we force the return value to 0 and log all traps to
+	 * see what's going on.
+	 */
+	//gnvs->smif = 0;
+	return 1;
+}
+
+/*
+ * Change LED_POWER# (SIO GPIO 45) state based on sleep type.
+ * The IO address is hardcoded as we don't have device path in SMM.
+ */
+#define SIO_GPIO_BASE_SET4	(0x730 + 3)
+#define SIO_GPIO_BLINK_GPIO45	0x25
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	u8 reg8;
+
+	switch (slp_typ) {
+	case SLP_TYP_S3:
+	case SLP_TYP_S4:
+		/* Blink LED */
+		it8772f_enter_conf();
+		it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+		/* Enable blink pin map */
+		it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP,
+				  SIO_GPIO_BLINK_GPIO45);
+		/* Enable 4HZ blink */
+		it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02);
+		/* Set GPIO to alternate function */
+		reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3));
+		reg8 &= ~(1 << 5);
+		it8772f_sio_write(GPIO_REG_ENABLE(3), reg8);
+		it8772f_exit_conf();
+		break;
+
+	case SLP_TYP_S5:
+		/* Turn off LED */
+		reg8 = inb(SIO_GPIO_BASE_SET4);
+		reg8 |= (1 << 5);
+		outb(reg8, SIO_GPIO_BASE_SET4);
+		break;
+	}
+}
+
+#define APMC_FINALIZE 0xcb
+
+static int mainboard_finalized = 0;
+
+void mainboard_smi_apmc(u8 apmc)
+{
+	switch (apmc) {
+	case APMC_FINALIZE:
+		if (mainboard_finalized) {
+			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
+			return;
+		}
+
+		intel_me_finalize_smm();
+		intel_pch_finalize_smm();
+		intel_sandybridge_finalize_smm();
+		intel_model_206ax_finalize_smm();
+
+		mainboard_finalized = 1;
+		break;
+	}
+}
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
new file mode 100644
index 0000000..001dc76
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -0,0 +1,387 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <lib.h>
+#include <timestamp.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <pc80/mc146818rtc.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include "superio/ite/it8772f/it8772f.h"
+#include "superio/ite/it8772f/early_serial.c"
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#include "northbridge/intel/sandybridge/raminit.h"
+#include "southbridge/intel/bd82x6x/pch.h"
+#include "southbridge/intel/bd82x6x/gpio.h"
+#include <arch/cpu.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/msr.h>
+#include "gpio.h"
+#if CONFIG_CONSOLE_SERIAL8250
+#include "superio/smsc/lpc47n207/lpc47n207.h"
+#include "superio/smsc/lpc47n207/early_serial.c"
+#endif
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+
+/* Stumpy USB Reset Disable defined in cmos.layout */
+#if CONFIG_USE_OPTION_TABLE
+#include "option_table.h"
+#define CMOS_USB_RESET_DISABLE  (CMOS_VSTART_stumpy_usb_reset_disable >> 3)
+#else
+#define CMOS_USB_RESET_DISABLE  (400 >> 3)
+#endif
+#define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */
+
+static void pch_enable_lpc(void)
+{
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);
+
+#if CONFIG_CONSOLE_SERIAL8250
+	/* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\
+			   CNF2_LPC_EN | COMA_LPC_EN);
+	try_enabling_LPC47N207_uart();
+#else
+	/* Enable SuperIO + PS/2 Keyboard/Mouse */
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN);
+#endif
+}
+
+static void rcba_config(void)
+{
+	u32 reg32;
+
+	/*
+	 *             GFX    INTA -> PIRQA (MSI)
+	 * D28IP_P1IP  WLAN   INTA -> PIRQB
+	 * D28IP_P4IP  ETH0   INTB -> PIRQC
+	 * D29IP_E1P   EHCI1  INTA -> PIRQD
+	 * D26IP_E2P   EHCI2  INTA -> PIRQE
+	 * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
+	 * D31IP_SMIP  SMBUS  INTB -> PIRQG
+	 * D31IP_TTIP  THRT   INTC -> PIRQH
+	 * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
+	 */
+
+	/* Device interrupt pin register (board specific) */
+	RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
+		(INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
+	RCBA32(D30IP) = (NOINT << D30IP_PIP);
+	RCBA32(D29IP) = (INTA << D29IP_E1P);
+	RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) |
+		(INTB << D28IP_P4IP);
+	RCBA32(D27IP) = (INTA << D27IP_ZIP);
+	RCBA32(D26IP) = (INTA << D26IP_E2P);
+	RCBA32(D25IP) = (NOINT << D25IP_LIP);
+	RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
+
+	/* Device interrupt route registers */
+	DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA);
+	DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
+	DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
+	DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB);
+	DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH);
+	DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
+	DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
+
+	/* Enable IOAPIC (generic) */
+	RCBA8(OIC) = 0x01;
+	/* PCH BWG says to read back the IOAPIC enable register */
+	(void) RCBA8(OIC);
+
+	/* Enable upper 128bytes of CMOS (generic) */
+	RCBA32(RC) = (1 << 2);
+
+	/* Disable unused devices (board specific) */
+	reg32 = RCBA32(FD);
+	reg32 |= PCH_DISABLE_ALWAYS;
+	RCBA32(FD) = reg32;
+}
+
+static void early_pch_init(void)
+{
+	u8 reg8;
+
+	// reset rtc power status
+	reg8 = pci_read_config8(PCH_LPC_DEV, 0xa4);
+	reg8 &= ~(1 << 2);
+	pci_write_config8(PCH_LPC_DEV, 0xa4, reg8);
+}
+
+static void setup_sio_gpios(void)
+{
+	/*
+	 * GPIO10 as USBPWRON12#
+	 * GPIO12 as USBPWRON13#
+	 */
+	it8772f_gpio_setup(1, 0x05, 0x05, 0x00, 0x05, 0x05);
+
+	/*
+	 * GPIO22 as wake SCI#
+	 */
+	it8772f_gpio_setup(2, 0x04, 0x04, 0x00, 0x04, 0x04);
+
+	/*
+	 * GPIO32 as EXTSMI#
+	 */
+	it8772f_gpio_setup(3, 0x04, 0x04, 0x00, 0x04, 0x04);
+
+	/*
+	 * GPIO45 as LED_POWER#
+	 */
+	it8772f_gpio_setup(4, 0x20, 0x20, 0x20, 0x20, 0x20);
+
+	/*
+	 * GPIO51 as USBPWRON8#
+	 * GPIO52 as USBPWRON1#
+	 */
+	it8772f_gpio_setup(5, 0x06, 0x06, 0x00, 0x06, 0x06);
+	it8772f_gpio_setup(6, 0x00, 0x00, 0x00, 0x00, 0x00);
+}
+
+void main(unsigned long bist)
+{
+	int boot_mode = 0;
+	int cbmem_was_initted;
+	u32 pm1_cnt;
+	u16 pm1_sts;
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	tsc_t start_romstage_time;
+	tsc_t before_dram_time;
+	tsc_t after_dram_time;
+	tsc_t base_time = {
+		.lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc),
+		.hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0)
+	};
+#endif
+	struct pei_data pei_data = {
+		mchbar: 0xfed10000,
+		dmibar: 0xfed18000,
+		epbar: 0xfed19000,
+		pciexbar: 0xf0000000,
+		smbusbar: 0x400,
+		wdbbar: 0x4000000,
+		wdbsize: 0x1000,
+		hpet_address: 0xfed00000,
+		rcba: 0xfed1c000,
+		pmbase: 0x500,
+		gpiobase: 0x480,
+		thermalbase: 0xfed08000,
+		system_type: 0, // 0 Mobile, 1 Desktop/Server
+		tseg_size: CONFIG_SMM_TSEG_SIZE,
+		spd_addresses: { 0x50, 0x00,0x52,0x00 },
+		ts_addresses: { 0x00, 0x00, 0x00, 0x00 },
+		ec_present: 0,
+		// 0 = leave channel enabled
+		// 1 = disable dimm 0 on channel
+		// 2 = disable dimm 1 on channel
+		// 3 = disable dimm 0+1 on channel
+		dimm_channel0_disabled: 2,
+		dimm_channel1_disabled: 2,
+		usb_port_config: {
+			{ 1, 0, 0x0080 }, /* P0: Front port  (OC0) */
+			{ 1, 1, 0x0040 }, /* P1: Back port   (OC1) */
+			{ 1, 0, 0x0040 }, /* P2: MINIPCIE1   (no OC) */
+			{ 1, 0, 0x0040 }, /* P3: MMC         (no OC) */
+			{ 1, 2, 0x0080 }, /* P4: Front port  (OC2) */
+			{ 0, 0, 0x0000 }, /* P5: Empty */
+			{ 0, 0, 0x0000 }, /* P6: Empty */
+			{ 0, 0, 0x0000 }, /* P7: Empty */
+			{ 1, 4, 0x0040 }, /* P8: Back port   (OC4) */
+			{ 1, 4, 0x0040 }, /* P9: MINIPCIE3   (no OC) */
+			{ 1, 4, 0x0040 }, /* P10: BLUETOOTH  (no OC) */
+			{ 0, 4, 0x0000 }, /* P11: Empty */
+			{ 1, 6, 0x0040 }, /* P12: Back port  (OC6) */
+			{ 1, 5, 0x0040 }, /* P13: Back port  (OC5) */
+		},
+	};
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	start_romstage_time = rdtsc();
+#endif
+
+	if (bist == 0)
+		enable_lapic();
+
+	pch_enable_lpc();
+
+	/* Enable GPIOs */
+	pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1);
+	pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+	setup_pch_gpios(&stumpy_gpio_map);
+	setup_sio_gpios();
+
+	/* Early SuperIO setup */
+	it8772f_kill_watchdog();
+	it8772f_ac_resume_southbridge();
+	it8772f_enable_serial(PNP_DEV(IT8772F_BASE, IT8772F_SP1),
+			      CONFIG_TTYS0_BASE);
+	console_init();
+
+#if CONFIG_CHROMEOS
+	save_chromeos_gpios();
+#endif
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	if (MCHBAR16(SSKPD) == 0xCAFE) {
+		printk(BIOS_DEBUG, "soft reset detected\n");
+		boot_mode = 1;
+
+		/* System is not happy after keyboard reset... */
+		printk(BIOS_DEBUG, "Issuing CF9 warm reset\n");
+		outb(0x6, 0xcf9);
+		hlt();
+	}
+
+	/* Perform some early chipset initialization required
+	 * before RAM initialization can work
+	 */
+	sandybridge_early_initialization(SANDYBRIDGE_MOBILE);
+	printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n");
+
+	/* Check PM1_STS[15] to see if we are waking from Sx */
+	pm1_sts = inw(DEFAULT_PMBASE + PM1_STS);
+
+	/* Read PM1_CNT[12:10] to determine which Sx state */
+	pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
+
+	if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
+#if CONFIG_HAVE_ACPI_RESUME
+		printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+		boot_mode = 2;
+		/* Clear SLP_TYPE. This will break stage2 but
+		 * we care for that when we get there.
+		 */
+		outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
+#else
+		printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+#endif
+	}
+
+	post_code(0x38);
+	/* Enable SPD ROMs and DDR-III DRAM */
+	enable_smbus();
+
+	/* Prepare USB controller early in S3 resume */
+	if (boot_mode == 2) {
+		/*
+		 * For Stumpy the back USB ports are reset on resume
+		 * so default to resetting the controller to make the
+		 * kernel happy.  There is a CMOS flag to disable the
+		 * controller reset in case the kernel can tolerate
+		 * the device power loss better in the future.
+		 */
+		u8 magic = cmos_read(CMOS_USB_RESET_DISABLE);
+
+		if (magic == USB_RESET_DISABLE_MAGIC) {
+			printk(BIOS_DEBUG, "USB Controller Reset Disabled\n");
+			enable_usb_bar();
+		} else {
+			printk(BIOS_DEBUG, "USB Controller Reset Enabled\n");
+		}
+	} else {
+		/* Ensure USB reset on resume is enabled at boot */
+		cmos_write(0, CMOS_USB_RESET_DISABLE);
+	}
+
+	post_code(0x39);
+	pei_data.boot_mode = boot_mode;
+#if CONFIG_COLLECT_TIMESTAMPS
+	before_dram_time = rdtsc();
+#endif
+	sdram_initialize(&pei_data);
+
+#if CONFIG_COLLECT_TIMESTAMPS
+	after_dram_time = rdtsc();
+#endif
+	post_code(0x3a);
+	/* Perform some initialization that must run before stage2 */
+	early_pch_init();
+	post_code(0x3b);
+
+	rcba_config();
+	post_code(0x3c);
+
+	/* Initialize the internal PCIe links before we go into stage2 */
+	sandybridge_late_initialization();
+
+	post_code(0x3e);
+	quick_ram_check();
+
+	MCHBAR16(SSKPD) = 0xCAFE;
+#if CONFIG_EARLY_CBMEM_INIT
+	cbmem_was_initted = !cbmem_initialize();
+#else
+	cbmem_was_initted = cbmem_reinit((uint64_t) (get_top_of_ram()
+						     - HIGH_MEMORY_SIZE));
+#endif
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* If there is no high memory area, we didn't boot before, so
+	 * this is not a resume. In that case we just create the cbmem toc.
+	 */
+
+	*(u32 *)CBMEM_BOOT_MODE = 0;
+	*(u32 *)CBMEM_RESUME_BACKUP = 0;
+
+	if ((boot_mode == 2) && cbmem_was_initted) {
+		void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);
+		if (resume_backup_memory) {
+			*(u32 *)CBMEM_BOOT_MODE = boot_mode;
+			*(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory;
+		}
+		/* Magic for S3 resume */
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d);
+	} else if (boot_mode == 2) {
+		/* Failed S3 resume, reset to come up cleanly */
+		outb(0x6, 0xcf9);
+		hlt();
+	} else {
+		pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe);
+	}
+#endif
+	post_code(0x3f);
+#if CONFIG_CHROMEOS
+	init_chromeos(boot_mode);
+#endif
+#if CONFIG_COLLECT_TIMESTAMPS
+	timestamp_init(base_time);
+	timestamp_add(TS_START_ROMSTAGE, start_romstage_time );
+	timestamp_add(TS_BEFORE_INITRAM, before_dram_time );
+	timestamp_add(TS_AFTER_INITRAM, after_dram_time );
+	timestamp_add_now(TS_END_ROMSTAGE);
+#endif
+#if CONFIG_CONSOLE_CBMEM
+	/* Keep this the last thing this function does. */
+	cbmemc_reinit();
+#endif
+}
diff --git a/src/mainboard/samsung/stumpy/thermal.h b/src/mainboard/samsung/stumpy/thermal.h
new file mode 100644
index 0000000..835e93f
--- /dev/null
+++ b/src/mainboard/samsung/stumpy/thermal.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef STUMPY_THERMAL_H
+#define STUMPY_THERMAL_H
+
+/* Fan is OFF */
+#define FAN4_THRESHOLD_OFF	0
+#define FAN4_THRESHOLD_ON	0
+#define FAN4_PWM		0x00
+
+/* Fan is at LOW speed */
+#define FAN3_THRESHOLD_OFF	48
+#define FAN3_THRESHOLD_ON	55
+#define FAN3_PWM		0x40
+
+/* Fan is at MEDIUM speed */
+#define FAN2_THRESHOLD_OFF	52
+#define FAN2_THRESHOLD_ON	64
+#define FAN2_PWM		0x80
+
+/* Fan is at HIGH speed */
+#define FAN1_THRESHOLD_OFF	60
+#define FAN1_THRESHOLD_ON	68
+#define FAN1_PWM		0xb0
+
+/* Fan is at FULL speed */
+#define FAN0_THRESHOLD_OFF	66
+#define FAN0_THRESHOLD_ON	78
+#define FAN0_PWM		0xff
+
+/* Temperature which OS will shutdown at */
+#define CRITICAL_TEMPERATURE	100
+
+/* Temperature which OS will throttle CPU */
+#define PASSIVE_TEMPERATURE	90
+
+/* Tj_max value for calculating PECI CPU temperature */
+#define MAX_TEMPERATURE		100
+
+#endif
diff --git a/src/mainboard/via/epia-m700/acpi_tables.c b/src/mainboard/via/epia-m700/acpi_tables.c
index 16c0b46..283d6e4 100644
--- a/src/mainboard/via/epia-m700/acpi_tables.c
+++ b/src/mainboard/via/epia-m700/acpi_tables.c
@@ -30,6 +30,7 @@
 
 #include <console/console.h>
 #include <string.h>
+#include <stdlib.h>
 #include <arch/acpi.h>
 #include <device/device.h>
 #include <device/pci_ids.h>
@@ -114,9 +115,6 @@
 	return current;
 }
 
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
diff --git a/src/mainboard/via/epia-n/acpi_tables.c b/src/mainboard/via/epia-n/acpi_tables.c
index 589e14c..b5f59f4 100644
--- a/src/mainboard/via/epia-n/acpi_tables.c
+++ b/src/mainboard/via/epia-n/acpi_tables.c
@@ -29,6 +29,7 @@
 
 #include <console/console.h>
 #include <string.h>
+#include <stdlib.h>
 #include <arch/acpi.h>
 #include <arch/ioapic.h>
 #include <device/device.h>
@@ -118,10 +119,6 @@
 	return current;
 }
 
-#define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1)
-#define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
-#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
-
 unsigned long write_acpi_tables(unsigned long start)
 {
 	unsigned long current;
diff --git a/src/mainboard/via/vt8454c/acpi_tables.c b/src/mainboard/via/vt8454c/acpi_tables.c
index 434bf87..03bacc3 100644
--- a/src/mainboard/via/vt8454c/acpi_tables.c
+++ b/src/mainboard/via/vt8454c/acpi_tables.c
@@ -26,7 +26,6 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include "dmi.h"
 
 extern const unsigned char AmlCode[];
 
@@ -194,10 +193,6 @@
 
 	acpi_create_fadt(fadt, facs, dsdt);
 	acpi_add_table(rsdp, fadt);
-
-	printk(BIOS_DEBUG, "ACPI:     * DMI (Linux workaround)\n");
-	memcpy((void *)0xfff80, dmi_table, DMI_TABLE_SIZE);
-
 	printk(BIOS_INFO, "ACPI: done.\n");
 	return current;
 }
diff --git a/src/mainboard/via/vt8454c/dmi.h b/src/mainboard/via/vt8454c/dmi.h
deleted file mode 100644
index 96b5873..0000000
--- a/src/mainboard/via/vt8454c/dmi.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#define DMI_TABLE_SIZE 0x55
-
-static u8 dmi_table[DMI_TABLE_SIZE] = {
-	0x5f, 0x53, 0x4d, 0x5f, 0x29, 0x1f, 0x02, 0x03, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-	0x5f, 0x44, 0x4d, 0x49, 0x5f, 0x61, 0x35, 0x00, 0xa0, 0xff, 0x0f, 0x00, 0x01, 0x00, 0x23, 0x00,
-	0x00, 0x14, 0x00, 0x00, 0x01, 0x02, 0x00, 0xe0, 0x03, 0x07, 0x90, 0xde, 0xcb, 0x7f, 0x00, 0x00,
-	0x00, 0x00, 0x37, 0x01, 0x63, 0x6f, 0x72, 0x65, 0x73, 0x79, 0x73, 0x74, 0x65, 0x6d, 0x73, 0x20,
-	0x47, 0x6d, 0x62, 0x48, 0x00, 0x32, 0x2e, 0x30, 0x00, 0x30, 0x33, 0x2f, 0x31, 0x33, 0x2f, 0x32,
-	0x30, 0x30, 0x38, 0x00, 0x00
-};
diff --git a/src/northbridge/intel/Kconfig b/src/northbridge/intel/Kconfig
index 409eb5e..8ec1ab7 100644
--- a/src/northbridge/intel/Kconfig
+++ b/src/northbridge/intel/Kconfig
@@ -9,3 +9,4 @@
 source src/northbridge/intel/i855/Kconfig
 source src/northbridge/intel/i945/Kconfig
 source src/northbridge/intel/sch/Kconfig
+source src/northbridge/intel/sandybridge/Kconfig
diff --git a/src/northbridge/intel/Makefile.inc b/src/northbridge/intel/Makefile.inc
index 266f6f8..33271f9 100644
--- a/src/northbridge/intel/Makefile.inc
+++ b/src/northbridge/intel/Makefile.inc
@@ -10,3 +10,4 @@
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GC) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_I945GM) += i945
 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += sandybridge
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c
index 925d108..8c0ae76 100644
--- a/src/northbridge/intel/i945/northbridge.c
+++ b/src/northbridge/intel/i945/northbridge.c
@@ -29,6 +29,7 @@
 #include <bitops.h>
 #include <cpu/cpu.h>
 #include <boot/tables.h>
+#include <arch/acpi.h>
 #include "chip.h"
 #include "i945.h"
 
@@ -252,8 +253,6 @@
 }
 
 #if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
-
 static void northbridge_init(struct device *dev)
 {
 	switch (pci_read_config32(dev, SKPAD)) {
diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h
index 4f77e8e..c7bead3 100644
--- a/src/northbridge/intel/i945/raminit.h
+++ b/src/northbridge/intel/i945/raminit.h
@@ -71,7 +71,6 @@
 void sdram_initialize(int boot_path, const u8 *sdram_addresses);
 unsigned long get_top_of_ram(void);
 int fixup_i945_errata(void);
-void udelay(u32 us);
 
 #if CONFIG_DEBUG_RAM_SETUP
 void sdram_dump_mchbar_registers(void);
diff --git a/src/northbridge/intel/ivybridge/Kconfig b/src/northbridge/intel/ivybridge/Kconfig
new file mode 100644
index 0000000..d50574e
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/Kconfig
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_SANDYBRIDGE
+	bool
+	# make sure our mrc.bin is cached.
+	select CACHE_MRC_BIN
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE
+
+config VGA_BIOS_ID
+	string
+	default "8086,0106"
+
+endif
diff --git a/src/northbridge/intel/ivybridge/Makefile.inc b/src/northbridge/intel/ivybridge/Makefile.inc
new file mode 100644
index 0000000..3fb9407
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/Makefile.inc
@@ -0,0 +1,37 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+driver-y += gma.c
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+romstage-y += udelay.c
+romstage-y += raminit.c
+romstage-y += early_init.c
+romstage-y += ../../../arch/x86/lib/walkcbfs.S
+
+# We don't ship that, but booting without it is bound to fail
+cbfs-files-y += mrc.bin
+mrc.bin-file := 3rdparty/intel/sandybridge/mrc.bin
+mrc.bin-type := 0xab
+# Normal version:
+# mrc.bin-position := 0xffff0000
+# Debugging version:
+mrc.bin-position := 0xfffe0000
diff --git a/src/northbridge/intel/ivybridge/acpi.c b/src/northbridge/intel/ivybridge/acpi.c
new file mode 100644
index 0000000..7a1d302
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/acpi.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "sandybridge.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	u32 pciexbar = 0;
+	u32 pciexbar_reg;
+	int max_buses;
+
+	dev = dev_find_device(0x8086, 0x0104, 0);
+	if (!dev)
+		return current;
+
+	pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
+
+	// MMCFG not supported or not enabled.
+	if (!(pciexbar_reg & (1 << 0)))
+		return current;
+
+	switch ((pciexbar_reg >> 1) & 3) {
+	case 0: // 256MB
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		max_buses = 256;
+		break;
+	case 1: // 128M
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		max_buses = 128;
+		break;
+	case 2: // 64M
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		max_buses = 64;
+		break;
+	default: // RSVD
+		return current;
+	}
+
+	if (!pciexbar)
+		return current;
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+			pciexbar, 0x0, 0x0, max_buses - 1);
+
+	return current;
+}
+
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/northbridge/intel/ivybridge/chip.h
similarity index 75%
copy from src/cpu/x86/mmx_disable.inc
copy to src/northbridge/intel/ivybridge/chip.h
index 1a4e70f..6e4e7cb 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/northbridge/intel/ivybridge/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+struct northbridge_intel_sandybridge_config {
+	/* Non-zero value will enable LVDS backlight */
+	u32 lvds_blc_freq;
+};
 
+extern struct chip_operations northbridge_intel_sandybridge_ops;
diff --git a/src/northbridge/intel/ivybridge/gma.c b/src/northbridge/intel/ivybridge/gma.c
new file mode 100644
index 0000000..6ed858f
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/gma.c
@@ -0,0 +1,313 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include "chip.h"
+#include "sandybridge.h"
+
+/* some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselfes
+ */
+
+u32 map_oprom_vendev(u32 vendev)
+{
+	u32 new_vendev=vendev;
+
+	switch (vendev) {
+	case 0x01028086:		/* GT1 Desktop */
+	case 0x010a8086:		/* GT1 Server */
+	case 0x01128086:		/* GT2 Desktop */
+	case 0x01168086:		/* GT2 Mobile */
+	case 0x01228086:		/* GT2 Desktop >=1.3GHz */
+	case 0x01268086:		/* GT2 Mobile >=1.3GHz */
+		new_vendev=0x01068086;	/* GT1 Mobile */
+		break;
+	}
+
+	return new_vendev;
+}
+
+static struct resource *gtt_res = NULL;
+
+static inline u32 gtt_read(u32 reg)
+{
+	return read32(gtt_res->base + reg);
+}
+
+static inline void gtt_write(u32 reg, u32 data)
+{
+	write32(gtt_res->base + reg, data);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(u32 reg, u32 mask, u32 value)
+{
+	unsigned try = GTT_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = gtt_read(reg);
+		if ((data & mask) == value)
+			return 1;
+		udelay(10);
+	}
+
+	printk(BIOS_ERR, "GT init timeout\n");
+	return 0;
+}
+
+static void gma_pm_init_pre_vbios(struct device *dev)
+{
+	u32 reg32;
+
+	printk(BIOS_DEBUG, "GT Power Management Init\n");
+
+	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!gtt_res || !gtt_res->base)
+		return;
+
+	/* 1: Enable force wake */
+	gtt_write(0xa18c, 0x00000001);
+	if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
+		return;
+
+	/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+	reg32 = gtt_read(0x42004);
+	reg32 |= (1 << 14) | (1 << 15);
+	gtt_write(0x42004, reg32);
+
+	/* 2: Get GT SKU from GTT+0x911c[13] */
+	reg32 = gtt_read(0x911c);
+	if (reg32 & (1 << 13)) {
+		printk(BIOS_DEBUG, "GT1 Power Meter Weights\n");
+		gtt_write(0xa200, 0xcc000000);
+		gtt_write(0xa204, 0x07000040);
+		gtt_write(0xa208, 0x0000fe00);
+		gtt_write(0xa20c, 0x00000000);
+		gtt_write(0xa210, 0x17000000);
+		gtt_write(0xa214, 0x00000021);
+		gtt_write(0xa218, 0x0817fe19);
+		gtt_write(0xa21c, 0x00000000);
+		gtt_write(0xa220, 0x00000000);
+		gtt_write(0xa224, 0xcc000000);
+		gtt_write(0xa228, 0x07000040);
+		gtt_write(0xa22c, 0x0000fe00);
+		gtt_write(0xa230, 0x00000000);
+		gtt_write(0xa234, 0x17000000);
+		gtt_write(0xa238, 0x00000021);
+		gtt_write(0xa23c, 0x0817fe19);
+		gtt_write(0xa240, 0x00000000);
+		gtt_write(0xa244, 0x00000000);
+		gtt_write(0xa248, 0x8000421e);
+	} else {
+		printk(BIOS_DEBUG, "GT2 Power Meter Weights\n");
+		gtt_write(0xa200, 0x330000a6);
+		gtt_write(0xa204, 0x402d0031);
+		gtt_write(0xa208, 0x00165f83);
+		gtt_write(0xa20c, 0xf1000000);
+		gtt_write(0xa210, 0x00000000);
+		gtt_write(0xa214, 0x00160016);
+		gtt_write(0xa218, 0x002a002b);
+		gtt_write(0xa21c, 0x00000000);
+		gtt_write(0xa220, 0x00000000);
+		gtt_write(0xa224, 0x330000a6);
+		gtt_write(0xa228, 0x402d0031);
+		gtt_write(0xa22c, 0x00165f83);
+		gtt_write(0xa230, 0xf1000000);
+		gtt_write(0xa234, 0x00000000);
+		gtt_write(0xa238, 0x00160016);
+		gtt_write(0xa23c, 0x002a002b);
+		gtt_write(0xa240, 0x00000000);
+		gtt_write(0xa244, 0x00000000);
+		gtt_write(0xa248, 0x8000421e);
+	}
+
+	/* 3: Gear ratio map */
+	gtt_write(0xa004, 0x00000010);
+
+	/* 4: GFXPAUSE */
+	gtt_write(0xa000, 0x00070020);
+
+	/* 5: Dynamic EU trip control */
+	gtt_write(0xa080, 0x00000004);
+
+	/* 6: ECO bits (bit 20=1 for step D1+) */
+	gtt_write(0xa180, 0x84100000);
+
+	/* 6a: SnB step D2+ */
+	reg32 = gtt_read(0x9400);
+	reg32 |= (1 << 7);
+	gtt_write(0x9400, reg32);
+
+	reg32 = gtt_read(0x941c);
+	reg32 |= (1 << 1);
+	gtt_write(0x941c, reg32);
+	if (!gtt_poll(0x941c, (1 << 1), (0 << 1)))
+		return;
+
+	/* 6b: Clocking reset controls */
+	gtt_write(0x9424, 0x00000000);
+
+	/* 7 */
+	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
+		return;
+	gtt_write(0x138128, 0x00000029); /* Mailbox Data */
+	gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
+	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
+		return;
+	gtt_write(0x138124, 0x8000000a); /* Mailbox Cmd to clear RC6 count */
+	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
+		return;
+
+	/* 8 */
+	gtt_write(0xa090, 0x00000000); /* RC Control */
+	gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+	gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+	gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+	gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+	gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+	/* 9 */
+	gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */
+	gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */
+	gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */
+
+	/* 10 */
+	gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+	gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */
+	gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */
+	gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */
+	gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+	/* 11 */
+	gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */
+	gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */
+	gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */
+	gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */
+	gtt_write(0xa068, 0x000186a0); /* RP Up EI */
+	gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
+	gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+	/* 11a: Enable Render Standby (RC6) */
+	gtt_write(0xa090, 0x88040000); /* HW RC Control */
+
+	/* 12: Normal Frequency Request */
+	/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+	reg32 = MCHBAR32(0x5998);
+	reg32 >>= 16;
+	reg32 &= 0xef;
+	reg32 <<= 25;
+	gtt_write(0xa008, reg32);
+
+	/* 13: RP Control */
+	gtt_write(0xa024, 0x00000592);
+
+	/* 14: Enable PM Interrupts */
+	gtt_write(0x4402c, 0x03000076);
+
+	/* Clear 0x6c024 [8:6] */
+	reg32 = gtt_read(0x6c024);
+	reg32 &= ~0x000001c0;
+	gtt_write(0x6c024, reg32);
+}
+
+static void gma_pm_init_post_vbios(struct device *dev)
+{
+	struct northbridge_intel_sandybridge_config *config = dev->chip_info;
+
+	printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
+
+	/* 15: Deassert Force Wake */
+	gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
+	if (!gtt_poll(0x130090, (1 << 0), (0 << 0)))
+		return;
+
+	/* 16: SW RC Control */
+	gtt_write(0xa094, 0x00060000);
+
+	if (config->lvds_blc_freq) {
+		/* Enable backlight */
+		gtt_write(0xc8250, 0x80000000);
+		gtt_write(0xc8254, config->lvds_blc_freq);
+	}
+}
+
+static void gma_func0_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* IGD needs to be Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Init graphics power management */
+	gma_pm_init_pre_vbios(dev);
+
+	/* PCI Init, will run VBIOS */
+	pci_dev_init(dev);
+
+	/* Post VBIOS init */
+	gma_pm_init_post_vbios(dev);
+}
+
+static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations gma_pci_ops = {
+	.set_subsystem    = gma_set_subsystem,
+};
+
+static struct device_operations gma_func0_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= gma_func0_init,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= &gma_pci_ops,
+};
+
+static const struct pci_driver gma_func0_driver_1 __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0106,
+};
+
+static const struct pci_driver gma_func0_driver_2 __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0116,
+};
+
diff --git a/src/northbridge/intel/ivybridge/ivybridge.h b/src/northbridge/intel/ivybridge/ivybridge.h
new file mode 100644
index 0000000..adb6d19
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/ivybridge.h
@@ -0,0 +1,190 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
+#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1
+
+/* SandyBridge stepping values for SRID */
+#define SNB_STEP_B2	3
+#define SNB_STEP_C0	4
+#define SNB_STEP_D0	7 /* Also J0 */
+#define SNB_STEP_D1	8
+#define SNB_STEP_D2	9 /* Also J1/Q0 */
+
+/* Northbridge BARs */
+#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */
+#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
+#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
+#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+
+#include "../../../southbridge/intel/bd82x6x/pch.h"
+
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define X60BAR		0x60
+
+#define GGC		0x50			/* GMCH Graphics Control */
+
+#define DEVEN		0x54			/* Device Enable */
+#define  DEVEN_PEG60	(1 << 13)
+#define  DEVEN_IGD	(1 << 4)
+#define  DEVEN_PEG10	(1 << 3)
+#define  DEVEN_PEG11	(1 << 2)
+#define  DEVEN_PEG12	(1 << 1)
+#define  DEVEN_HOST	(1 << 0)
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+#define LAC		0x87	/* Legacy Access Control */
+#define SMRAM		0x88	/* System Management RAM Control */
+#define  D_OPEN		(1 << 6)
+#define  D_CLS		(1 << 5)
+#define  D_LCK		(1 << 4)
+#define  G_SMRAME	(1 << 3)
+#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+#define TOM		0xa0
+#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
+#define TSEG		0xb8	/* TSEG base */
+#define TOLUD		0xbc	/* Top of Low Used Memory */
+
+#define SKPAD		0xdc	/* Scratchpad Data */
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+
+#define BCTRL1		0x3e	/* 16bit */
+
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define MSAC		0x62	/* Multi Size Aperture Control */
+
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+
+#define SSKPD		0x5d14	/* 16bit (scratchpad) */
+#define BIOS_RESET_CPL	0x5da8	/* 8bit */
+
+/*
+ * EPBAR - Egress Port Root Complex Register Block
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+#define EPPVCCAP1	0x004	/* 32bit */
+#define EPPVCCAP2	0x008	/* 32bit */
+
+#define EPVC0RCAP	0x010	/* 32bit */
+#define EPVC0RCTL	0x014	/* 32bit */
+#define EPVC0RSTS	0x01a	/* 16bit */
+
+#define EPVC1RCAP	0x01c	/* 32bit */
+#define EPVC1RCTL	0x020	/* 32bit */
+#define EPVC1RSTS	0x026	/* 16bit */
+
+#define EPVC1MTS	0x028	/* 32bit */
+#define EPVC1IST	0x038	/* 64bit */
+
+#define EPESD		0x044	/* 32bit */
+
+#define EPLE1D		0x050	/* 32bit */
+#define EPLE1A		0x058	/* 64bit */
+#define EPLE2D		0x060	/* 32bit */
+#define EPLE2A		0x068	/* 64bit */
+
+#define PORTARB		0x100	/* 256bit */
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+#define DMIVCECH	0x000	/* 32bit */
+#define DMIPVCCAP1	0x004	/* 32bit */
+#define DMIPVCCAP2	0x008	/* 32bit */
+
+#define DMIPVCCCTL	0x00c	/* 16bit */
+
+#define DMIVC0RCAP	0x010	/* 32bit */
+#define DMIVC0RCTL0	0x014	/* 32bit */
+#define DMIVC0RSTS	0x01a	/* 16bit */
+
+#define DMIVC1RCAP	0x01c	/* 32bit */
+#define DMIVC1RCTL	0x020	/* 32bit */
+#define DMIVC1RSTS	0x026	/* 16bit */
+
+#define DMILE1D		0x050	/* 32bit */
+#define DMILE1A		0x058	/* 64bit */
+#define DMILE2D		0x060	/* 32bit */
+#define DMILE2A		0x068	/* 64bit */
+
+#define DMILCAP		0x084	/* 32bit */
+#define DMILCTL		0x088	/* 16bit */
+#define DMILSTS		0x08a	/* 16bit */
+
+#define DMICTL1		0x0f0	/* 32bit */
+#define DMICTL2		0x0fc	/* 32bit */
+
+#define DMICC		0x208	/* 32bit */
+
+#define DMIDRCCFG	0xeb4	/* 32bit */
+
+static inline void barrier(void) { asm("" ::: "memory"); }
+
+int sandybridge_silicon_revision(void);
+void sandybridge_early_initialization(void);
+void sandybridge_late_initialization(void);
+
+/* provided by mainboard code */
+void setup_pch_gpios(void);
+
+/* debugging functions */
+void print_pci_devices(void);
+void dump_pci_device(unsigned dev);
+void dump_pci_devices(void);
+void dump_spd_registers(void);
+void dump_mem(unsigned start, unsigned end);
+
+#endif
+#endif
diff --git a/src/northbridge/intel/ivybridge/northbridge.c b/src/northbridge/intel/ivybridge/northbridge.c
new file mode 100644
index 0000000..ed33de5
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/northbridge.c
@@ -0,0 +1,408 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include "chip.h"
+#include "sandybridge.h"
+
+static int sandybridge_revision_id = -1;
+
+int sandybridge_silicon_revision(void)
+{
+	if (sandybridge_revision_id < 0)
+		sandybridge_revision_id = pci_read_config8(
+			dev_find_slot(0, PCI_DEVFN(0, 0)),
+			PCI_REVISION_ID);
+	return sandybridge_revision_id;
+}
+
+/* Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 384;
+
+int add_northbridge_resources(struct lb_memory *mem)
+{
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
+		legacy_hole_base_k * 1024, legacy_hole_size_k * 1024);
+
+#if CONFIG_CHROMEOS_RAMOOPS
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
+		CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+		CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE);
+#endif
+
+	return 0;
+}
+
+static int get_pcie_bar(u32 *base, u32 *len)
+{
+	device_t dev;
+	u32 pciexbar_reg;
+
+	*base = 0;
+	*len = 0;
+
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (!dev)
+		return 0;
+
+	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+	if (!(pciexbar_reg & (1 << 0)))
+		return 0;
+
+	switch ((pciexbar_reg >> 1) & 3) {
+	case 0: // 256MB
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		*len = 256 * 1024 * 1024;
+		return 1;
+	case 1: // 128M
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		*len = 128 * 1024 * 1024;
+		return 1;
+	case 2: // 64M
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		*len = 64 * 1024 * 1024;
+		return 1;
+	}
+
+	return 0;
+}
+
+/* IDG memory */
+uint64_t uma_memory_base=0, uma_memory_size=0;
+
+static void add_fixed_resources(struct device *dev, int index)
+{
+	struct resource *resource;
+	u32 pcie_config_base, pcie_config_size;
+
+	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
+	       "size=0x%llx\n", uma_memory_base, uma_memory_size);
+	resource = new_resource(dev, index);
+	resource->base = (resource_t) uma_memory_base;
+	resource->size = (resource_t) uma_memory_size;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
+		       "size=0x%x\n", pcie_config_base, pcie_config_size);
+		resource = new_resource(dev, index+1);
+		resource->base = (resource_t) pcie_config_base;
+		resource->size = (resource_t) pcie_config_size;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+}
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	uint64_t tom, me_base;
+	uint32_t tseg_base, uma_size;
+	uint16_t ggc;
+	unsigned long long tomk;
+
+	/* Top of Memory - does not account for any UMA */
+	tom = pci_read_config32(dev, 0xa4);
+	tom <<= 32;
+	tom |= pci_read_config32(dev, 0xa0);
+	tomk = tom >> 10;
+
+	/* ME UMA is right below TOM, read MEBASE */
+	me_base = pci_read_config32(dev, 0x74);
+	me_base <<= 32;
+	me_base |= pci_read_config32(dev, 0x70);
+	uma_size = (tom - me_base) >> 10;
+	tomk -= uma_size;
+	uma_memory_base = tomk * 1024ULL;
+	uma_memory_size = uma_size * 1024ULL;
+	printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n",
+	       me_base, uma_size >> 10);
+
+	/* Graphics memory comes next */
+	ggc = pci_read_config16(dev, GGC);
+	if (!(ggc & 2)) {
+		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
+
+		/* Graphics memory */
+		uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
+		printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10);
+		tomk -= uma_size;
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size += uma_size * 1024ULL;
+
+		/* GTT Graphics Stolen Memory Size (GGMS) */
+		uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
+		tomk -= uma_size;
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size += uma_size * 1024ULL;
+		printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10);
+	}
+
+	/* Calcualte TSEG size from its base which must be below GTT */
+	tseg_base = pci_read_config32(dev, 0xb8);
+	uma_size = (uma_memory_base - tseg_base) >> 10;
+	tomk -= uma_size;
+	uma_memory_base = tomk * 1024ULL;
+	uma_memory_size += uma_size * 1024ULL;
+	printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n",
+	       tseg_base, uma_size >> 10);
+
+	/* The following needs to be 2 lines, otherwise the second
+	 * number is always 0
+	 */
+	printk(BIOS_INFO, "Available memory: %dK", (uint32_t)tomk);
+	printk(BIOS_INFO, " (%dM)\n", (uint32_t)(tomk >> 10));
+
+	/* Report the memory regions */
+	ram_resource(dev, 3, 0, legacy_hole_base_k);
+	ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
+			(tomk - (legacy_hole_base_k + legacy_hole_size_k)));
+
+	/* This code does not cope with the 1GB memory hole for PCI devices: */
+	if (tomk > 4 * 1024 * 1024) {
+		ram_resource(dev, 5, 4096 * 1024, tomk - 4 * 1024 * 1024);
+	}
+
+	add_fixed_resources(dev, 6);
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+#endif
+}
+
+	/* TODO We could determine how many PCIe busses we need in
+	 * the bar. For now that number is hardcoded to a max of 64.
+	 * See e7525/northbridge.c for an example.
+	 */
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void mc_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	pci_dev_read_resources(dev);
+
+	/* So, this is one of the big mysteries in the coreboot resource
+	 * allocator. This resource should make sure that the address space
+	 * of the PCIe memory mapped config space bar. But it does not.
+	 */
+
+	/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
+	resource = new_resource(dev, 0xcf);
+	resource->base = DEFAULT_PCIEXBAR;
+	resource->size = 64 * 1024 * 1024;	/* 64MB hard coded PCIe config space */
+	resource->flags =
+	    IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+	    IORESOURCE_ASSIGNED;
+	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+		     (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
+}
+
+static void mc_set_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Report the PCIe BAR */
+	resource = find_resource(dev, 0xcf);
+	if (resource) {
+		report_resource_stored(dev, resource, "<mmconfig>");
+	}
+
+	/* And call the normal set_resources */
+	pci_dev_set_resources(dev);
+}
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static void northbridge_dmi_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Clear error status bits */
+	DMIBAR32(0x1c4) = 0xffffffff;
+	DMIBAR32(0x1d0) = 0xffffffff;
+
+	/* Steps prior to DMI ASPM */
+	reg32 = DMIBAR32(0x250);
+	reg32 &= ~((1 << 22)|(1 << 20));
+	reg32 |= (1 << 21);
+	DMIBAR32(0x250) = reg32;
+
+	reg32 = DMIBAR32(0x238);
+	reg32 |= (1 << 29);
+	DMIBAR32(0x238) = reg32;
+
+	if (sandybridge_silicon_revision() >= SNB_STEP_D0) {
+		reg32 = DMIBAR32(0x1f8);
+		reg32 |= (1 << 16);
+		DMIBAR32(0x1f8) = reg32;
+	} else if (sandybridge_silicon_revision() >= SNB_STEP_D1) {
+		reg32 = DMIBAR32(0x1f8);
+		reg32 &= ~(1 << 26);
+		reg32 |= (1 << 16);
+		DMIBAR32(0x1f8) = reg32;
+
+		reg32 = DMIBAR32(0x1fc);
+		reg32 |= (1 << 12) | (1 << 23);
+		DMIBAR32(0x1fc) = reg32;
+	}
+
+	/* Enable ASPM on SNB link, should happen before PCH link */
+	reg32 = DMIBAR32(0xd04);
+	reg32 |= (1 << 4);
+	DMIBAR32(0xd04) = reg32;
+
+	reg32 = DMIBAR32(0x88);
+	reg32 |= (1 << 1) | (1 << 0);
+	DMIBAR32(0x88) = reg32;
+}
+
+static void northbridge_init(struct device *dev)
+{
+	u8 bios_reset_cpl;
+
+	northbridge_dmi_init(dev);
+
+	/*
+	 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
+	 * that BIOS has initialized memory and power management
+	 */
+	bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
+	bios_reset_cpl |= 1;
+	MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
+
+	/* Set here before graphics PM init */
+	MCHBAR32(0x5500) = 0x00100001;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	switch (pci_read_config32(dev, SKPAD)) {
+	case 0xcafebabe:
+		printk(BIOS_DEBUG, "Normal boot.\n");
+		acpi_slp_type=0;
+		break;
+	case 0xcafed00d:
+		printk(BIOS_DEBUG, "S3 Resume.\n");
+		acpi_slp_type=3;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
+		acpi_slp_type=0;
+		break;
+	}
+#endif
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = mc_read_resources,
+	.set_resources    = mc_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = northbridge_init,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x0104,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_sandybridge_ops = {
+	CHIP_NAME("Intel i7 (Sandybridge) integrated Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/ivybridge/pcie_config.c b/src/northbridge/intel/ivybridge/pcie_config.c
new file mode 100644
index 0000000..96e4bcf
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/pcie_config.c
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "sandybridge.h"
+
+static inline __attribute__ ((always_inline))
+u8 pcie_read_config8(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read8(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u16 pcie_read_config16(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read16(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u32 pcie_read_config32(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read32(addr);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config8(device_t dev, unsigned int where, u8 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write8(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config16(device_t dev, unsigned int where, u16 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write16(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config32(device_t dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write32(addr, value);
+}
diff --git a/src/northbridge/intel/ivybridge/raminit.c b/src/northbridge/intel/ivybridge/raminit.c
new file mode 100644
index 0000000..dee17e8
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/raminit.c
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cbmem.h>
+#include <arch/cbfs.h>
+#include <cbfs.h>
+#include <pc80/mc146818rtc.h>
+#include "raminit.h"
+#include "pei_data.h"
+#include "sandybridge.h"
+
+/* Management Engine is in the southbridge */
+#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+#include "southbridge/intel/bd82x6x/me.h"
+#endif
+
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <fdt/libfdt.h>
+
+/*
+ * MRC scrambler seed offsets should be reserved in
+ * mainboard cmos.layout and not covered by checksum.
+ */
+#if CONFIG_USE_OPTION_TABLE
+#include "option_table.h"
+#define CMOS_OFFSET_MRC_SEED     (CMOS_VSTART_mrc_scrambler_seed >> 3)
+#define CMOS_OFFSET_MRC_SEED_S3  (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
+#else
+#define CMOS_OFFSET_MRC_SEED     112
+#define CMOS_OFFSET_MRC_SEED_S3  116
+#endif
+
+struct mrc_data_container {
+	u32	mrc_data_size;	// Actual total size of this structure
+	u8	mrc_data[0];	// Variable size, platform/run time dependent.
+};
+
+static void save_mrc_data(struct pei_data *pei_data)
+{
+#if CONFIG_EARLY_CBMEM_INIT
+	struct mrc_data_container *mrcdata;
+
+	/* Save the MRC S3 restore data to cbmem */
+	cbmem_initialize();
+	mrcdata = cbmem_add
+		(CBMEM_ID_MRCDATA,
+		 pei_data->mrc_output_len + sizeof(struct mrc_data_container));
+
+	printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
+	       pei_data->mrc_output, mrcdata, pei_data->mrc_output_len);
+
+	mrcdata->mrc_data_size = pei_data->mrc_output_len +
+		sizeof(struct mrc_data_container);
+	memcpy(mrcdata->mrc_data, pei_data->mrc_output,
+	       pei_data->mrc_output_len);
+#endif
+
+	/* Save the MRC seed values to CMOS */
+	cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
+	printk(BIOS_DEBUG, "Save scrambler seed    0x%08x to CMOS 0x%02x\n",
+	       pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
+
+	cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
+	printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
+	       pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
+}
+
+#if CONFIG_CHROMEOS
+static void prepare_mrc_cache(struct pei_data *pei_data)
+{
+	const struct fdt_header *fdt_header;
+	const struct fdt_property *fdtp;
+	int offset, len;
+	const char *compatible = "chromeos,flashmap";
+	const char *subnode = "rw-mrc-cache";
+	const char *property = "reg";
+	u32 *data, *mrc_cache;
+	u64 flashrom_base = 0;
+
+	// preset just in case there is an error
+	pei_data->mrc_input = NULL;
+	pei_data->mrc_input_len = 0;
+
+	fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT);
+
+	if (!fdt_header) {
+		printk(BIOS_ERR, "%s: no FDT found!\n", __func__);
+		return;
+	}
+
+	offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible);
+	if (offset < 0) {
+		printk(BIOS_ERR, "%s: no %s  node found!\n",
+		       __func__, compatible);
+		return;
+	}
+
+	if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) {
+		printk(BIOS_ERR, "%s: no base address in node name!\n",
+		       __func__);
+		return;
+	}
+
+	offset = fdt_subnode_offset(fdt_header, offset, subnode);
+	if (offset < 0) {
+		printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode);
+		return;
+	}
+
+	fdtp = fdt_get_property(fdt_header, offset, property, &len);
+	if (!fdtp || (len != 8)) {
+		printk(BIOS_ERR, "%s: property %s at %p, len %d!\n",
+		       __func__, property, fdtp, len);
+		return;
+	}
+
+	data = (u32 *)fdtp->data;
+
+	// Calculate actual address of the MRC cache in memory
+	mrc_cache = (u32 *)
+		((unsigned long)flashrom_base + fdt32_to_cpu(data[0]));
+
+	// First 4 byte word of the MRC cache space is its size.
+	if (mrc_cache[0] > data[1]) {
+		printk(BIOS_ERR, "%s: MRC cache not initialized?\n",  __func__);
+		return;
+	}
+
+	pei_data->mrc_input = (u8 *)(mrc_cache + 1);
+	pei_data->mrc_input_len = mrc_cache[0];
+
+	printk(BIOS_DEBUG, "%s: at %p, size %x\n",
+	       __func__, pei_data->mrc_input, pei_data->mrc_input_len);
+
+	/* Read scrambler seeds from CMOS */
+	pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED);
+	printk(BIOS_DEBUG, "Read scrambler seed    0x%08x from CMOS 0x%02x\n",
+	       pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
+
+	pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3);
+	printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
+	       pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
+}
+#endif
+
+/**
+ * Find PEI executable in coreboot filesystem and execute it.
+ *
+ * @param pei_data: configuration data for UEFI PEI reference code
+ */
+void sdram_initialize(struct pei_data *pei_data)
+{
+	struct sys_info sysinfo;
+	const char *target = "mrc.bin";
+	unsigned long entry;
+
+#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+	/* Wait for ME to be ready */
+	intel_early_me_init();
+	intel_early_me_uma_size();
+#endif
+
+	printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
+
+	memset(&sysinfo, 0, sizeof(sysinfo));
+
+	sysinfo.boot_path = pei_data->boot_mode;
+
+#if CONFIG_CHROMEOS
+	/*
+	 * Do not pass MRC data in for recovery mode boot,
+	 * Always pass it in for S3 resume.
+	 */
+	if (!recovery_mode_enabled() || pei_data->boot_mode == 2)
+		prepare_mrc_cache(pei_data);
+#endif
+
+	//findstage seems to be faster but requires an ELF at compile time.
+	//entry = findstage((char *)target);
+	entry = (unsigned long)cbfs_find_file(target, 0xab);
+
+	if (entry) {
+		//call(entry, pei_data);
+		asm volatile ("call *%%ecx\n\t" : : "c" (entry), "a" (pei_data));
+	} else {
+		die("UEFI PEI System Agent not found.\n");
+	}
+
+	/* For reference print the System Agent version
+	 * after executing the UEFI PEI stage.
+	 */
+	u32 version = MCHBAR32(0x5034);
+	printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
+		version >> 24 , (version >> 16) & 0xff,
+		(version >> 8) & 0xff, version & 0xff);
+
+#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+	/* Tell the ME that DRAM init is done and perform
+	 * the requested action, which may be a reset.
+	 */
+	intel_early_me_dram_init_done(ME_DRAM_STATUS_SUCCESS);
+#endif
+
+	/* S3 resume: don't save scrambler seed or MRC data */
+	if (pei_data->boot_mode != 2)
+		save_mrc_data(pei_data);
+}
+
+struct cbmem_entry *get_cbmem_toc(void)
+{
+	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
+}
+
+unsigned long get_top_of_ram(void)
+{
+	/* Base of TSEG is top of usable DRAM */
+	u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+	return (unsigned long) tom;
+}
diff --git a/src/cpu/x86/mmx_disable.inc b/src/northbridge/intel/ivybridge/raminit.h
similarity index 64%
copy from src/cpu/x86/mmx_disable.inc
copy to src/northbridge/intel/ivybridge/raminit.h
index 1a4e70f..124f694 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/northbridge/intel/ivybridge/raminit.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2010 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,20 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef RAMINIT_H
+#define RAMINIT_H
 
+#include "pei_data.h"
+
+struct sys_info {
+	u8 boot_path;
+#define BOOT_PATH_NORMAL	0
+#define BOOT_PATH_RESET		1
+#define BOOT_PATH_RESUME	2
+} __attribute__ ((packed));
+
+void sdram_initialize(struct pei_data *pei_data);
+unsigned long get_top_of_ram(void);
+int fixup_sandybridge_errata(void);
+
+#endif				/* RAMINIT_H */
diff --git a/src/northbridge/intel/ivybridge/udelay.c b/src/northbridge/intel/ivybridge/udelay.c
new file mode 100644
index 0000000..c606661
--- /dev/null
+++ b/src/northbridge/intel/ivybridge/udelay.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 100, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xce);
+	divisor = (msr.lo >> 8) & 0xff;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi > tsc1.hi)
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo > tsc1.lo)));
+
+}
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
new file mode 100644
index 0000000..d50574e
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -0,0 +1,31 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config NORTHBRIDGE_INTEL_SANDYBRIDGE
+	bool
+	# make sure our mrc.bin is cached.
+	select CACHE_MRC_BIN
+
+if NORTHBRIDGE_INTEL_SANDYBRIDGE
+
+config VGA_BIOS_ID
+	string
+	default "8086,0106"
+
+endif
diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc
new file mode 100644
index 0000000..aa7d6d4
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/Makefile.inc
@@ -0,0 +1,39 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2010 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+driver-y += northbridge.c
+driver-y += gma.c
+
+ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c
+
+romstage-y += udelay.c
+romstage-y += raminit.c
+romstage-y += early_init.c
+romstage-y += ../../../arch/x86/lib/walkcbfs.S
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
+
+# We don't ship that, but booting without it is bound to fail
+cbfs-files-y += mrc.bin
+mrc.bin-file := 3rdparty/intel/sandybridge/mrc.bin
+mrc.bin-type := 0xab
+# Normal version:
+# mrc.bin-position := 0xffff0000
+# Debugging version:
+mrc.bin-position := 0xfffe0000
diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
new file mode 100644
index 0000000..7a1d302
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "sandybridge.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	u32 pciexbar = 0;
+	u32 pciexbar_reg;
+	int max_buses;
+
+	dev = dev_find_device(0x8086, 0x0104, 0);
+	if (!dev)
+		return current;
+
+	pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
+
+	// MMCFG not supported or not enabled.
+	if (!(pciexbar_reg & (1 << 0)))
+		return current;
+
+	switch ((pciexbar_reg >> 1) & 3) {
+	case 0: // 256MB
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		max_buses = 256;
+		break;
+	case 1: // 128M
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		max_buses = 128;
+		break;
+	case 2: // 64M
+		pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		max_buses = 64;
+		break;
+	default: // RSVD
+		return current;
+	}
+
+	if (!pciexbar)
+		return current;
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+			pciexbar, 0x0, 0x0, max_buses - 1);
+
+	return current;
+}
+
+
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
new file mode 100644
index 0000000..e5e0e77
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include "../../../northbridge/intel/sandybridge/acpi/sandybridge_hostbridge.asl"
+#include "../../../northbridge/intel/sandybridge/sandybridge.h"
+
+/* PCI Device Resource Consumption */
+Device (PDRC)
+{
+	Name (_HID, EISAID("PNP0C02"))
+	Name (_UID, 1)
+
+	Name (PDRS, ResourceTemplate() {
+		Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+		Memory32Fixed(ReadWrite, DEFAULT_MCHBAR,   0x00004000)
+		Memory32Fixed(ReadWrite, DEFAULT_DMIBAR,   0x00001000)
+		Memory32Fixed(ReadWrite, DEFAULT_EPBAR,    0x00001000)
+		Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000)
+		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
+
+#if CONFIG_CHROMEOS_RAMOOPS
+		Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+					 CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE)
+#endif
+
+		/* Required for SandyBridge sighting 3715511 */
+		Memory32Fixed(ReadWrite, 0x20000000, 0x00200000)
+		Memory32Fixed(ReadWrite, 0x40000000, 0x00200000)
+	})
+
+	// Current Resource Settings
+	Method (_CRS, 0, Serialized)
+	{
+		Return(PDRS)
+	}
+}
+
+// Integrated graphics 0:2.0
+#include "../../../northbridge/intel/sandybridge/acpi/sandybridge_igd.asl"
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge_hostbridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge_hostbridge.asl
new file mode 100644
index 0000000..592c4c6
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge_hostbridge.asl
@@ -0,0 +1,250 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+Name(_HID,EISAID("PNP0A08"))	// PCIe
+Name(_CID,EISAID("PNP0A03"))	// PCI
+
+Name(_ADR, 0)
+Name(_BBN, 0)
+
+Device (MCHC)
+{
+	Name(_ADR, 0x00000000)	// 0:0.0
+
+	OperationRegion(MCHP, PCI_Config, 0x00, 0x100)
+	Field (MCHP, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x40),	// EPBAR
+		EPEN,	 1,	// Enable
+		,	11,	//
+		EPBR,	24,	// EPBAR
+
+		Offset (0x48),	// MCHBAR
+		MHEN,	 1,	// Enable
+		,	13,	//
+		MHBR,	22,	// MCHBAR
+
+		Offset (0x60),	// PCIe BAR
+		PXEN,	 1,	// Enable
+		PXSZ,	 2,	// BAR size
+		,	23,	//
+		PXBR,	10,	// PCIe BAR
+
+		Offset (0x68),	// DMIBAR
+		DMEN,	 1,	// Enable
+		,	11,	//
+		DMBR,	24,	// DMIBAR
+
+		Offset (0x70),	// ME Base Address
+		MEBA,	 64,
+
+		// ...
+
+		Offset (0x80),	// PAM0
+		,	 4,
+		PM0H,	 2,
+		,	 2,
+		Offset (0x81),	// PAM1
+		PM1L,	 2,
+		,	 2,
+		PM1H,	 2,
+		,	 2,
+		Offset (0x82),	// PAM2
+		PM2L,	 2,
+		,	 2,
+		PM2H,	 2,
+		,	 2,
+		Offset (0x83),	// PAM3
+		PM3L,	 2,
+		,	 2,
+		PM3H,	 2,
+		,	 2,
+		Offset (0x84),	// PAM4
+		PM4L,	 2,
+		,	 2,
+		PM4H,	 2,
+		,	 2,
+		Offset (0x85),	// PAM5
+		PM5L,	 2,
+		,	 2,
+		PM5H,	 2,
+		,	 2,
+		Offset (0x86),	// PAM6
+		PM6L,	 2,
+		,	 2,
+		PM6H,	 2,
+		,	 2,
+
+		Offset (0xa0),	// Top of Used Memory
+		TOM,	 64,
+
+		Offset (0xbc),	// Top of Low Used Memory
+		TLUD,	 32,
+	}
+
+}
+
+
+// Current Resource Settings
+
+Method (_CRS, 0, Serialized)
+{
+	Name (MCRS, ResourceTemplate()
+	{
+		// Bus Numbers
+		WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+				0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00)
+
+		// IO Region 0
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00)
+
+		// PCI Config Space
+		Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008)
+
+		// IO Region 1
+		DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+				0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01)
+
+		// VGA memory (0xa0000-0xbffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000a0000, 0x000bffff, 0x00000000,
+				0x00020000,,, ASEG)
+
+		// OPROM reserved (0xc0000-0xc3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c0000, 0x000c3fff, 0x00000000,
+				0x00004000,,, OPR0)
+
+		// OPROM reserved (0xc4000-0xc7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c4000, 0x000c7fff, 0x00000000,
+				0x00004000,,, OPR1)
+
+		// OPROM reserved (0xc8000-0xcbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000c8000, 0x000cbfff, 0x00000000,
+				0x00004000,,, OPR2)
+
+		// OPROM reserved (0xcc000-0xcffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000cc000, 0x000cffff, 0x00000000,
+				0x00004000,,, OPR3)
+
+		// OPROM reserved (0xd0000-0xd3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d0000, 0x000d3fff, 0x00000000,
+				0x00004000,,, OPR4)
+
+		// OPROM reserved (0xd4000-0xd7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d4000, 0x000d7fff, 0x00000000,
+				0x00004000,,, OPR5)
+
+		// OPROM reserved (0xd8000-0xdbfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000d8000, 0x000dbfff, 0x00000000,
+				0x00004000,,, OPR6)
+
+		// OPROM reserved (0xdc000-0xdffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
+				0x00004000,,, OPR7)
+
+		// BIOS Extension (0xe0000-0xe3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000,,, ESG0)
+
+		// BIOS Extension (0xe4000-0xe7fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000,,, ESG1)
+
+		// BIOS Extension (0xe8000-0xebfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000,,, ESG2)
+
+		// BIOS Extension (0xec000-0xeffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000,,, ESG3)
+
+		// System BIOS (0xf0000-0xfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000f0000, 0x000fffff, 0x00000000,
+				0x00010000,,, FSEG)
+
+		// PCI Memory Region (Top of memory-0xfebfffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
+				0xfec00000,,, PM01)
+
+		// TPM Area (0xfed40000-0xfed44fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+				0x00005000,,, TPMR)
+	})
+
+	// Find PCI resource area in MCRS
+	CreateDwordField(MCRS, PM01._MIN, PMIN)
+	CreateDwordField(MCRS, PM01._MAX, PMAX)
+	CreateDwordField(MCRS, PM01._LEN, PLEN)
+
+	// Fix up PCI memory region
+	// Start with Top of Lower Usable DRAM
+	Store (^MCHC.TLUD, Local0)
+	Store (^MCHC.MEBA, Local1)
+
+	// Check if ME base is equal
+	If (LEqual (Local0, Local1)) {
+		// Use Top Of Memory instead
+		Store (^MCHC.TOM, Local0)
+	}
+
+	Store (Local0, PMIN)
+	Add(Subtract(PMAX, PMIN), 1, PLEN)
+
+	Return (MCRS)
+}
+
+/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
+#include "acpi/sandybridge_pci_irqs.asl"
+
+
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge_igd.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge_igd.asl
new file mode 100644
index 0000000..a6804ad
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge_igd.asl
@@ -0,0 +1,324 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+
+	/* Display Output Switching */
+	Method (_DOS, 1)
+	{
+		/* Windows 2000 and Windows XP call _DOS to enable/disable
+		 * Display Output Switching during init and while a switch
+		 * is already active
+		 */
+		Store (And(Arg0, 7), DSEN)
+	}
+
+	/* We try to support as many i945 systems as possible,
+	 * so keep the number of DIDs flexible.
+	 */
+	Method (_DOD, 0)
+	{
+		If (LEqual(NDID, 1)) {
+			Name(DOD1, Package() {
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD1, 0))
+			Return(DOD1)
+		}
+
+		If (LEqual(NDID, 2)) {
+			Name(DOD2, Package() {
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID2), Index(DOD2, 0))
+			Store (Or(0x00010000, DID2), Index(DOD2, 1))
+			Return(DOD2)
+		}
+
+		If (LEqual(NDID, 3)) {
+			Name(DOD3, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID3), Index(DOD3, 0))
+			Store (Or(0x00010000, DID3), Index(DOD3, 1))
+			Store (Or(0x00010000, DID3), Index(DOD3, 2))
+			Return(DOD3)
+		}
+
+		If (LEqual(NDID, 4)) {
+			Name(DOD4, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID4), Index(DOD4, 0))
+			Store (Or(0x00010000, DID4), Index(DOD4, 1))
+			Store (Or(0x00010000, DID4), Index(DOD4, 2))
+			Store (Or(0x00010000, DID4), Index(DOD4, 3))
+			Return(DOD4)
+		}
+
+		If (LGreater(NDID, 4)) {
+			Name(DOD5, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID5), Index(DOD5, 0))
+			Store (Or(0x00010000, DID5), Index(DOD5, 1))
+			Store (Or(0x00010000, DID5), Index(DOD5, 2))
+			Store (Or(0x00010000, DID5), Index(DOD5, 3))
+			Store (Or(0x00010000, DID5), Index(DOD5, 4))
+			Return(DOD5)
+		}
+
+		/* Some error happened, but we have to return something */
+		Return (Package() {0x00000400})
+	}
+
+	Device(DD01)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID1, 0)) {
+				Return (1)
+			} Else {
+				Return (And(0xffff, DID1))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 1)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 1)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+	Device(DD02)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID2, 0)) {
+				Return (2)
+			} Else {
+				Return (And(0xffff, DID2))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 2)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 2)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD03)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID3, 0)) {
+				Return (3)
+			} Else {
+				Return (And(0xffff, DID3))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 4)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD04)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID4, 0)) {
+				Return (4)
+			} Else {
+				Return (And(0xffff, DID4))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 8)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD05)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID5, 0)) {
+				Return (5)
+			} Else {
+				Return (And(0xffff, DID5))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 16)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+}
+
diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h
new file mode 100644
index 0000000..b891884
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/chip.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/*
+ * Digital Port Hotplug Enable:
+ *  0x04 = Enabled, 2ms short pulse
+ *  0x05 = Enabled, 4.5ms short pulse
+ *  0x06 = Enabled, 6ms short pulse
+ *  0x07 = Enabled, 100ms short pulse
+ */
+struct northbridge_intel_sandybridge_config {
+	u8 gpu_dp_b_hotplug; /* Digital Port B Hotplug Config */
+	u8 gpu_dp_c_hotplug; /* Digital Port C Hotplug Config */
+	u8 gpu_dp_d_hotplug; /* Digital Port D Hotplug Config */
+
+	u8 gpu_panel_port_select; /* 0=LVDS 1=DP_B 2=DP_C 3=DP_D */
+	u8 gpu_panel_power_cycle_delay;          /* T4 time sequence */
+	u16 gpu_panel_power_up_delay;            /* T1+T2 time sequence */
+	u16 gpu_panel_power_down_delay;          /* T3 time sequence */
+	u16 gpu_panel_power_backlight_on_delay;  /* T5 time sequence */
+	u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */
+};
+
+extern struct chip_operations northbridge_intel_sandybridge_ops;
diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c
new file mode 100644
index 0000000..c7ea18c
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/early_init.c
@@ -0,0 +1,164 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2010 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include "sandybridge.h"
+#include "pcie_config.c"
+
+static void sandybridge_setup_bars(void)
+{
+	/* Setting up Southbridge. In the northbridge code. */
+	printk(BIOS_DEBUG, "Setting up static southbridge registers...");
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, DEFAULT_RCBA | 1);
+
+	pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI BAR */
+
+	printk(BIOS_DEBUG, " done.\n");
+
+	printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
+	RCBA32(GCS) = RCBA32(GCS) | (1 << 5);	/* No reset */
+	outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08);	/* halt timer */
+	printk(BIOS_DEBUG, " done.\n");
+
+	printk(BIOS_DEBUG, "Setting up static northbridge registers...");
+	/* Set up all hardcoded northbridge BARs */
+	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR + 4, (0LL+DEFAULT_EPBAR) >> 32);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR + 4, (0LL+DEFAULT_MCHBAR) >> 32);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */
+	pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR + 4, (0LL+DEFAULT_PCIEXBAR) >> 32);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1);
+	pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR + 4, (0LL+DEFAULT_DMIBAR) >> 32);
+
+	/* Set C0000-FFFFF to access RAM on both reads and writes */
+	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM0, 0x30);
+	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM1, 0x33);
+	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM2, 0x33);
+	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM3, 0x33);
+	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM4, 0x33);
+	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33);
+	pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33);
+
+	printk(BIOS_DEBUG, " done.\n");
+}
+
+static void sandybridge_setup_graphics(void)
+{
+	u32 reg32;
+	u16 reg16;
+	u8 reg8;
+
+	reg16 = pci_read_config16(PCI_DEV(0,2,0), PCI_DEVICE_ID);
+	switch (reg16) {
+	case 0x0102: /* GT1 Desktop */
+	case 0x0106: /* GT1 Mobile */
+	case 0x010a: /* GT1 Server */
+	case 0x0112: /* GT2 Desktop */
+	case 0x0116: /* GT2 Mobile */
+	case 0x0122: /* GT2 Desktop >=1.3GHz */
+	case 0x0126: /* GT2 Mobile >=1.3GHz */
+		break;
+	default:
+		printk(BIOS_DEBUG, "Graphics not supported by this CPU/chipset.\n");
+		return;
+	}
+
+	printk(BIOS_DEBUG, "Initializing Graphics...\n");
+
+	/* Setup IGD memory by setting GGC[7:3] = 1 for 32MB */
+	reg16 = pci_read_config16(PCI_DEV(0,0,0), GGC);
+	reg16 &= ~0x00f8;
+	reg16 |= 1 << 3;
+	/* Program GTT memory by setting GGC[9:8] = 2MB */
+	reg16 &= ~0x0300;
+	reg16 |= 2 << 8;
+	/* Enable VGA decode */
+	reg16 &= ~0x0002;
+	pci_write_config16(PCI_DEV(0,0,0), GGC, reg16);
+
+	/* Enable 256MB aperture */
+	reg8 = pci_read_config8(PCI_DEV(0, 2, 0), MSAC);
+	reg8 &= ~0x06;
+	reg8 |= 0x02;
+	pci_write_config8(PCI_DEV(0, 2, 0), MSAC, reg8);
+
+	/* Erratum workarounds */
+	MCHBAR8(0x5f10) = 0x20;
+
+	reg32 = MCHBAR32(0x5f00);
+	reg32 |= (1 << 9)|(1 << 10);
+	MCHBAR32(0x5f00) = reg32;
+
+	/* Enable SA Clock Gating */
+	reg32 = MCHBAR32(0x5f00);
+	MCHBAR32(0x5f00) = reg32 | 1;
+
+	/* GPU RC6 workaround for sighting 366252 */
+	reg32 = MCHBAR32(0x5d14);
+	reg32 |= (1 << 31);
+	MCHBAR32(0x5d14) = reg32;
+
+	/* VLW */
+	reg32 = MCHBAR32(0x6120);
+	reg32 &= ~(1 << 0);
+	MCHBAR32(0x6120) = reg32;
+
+	reg32 = MCHBAR32(0x5418);
+	reg32 |= (1 << 4) | (1 << 5);
+	MCHBAR32(0x5418) = reg32;
+}
+
+void sandybridge_early_initialization(int chipset_type)
+{
+	u32 capid0_a;
+	u8 reg8;
+
+	/* Device ID Override Enable should be done very early */
+	capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4);
+	if (capid0_a & (1 << 10)) {
+		reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf3);
+		reg8 &= ~7; /* Clear 2:0 */
+
+		if (chipset_type == SANDYBRIDGE_MOBILE)
+			reg8 |= 1; /* Set bit 0 */
+
+		pci_write_config8(PCI_DEV(0, 0, 0), 0xf3, reg8);
+	}
+
+	/* Setup all BARs required for early PCIe and raminit */
+	sandybridge_setup_bars();
+
+	/* Device Enable */
+	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, DEVEN_HOST | DEVEN_IGD);
+
+	sandybridge_setup_graphics();
+}
+
+void sandybridge_late_initialization(void)
+{
+}
+
diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c
new file mode 100644
index 0000000..5bd3f1a
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/finalize.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <stdlib.h>
+#include "pcie_config.c"
+#include "sandybridge.h"
+
+#define PCI_DEV_SNB PCI_DEV(0, 0, 0)
+
+void intel_sandybridge_finalize_smm(void)
+{
+	pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0);	/* GGC */
+	pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0);	/* DPR */
+	pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10);	/* ME */
+	pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0);	/* REMAPBASE */
+	pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0);	/* REMAPLIMIT */
+	pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0);	/* TOM */
+	pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0);	/* TOUUD */
+	pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0);	/* BDSM */
+	pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0);	/* BGSM */
+	pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0);	/* TSEGMB */
+	pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0);	/* TOLUD */
+
+	MCHBAR32_OR(0x5500, 1 << 0);	/* PAVP */
+	MCHBAR32_OR(0x5f00, 1 << 31);	/* SA PM */
+	MCHBAR32_OR(0x6020, 1 << 0);	/* UMA GFX */
+	MCHBAR32_OR(0x63fc, 1 << 0);	/* VTDTRK */
+	MCHBAR32_OR(0x6800, 1 << 31);
+	MCHBAR32_OR(0x7000, 1 << 31);
+	MCHBAR32_OR(0x77fc, 1 << 0);
+
+	/* Memory Controller Lockdown */
+	MCHBAR8(0x50fc) = 0x8f;
+
+	/* Read+write the following */
+	MCHBAR32(0x6030) = MCHBAR32(0x6030);
+	MCHBAR32(0x6034) = MCHBAR32(0x6034);
+	MCHBAR32(0x6008) = MCHBAR32(0x6008);
+}
diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
new file mode 100644
index 0000000..c2b03d0
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -0,0 +1,379 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Chromium OS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+
+#include "chip.h"
+#include "sandybridge.h"
+
+/* some vga option roms are used for several chipsets but they only have one
+ * PCI ID in their header. If we encounter such an option rom, we need to do
+ * the mapping ourselfes
+ */
+
+u32 map_oprom_vendev(u32 vendev)
+{
+	u32 new_vendev=vendev;
+
+	switch (vendev) {
+	case 0x01028086:		/* GT1 Desktop */
+	case 0x010a8086:		/* GT1 Server */
+	case 0x01128086:		/* GT2 Desktop */
+	case 0x01168086:		/* GT2 Mobile */
+	case 0x01228086:		/* GT2 Desktop >=1.3GHz */
+	case 0x01268086:		/* GT2 Mobile >=1.3GHz */
+		new_vendev=0x01068086;	/* GT1 Mobile */
+		break;
+	}
+
+	return new_vendev;
+}
+
+static struct resource *gtt_res = NULL;
+
+static inline u32 gtt_read(u32 reg)
+{
+	return read32(gtt_res->base + reg);
+}
+
+static inline void gtt_write(u32 reg, u32 data)
+{
+	write32(gtt_res->base + reg, data);
+}
+
+#define GTT_RETRY 1000
+static int gtt_poll(u32 reg, u32 mask, u32 value)
+{
+	unsigned try = GTT_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = gtt_read(reg);
+		if ((data & mask) == value)
+			return 1;
+		udelay(10);
+	}
+
+	printk(BIOS_ERR, "GT init timeout\n");
+	return 0;
+}
+
+static void gma_pm_init_pre_vbios(struct device *dev)
+{
+	u32 reg32;
+
+	printk(BIOS_DEBUG, "GT Power Management Init\n");
+
+	gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!gtt_res || !gtt_res->base)
+		return;
+
+	/* 1: Enable force wake */
+	gtt_write(0xa18c, 0x00000001);
+	if (!gtt_poll(0x130090, (1 << 0), (1 << 0)))
+		return;
+
+	/* 1d: Set GTT+0x42004 [15:14]=11 (SnB C1+) */
+	reg32 = gtt_read(0x42004);
+	reg32 |= (1 << 14) | (1 << 15);
+	gtt_write(0x42004, reg32);
+
+	/* 2: Get GT SKU from GTT+0x911c[13] */
+	reg32 = gtt_read(0x911c);
+	if (reg32 & (1 << 13)) {
+		printk(BIOS_DEBUG, "GT1 Power Meter Weights\n");
+		gtt_write(0xa200, 0xcc000000);
+		gtt_write(0xa204, 0x07000040);
+		gtt_write(0xa208, 0x0000fe00);
+		gtt_write(0xa20c, 0x00000000);
+		gtt_write(0xa210, 0x17000000);
+		gtt_write(0xa214, 0x00000021);
+		gtt_write(0xa218, 0x0817fe19);
+		gtt_write(0xa21c, 0x00000000);
+		gtt_write(0xa220, 0x00000000);
+		gtt_write(0xa224, 0xcc000000);
+		gtt_write(0xa228, 0x07000040);
+		gtt_write(0xa22c, 0x0000fe00);
+		gtt_write(0xa230, 0x00000000);
+		gtt_write(0xa234, 0x17000000);
+		gtt_write(0xa238, 0x00000021);
+		gtt_write(0xa23c, 0x0817fe19);
+		gtt_write(0xa240, 0x00000000);
+		gtt_write(0xa244, 0x00000000);
+		gtt_write(0xa248, 0x8000421e);
+	} else {
+		printk(BIOS_DEBUG, "GT2 Power Meter Weights\n");
+		gtt_write(0xa200, 0x330000a6);
+		gtt_write(0xa204, 0x402d0031);
+		gtt_write(0xa208, 0x00165f83);
+		gtt_write(0xa20c, 0xf1000000);
+		gtt_write(0xa210, 0x00000000);
+		gtt_write(0xa214, 0x00160016);
+		gtt_write(0xa218, 0x002a002b);
+		gtt_write(0xa21c, 0x00000000);
+		gtt_write(0xa220, 0x00000000);
+		gtt_write(0xa224, 0x330000a6);
+		gtt_write(0xa228, 0x402d0031);
+		gtt_write(0xa22c, 0x00165f83);
+		gtt_write(0xa230, 0xf1000000);
+		gtt_write(0xa234, 0x00000000);
+		gtt_write(0xa238, 0x00160016);
+		gtt_write(0xa23c, 0x002a002b);
+		gtt_write(0xa240, 0x00000000);
+		gtt_write(0xa244, 0x00000000);
+		gtt_write(0xa248, 0x8000421e);
+	}
+
+	/* 3: Gear ratio map */
+	gtt_write(0xa004, 0x00000010);
+
+	/* 4: GFXPAUSE */
+	gtt_write(0xa000, 0x00070020);
+
+	/* 5: Dynamic EU trip control */
+	gtt_write(0xa080, 0x00000004);
+
+	/* 6: ECO bits */
+	reg32 = gtt_read(0xa180);
+	reg32 |= (1 << 26) | (1 << 31);
+	/* (bit 20=1 for step D1+) */
+	if (sandybridge_silicon_revision() >= SNB_STEP_D1)
+		reg32 |= (1 << 20);
+	gtt_write(0xa180, reg32);
+
+	/* 6a: for SnB step D2+ only */
+	if (sandybridge_silicon_revision() >= SNB_STEP_D2) {
+		reg32 = gtt_read(0x9400);
+		reg32 |= (1 << 7);
+		gtt_write(0x9400, reg32);
+
+		reg32 = gtt_read(0x941c);
+		reg32 &= 0xf;
+		reg32 |= (1 << 1);
+		gtt_write(0x941c, reg32);
+		if (!gtt_poll(0x941c, (1 << 1), (0 << 1)))
+			return;
+	}
+
+	/* 6b: Clocking reset controls */
+	gtt_write(0x9424, 0x00000000);
+
+	/* 7 */
+	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
+		return;
+	gtt_write(0x138128, 0x00000029); /* Mailbox Data */
+	gtt_write(0x138124, 0x80000004); /* Mailbox Cmd for RC6 VID */
+	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
+		return;
+	gtt_write(0x138124, 0x8000000a); /* Mailbox Cmd to clear RC6 count */
+	if (!gtt_poll(0x138124, (1 << 31), (0 << 31)))
+		return;
+
+	/* 8 */
+	gtt_write(0xa090, 0x00000000); /* RC Control */
+	gtt_write(0xa098, 0x03e80000); /* RC1e Wake Rate Limit */
+	gtt_write(0xa09c, 0x0028001e); /* RC6/6p Wake Rate Limit */
+	gtt_write(0xa0a0, 0x0000001e); /* RC6pp Wake Rate Limit */
+	gtt_write(0xa0a8, 0x0001e848); /* RC Evaluation Interval */
+	gtt_write(0xa0ac, 0x00000019); /* RC Idle Hysteresis */
+
+	/* 9 */
+	gtt_write(0x2054, 0x0000000a); /* Render Idle Max Count */
+	gtt_write(0x12054,0x0000000a); /* Video Idle Max Count */
+	gtt_write(0x22054,0x0000000a); /* Blitter Idle Max Count */
+
+	/* 10 */
+	gtt_write(0xa0b0, 0x00000000); /* Unblock Ack to Busy */
+	gtt_write(0xa0b4, 0x000003e8); /* RC1e Threshold */
+	gtt_write(0xa0b8, 0x0000c350); /* RC6 Threshold */
+	gtt_write(0xa0bc, 0x000186a0); /* RC6p Threshold */
+	gtt_write(0xa0c0, 0x0000fa00); /* RC6pp Threshold */
+
+	/* 11 */
+	gtt_write(0xa010, 0x000f4240); /* RP Down Timeout */
+	gtt_write(0xa014, 0x12060000); /* RP Interrupt Limits */
+	gtt_write(0xa02c, 0x00015f90); /* RP Up Threshold */
+	gtt_write(0xa030, 0x000186a0); /* RP Down Threshold */
+	gtt_write(0xa068, 0x000186a0); /* RP Up EI */
+	gtt_write(0xa06c, 0x000493e0); /* RP Down EI */
+	gtt_write(0xa070, 0x0000000a); /* RP Idle Hysteresis */
+
+	/* 11a: Enable Render Standby (RC6) */
+	gtt_write(0xa090, 0x88040000); /* HW RC Control */
+
+	/* 12: Normal Frequency Request */
+	/* RPNFREQ_VAL comes from MCHBAR 0x5998 23:16 (8 bits!? use 7) */
+	reg32 = MCHBAR32(0x5998);
+	reg32 >>= 16;
+	reg32 &= 0xef;
+	reg32 <<= 25;
+	gtt_write(0xa008, reg32);
+
+	/* 13: RP Control */
+	gtt_write(0xa024, 0x00000592);
+
+	/* 14: Enable PM Interrupts */
+	gtt_write(0x4402c, 0x03000076);
+
+	/* Clear 0x6c024 [8:6] */
+	reg32 = gtt_read(0x6c024);
+	reg32 &= ~0x000001c0;
+	gtt_write(0x6c024, reg32);
+}
+
+static void gma_pm_init_post_vbios(struct device *dev)
+{
+	struct northbridge_intel_sandybridge_config *conf = dev->chip_info;
+	u32 reg32;
+
+	printk(BIOS_DEBUG, "GT Power Management Init (post VBIOS)\n");
+
+	/* 15: Deassert Force Wake */
+	gtt_write(0xa18c, gtt_read(0xa18c) & ~1);
+	if (!gtt_poll(0x130090, (1 << 0), (0 << 0)))
+		return;
+
+	/* 16: SW RC Control */
+	gtt_write(0xa094, 0x00060000);
+
+	/* Setup Digital Port Hotplug */
+	reg32 = gtt_read(0xc4030);
+	if (!reg32) {
+		reg32 = (conf->gpu_dp_b_hotplug & 0x7) << 2;
+		reg32 |= (conf->gpu_dp_c_hotplug & 0x7) << 10;
+		reg32 |= (conf->gpu_dp_d_hotplug & 0x7) << 18;
+		gtt_write(0xc4030, reg32);
+	}
+
+	/* Setup Panel Power On Delays */
+	reg32 = gtt_read(0xc7208);
+	if (!reg32) {
+		reg32 = (conf->gpu_panel_port_select & 0x3) << 30;
+		reg32 |= (conf->gpu_panel_power_up_delay & 0x1fff) << 16;
+		reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff);
+		gtt_write(0xc7208, reg32);
+	}
+
+	/* Setup Panel Power Off Delays */
+	reg32 = gtt_read(0xc720c);
+	if (!reg32) {
+		reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16;
+		reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff);
+		gtt_write(0xc720c, reg32);
+	}
+
+	/* Setup Panel Power Cycle Delay */
+	if (conf->gpu_panel_power_cycle_delay) {
+		reg32 = gtt_read(0xc7210);
+		reg32 &= ~0xff;
+		reg32 |= conf->gpu_panel_power_cycle_delay & 0xff;
+		gtt_write(0xc7210, reg32);
+	}
+}
+
+static void gma_func0_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* IGD needs to be Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Init graphics power management */
+	gma_pm_init_pre_vbios(dev);
+
+	/* PCI Init, will run VBIOS */
+	pci_dev_init(dev);
+
+	/* Post VBIOS init */
+	gma_pm_init_post_vbios(dev);
+}
+
+static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations gma_pci_ops = {
+	.set_subsystem    = gma_set_subsystem,
+};
+
+static struct device_operations gma_func0_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= gma_func0_init,
+	.scan_bus		= 0,
+	.enable			= 0,
+	.ops_pci		= &gma_pci_ops,
+};
+
+static const struct pci_driver gma_gt1_desktop __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0102,
+};
+
+static const struct pci_driver gma_gt1_mobile __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0106,
+};
+
+static const struct pci_driver gma_gt1_server __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x010a,
+};
+
+static const struct pci_driver gma_gt2_desktop __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0112,
+};
+
+static const struct pci_driver gma_gt2_mobile __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0116,
+};
+
+static const struct pci_driver gma_gt2_desktop_fast __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0122,
+};
+
+static const struct pci_driver gma_gt2_mobile_fast __pci_driver = {
+	.ops	= &gma_func0_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x0126,
+};
diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c
new file mode 100644
index 0000000..b168647
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/northbridge.c
@@ -0,0 +1,482 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <stdint.h>
+#include <delay.h>
+#include <cpu/intel/model_206ax/model_206ax.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/hypertransport.h>
+#include <stdlib.h>
+#include <string.h>
+#include <bitops.h>
+#include <cpu/cpu.h>
+#include <boot/tables.h>
+#include "chip.h"
+#include "sandybridge.h"
+
+static int sandybridge_revision_id = -1;
+
+int sandybridge_silicon_revision(void)
+{
+	if (sandybridge_revision_id < 0)
+		sandybridge_revision_id = pci_read_config8(
+			dev_find_slot(0, PCI_DEVFN(0, 0)),
+			PCI_REVISION_ID);
+	return sandybridge_revision_id;
+}
+
+/* Reserve everything between A segment and 1MB:
+ *
+ * 0xa0000 - 0xbffff: legacy VGA
+ * 0xc0000 - 0xcffff: VGA OPROM (needed by kernel)
+ * 0xe0000 - 0xfffff: SeaBIOS, if used, otherwise DMI
+ */
+static const int legacy_hole_base_k = 0xa0000 / 1024;
+static const int legacy_hole_size_k = 384;
+
+int add_northbridge_resources(struct lb_memory *mem)
+{
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
+		legacy_hole_base_k * 1024, legacy_hole_size_k * 1024);
+
+#if CONFIG_CHROMEOS_RAMOOPS
+	lb_add_memory_range(mem, LB_MEM_RESERVED,
+		CONFIG_CHROMEOS_RAMOOPS_RAM_START,
+		CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE);
+#endif
+
+	/* Required for SandyBridge sighting 3715511 */
+	lb_add_memory_range(mem, LB_MEM_RESERVED, 0x20000000, 0x00200000);
+	lb_add_memory_range(mem, LB_MEM_RESERVED, 0x40000000, 0x00200000);
+
+	return 0;
+}
+
+static int get_pcie_bar(u32 *base, u32 *len)
+{
+	device_t dev;
+	u32 pciexbar_reg;
+
+	*base = 0;
+	*len = 0;
+
+	dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	if (!dev)
+		return 0;
+
+	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
+
+	if (!(pciexbar_reg & (1 << 0)))
+		return 0;
+
+	switch ((pciexbar_reg >> 1) & 3) {
+	case 0: // 256MB
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+		*len = 256 * 1024 * 1024;
+		return 1;
+	case 1: // 128M
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+		*len = 128 * 1024 * 1024;
+		return 1;
+	case 2: // 64M
+		*base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+		*len = 64 * 1024 * 1024;
+		return 1;
+	}
+
+	return 0;
+}
+
+/* IDG memory */
+uint64_t uma_memory_base=0, uma_memory_size=0;
+
+static void add_fixed_resources(struct device *dev, int index)
+{
+	struct resource *resource;
+	u32 pcie_config_base, pcie_config_size;
+
+	printk(BIOS_DEBUG, "Adding UMA memory area base=0x%llx "
+	       "size=0x%llx\n", uma_memory_base, uma_memory_size);
+	resource = new_resource(dev, index);
+	resource->base = (resource_t) uma_memory_base;
+	resource->size = (resource_t) uma_memory_size;
+	resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+	    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* Clear these values here so they don't get used by MTRR code */
+	uma_memory_base = 0;
+	uma_memory_size = 0;
+
+	if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
+		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
+		       "size=0x%x\n", pcie_config_base, pcie_config_size);
+		resource = new_resource(dev, index+1);
+		resource->base = (resource_t) pcie_config_base;
+		resource->size = (resource_t) pcie_config_size;
+		resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+		    IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
+}
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+#include <cbmem.h>
+#endif
+
+static void pci_domain_set_resources(device_t dev)
+{
+	uint64_t tom, me_base, touud;
+	uint32_t tseg_base, uma_size, tolud;
+	uint16_t ggc;
+	unsigned long long tomk;
+
+	/* Total Memory 2GB example:
+	 *
+	 *  00000000  0000MB-1992MB  1992MB  RAM     (writeback)
+	 *  7c800000  1992MB-2000MB     8MB  TSEG    (SMRR)
+	 *  7d000000  2000MB-2002MB     2MB  GFX GTT (uncached)
+	 *  7d200000  2002MB-2034MB    32MB  GFX UMA (uncached)
+	 *  7f200000   2034MB TOLUD
+	 *  7f800000   2040MB MEBASE
+	 *  7f800000  2040MB-2048MB     8MB  ME UMA  (uncached)
+	 *  80000000   2048MB TOM
+	 * 100000000  4096MB-4102MB     6MB  RAM     (writeback)
+	 *
+	 * Total Memory 4GB example:
+	 *
+	 *  00000000  0000MB-2768MB  2768MB  RAM     (writeback)
+	 *  ad000000  2768MB-2776MB     8MB  TSEG    (SMRR)
+	 *  ad800000  2776MB-2778MB     2MB  GFX GTT (uncached)
+	 *  ada00000  2778MB-2810MB    32MB  GFX UMA (uncached)
+	 *  afa00000   2810MB TOLUD
+	 *  ff800000   4088MB MEBASE
+	 *  ff800000  4088MB-4096MB     8MB  ME UMA  (uncached)
+	 * 100000000   4096MB TOM
+	 * 100000000  4096MB-5374MB  1278MB  RAM     (writeback)
+	 * 14fe00000   5368MB TOUUD
+	 */
+
+	/* Top of Upper Usable DRAM, including remap */
+	touud = pci_read_config32(dev, TOUUD+4);
+	touud <<= 32;
+	touud |= pci_read_config32(dev, TOUUD);
+
+	/* Top of Lower Usable DRAM */
+	tolud = pci_read_config32(dev, TOLUD);
+
+	/* Top of Memory - does not account for any UMA */
+	tom = pci_read_config32(dev, 0xa4);
+	tom <<= 32;
+	tom |= pci_read_config32(dev, 0xa0);
+
+	printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n",
+	       touud, tolud, tom);
+
+	/* ME UMA needs excluding if total memory <4GB */
+	me_base = pci_read_config32(dev, 0x74);
+	me_base <<= 32;
+	me_base |= pci_read_config32(dev, 0x70);
+
+	printk(BIOS_DEBUG, "MEBASE 0x%llx\n", me_base);
+
+	tomk = tolud >> 10;
+	if (me_base == tolud) {
+		/* ME is from MEBASE-TOM */
+		uma_size = (tom - me_base) >> 10;
+		/* Increment TOLUD to account for ME as RAM */
+		tolud += uma_size << 10;
+		/* UMA starts at old TOLUD */
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size = uma_size * 1024ULL;
+		printk(BIOS_DEBUG, "ME UMA base 0x%llx size %uM\n",
+		       me_base, uma_size >> 10);
+	}
+
+	/* Graphics memory comes next */
+	ggc = pci_read_config16(dev, GGC);
+	if (!(ggc & 2)) {
+		printk(BIOS_DEBUG, "IGD decoded, subtracting ");
+
+		/* Graphics memory */
+		uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
+		printk(BIOS_DEBUG, "%uM UMA", uma_size >> 10);
+		tomk -= uma_size;
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size += uma_size * 1024ULL;
+
+		/* GTT Graphics Stolen Memory Size (GGMS) */
+		uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
+		tomk -= uma_size;
+		uma_memory_base = tomk * 1024ULL;
+		uma_memory_size += uma_size * 1024ULL;
+		printk(BIOS_DEBUG, " and %uM GTT\n", uma_size >> 10);
+	}
+
+	/* Calculate TSEG size from its base which must be below GTT */
+	tseg_base = pci_read_config32(dev, 0xb8);
+	uma_size = (uma_memory_base - tseg_base) >> 10;
+	tomk -= uma_size;
+	uma_memory_base = tomk * 1024ULL;
+	uma_memory_size += uma_size * 1024ULL;
+	printk(BIOS_DEBUG, "TSEG base 0x%08x size %uM\n",
+	       tseg_base, uma_size >> 10);
+
+	printk(BIOS_INFO, "Available memory below 4GB: %lluM\n", tomk >> 10);
+
+	/* Report the memory regions */
+	ram_resource(dev, 3, 0, legacy_hole_base_k);
+	ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
+	     (tomk - (legacy_hole_base_k + legacy_hole_size_k)));
+
+	/*
+	 * If >= 4GB installed then memory from TOLUD to 4GB
+	 * is remapped above TOM, TOUUD will account for both
+	 */
+	touud >>= 10; /* Convert to KB */
+	if (touud > 4096 * 1024) {
+		ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024));
+		printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
+		       (touud >> 10) - 4096);
+	}
+
+	add_fixed_resources(dev, 6);
+
+	assign_resources(dev->link_list);
+
+#if CONFIG_WRITE_HIGH_TABLES==1
+	/* Leave some space for ACPI, PIRQ and MP tables */
+	high_tables_base = (tomk * 1024) - HIGH_MEMORY_SIZE;
+	high_tables_size = HIGH_MEMORY_SIZE;
+#endif
+}
+
+	/* TODO We could determine how many PCIe busses we need in
+	 * the bar. For now that number is hardcoded to a max of 64.
+	 * See e7525/northbridge.c for an example.
+	 */
+static struct device_operations pci_domain_ops = {
+	.read_resources   = pci_domain_read_resources,
+	.set_resources    = pci_domain_set_resources,
+	.enable_resources = NULL,
+	.init             = NULL,
+	.scan_bus         = pci_domain_scan_bus,
+#if CONFIG_MMCONF_SUPPORT_DEFAULT
+	.ops_pci_bus	  = &pci_ops_mmconf,
+#else
+	.ops_pci_bus	  = &pci_cf8_conf1,
+#endif
+};
+
+static void mc_read_resources(device_t dev)
+{
+	struct resource *resource;
+
+	pci_dev_read_resources(dev);
+
+	/* So, this is one of the big mysteries in the coreboot resource
+	 * allocator. This resource should make sure that the address space
+	 * of the PCIe memory mapped config space bar. But it does not.
+	 */
+
+	/* We use 0xcf as an unused index for our PCIe bar so that we find it again */
+	resource = new_resource(dev, 0xcf);
+	resource->base = DEFAULT_PCIEXBAR;
+	resource->size = 64 * 1024 * 1024;	/* 64MB hard coded PCIe config space */
+	resource->flags =
+	    IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
+	    IORESOURCE_ASSIGNED;
+	printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n",
+		     (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size));
+}
+
+static void mc_set_resources(device_t dev)
+{
+	struct resource *resource;
+
+	/* Report the PCIe BAR */
+	resource = find_resource(dev, 0xcf);
+	if (resource) {
+		report_resource_stored(dev, resource, "<mmconfig>");
+	}
+
+	/* And call the normal set_resources */
+	pci_dev_set_resources(dev);
+}
+
+static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static void northbridge_dmi_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Clear error status bits */
+	DMIBAR32(0x1c4) = 0xffffffff;
+	DMIBAR32(0x1d0) = 0xffffffff;
+
+	/* Steps prior to DMI ASPM */
+	reg32 = DMIBAR32(0x250);
+	reg32 &= ~((1 << 22)|(1 << 20));
+	reg32 |= (1 << 21);
+	DMIBAR32(0x250) = reg32;
+
+	reg32 = DMIBAR32(0x238);
+	reg32 |= (1 << 29);
+	DMIBAR32(0x238) = reg32;
+
+	if (sandybridge_silicon_revision() == SNB_STEP_C0) {
+		/* ASPM Workaround for C0 */
+		reg32 = DMIBAR32(0xbc8);
+		reg32 &= ~0x0007ff80;
+		reg32 |= 0x0003e980;
+		DMIBAR32(0xbc8) = reg32;
+	}
+
+	if (sandybridge_silicon_revision() >= SNB_STEP_D0) {
+		reg32 = DMIBAR32(0x1f8);
+		reg32 |= (1 << 16);
+		DMIBAR32(0x1f8) = reg32;
+	} else if (sandybridge_silicon_revision() >= SNB_STEP_D1) {
+		reg32 = DMIBAR32(0x1f8);
+		reg32 &= ~(1 << 26);
+		reg32 |= (1 << 16);
+		DMIBAR32(0x1f8) = reg32;
+
+		reg32 = DMIBAR32(0x1fc);
+		reg32 |= (1 << 12) | (1 << 23);
+		DMIBAR32(0x1fc) = reg32;
+	}
+
+	/* Enable ASPM on SNB link, should happen before PCH link */
+	reg32 = DMIBAR32(0xd04);
+	reg32 |= (1 << 4);
+	DMIBAR32(0xd04) = reg32;
+
+	reg32 = DMIBAR32(0x88);
+	reg32 |= (1 << 1) | (1 << 0);
+	DMIBAR32(0x88) = reg32;
+}
+
+static void northbridge_init(struct device *dev)
+{
+	u8 bios_reset_cpl;
+
+	northbridge_dmi_init(dev);
+
+	/*
+	 * Set bit 0 of BIOS_RESET_CPL to indicate to the CPU
+	 * that BIOS has initialized memory and power management
+	 */
+	bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL);
+	bios_reset_cpl |= 1;
+	MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl;
+	printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n");
+
+	/* Configure turbo power limits 1ms after reset complete bit */
+	mdelay(1);
+	set_power_limits(28);
+
+	/* Set here before graphics PM init */
+	MCHBAR32(0x5500) = 0x00100001;
+}
+
+static void northbridge_enable(device_t dev)
+{
+#if CONFIG_HAVE_ACPI_RESUME
+	switch (pci_read_config32(dev, SKPAD)) {
+	case 0xcafebabe:
+		printk(BIOS_DEBUG, "Normal boot.\n");
+		acpi_slp_type=0;
+		break;
+	case 0xcafed00d:
+		printk(BIOS_DEBUG, "S3 Resume.\n");
+		acpi_slp_type=3;
+		break;
+	default:
+		printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n");
+		acpi_slp_type=0;
+		break;
+	}
+#endif
+}
+
+static struct pci_operations intel_pci_ops = {
+	.set_subsystem    = intel_set_subsystem,
+};
+
+static struct device_operations mc_ops = {
+	.read_resources   = mc_read_resources,
+	.set_resources    = mc_set_resources,
+	.enable_resources = pci_dev_enable_resources,
+	.init             = northbridge_init,
+	.enable           = northbridge_enable,
+	.scan_bus         = 0,
+	.ops_pci          = &intel_pci_ops,
+};
+
+static const struct pci_driver mc_driver __pci_driver = {
+	.ops    = &mc_ops,
+	.vendor = PCI_VENDOR_ID_INTEL,
+	.device = 0x0104,
+};
+
+static void cpu_bus_init(device_t dev)
+{
+	initialize_cpus(dev->link_list);
+}
+
+static void cpu_bus_noop(device_t dev)
+{
+}
+
+static struct device_operations cpu_bus_ops = {
+	.read_resources   = cpu_bus_noop,
+	.set_resources    = cpu_bus_noop,
+	.enable_resources = cpu_bus_noop,
+	.init             = cpu_bus_init,
+	.scan_bus         = 0,
+};
+
+static void enable_dev(device_t dev)
+{
+	/* Set the operations if it is a special bus type */
+	if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
+		dev->ops = &pci_domain_ops;
+	} else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
+		dev->ops = &cpu_bus_ops;
+	}
+}
+
+struct chip_operations northbridge_intel_sandybridge_ops = {
+	CHIP_NAME("Intel i7 (Sandybridge) integrated Northbridge")
+	.enable_dev = enable_dev,
+};
diff --git a/src/northbridge/intel/sandybridge/pcie_config.c b/src/northbridge/intel/sandybridge/pcie_config.c
new file mode 100644
index 0000000..21e131f
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/pcie_config.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "sandybridge.h"
+
+static inline __attribute__ ((always_inline))
+u8 pcie_read_config8(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read8(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u16 pcie_read_config16(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read16(addr);
+}
+
+static inline __attribute__ ((always_inline))
+u32 pcie_read_config32(device_t dev, unsigned int where)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	return read32(addr);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config8(device_t dev, unsigned int where, u8 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write8(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config16(device_t dev, unsigned int where, u16 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write16(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_write_config32(device_t dev, unsigned int where, u32 value)
+{
+	unsigned long addr;
+	addr = DEFAULT_PCIEXBAR | dev | where;
+	write32(addr, value);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config8(device_t dev, unsigned int where, u8 ormask)
+{
+	u8 value = pcie_read_config8(dev, where);
+	pcie_write_config8(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config16(device_t dev, unsigned int where, u16 ormask)
+{
+	u16 value = pcie_read_config16(dev, where);
+	pcie_write_config16(dev, where, value | ormask);
+}
+
+static inline __attribute__ ((always_inline))
+void pcie_or_config32(device_t dev, unsigned int where, u32 ormask)
+{
+	u32 value = pcie_read_config32(dev, where);
+	pcie_write_config32(dev, where, value | ormask);
+}
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h
new file mode 100644
index 0000000..427d374
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/pei_data.h
@@ -0,0 +1,91 @@
+/*
+ * coreboot UEFI PEI wrapper
+ *
+ * Copyright (c) 2011, Google Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Google Inc. nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PEI_DATA_H
+#define PEI_DATA_H
+
+struct pei_data
+{
+	uint32_t mchbar;
+	uint32_t dmibar;
+	uint32_t epbar;
+	uint32_t pciexbar;
+	uint16_t smbusbar;
+	uint32_t wdbbar;
+	uint32_t wdbsize;
+	uint32_t hpet_address;
+	uint32_t rcba;
+	uint32_t pmbase;
+	uint32_t gpiobase;
+	uint32_t thermalbase;
+	uint32_t system_type; // 0 Mobile, 1 Desktop/Server
+	uint32_t tseg_size;
+	uint8_t spd_addresses[4];
+	uint8_t ts_addresses[4];
+	int boot_mode;
+	int ec_present;
+	// 0 = leave channel enabled
+	// 1 = disable dimm 0 on channel
+	// 2 = disable dimm 1 on channel
+	// 3 = disable dimm 0+1 on channel
+	int dimm_channel0_disabled;
+	int dimm_channel1_disabled;
+	/* Seed values saved in CMOS */
+	uint32_t scrambler_seed;
+	uint32_t scrambler_seed_s3;
+	/* Data read from flash and passed into MRC */
+	unsigned char *mrc_input;
+	unsigned int mrc_input_len;
+	/* Data from MRC that should be saved to flash */
+	unsigned char *mrc_output;
+	unsigned int mrc_output_len;
+	/*
+	 * USB Port Configuration:
+	 *  [0] = enable
+	 *  [1] = overcurrent pin
+	 *  [2] = length
+	 *
+	 * Port Length
+	 *  MOBILE:
+	 *   < 0x050 = Setting 1 (back panel, 1-5in, lowest tx amplitude)
+	 *   < 0x140 = Setting 2 (back panel, 5-14in, highest tx amplitude)
+	 *  DESKTOP:
+	 *   < 0x080 = Setting 1 (front/back panel, <8in, lowest tx amplitude)
+	 *   < 0x130 = Setting 2 (back panel, 8-13in, higher tx amplitude)
+	 *   < 0x150 = Setting 3 (back panel, 13-15in, higest tx amplitude)
+	 */
+	uint16_t usb_port_config[16][3];
+	/* SPD data array for onboard RAM. Specify address 0xf0,
+	 * 0xf1, 0xf2, 0xf3 to index one of the 4 slots in
+	 * spd_address for a given "DIMM".
+	 */
+	uint8_t spd_data[4][256];
+} __attribute__((packed));
+
+#endif
diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
new file mode 100644
index 0000000..dcd019a
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -0,0 +1,329 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cbmem.h>
+#include <arch/cbfs.h>
+#include <cbfs.h>
+#include <ip_checksum.h>
+#include <pc80/mc146818rtc.h>
+#include "raminit.h"
+#include "pei_data.h"
+#include "sandybridge.h"
+
+/* Management Engine is in the southbridge */
+#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+#include "southbridge/intel/bd82x6x/me.h"
+#endif
+
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/chromeos.h>
+#endif
+#include <fdt/libfdt.h>
+
+/*
+ * MRC scrambler seed offsets should be reserved in
+ * mainboard cmos.layout and not covered by checksum.
+ */
+#if CONFIG_USE_OPTION_TABLE
+#include "option_table.h"
+#define CMOS_OFFSET_MRC_SEED     (CMOS_VSTART_mrc_scrambler_seed >> 3)
+#define CMOS_OFFSET_MRC_SEED_S3  (CMOS_VSTART_mrc_scrambler_seed_s3 >> 3)
+#define CMOS_OFFSET_MRC_SEED_CHK (CMOS_VSTART_mrc_scrambler_seed_chk >> 3)
+#else
+#define CMOS_OFFSET_MRC_SEED     112
+#define CMOS_OFFSET_MRC_SEED_S3  116
+#define CMOS_OFFSET_MRC_SEED_CHK 120
+#endif
+
+#define MRC_DATA_ALIGN           0x1000
+#define MRC_DATA_SIGNATURE       (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))
+
+struct mrc_data_container {
+	u32	mrc_signature;	// "MRCD"
+	u32	mrc_data_size;	// Actual total size of this structure
+	u32	mrc_checksum;	// IP style checksum
+	u32	reserved;	// For header alignment
+	u8	mrc_data[0];	// Variable size, platform/run time dependent.
+} __attribute__ ((packed));
+
+static void save_mrc_data(struct pei_data *pei_data)
+{
+	u16 c1, c2, checksum;
+
+#if CONFIG_EARLY_CBMEM_INIT
+	struct mrc_data_container *mrcdata;
+	int output_len = ALIGN(pei_data->mrc_output_len, 16);
+
+	/* Save the MRC S3 restore data to cbmem */
+	cbmem_initialize();
+	mrcdata = cbmem_add
+		(CBMEM_ID_MRCDATA,
+		 output_len + sizeof(struct mrc_data_container));
+
+	printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
+	       pei_data->mrc_output, mrcdata, output_len);
+
+	mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
+	mrcdata->mrc_data_size = output_len;
+	mrcdata->reserved = 0;
+	memcpy(mrcdata->mrc_data, pei_data->mrc_output,
+	       pei_data->mrc_output_len);
+
+	/* Zero the unused space in aligned buffer. */
+	if (output_len > pei_data->mrc_output_len)
+		memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0,
+		       output_len - pei_data->mrc_output_len);
+
+	mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
+						    mrcdata->mrc_data_size);
+#endif
+
+	/* Save the MRC seed values to CMOS */
+	cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
+	printk(BIOS_DEBUG, "Save scrambler seed    0x%08x to CMOS 0x%02x\n",
+	       pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
+
+	cmos_write32(CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
+	printk(BIOS_DEBUG, "Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
+	       pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
+
+	/* Save a simple checksum of the seed values */
+	c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
+				 sizeof(u32));
+	c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
+				 sizeof(u32));
+	checksum = add_ip_checksums(sizeof(u32), c1, c2);
+
+	cmos_write(checksum & 0xff, CMOS_OFFSET_MRC_SEED_CHK);
+	cmos_write((checksum >> 8) & 0xff, CMOS_OFFSET_MRC_SEED_CHK+1);
+}
+
+#if CONFIG_CHROMEOS
+static void prepare_mrc_cache(struct pei_data *pei_data)
+{
+	const struct fdt_header *fdt_header;
+	const struct fdt_property *fdtp;
+	int offset, len;
+	const char *compatible = "chromeos,flashmap";
+	const char *subnode = "rw-mrc-cache";
+	const char *property = "reg";
+	u32 *data;
+	struct mrc_data_container *mrc_cache, *mrc_next;
+	u8 *mrc_region, *region_ptr;
+	u16 c1, c2, checksum, seed_checksum;
+	u32 region_size, entry_id = 0;
+	u64 flashrom_base = 0;
+
+	// preset just in case there is an error
+	pei_data->mrc_input = NULL;
+	pei_data->mrc_input_len = 0;
+
+	/* Read scrambler seeds from CMOS */
+	pei_data->scrambler_seed = cmos_read32(CMOS_OFFSET_MRC_SEED);
+	printk(BIOS_DEBUG, "Read scrambler seed    0x%08x from CMOS 0x%02x\n",
+	       pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
+
+	pei_data->scrambler_seed_s3 = cmos_read32(CMOS_OFFSET_MRC_SEED_S3);
+	printk(BIOS_DEBUG, "Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
+	       pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
+
+	/* Compute seed checksum and compare */
+	c1 = compute_ip_checksum((u8*)&pei_data->scrambler_seed,
+				 sizeof(u32));
+	c2 = compute_ip_checksum((u8*)&pei_data->scrambler_seed_s3,
+				 sizeof(u32));
+	checksum = add_ip_checksums(sizeof(u32), c1, c2);
+
+	seed_checksum = cmos_read(CMOS_OFFSET_MRC_SEED_CHK);
+	seed_checksum |= cmos_read(CMOS_OFFSET_MRC_SEED_CHK+1) << 8;
+
+	if (checksum != seed_checksum) {
+		printk(BIOS_ERR, "%s: invalid seed checksum\n", __func__);
+		pei_data->scrambler_seed = 0;
+		pei_data->scrambler_seed_s3 = 0;
+		return;
+	}
+
+	fdt_header = cbfs_find_file(CONFIG_FDT_FILE_NAME, CBFS_TYPE_FDT);
+
+	if (!fdt_header) {
+		printk(BIOS_ERR, "%s: no FDT found!\n", __func__);
+		return;
+	}
+
+	offset = fdt_node_offset_by_compatible(fdt_header, 0, compatible);
+	if (offset < 0) {
+		printk(BIOS_ERR, "%s: no %s  node found!\n",
+		       __func__, compatible);
+		return;
+	}
+
+	if (fdt_get_base_addr(fdt_header, offset, &flashrom_base) < 0) {
+		printk(BIOS_ERR, "%s: no base address in node name!\n",
+		       __func__);
+		return;
+	}
+
+	offset = fdt_subnode_offset(fdt_header, offset, subnode);
+	if (offset < 0) {
+		printk(BIOS_ERR, "%s: no %s found!\n", __func__, subnode);
+		return;
+	}
+
+	fdtp = fdt_get_property(fdt_header, offset, property, &len);
+	if (!fdtp || (len != 8)) {
+		printk(BIOS_ERR, "%s: property %s at %p, len %d!\n",
+		       __func__, property, fdtp, len);
+		return;
+	}
+
+	data = (u32 *)fdtp->data;
+
+	// Calculate actual address of the MRC cache in memory
+	region_size = fdt32_to_cpu(data[1]);
+	mrc_region = region_ptr = (u8*)
+		((unsigned long)flashrom_base + fdt32_to_cpu(data[0]));
+	mrc_cache = mrc_next = (struct mrc_data_container *)mrc_region;
+
+	if (!mrc_cache || mrc_cache->mrc_signature != MRC_DATA_SIGNATURE) {
+		printk(BIOS_ERR, "%s: invalid MRC data\n", __func__);
+		return;
+	}
+
+	if (mrc_cache->mrc_data_size == -1UL) {
+		printk(BIOS_ERR, "%s: MRC cache not initialized?\n",  __func__);
+		return;
+	} else {
+		/* MRC data blocks are aligned within the region */
+		u32 mrc_size = sizeof(*mrc_cache) + mrc_cache->mrc_data_size;
+		if (mrc_size & (MRC_DATA_ALIGN - 1UL)) {
+			mrc_size &= ~(MRC_DATA_ALIGN - 1UL);
+			mrc_size += MRC_DATA_ALIGN;
+		}
+
+		/* Search for the last filled entry in the region */
+		while (mrc_next &&
+		       mrc_next->mrc_signature == MRC_DATA_SIGNATURE) {
+			entry_id++;
+			mrc_cache = mrc_next;
+			/* Stay in the mrcdata region defined in fdt */
+			if ((entry_id * mrc_size) > region_size)
+				break;
+			region_ptr += mrc_size;
+			mrc_next = (struct mrc_data_container *)region_ptr;
+		}
+		entry_id--;
+	}
+
+	/* Verify checksum */
+	if (mrc_cache->mrc_checksum !=
+	    compute_ip_checksum(mrc_cache->mrc_data,
+				mrc_cache->mrc_data_size)) {
+		printk(BIOS_ERR, "%s: MRC cache checksum mismatch\n", __func__);
+		return;
+	}
+
+	pei_data->mrc_input = mrc_cache->mrc_data;
+	pei_data->mrc_input_len = mrc_cache->mrc_data_size;
+
+	printk(BIOS_DEBUG, "%s: at %p, entry %u size %x checksum %04x\n",
+	       __func__, pei_data->mrc_input, entry_id,
+	       pei_data->mrc_input_len, mrc_cache->mrc_checksum);
+}
+#endif
+
+/**
+ * Find PEI executable in coreboot filesystem and execute it.
+ *
+ * @param pei_data: configuration data for UEFI PEI reference code
+ */
+void sdram_initialize(struct pei_data *pei_data)
+{
+	struct sys_info sysinfo;
+	const char *target = "mrc.bin";
+	unsigned long entry;
+
+#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+	/* Wait for ME to be ready */
+	intel_early_me_init();
+	intel_early_me_uma_size();
+#endif
+
+	printk(BIOS_DEBUG, "Starting UEFI PEI System Agent\n");
+
+	memset(&sysinfo, 0, sizeof(sysinfo));
+
+	sysinfo.boot_path = pei_data->boot_mode;
+
+#if CONFIG_CHROMEOS
+	/*
+	 * Do not pass MRC data in for recovery mode boot,
+	 * Always pass it in for S3 resume.
+	 */
+	if (!recovery_mode_enabled() || pei_data->boot_mode == 2)
+		prepare_mrc_cache(pei_data);
+
+	/* If MRC data is not found we cannot continue S3 resume. */
+	if (pei_data->boot_mode == 2 && !pei_data->mrc_input) {
+		outb(0x6, 0xcf9);
+		hlt();
+	}
+#endif
+
+	/* Locate and call UEFI System Agent binary. */
+	entry = (unsigned long)cbfs_find_file(target, 0xab);
+	if (entry) {
+		asm volatile ("call *%%ecx\n\t" : : "c" (entry), "a" (pei_data));
+	} else {
+		die("UEFI PEI System Agent not found.\n");
+	}
+
+	/* For reference print the System Agent version
+	 * after executing the UEFI PEI stage.
+	 */
+	u32 version = MCHBAR32(0x5034);
+	printk(BIOS_DEBUG, "System Agent Version %d.%d.%d Build %d\n",
+		version >> 24 , (version >> 16) & 0xff,
+		(version >> 8) & 0xff, version & 0xff);
+
+#if CONFIG_SOUTHBRIDGE_INTEL_BD82X6X
+	intel_early_me_init_done(ME_INIT_STATUS_SUCCESS);
+#endif
+
+	/* S3 resume: don't save scrambler seed or MRC data */
+	if (pei_data->boot_mode != 2)
+		save_mrc_data(pei_data);
+}
+
+struct cbmem_entry *get_cbmem_toc(void)
+{
+	return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
+}
+
+unsigned long get_top_of_ram(void)
+{
+	/* Base of TSEG is top of usable DRAM */
+	u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG);
+	return (unsigned long) tom;
+}
diff --git a/src/cpu/x86/mmx_disable.inc b/src/northbridge/intel/sandybridge/raminit.h
similarity index 64%
copy from src/cpu/x86/mmx_disable.inc
copy to src/northbridge/intel/sandybridge/raminit.h
index 1a4e70f..124f694 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/northbridge/intel/sandybridge/raminit.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2010 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,20 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef RAMINIT_H
+#define RAMINIT_H
 
+#include "pei_data.h"
+
+struct sys_info {
+	u8 boot_path;
+#define BOOT_PATH_NORMAL	0
+#define BOOT_PATH_RESET		1
+#define BOOT_PATH_RESUME	2
+} __attribute__ ((packed));
+
+void sdram_initialize(struct pei_data *pei_data);
+unsigned long get_top_of_ram(void);
+int fixup_sandybridge_errata(void);
+
+#endif				/* RAMINIT_H */
diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h
new file mode 100644
index 0000000..8c138ab
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/sandybridge.h
@@ -0,0 +1,207 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__
+#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1
+
+/* Chipset types */
+#define SANDYBRIDGE_MOBILE	0
+#define SANDYBRIDGE_DESKTOP	1
+#define SANDYBRIDGE_SERVER	2
+
+/* SandyBridge stepping values for SRID */
+#define SNB_STEP_B2	3
+#define SNB_STEP_C0	4
+#define SNB_STEP_D0	7 /* Also J0 */
+#define SNB_STEP_D1	8
+#define SNB_STEP_D2	9 /* Also J1/Q0 */
+
+/* Intel Enhanced Debug region must be 4MB */
+#define IED_SIZE	0x400000
+
+/* Northbridge BARs */
+#define DEFAULT_PCIEXBAR	CONFIG_MMCONF_BASE_ADDRESS	/* 4 KB per PCIe device */
+#define DEFAULT_MCHBAR		0xfed10000	/* 16 KB */
+#define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
+#define DEFAULT_EPBAR		0xfed19000	/* 4 KB */
+
+#include "../../../southbridge/intel/bd82x6x/pch.h"
+
+/* Everything below this line is ignored in the DSDT */
+#ifndef __ACPI__
+
+/* Device 0:0.0 PCI configuration space (Host Bridge) */
+
+#define EPBAR		0x40
+#define MCHBAR		0x48
+#define PCIEXBAR	0x60
+#define DMIBAR		0x68
+#define X60BAR		0x60
+
+#define GGC		0x50			/* GMCH Graphics Control */
+
+#define DEVEN		0x54			/* Device Enable */
+#define  DEVEN_PEG60	(1 << 13)
+#define  DEVEN_IGD	(1 << 4)
+#define  DEVEN_PEG10	(1 << 3)
+#define  DEVEN_PEG11	(1 << 2)
+#define  DEVEN_PEG12	(1 << 1)
+#define  DEVEN_HOST	(1 << 0)
+
+#define PAM0		0x80
+#define PAM1		0x81
+#define PAM2		0x82
+#define PAM3		0x83
+#define PAM4		0x84
+#define PAM5		0x85
+#define PAM6		0x86
+
+#define LAC		0x87	/* Legacy Access Control */
+#define SMRAM		0x88	/* System Management RAM Control */
+#define  D_OPEN		(1 << 6)
+#define  D_CLS		(1 << 5)
+#define  D_LCK		(1 << 4)
+#define  G_SMRAME	(1 << 3)
+#define  C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
+
+#define TOM		0xa0
+#define TOUUD		0xa8	/* Top of Upper Usable DRAM */
+#define TSEG		0xb8	/* TSEG base */
+#define TOLUD		0xbc	/* Top of Low Used Memory */
+
+#define SKPAD		0xdc	/* Scratchpad Data */
+
+/* Device 0:1.0 PCI configuration space (PCI Express) */
+
+#define BCTRL1		0x3e	/* 16bit */
+
+
+/* Device 0:2.0 PCI configuration space (Graphics Device) */
+
+#define MSAC		0x62	/* Multi Size Aperture Control */
+
+
+/*
+ * MCHBAR
+ */
+
+#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x))
+#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))
+
+#define SSKPD		0x5d14	/* 16bit (scratchpad) */
+#define BIOS_RESET_CPL	0x5da8	/* 8bit */
+
+/*
+ * EPBAR - Egress Port Root Complex Register Block
+ */
+
+#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x))
+#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x))
+#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x))
+
+#define EPPVCCAP1	0x004	/* 32bit */
+#define EPPVCCAP2	0x008	/* 32bit */
+
+#define EPVC0RCAP	0x010	/* 32bit */
+#define EPVC0RCTL	0x014	/* 32bit */
+#define EPVC0RSTS	0x01a	/* 16bit */
+
+#define EPVC1RCAP	0x01c	/* 32bit */
+#define EPVC1RCTL	0x020	/* 32bit */
+#define EPVC1RSTS	0x026	/* 16bit */
+
+#define EPVC1MTS	0x028	/* 32bit */
+#define EPVC1IST	0x038	/* 64bit */
+
+#define EPESD		0x044	/* 32bit */
+
+#define EPLE1D		0x050	/* 32bit */
+#define EPLE1A		0x058	/* 64bit */
+#define EPLE2D		0x060	/* 32bit */
+#define EPLE2A		0x068	/* 64bit */
+
+#define PORTARB		0x100	/* 256bit */
+
+/*
+ * DMIBAR
+ */
+
+#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x))
+#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x))
+
+#define DMIVCECH	0x000	/* 32bit */
+#define DMIPVCCAP1	0x004	/* 32bit */
+#define DMIPVCCAP2	0x008	/* 32bit */
+
+#define DMIPVCCCTL	0x00c	/* 16bit */
+
+#define DMIVC0RCAP	0x010	/* 32bit */
+#define DMIVC0RCTL0	0x014	/* 32bit */
+#define DMIVC0RSTS	0x01a	/* 16bit */
+
+#define DMIVC1RCAP	0x01c	/* 32bit */
+#define DMIVC1RCTL	0x020	/* 32bit */
+#define DMIVC1RSTS	0x026	/* 16bit */
+
+#define DMILE1D		0x050	/* 32bit */
+#define DMILE1A		0x058	/* 64bit */
+#define DMILE2D		0x060	/* 32bit */
+#define DMILE2A		0x068	/* 64bit */
+
+#define DMILCAP		0x084	/* 32bit */
+#define DMILCTL		0x088	/* 16bit */
+#define DMILSTS		0x08a	/* 16bit */
+
+#define DMICTL1		0x0f0	/* 32bit */
+#define DMICTL2		0x0fc	/* 32bit */
+
+#define DMICC		0x208	/* 32bit */
+
+#define DMIDRCCFG	0xeb4	/* 32bit */
+
+#ifndef __ASSEMBLER__
+static inline void barrier(void) { asm("" ::: "memory"); }
+
+struct ied_header {
+	char signature[10];
+	u32 size;
+	u8 reserved[34];
+} __attribute__ ((packed));
+
+#ifdef __SMM__
+void intel_sandybridge_finalize_smm(void);
+#else /* !__SMM__ */
+int sandybridge_silicon_revision(void);
+void sandybridge_early_initialization(int chipset_type);
+void sandybridge_late_initialization(void);
+
+/* debugging functions */
+void print_pci_devices(void);
+void dump_pci_device(unsigned dev);
+void dump_pci_devices(void);
+void dump_spd_registers(void);
+void dump_mem(unsigned start, unsigned end);
+#endif /* !__SMM__ */
+#endif
+#endif
+#endif
diff --git a/src/northbridge/intel/sandybridge/udelay.c b/src/northbridge/intel/sandybridge/udelay.c
new file mode 100644
index 0000000..3d8ba96
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/udelay.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+
+/**
+ * Intel Core(tm) cpus always run the TSC at the maximum possible CPU clock
+ */
+
+void udelay(u32 us)
+{
+	u32 dword;
+	tsc_t tsc, tsc1, tscd;
+	msr_t msr;
+	u32 fsb = 100, divisor;
+	u32 d;			/* ticks per us */
+	u32 dn = 0x1000000 / 2;	/* how many us before we need to use hi */
+
+	msr = rdmsr(0xce);
+	divisor = (msr.lo >> 8) & 0xff;
+
+	d = fsb * divisor;
+
+	tscd.hi = us / dn;
+	tscd.lo = (us - tscd.hi * dn) * d;
+
+	tsc1 = rdtsc();
+	dword = tsc1.lo + tscd.lo;
+	if ((dword < tsc1.lo) || (dword < tscd.lo)) {
+		tsc1.hi++;
+	}
+	tsc1.lo = dword;
+	tsc1.hi += tscd.hi;
+
+	do {
+		tsc = rdtsc();
+	} while ((tsc.hi < tsc1.hi)
+		 || ((tsc.hi == tsc1.hi) && (tsc.lo <= tsc1.lo)));
+}
diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c
index ccd0d33..7b7c67b 100644
--- a/src/northbridge/intel/sch/northbridge.c
+++ b/src/northbridge/intel/sch/northbridge.c
@@ -29,6 +29,7 @@
 #include <bitops.h>
 #include <cpu/cpu.h>
 #include <boot/tables.h>
+#include <arch/acpi.h>
 #include "chip.h"
 #include "sch.h"
 
@@ -267,8 +268,6 @@
 }
 
 #if CONFIG_HAVE_ACPI_RESUME
-extern u8 acpi_slp_type;
-
 static void northbridge_init(struct device *dev)
 {
 	switch (pci_read_config32(dev, SKPAD)) {
diff --git a/src/pc80/Makefile.inc b/src/pc80/Makefile.inc
index 0bc57b2..6d8001e 100644
--- a/src/pc80/Makefile.inc
+++ b/src/pc80/Makefile.inc
@@ -1,8 +1,12 @@
 ramstage-y += mc146818rtc.c
 ramstage-y += isa-dma.c
+ramstage-y += i8254.c
 ramstage-y += i8259.c
 ramstage-$(CONFIG_UDELAY_IO) += udelay_io.c
 ramstage-y += keyboard.c
+romstage-$(CONFIG_TPM) += tpm.c
+
+smm-y += udelay_io.c
 
 romstage-$(CONFIG_USE_OPTION_TABLE) += mc146818rtc_early.c
 subdirs-y += vga
diff --git a/src/pc80/i8254.c b/src/pc80/i8254.c
index ca993f4..f75216d 100644
--- a/src/pc80/i8254.c
+++ b/src/pc80/i8254.c
@@ -35,7 +35,7 @@
 	outb(0x12, TIMER1_PORT);
 }
 
-#if CONFIG_UDELAY_TIMER2
+#if defined(CONFIG_UDELAY_TIMER2) &&  CONFIG_UDELAY_TIMER2
 static void load_timer2(unsigned int ticks)
 {
         /* Set up the timer gate, turn off the speaker */
diff --git a/src/pc80/mc146818rtc.c b/src/pc80/mc146818rtc.c
index 5850ec6..40f8158 100644
--- a/src/pc80/mc146818rtc.c
+++ b/src/pc80/mc146818rtc.c
@@ -98,7 +98,6 @@
 	for(i = range_start; i <= range_end; i++) {
 		sum += cmos_read(i);
 	}
-	sum = ~(sum & 0x0ffff);
 	cmos_write(((sum >> 8) & 0x0ff), cks_loc);
 	cmos_write(((sum >> 0) & 0x0ff), cks_loc+1);
 }
@@ -132,12 +131,14 @@
 	checksum_invalid = !rtc_checksum_valid(PC_CKS_RANGE_START,
 			PC_CKS_RANGE_END,PC_CKS_LOC);
 
+#define CLEAR_CMOS 0
 	if (invalid || cmos_invalid || checksum_invalid) {
-		printk(BIOS_WARNING, "RTC:%s%s%s zeroing cmos\n",
+		printk(BIOS_WARNING, "RTC:%s%s%s%s\n",
 			invalid?" Clear requested":"",
 			cmos_invalid?" Power Problem":"",
-			checksum_invalid?" Checksum invalid":"");
-#if 0
+			checksum_invalid?" Checksum invalid":"",
+			CLEAR_CMOS?" zeroing cmos":"");
+#if CLEAR_CMOS
 		cmos_write(0, 0x01);
 		cmos_write(0, 0x03);
 		cmos_write(0, 0x05);
@@ -169,7 +170,7 @@
 	checksum_invalid = !rtc_checksum_valid(LB_CKS_RANGE_START,
 			LB_CKS_RANGE_END,LB_CKS_LOC);
 	if(checksum_invalid)
-		printk(BIOS_DEBUG, "Invalid CMOS LB checksum\n");
+		printk(BIOS_DEBUG, "RTC: coreboot checksum invalid\n");
 
 	/* Make certain we have a valid checksum */
 	rtc_set_checksum(PC_CKS_RANGE_START,
@@ -229,7 +230,8 @@
 	/* find the requested entry record */
 	ct=cbfs_find_file("cmos_layout.bin", CBFS_COMPONENT_CMOS_LAYOUT);
 	if (!ct) {
-		printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n");
+		printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. "
+						"Options are disabled\n");
 		return(-2);
 	}
 	ce=(struct cmos_entries*)((unsigned char *)ct + ct->header_length);
diff --git a/src/pc80/tpm.c b/src/pc80/tpm.c
new file mode 100644
index 0000000..8e94303
--- /dev/null
+++ b/src/pc80/tpm.c
@@ -0,0 +1,555 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * The code in this file has been heavily based on the article "Writing a TPM
+ * Device Driver" published on http://ptgmedia.pearsoncmg.com and the
+ * submission by Stefan Berger on Qemu-devel mailing list.
+ *
+ * One principal difference is that in the simplest config the other than 0
+ * TPM localities do not get mapped by some devices (for instance, by
+ * Infineon slb9635), so this driver provides access to locality 0 only.
+ */
+
+/* #define DEBUG */
+#include <stdlib.h>
+#include <string.h>
+#include <delay.h>
+#include <arch/io.h>
+#include <arch/byteorder.h>
+#include <console/console.h>
+#include <pc80/tpm.h>
+#include <cpu/x86/car.h>
+
+#ifdef DEBUG
+#define TPM_DEBUG_ON	1
+#else
+#define TPM_DEBUG_ON	0
+#endif
+
+#define PREFIX "lpc_tpm: "
+
+/* coreboot wrapper for TPM driver (start) */
+#define	TPM_DEBUG(fmt, args...)		\
+	if (TPM_DEBUG_ON) {		\
+		printk(BIOS_DEBUG, PREFIX);		\
+		printk(BIOS_DEBUG, fmt , ##args);	\
+	}
+#define printf(x...) printk(BIOS_ERR, x)
+
+#define min(a,b) MIN(a,b)
+#define max(a,b) MAX(a,b)
+#define readb(_a) (*(volatile unsigned char *) (_a))
+#define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v))
+#define readl(_a) (*(volatile unsigned long *) (_a))
+#define writel(_v, _a) (*(volatile unsigned long *) (_a) = (_v))
+/* coreboot wrapper for TPM driver (end) */
+
+#ifndef CONFIG_TPM_TIS_BASE_ADDRESS
+/* Base TPM address standard for x86 systems */
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+#endif
+
+/* the macro accepts the locality value, but only locality 0 is operational */
+#define TIS_REG(LOCALITY, REG) \
+    (void *)(CONFIG_TPM_TIS_BASE_ADDRESS + (LOCALITY << 12) + REG)
+
+/* hardware registers' offsets */
+#define TIS_REG_ACCESS                 0x0
+#define TIS_REG_INT_ENABLE             0x8
+#define TIS_REG_INT_VECTOR             0xc
+#define TIS_REG_INT_STATUS             0x10
+#define TIS_REG_INTF_CAPABILITY        0x14
+#define TIS_REG_STS                    0x18
+#define TIS_REG_DATA_FIFO              0x24
+#define TIS_REG_DID_VID                0xf00
+#define TIS_REG_RID                    0xf04
+
+/* Some registers' bit field definitions */
+#define TIS_STS_VALID                  (1 << 7) /* 0x80 */
+#define TIS_STS_COMMAND_READY          (1 << 6) /* 0x40 */
+#define TIS_STS_TPM_GO                 (1 << 5) /* 0x20 */
+#define TIS_STS_DATA_AVAILABLE         (1 << 4) /* 0x10 */
+#define TIS_STS_EXPECT                 (1 << 3) /* 0x08 */
+#define TIS_STS_RESPONSE_RETRY         (1 << 1) /* 0x02 */
+
+#define TIS_ACCESS_TPM_REG_VALID_STS   (1 << 7) /* 0x80 */
+#define TIS_ACCESS_ACTIVE_LOCALITY     (1 << 5) /* 0x20 */
+#define TIS_ACCESS_BEEN_SEIZED         (1 << 4) /* 0x10 */
+#define TIS_ACCESS_SEIZE               (1 << 3) /* 0x08 */
+#define TIS_ACCESS_PENDING_REQUEST     (1 << 2) /* 0x04 */
+#define TIS_ACCESS_REQUEST_USE         (1 << 1) /* 0x02 */
+#define TIS_ACCESS_TPM_ESTABLISHMENT   (1 << 0) /* 0x01 */
+
+#define TIS_STS_BURST_COUNT_MASK       (0xffff)
+#define TIS_STS_BURST_COUNT_SHIFT      (8)
+
+/*
+ * Error value returned if a tpm register does not enter the expected state
+ * after continuous polling. No actual TPM register reading ever returns ~0,
+ * so this value is a safe error indication to be mixed with possible status
+ * register values.
+ */
+#define TPM_TIMEOUT_ERR			(~0)
+
+/* Error value returned on various TPM driver errors */
+#define TPM_DRIVER_ERR		(~0)
+
+ /* 1 second is plenty for anything TPM does.*/
+#define MAX_DELAY_US	(1000 * 1000)
+
+/* Retrieve burst count value out of the status register contents. */
+#define BURST_COUNT(status) ((u16)(((status) >> TIS_STS_BURST_COUNT_SHIFT) & \
+				   TIS_STS_BURST_COUNT_MASK))
+
+/*
+ * Structures defined below allow creating descriptions of TPM vendor/device
+ * ID information for run time discovery. The only device the system knows
+ * about at this time is Infineon slb9635
+ */
+struct device_name {
+	u16 dev_id;
+	const char * const dev_name;
+};
+
+struct vendor_name {
+	u16 vendor_id;
+	const char * vendor_name;
+	const struct device_name* dev_names;
+};
+
+static const struct device_name infineon_devices[] = {
+	{0xb, "SLB9635 TT 1.2"},
+	{0}
+};
+
+static const struct vendor_name vendor_names[] = {
+	{0x15d1, "Infineon", infineon_devices},
+};
+
+/*
+ * Cached vendor/device ID pair to indicate that the device has been already
+ * discovered
+ */
+static u32 vendor_dev_id CAR_GLOBAL;
+
+static int is_byte_reg(u32 reg)
+{
+	/*
+	 * These TPM registers are 8 bits wide and as such require byte access
+	 * on writes and truncated value on reads.
+	 */
+	return ((reg == TIS_REG_ACCESS)	||
+		(reg == TIS_REG_INT_VECTOR) ||
+		(reg == TIS_REG_DATA_FIFO));
+}
+
+/* TPM access functions are carved out to make tracing easier. */
+static u32 tpm_read(int locality, u32 reg)
+{
+	u32 value;
+	/*
+	 * Data FIFO register must be read and written in byte access mode,
+	 * otherwise the FIFO values are returned 4 bytes at a time.
+	 */
+	if (is_byte_reg(reg))
+		value = readb(TIS_REG(locality, reg));
+	else
+		value = readl(TIS_REG(locality, reg));
+
+	TPM_DEBUG("Read reg 0x%x returns 0x%x\n", reg, value);
+	return value;
+}
+
+static void tpm_write(u32 value, int locality,  u32 reg)
+{
+	TPM_DEBUG("Write reg 0x%x with 0x%x\n", reg, value);
+
+	if (is_byte_reg(reg))
+		writeb(value & 0xff, TIS_REG(locality, reg));
+	else
+		writel(value, TIS_REG(locality, reg));
+}
+
+/*
+ * tis_wait_reg()
+ *
+ * Wait for at least a second for a register to change its state to match the
+ * expected state. Normally the transition happens within microseconds.
+ *
+ * @reg - the TPM register offset
+ * @locality - locality
+ * @mask - bitmask for the bitfield(s) to watch
+ * @expected - value the field(s) are supposed to be set to
+ *
+ * Returns the register contents in case the expected value was found in the
+ * appropriate register bits, or TPM_TIMEOUT_ERR on timeout.
+ */
+static u32 tis_wait_reg(u8 reg, u8 locality, u8 mask, u8 expected)
+{
+	u32 time_us = MAX_DELAY_US;
+	while (time_us > 0) {
+		u32 value = tpm_read(locality, reg);
+		if ((value & mask) == expected)
+			return value;
+		udelay(1); /* 1 us */
+		time_us--;
+	}
+	return TPM_TIMEOUT_ERR;
+}
+
+/*
+ * Probe the TPM device and try determining its manufacturer/device name.
+ *
+ * Returns 0 on success (the device is found or was found during an earlier
+ * invocation) or TPM_DRIVER_ERR if the device is not found.
+ */
+static u32 tis_probe(void)
+{
+	u32 didvid = tpm_read(0, TIS_REG_DID_VID);
+	int i;
+	const char *device_name = "unknown";
+	const char *vendor_name = device_name;
+	u16 vid, did;
+
+	if (vendor_dev_id)
+		return 0;  /* Already probed. */
+
+	if (!didvid || (didvid == 0xffffffff)) {
+		printf("%s: No TPM device found\n", __FUNCTION__);
+		return TPM_DRIVER_ERR;
+	}
+
+	vendor_dev_id = didvid;
+
+	vid = didvid & 0xffff;
+	did = (didvid >> 16) & 0xffff;
+	for (i = 0; i < ARRAY_SIZE(vendor_names); i++) {
+		int j = 0;
+		u16 known_did;
+		if (vid == vendor_names[i].vendor_id) {
+			vendor_name = vendor_names[i].vendor_name;
+		}
+		while ((known_did = vendor_names[i].dev_names[j].dev_id) != 0) {
+			if (known_did == did) {
+				device_name =
+					vendor_names[i].dev_names[j].dev_name;
+				break;
+			}
+			j++;
+		}
+		break;
+	}
+	/* this will have to be converted into debug printout */
+	TPM_DEBUG("Found TPM %s by %s\n", device_name, vendor_name);
+	return 0;
+}
+
+/*
+ * tis_senddata()
+ *
+ * send the passed in data to the TPM device.
+ *
+ * @data - address of the data to send, byte by byte
+ * @len - length of the data to send
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on error (in case the device does
+ * not accept the entire command).
+ */
+static u32 tis_senddata(const u8 * const data, u32 len)
+{
+	u32 offset = 0;
+	u16 burst = 0;
+	u32 max_cycles = 0;
+	u8 locality = 0;
+	u32 value;
+
+	value = tis_wait_reg(TIS_REG_STS, locality, TIS_STS_COMMAND_READY,
+			     TIS_STS_COMMAND_READY);
+	if (value == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to get 'command_ready' status\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+	burst = BURST_COUNT(value);
+
+	while (1) {
+		unsigned count;
+
+		/* Wait till the device is ready to accept more data. */
+		while (!burst) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d failed to feed %d bytes of %d\n",
+				       __FILE__, __LINE__, len - offset, len);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			burst = BURST_COUNT(tpm_read(locality, TIS_REG_STS));
+		}
+
+		max_cycles = 0;
+
+		/*
+		 * Calculate number of bytes the TPM is ready to accept in one
+		 * shot.
+		 *
+		 * We want to send the last byte outside of the loop (hence
+		 * the -1 below) to make sure that the 'expected' status bit
+		 * changes to zero exactly after the last byte is fed into the
+		 * FIFO.
+		 */
+		count = min(burst, len - offset - 1);
+		while (count--)
+			tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+		value = tis_wait_reg(TIS_REG_STS, locality,
+				     TIS_STS_VALID, TIS_STS_VALID);
+
+		if ((value == TPM_TIMEOUT_ERR) || !(value & TIS_STS_EXPECT)) {
+			printf("%s:%d TPM command feed overflow\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		burst = BURST_COUNT(value);
+		if ((offset == (len - 1)) && burst)
+			/*
+			 * We need to be able to send the last byte to the
+			 * device, so burst size must be nonzero before we
+			 * break out.
+			 */
+			break;
+	}
+
+	/* Send the last byte. */
+	tpm_write(data[offset++], locality, TIS_REG_DATA_FIFO);
+
+	/*
+	 * Verify that TPM does not expect any more data as part of this
+	 * command.
+	 */
+	value = tis_wait_reg(TIS_REG_STS, locality,
+			     TIS_STS_VALID, TIS_STS_VALID);
+	if ((value == TPM_TIMEOUT_ERR) || (value & TIS_STS_EXPECT)) {
+		printf("%s:%d unexpected TPM status 0x%x\n",
+		       __FILE__, __LINE__, value);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* OK, sitting pretty, let's start the command execution. */
+	tpm_write(TIS_STS_TPM_GO, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_readresponse()
+ *
+ * read the TPM device response after a command was issued.
+ *
+ * @buffer - address where to read the response, byte by byte.
+ * @len - pointer to the size of buffer
+ *
+ * On success stores the number of received bytes to len and returns 0. On
+ * errors (misformatted TPM data or synchronization problems) returns
+ * TPM_DRIVER_ERR.
+ */
+static u32 tis_readresponse(u8 *buffer, size_t *len)
+{
+	u16 burst_count;
+	u32 status;
+	u32 offset = 0;
+	u8 locality = 0;
+	const u32 has_data = TIS_STS_DATA_AVAILABLE | TIS_STS_VALID;
+	u32 expected_count = *len;
+	int max_cycles = 0;
+
+	/* Wait for the TPM to process the command */
+	status = tis_wait_reg(TIS_REG_STS, locality, has_data, has_data);
+	if (status == TPM_TIMEOUT_ERR) {
+		printf("%s:%d failed processing command\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	do {
+		while ((burst_count = BURST_COUNT(status)) == 0) {
+			if (max_cycles++ == MAX_DELAY_US) {
+				printf("%s:%d TPM stuck on read\n",
+				       __FILE__, __LINE__);
+				return TPM_DRIVER_ERR;
+			}
+			udelay(1);
+			status = tpm_read(locality, TIS_REG_STS);
+		}
+
+		max_cycles = 0;
+
+		while (burst_count-- && (offset < expected_count)) {
+			buffer[offset++] = (u8) tpm_read(locality,
+							 TIS_REG_DATA_FIFO);
+			if (offset == 6) {
+				/*
+				 * We got the first six bytes of the reply,
+				 * let's figure out how many bytes to expect
+				 * total - it is stored as a 4 byte number in
+				 * network order, starting with offset 2 into
+				 * the body of the reply.
+				 */
+				u32 real_length;
+				memcpy(&real_length,
+				       buffer + 2,
+				       sizeof(real_length));
+				expected_count = be32_to_cpu(real_length);
+
+				if ((expected_count < offset) ||
+				    (expected_count > *len)) {
+					printf("%s:%d bad response size %d\n",
+					       __FILE__, __LINE__,
+					       expected_count);
+					return TPM_DRIVER_ERR;
+				}
+			}
+		}
+
+		/* Wait for the next portion */
+		status = tis_wait_reg(TIS_REG_STS, locality,
+				      TIS_STS_VALID, TIS_STS_VALID);
+		if (status == TPM_TIMEOUT_ERR) {
+			printf("%s:%d failed to read response\n",
+			       __FILE__, __LINE__);
+			return TPM_DRIVER_ERR;
+		}
+
+		if (offset == expected_count)
+			break;	/* We got all we need */
+
+	} while ((status & has_data) == has_data);
+
+	/*
+	 * Make sure we indeed read all there was. The TIS_STS_VALID bit is
+	 * known to be set.
+	 */
+	if (status & TIS_STS_DATA_AVAILABLE) {
+		printf("%s:%d wrong receive status %x\n",
+		       __FILE__, __LINE__, status);
+		return TPM_DRIVER_ERR;
+	}
+
+	/* Tell the TPM that we are done. */
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	*len = offset;
+	return 0;
+}
+
+/*
+ * tis_init()
+ *
+ * Initialize the TPM device. Returns 0 on success or TPM_DRIVER_ERR on
+ * failure (in case device probing did not succeed).
+ */
+int tis_init(void)
+{
+	if (tis_probe())
+		return TPM_DRIVER_ERR;
+	return 0;
+}
+
+/*
+ * tis_open()
+ *
+ * Requests access to locality 0 for the caller. After all commands have been
+ * completed the caller is supposed to call tis_close().
+ *
+ * Returns 0 on success, TPM_DRIVER_ERR on failure.
+ */
+int tis_open(void)
+{
+	u8 locality = 0; /* we use locality zero for everything */
+
+	if (tis_close())
+		return TPM_DRIVER_ERR;
+
+	/* now request access to locality */
+	tpm_write(TIS_ACCESS_REQUEST_USE, locality, TIS_REG_ACCESS);
+
+	/* did we get a lock? */
+	if (tis_wait_reg(TIS_REG_ACCESS, locality,
+			 TIS_ACCESS_ACTIVE_LOCALITY,
+			 TIS_ACCESS_ACTIVE_LOCALITY) == TPM_TIMEOUT_ERR) {
+		printf("%s:%d - failed to lock locality %d\n",
+		       __FILE__, __LINE__, locality);
+		return TPM_DRIVER_ERR;
+	}
+
+	tpm_write(TIS_STS_COMMAND_READY, locality, TIS_REG_STS);
+
+	return 0;
+}
+
+/*
+ * tis_close()
+ *
+ * terminate the currect session with the TPM by releasing the locked
+ * locality. Returns 0 on success of TPM_DRIVER_ERR on failure (in case lock
+ * removal did not succeed).
+ */
+int tis_close(void)
+{
+	u8 locality = 0;
+	if (tpm_read(locality, TIS_REG_ACCESS) &
+	    TIS_ACCESS_ACTIVE_LOCALITY) {
+		tpm_write(TIS_ACCESS_ACTIVE_LOCALITY, locality, TIS_REG_ACCESS);
+
+		if (tis_wait_reg(TIS_REG_ACCESS, locality,
+				 TIS_ACCESS_ACTIVE_LOCALITY, 0) ==
+		    TPM_TIMEOUT_ERR) {
+			printf("%s:%d - failed to release locality %d\n",
+			       __FILE__, __LINE__, locality);
+			return TPM_DRIVER_ERR;
+		}
+	}
+	return 0;
+}
+
+/*
+ * tis_sendrecv()
+ *
+ * Send the requested data to the TPM and then try to get its response
+ *
+ * @sendbuf - buffer of the data to send
+ * @send_size size of the data to send
+ * @recvbuf - memory to save the response to
+ * @recv_len - pointer to the size of the response buffer
+ *
+ * Returns 0 on success (and places the number of response bytes at recv_len)
+ * or TPM_DRIVER_ERR on failure.
+ */
+int tis_sendrecv(const uint8_t *sendbuf, size_t send_size,
+		 uint8_t *recvbuf, size_t *recv_len)
+{
+	if (tis_senddata(sendbuf, send_size)) {
+		printf("%s:%d failed sending data to TPM\n",
+		       __FILE__, __LINE__);
+		return TPM_DRIVER_ERR;
+	}
+
+	return tis_readresponse(recvbuf, recv_len);
+}
diff --git a/src/southbridge/amd/sb600/sb600.h b/src/southbridge/amd/sb600/sb600.h
index 97a7ad2..629f389 100644
--- a/src/southbridge/amd/sb600/sb600.h
+++ b/src/southbridge/amd/sb600/sb600.h
@@ -40,5 +40,4 @@
 void sb600_lpc_port80(void);
 void sb600_pci_port80(void);
 
-void enable_usbdebug(unsigned int port);
 #endif /* SB600_H */
diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h
index 60eea47..8ef6b61 100644
--- a/src/southbridge/amd/sb700/sb700.h
+++ b/src/southbridge/amd/sb700/sb700.h
@@ -75,5 +75,4 @@
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void enable_usbdebug(unsigned int port);
 #endif /* SB700_H */
diff --git a/src/southbridge/amd/sb800/sb800.h b/src/southbridge/amd/sb800/sb800.h
index d7a4a38..ffe7aeb 100644
--- a/src/southbridge/amd/sb800/sb800.h
+++ b/src/southbridge/amd/sb800/sb800.h
@@ -58,7 +58,6 @@
 int s3_save_nvram_early(u32 dword, int size, int  nvram_pos);
 int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);
 
-void enable_usbdebug(unsigned int port);
 #else
 void sb800_enable(device_t dev);
 void __attribute__((weak)) sb800_setup_sata_phys(struct device *dev);
diff --git a/src/southbridge/intel/Kconfig b/src/southbridge/intel/Kconfig
index e6ffac9..cb0ac83 100644
--- a/src/southbridge/intel/Kconfig
+++ b/src/southbridge/intel/Kconfig
@@ -10,3 +10,4 @@
 source src/southbridge/intel/i82870/Kconfig
 source src/southbridge/intel/pxhd/Kconfig
 source src/southbridge/intel/sch/Kconfig
+source src/southbridge/intel/bd82x6x/Kconfig
diff --git a/src/southbridge/intel/Makefile.inc b/src/southbridge/intel/Makefile.inc
index b399955..ced1057 100644
--- a/src/southbridge/intel/Makefile.inc
+++ b/src/southbridge/intel/Makefile.inc
@@ -10,3 +10,4 @@
 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_I82870) += i82870
 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_PXHD) += pxhd
 subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_SCH) += sch
+subdirs-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += bd82x6x
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
new file mode 100644
index 0000000..af1ae97d
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -0,0 +1,44 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+config SOUTHBRIDGE_INTEL_BD82X6X
+	bool
+	select IOAPIC
+	select HAVE_HARD_RESET
+	select HAVE_USBDEBUG
+	select TINY_BOOTBLOCK
+	select USE_WATCHDOG_ON_BOOT
+	select PCIEXP_ASPM
+	select PCIEXP_COMMON_CLOCK
+
+if SOUTHBRIDGE_INTEL_BD82X6X
+
+config EHCI_BAR
+	hex
+	default 0xfef00000
+
+config EHCI_DEBUG_OFFSET
+	hex
+	default 0xa0
+
+config BOOTBLOCK_SOUTHBRIDGE_INIT
+	string
+	default "southbridge/intel/bd82x6x/bootblock.c"
+
+endif
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc
new file mode 100644
index 0000000..e42d07a
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/Makefile.inc
@@ -0,0 +1,40 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+driver-y += pch.c
+driver-y += azalia.c
+driver-y += lpc.c
+driver-y += pci.c
+driver-y += pcie.c
+driver-y += sata.c
+driver-y += usb_ehci.c
+driver-y += me.c
+driver-y += smbus.c
+
+ramstage-y += me_status.c
+ramstage-y += reset.c
+ramstage-y += watchdog.c
+
+ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c finalize.c
+
+romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
+romstage-$(CONFIG_USBDEBUG) += usb_debug.c
+romstage-y += reset.c
+
diff --git a/src/southbridge/intel/bd82x6x/acpi/audio.asl b/src/southbridge/intel/bd82x6x/acpi/audio.asl
new file mode 100644
index 0000000..a455328
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/audio.asl
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel PCH HDA */
+
+// Intel High Definition Audio (Azalia) 0:1b.0
+
+Device (HDEF)
+{
+	Name (_ADR, 0x001b0000)
+
+	// Power Resources for Wake
+	Name (_PRW, Package(){
+		13,  // Bit 13 of GPE
+		 4   // Can wake from S4 state.
+	})
+}
+
diff --git a/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
new file mode 100644
index 0000000..df450e3
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/globalnvs.asl
@@ -0,0 +1,244 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Global Variables */
+
+Name(\PICM, 0)		// IOAPIC/8259
+Name(\DSEN, 1)		// Display Output Switching Enable
+
+/* Global ACPI memory region. This region is used for passing information
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we have to fix it up in coreboot's ACPI creation phase.
+ */
+
+
+OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	Offset (0x00),
+	OSYS,	16,	// 0x00 - Operating System
+	SMIF,	 8,	// 0x02 - SMI function
+	PRM0,	 8,	// 0x03 - SMI function parameter
+	PRM1,	 8,	// 0x04 - SMI function parameter
+	SCIF,	 8,	// 0x05 - SCI function
+	PRM2,	 8,	// 0x06 - SCI function parameter
+	PRM3,	 8,	// 0x07 - SCI function parameter
+	LCKF,	 8,	// 0x08 - Global Lock function for EC
+	PRM4,	 8,	// 0x09 - Lock function parameter
+	PRM5,	 8,	// 0x0a - Lock function parameter
+	P80D,	32,	// 0x0b - Debug port (IO 0x80) value
+	LIDS,	 8,	// 0x0f - LID state (open = 1)
+	PWRS,	 8,	// 0x10 - Power State (AC = 1)
+	/* Thermal policy */
+	Offset (0x11),
+	TLVL,    8,	// 0x11 - Throttle Level Limit
+	FLVL,	 8,	// 0x12 - Current FAN Level
+	TCRT,    8,	// 0x13 - Critical Threshold
+	TPSV,	 8,	// 0x14 - Passive Threshold
+	TMAX,	 8,	// 0x15 - CPU Tj_max
+	F0OF,	 8,	// 0x16 - FAN 0 OFF Threshold
+	F0ON,	 8,	// 0x17 - FAN 0 ON Threshold
+	F0PW,	 8,	// 0x18 - FAN 0 PWM value
+	F1OF,	 8,	// 0x19 - FAN 1 OFF Threshold
+	F1ON,	 8,	// 0x1a - FAN 1 ON Threshold
+	F1PW,	 8,	// 0x1b - FAN 1 PWM value
+	F2OF,	 8,	// 0x1c - FAN 2 OFF Threshold
+	F2ON,	 8,	// 0x1d - FAN 2 ON Threshold
+	F2PW,	 8,	// 0x1e - FAN 2 PWM value
+	F3OF,	 8,	// 0x1f - FAN 3 OFF Threshold
+	F3ON,	 8,	// 0x20 - FAN 3 ON Threshold
+	F3PW,	 8,	// 0x21 - FAN 3 PWM value
+	F4OF,	 8,	// 0x22 - FAN 4 OFF Threshold
+	F4ON,	 8,	// 0x23 - FAN 4 ON Threshold
+	F4PW,	 8,	// 0x24 - FAN 4 PWM value
+	/* Processor Identification */
+	Offset (0x28),
+	APIC,	 8,	// 0x28 - APIC Enabled by coreboot
+	MPEN,	 8,	// 0x29 - Multi Processor Enable
+	PCP0,	 8,	// 0x2a - PDC CPU/CORE 0
+	PCP1,	 8,	// 0x2b - PDC CPU/CORE 1
+	PPCM,	 8,	// 0x2c - Max. PPC state
+	PCNT,	 8,	// 0x2d - Processor count
+	/* Super I/O & CMOS config */
+	Offset (0x32),
+	NATP,	 8,	// 0x32 -
+	S5U0,	 8,	// 0x32 - Enable USB0 in S5
+	S5U1,	 8,	// 0x33 - Enable USB1 in S5
+	S3U0,	 8,	// 0x35 - Enable USB0 in S3
+	S3U1,	 8,	// 0x36 - Enable USB1 in S3
+	S33G,	 8,	// 0x37 - Enable 3G in S3
+	CMEM,	 32,	// 0x38 - CBMEM TOC
+	/* Integrated Graphics Device */
+	Offset (0x3c),
+	IGDS,	 8,	// 0x3c - IGD state (primary = 1)
+	TLST,	 8,	// 0x3d - Display Toggle List pointer
+	CADL,	 8,	// 0x3e - Currently Attached Devices List
+	PADL,	 8,	// 0x3f - Previously Attached Devices List
+	CSTE,	16,	// 0x40 - Current display state
+	NSTE,	16,	// 0x42 - Next display state
+	SSTE,	16,	// 0x44 - Set display state
+	Offset (0x46),
+	NDID,	 8,	// 0x46 - Number of Device IDs
+	DID1,	32,	// 0x47 - Device ID 1
+	DID2,	32,	// 0x4b - Device ID 2
+	DID3,	32,	// 0x4f - Device ID 3
+	DID4,	32,	// 0x53 - Device ID 4
+	DID5,	32,	// 0x57 - Device ID 5
+	/* Backlight Control */
+	Offset (0x64),
+	BLCS,	 8,	// 0x64 - Backlight control possible?
+	BRTL,	 8,	// 0x65 - Brightness Level
+	ODDS,	 8,	// 0x66
+	/* Ambient Light Sensors */
+	Offset (0x6e),
+	ALSE,	 8,	// 0x6e - ALS enable
+	ALAF,	 8,	// 0x6f - Ambient light adjustment factor
+	LLOW,	 8,	// 0x70 - LUX Low
+	LHIH,	 8,	// 0x71 - LUX High
+	/* EMA */
+	Offset (0x78),
+	EMAE,	 8,	// 0x78 - EMA enable
+	EMAP,	16,	// 0x79 - EMA pointer
+	EMAL,	16,	// 0x7b - EMA length
+	/* MEF */
+	Offset (0x82),
+	MEFE,	 8,	// 0x82 - MEF enable
+	/* TPM support */
+	Offset (0x8c),
+	TPMP,	 8,	// 0x8c - TPM
+	TPME,	 8,	// 0x8d - TPM enable
+	/* SATA */
+	Offset (0x96),
+	GTF0,	56,	// 0x96 - GTF task file buffer for port 0
+	GTF1,	56,	// 0x9d - GTF task file buffer for port 1
+	GTF2,	56,	// 0xa4 - GTF task file buffer for port 2
+	IDEM,	 8,	// 0xab - IDE mode (compatible / enhanced)
+	IDET,	 8,	// 0xac - IDE
+	/* IGD OpRegion */
+	Offset (0xb4),
+	ASLB,	32,	// 0xb4 - IGD OpRegion Base Address
+	IBTT,	 8,	// 0xb8 - IGD boot panel device
+	IPAT,	 8,	// 0xb9 - IGD panel type cmos option
+	ITVF,	 8,	// 0xba - IGD TV format cmos option
+	ITVM,	 8,	// 0xbb - IGD TV minor format option
+	IPSC,	 8,	// 0xbc - IGD panel scaling
+	IBLC,	 8,	// 0xbd - IGD BLC config
+	IBIA,	 8,	// 0xbe - IGD BIA config
+	ISSC,	 8,	// 0xbf - IGD SSC config
+	I409,	 8,	// 0xc0 - IGD 0409 modified settings
+	I509,	 8,	// 0xc1 - IGD 0509 modified settings
+	I609,	 8,	// 0xc2 - IGD 0609 modified settings
+	I709,	 8,	// 0xc3 - IGD 0709 modified settings
+	IDMM,	 8,	// 0xc4 - IGD DVMT Mode
+	IDMS,	 8,	// 0xc5 - IGD DVMT memory size
+	IF1E,	 8,	// 0xc6 - IGD function 1 enable
+	HVCO,	 8,	// 0xc7 - IGD HPLL VCO
+	NXD1,	32,	// 0xc8 - IGD _DGS next DID1
+	NXD2,	32,	// 0xcc - IGD _DGS next DID2
+	NXD3,	32,	// 0xd0 - IGD _DGS next DID3
+	NXD4,	32,	// 0xd4 - IGD _DGS next DID4
+	NXD5,	32,	// 0xd8 - IGD _DGS next DID5
+	NXD6,	32,	// 0xdc - IGD _DGS next DID6
+	NXD7,	32,	// 0xe0 - IGD _DGS next DID7
+	NXD8,	32,	// 0xe4 - IGD _DGS next DID8
+
+	/* ChromeOS specific */
+	Offset (0xf0),
+	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+	// 0xe8a - end
+}
+
+/* Set flag to enable USB charging in S3 */
+Method (S3UE)
+{
+	Store (One, \S3U0)
+	Store (One, \S3U1)
+}
+
+/* Set flag to disable USB charging in S3 */
+Method (S3UD)
+{
+	Store (Zero, \S3U0)
+	Store (Zero, \S3U1)
+}
+
+/* Set flag to enable USB charging in S5 */
+Method (S5UE)
+{
+	Store (One, \S5U0)
+	Store (One, \S5U1)
+}
+
+/* Set flag to disable USB charging in S5 */
+Method (S5UD)
+{
+	Store (Zero, \S5U0)
+	Store (Zero, \S5U1)
+}
+
+/* Set flag to enable 3G module in S3 */
+Method (S3GE)
+{
+	Store (One, \S33G)
+}
+
+/* Set flag to disable 3G module in S3 */
+Method (S3GD)
+{
+	Store (Zero, \S33G)
+}
+
+/* Update Fan 0 thresholds */
+Method (F0UT, 2)
+{
+	Store (Arg0, \F0OF)
+	Store (Arg1, \F0ON)
+}
+
+/* Update Fan 1 thresholds */
+Method (F1UT, 2)
+{
+	Store (Arg0, \F1OF)
+	Store (Arg1, \F1ON)
+}
+
+/* Update Fan 2 thresholds */
+Method (F2UT, 2)
+{
+	Store (Arg0, \F2OF)
+	Store (Arg1, \F2ON)
+}
+
+/* Update Fan 3 thresholds */
+Method (F3UT, 2)
+{
+	Store (Arg0, \F3OF)
+	Store (Arg1, \F3ON)
+}
+
+/* Update Fan 4 thresholds */
+Method (F4UT, 2)
+{
+	Store (Arg0, \F4OF)
+	Store (Arg1, \F4ON)
+}
diff --git a/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl
new file mode 100644
index 0000000..5fcee45
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/irqlinks.asl
@@ -0,0 +1,493 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Device (LNKA)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 1)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTA)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLA, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLA, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTA
+		ShiftLeft(1, And(PRTA, 0x0f), IRQ0)
+
+		Return (RTLA)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTA)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTA, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKB)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 2)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTB)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLB, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLB, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTB
+		ShiftLeft(1, And(PRTB, 0x0f), IRQ0)
+
+		Return (RTLB)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTB)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTB, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKC)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 3)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTC)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLC, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLC, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTC
+		ShiftLeft(1, And(PRTC, 0x0f), IRQ0)
+
+		Return (RTLC)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTC)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTC, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKD)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 4)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTD)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLD, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLD, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTD
+		ShiftLeft(1, And(PRTD, 0x0f), IRQ0)
+
+		Return (RTLD)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTD)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTD, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKE)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 5)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTE)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLE, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLE, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTE
+		ShiftLeft(1, And(PRTE, 0x0f), IRQ0)
+
+		Return (RTLE)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTE)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTE, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKF)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 6)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTF)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLF, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLF, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTF
+		ShiftLeft(1, And(PRTF, 0x0f), IRQ0)
+
+		Return (RTLF)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTF)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTF, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKG)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 7)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTG)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 10, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLG, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLG, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTG
+		ShiftLeft(1, And(PRTG, 0x0f), IRQ0)
+
+		Return (RTLG)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTG)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTG, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
+Device (LNKH)
+{
+	Name (_HID, EISAID("PNP0C0F"))
+	Name (_UID, 8)
+
+	// Disable method
+	Method (_DIS, 0, Serialized)
+	{
+		Store (0x80, PRTH)
+	}
+
+	// Possible Resource Settings for this Link
+	Name (_PRS, ResourceTemplate()
+	{
+		IRQ(Level, ActiveLow, Shared)
+			{ 1, 3, 4, 5, 6, 7, 11, 12, 14, 15 }
+	})
+
+	// Current Resource Settings for this link
+	Method (_CRS, 0, Serialized)
+	{
+		Name (RTLH, ResourceTemplate()
+		{
+			IRQ(Level, ActiveLow, Shared) {}
+		})
+		CreateWordField(RTLH, 1, IRQ0)
+
+		// Clear the WordField
+		Store (Zero, IRQ0)
+
+		// Set the bit from PRTH
+		ShiftLeft(1, And(PRTH, 0x0f), IRQ0)
+
+		Return (RTLH)
+	}
+
+	// Set Resource Setting for this IRQ link
+	Method (_SRS, 1, Serialized)
+	{
+		CreateWordField(Arg0, 1, IRQ0)
+
+		// Which bit is set?
+		FindSetRightBit(IRQ0, Local0)
+
+		Decrement(Local0)
+		Store(Local0, PRTH)
+	}
+
+	// Status
+	Method (_STA, 0, Serialized)
+	{
+		If(And(PRTH, 0x80)) {
+			Return (0x9)
+		} Else {
+			Return (0xb)
+		}
+	}
+}
+
diff --git a/src/southbridge/intel/bd82x6x/acpi/lpc.asl b/src/southbridge/intel/bd82x6x/acpi/lpc.asl
new file mode 100644
index 0000000..d905a0d
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/lpc.asl
@@ -0,0 +1,248 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel LPC Bus Device  - 0:1f.0
+
+Device (LPCB)
+{
+	Name(_ADR, 0x001f0000)
+
+	OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
+	Field (LPC0, AnyAcc, NoLock, Preserve)
+	{
+		Offset (0x40),
+		PMBS,	16,	// PMBASE
+		Offset (0x60),	// Interrupt Routing Registers
+		PRTA,	8,
+		PRTB,	8,
+		PRTC,	8,
+		PRTD,	8,
+		Offset (0x68),
+		PRTE,	8,
+		PRTF,	8,
+		PRTG,	8,
+		PRTH,	8,
+
+		Offset (0x80),	// IO Decode Ranges
+		IOD0,	8,
+		IOD1,	8,
+
+		Offset (0xb8),	// GPIO Routing Control
+		GR00,	 2,
+		GR01,	 2,
+		GR02,	 2,
+		GR03,	 2,
+		GR04,	 2,
+		GR05,	 2,
+		GR06,	 2,
+		GR07,	 2,
+		GR08,	 2,
+		GR09,	 2,
+		GR10,	 2,
+		GR11,	 2,
+		GR12,	 2,
+		GR13,	 2,
+		GR14,	 2,
+		GR15,	 2,
+
+		Offset (0xf0),	// RCBA
+		RCEN,	1,
+		,	13,
+		RCBA,	18,
+	}
+
+	#include "../../../southbridge/intel/bd82x6x/acpi/irqlinks.asl"
+
+	#include "acpi/ec.asl"
+
+	Device (DMAC)		// DMA Controller
+	{
+		Name(_HID, EISAID("PNP0200"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x00, 0x00, 0x01, 0x20)
+			IO (Decode16, 0x81, 0x81, 0x01, 0x11)
+			IO (Decode16, 0x93, 0x93, 0x01, 0x0d)
+			IO (Decode16, 0xc0, 0xc0, 0x01, 0x20)
+			DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 }
+		})
+	}
+
+	Device (FWH)		// Firmware Hub
+	{
+		Name (_HID, EISAID("INT0800"))
+		Name (_CRS, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xff000000, 0x01000000)
+		})
+	}
+
+	Device (HPET)
+	{
+		Name (_HID, EISAID("PNP0103"))
+		Name (_CID, 0x010CD041)
+
+		Name(BUF0, ResourceTemplate()
+		{
+			Memory32Fixed(ReadOnly, 0xfed00000, 0x400, FED0)
+		})
+
+		Method (_STA, 0)	// Device Status
+		{
+			If (HPTE) {
+				// Note: Ancient versions of Windows don't want
+				// to see the HPET in order to work right
+				If (LGreaterEqual(OSYS, 2001)) {
+					Return (0xf)	// Enable and show device
+				} Else {
+					Return (0xb)	// Enable and don't show device
+				}
+			}
+
+			Return (0x0)	// Not enabled, don't show.
+		}
+
+		Method (_CRS, 0, Serialized) // Current resources
+		{
+			If (HPTE) {
+				CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
+				If (Lequal(HPAS, 1)) {
+					Store(0xfed01000, HPT0)
+				}
+
+				If (Lequal(HPAS, 2)) {
+					Store(0xfed02000, HPT0)
+				}
+
+				If (Lequal(HPAS, 3)) {
+					Store(0xfed03000, HPT0)
+				}
+			}
+
+			Return (BUF0)
+		}
+	}
+
+	Device(PIC)	// 8259 Interrupt Controller
+	{
+		Name(_HID,EISAID("PNP0000"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x20, 0x20, 0x01, 0x02)
+			IO (Decode16, 0x24, 0x24, 0x01, 0x02)
+			IO (Decode16, 0x28, 0x28, 0x01, 0x02)
+			IO (Decode16, 0x2c, 0x2c, 0x01, 0x02)
+			IO (Decode16, 0x30, 0x30, 0x01, 0x02)
+			IO (Decode16, 0x34, 0x34, 0x01, 0x02)
+			IO (Decode16, 0x38, 0x38, 0x01, 0x02)
+			IO (Decode16, 0x3c, 0x3c, 0x01, 0x02)
+			IO (Decode16, 0xa0, 0xa0, 0x01, 0x02)
+			IO (Decode16, 0xa4, 0xa4, 0x01, 0x02)
+			IO (Decode16, 0xa8, 0xa8, 0x01, 0x02)
+			IO (Decode16, 0xac, 0xac, 0x01, 0x02)
+			IO (Decode16, 0xb0, 0xb0, 0x01, 0x02)
+			IO (Decode16, 0xb4, 0xb4, 0x01, 0x02)
+			IO (Decode16, 0xb8, 0xb8, 0x01, 0x02)
+			IO (Decode16, 0xbc, 0xbc, 0x01, 0x02)
+			IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02)
+			IRQNoFlags () { 2 }
+		})
+	}
+
+	Device(MATH)	// FPU
+	{
+		Name (_HID, EISAID("PNP0C04"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0xf0, 0xf0, 0x01, 0x01)
+			IRQNoFlags() { 13 }
+		})
+	}
+
+	Device(LDRC)	// LPC device: Resource consumption
+	{
+		Name (_HID, EISAID("PNP0C02"))
+		Name (_UID, 2)
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x2e, 0x2e, 0x1, 0x02)		// First SuperIO
+			IO (Decode16, 0x4e, 0x4e, 0x1, 0x02)		// Second SuperIO
+			IO (Decode16, 0x61, 0x61, 0x1, 0x01)		// NMI Status
+			IO (Decode16, 0x63, 0x63, 0x1, 0x01)		// CPU Reserved
+			IO (Decode16, 0x65, 0x65, 0x1, 0x01)		// CPU Reserved
+			IO (Decode16, 0x67, 0x67, 0x1, 0x01)		// CPU Reserved
+			IO (Decode16, 0x80, 0x80, 0x1, 0x01)		// Port 80 Post
+			IO (Decode16, 0x92, 0x92, 0x1, 0x01)		// CPU Reserved
+			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02)		// SWSMI
+			//IO (Decode16, 0x800, 0x800, 0x1, 0x10)		// ACPI I/O trap
+			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80)	// ICH7-M ACPI
+			IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40)	// ICH7-M GPIO
+		})
+	}
+
+	Device (RTC)	// Real Time Clock
+	{
+		Name (_HID, EISAID("PNP0B00"))
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x70, 0x70, 1, 8)
+// Disable as Windows doesn't like it, and systems don't seem to use it.
+//			IRQNoFlags() { 8 }
+		})
+	}
+
+	Device (TIMR)	// Intel 8254 timer
+	{
+		Name(_HID, EISAID("PNP0100"))
+		Name(_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
+			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
+			IRQNoFlags() {0}
+		})
+	}
+
+	#include "acpi/superio.asl"
+
+#ifdef ENABLE_TPM
+	Device (TPM)		// Trusted Platform Module
+	{
+		Name(_HID, EISAID("IFX0102"))
+		Name(_CID, 0x310cd041)
+		Name(_UID, 1)
+
+		Method(_STA, 0)
+		{
+			If (TPMP) {
+				Return (0xf)
+			}
+			Return (0x0)
+		}
+
+		Name(_CRS, ResourceTemplate() {
+			IO (Decode16, 0x2e, 0x2e, 0x01, 0x02)
+			IO (Decode16, 0x6f0, 0x6f0, 0x01, 0x10)
+			Memory32Fixed (ReadWrite, 0xfed40000, 0x5000)
+			IRQ (Edge, Activehigh, Exclusive) { 6 }
+		})
+	}
+#endif
+}
diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl
new file mode 100644
index 0000000..ad2ce42
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl
@@ -0,0 +1,269 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel Cougar Point PCH support */
+
+Scope(\)
+{
+	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
+
+	OperationRegion(IO_T, SystemIO, 0x800, 0x10)
+	Field(IO_T, ByteAcc, NoLock, Preserve)
+	{
+		Offset(0x8),
+		TRP0, 8		// IO-Trap at 0x808
+	}
+
+	// PCH Power Management Registers, located at PMBASE (0x1f.0 0x40.l)
+	OperationRegion(PMIO, SystemIO, DEFAULT_PMBASE, 0x80)
+	Field(PMIO, ByteAcc, NoLock, Preserve)
+	{
+		Offset(0x20),	// GPE0_STS
+		, 16,
+		GS00, 1,	// GPIO00 SCI/Wake Status
+		GS01, 1,	// GPIO01 SCI/Wake Status
+		GS02, 1,	// GPIO02 SCI/Wake Status
+		GS03, 1,	// GPIO03 SCI/Wake Status
+		GS04, 1,	// GPIO04 SCI/Wake Status
+		GS05, 1,	// GPIO05 SCI/Wake Status
+		GS06, 1,	// GPIO06 SCI/Wake Status
+		GS07, 1,	// GPIO07 SCI/Wake Status
+		GS08, 1,	// GPIO08 SCI/Wake Status
+		GS09, 1,	// GPIO09 SCI/Wake Status
+		GS10, 1,	// GPIO10 SCI/Wake Status
+		GS11, 1,	// GPIO11 SCI/Wake Status
+		GS12, 1,	// GPIO12 SCI/Wake Status
+		GS13, 1,	// GPIO13 SCI/Wake Status
+		GS14, 1,	// GPIO14 SCI/Wake Status
+		GS15, 1,	// GPIO15 SCI/Wake Status
+		Offset(0x28),	// GPE0_EN
+		, 16,
+		GE00, 1,	// GPIO00 SCI/Wake Enable
+		GE01, 1,	// GPIO01 SCI/Wake Enable
+		GE02, 1,	// GPIO02 SCI/Wake Enable
+		GE03, 1,	// GPIO03 SCI/Wake Enable
+		GE04, 1,	// GPIO04 SCI/Wake Enable
+		GE05, 1,	// GPIO05 SCI/Wake Enable
+		GE06, 1,	// GPIO06 SCI/Wake Enable
+		GE07, 1,	// GPIO07 SCI/Wake Enable
+		GE08, 1,	// GPIO08 SCI/Wake Enable
+		GE09, 1,	// GPIO09 SCI/Wake Enable
+		GE10, 1,	// GPIO10 SCI/Wake Enable
+		GE11, 1,	// GPIO11 SCI/Wake Enable
+		GE12, 1,	// GPIO12 SCI/Wake Enable
+		GE13, 1,	// GPIO13 SCI/Wake Enable
+		GE14, 1,	// GPIO14 SCI/Wake Enable
+		GE15, 1,	// GPIO15 SCI/Wake Enable
+		Offset(0x42),	// General Purpose Control
+		, 1,		// skip 1 bit
+		GPEC, 1,	// SWGPE_CTRL
+	}
+
+	// GPIO IO mapped registers (0x1f.0 reg 0x48.l)
+	OperationRegion(GPIO, SystemIO, DEFAULT_GPIOBASE, 0x6c)
+	Field(GPIO, ByteAcc, NoLock, Preserve)
+	{
+		Offset(0x00),	// GPIO Use Select
+		GU00, 8,
+		GU01, 8,
+		GU02, 8,
+		GU03, 8,
+		Offset(0x04),	// GPIO IO Select
+		GIO0, 8,
+		GIO1, 8,
+		GIO2, 8,
+		GIO3, 8,
+		Offset(0x0c),	// GPIO Level
+		GL00, 1,
+		GP01, 1,
+		GP02, 1,
+		GP0e, 1,
+		GP04, 1,
+		GP05, 1,
+		GP06, 1,
+		GP07, 1,
+		GP08, 1,
+		GP09, 1,
+		GP10, 1,
+		GP11, 1,
+		GP12, 1,
+		GP13, 1,
+		GP14, 1,
+		GP15, 1,
+		GP16, 1,
+		GP17, 1,
+		GP18, 1,
+		GP19, 1,
+		GP20, 1,
+		GP21, 1,
+		GP22, 1,
+		GP23, 1,
+		GP24, 1,
+		GP25, 1,
+		GP26, 1,
+		GP27, 1,
+		GP28, 1,
+		GP29, 1,
+		GP30, 1,
+		GP31, 1,
+		Offset(0x18),	// GPIO Blink
+		GB00, 8,
+		GB01, 8,
+		GB02, 8,
+		GB03, 8,
+		Offset(0x2c),	// GPIO Invert
+		GIV0, 8,
+		GIV1, 8,
+		GIV2, 8,
+		GIV3, 8,
+		Offset(0x30),	// GPIO Use Select 2
+		GU04, 8,
+		GU05, 8,
+		GU06, 8,
+		GU07, 8,
+		Offset(0x34),	// GPIO IO Select 2
+		GIO4, 8,
+		GIO5, 8,
+		GIO6, 8,
+		GIO7, 8,
+		Offset(0x38),	// GPIO Level 2
+		GP32, 1,
+		GP33, 1,
+		GP34, 1,
+		GP35, 1,
+		GP36, 1,
+		GP37, 1,
+		GP38, 1,
+		GP39, 1,
+		GP40, 1,
+		GP41, 1,
+		GP42, 1,
+		GP43, 1,
+		GP44, 1,
+		GP45, 1,
+		GP46, 1,
+		GP47, 1,
+		GP48, 1,
+		GP49, 1,
+		GP50, 1,
+		GP51, 1,
+		GP52, 1,
+		GP53, 1,
+		GP54, 1,
+		GP55, 1,
+		GP56, 1,
+		GP57, 1,
+		GP58, 1,
+		GP59, 1,
+		GP60, 1,
+		GP61, 1,
+		GP62, 1,
+		GP63, 1,
+		Offset(0x40),	// GPIO Use Select 3
+		GU08, 8,
+		GU09, 4,
+		Offset(0x44),	// GPIO IO Select 3
+		GIO8, 8,
+		GIO9, 4,
+		Offset(0x48),	// GPIO Level 3
+		GP64, 1,
+		GP65, 1,
+		GP66, 1,
+		GP67, 1,
+		GP68, 1,
+		GP69, 1,
+		GP70, 1,
+		GP71, 1,
+		GP72, 1,
+		GP73, 1,
+		GP74, 1,
+		GP75, 1,
+	}
+
+
+	// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
+	OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
+	Field(RCRB, DWordAcc, Lock, Preserve)
+	{
+		Offset(0x0000), // Backbone
+		Offset(0x1000), // Chipset
+		Offset(0x3000), // Legacy Configuration Registers
+		Offset(0x3404), // High Performance Timer Configuration
+		HPAS, 2, 	// Address Select
+		, 5,
+		HPTE, 1,	// Address Enable
+		Offset(0x3418), // FD (Function Disable)
+		, 2,		// Reserved
+		SATD, 1,	// SATA disable
+		SMBD, 1,	// SMBUS disable
+		HDAD, 1,	// Azalia disable
+		, 2,		// Reserved
+		ILND, 1,	// Internal LAN disable
+		US1D, 1,	// UHCI #1 disable
+		US2D, 1,	// UHCI #2 disable
+		US3D, 1,	// UHCI #3 disable
+		US4D, 1,	// UHCI #4 disable
+		, 2,		// Reserved
+		LPBD, 1,	// LPC bridge disable
+		EHCD, 1,	// EHCI disable
+		Offset(0x341a), // FD Root Ports
+		RP1D, 1,	// Root Port 1 disable
+		RP2D, 1,	// Root Port 2 disable
+		RP3D, 1,	// Root Port 3 disable
+		RP4D, 1		// Root Port 4 disable
+	}
+
+}
+
+// High Definition Audio (Azalia) 0:1b.0
+#include "../../../southbridge/intel/bd82x6x/acpi/audio.asl"
+
+// PCI Express Ports 0:1c.x
+#include "../../../southbridge/intel/bd82x6x/acpi/pcie.asl"
+
+// USB 0:1d.0 and 0:1a.0
+#include "../../../southbridge/intel/bd82x6x/acpi/usb.asl"
+
+// LPC Bridge 0:1f.0
+#include "../../../southbridge/intel/bd82x6x/acpi/lpc.asl"
+
+// SATA 0:1f.2, 0:1f.5
+#include "../../../southbridge/intel/bd82x6x/acpi/sata.asl"
+
+// SMBus 0:1f.3
+#include "../../../southbridge/intel/bd82x6x/acpi/smbus.asl"
+
+Method (_OSC, 4)
+{
+	/* Check for proper GUID */
+	If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+	{
+		/* Let OS control everything */
+		Return (Arg3)
+	}
+	Else
+	{
+		/* Unrecognized UUID */
+		CreateDWordField (Arg3, 0, CDW1)
+		Or (CDW1, 4, CDW1)
+		Return (Arg3)
+	}
+}
diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
new file mode 100644
index 0000000..f6b93bf
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl
@@ -0,0 +1,234 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel Cougar Point PCH PCIe support */
+
+// PCI Express Ports
+
+Device (RP01)
+{
+	NAME(_ADR, 0x001c0000) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 16 },
+				Package() { 0x0000ffff, 1, 0, 17 },
+				Package() { 0x0000ffff, 2, 0, 18 },
+				Package() { 0x0000ffff, 3, 0, 19 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP02)
+{
+	NAME(_ADR, 0x001c0001) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 17 },
+				Package() { 0x0000ffff, 1, 0, 18 },
+				Package() { 0x0000ffff, 2, 0, 19 },
+				Package() { 0x0000ffff, 3, 0, 16 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP03)
+{
+	NAME(_ADR, 0x001c0002) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 18 },
+				Package() { 0x0000ffff, 1, 0, 19 },
+				Package() { 0x0000ffff, 2, 0, 16 },
+				Package() { 0x0000ffff, 3, 0, 17 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP04)
+{
+	NAME(_ADR, 0x001c0003) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 17 },
+				Package() { 0x0000ffff, 1, 0, 18 },
+				Package() { 0x0000ffff, 2, 0, 19 },
+				Package() { 0x0000ffff, 3, 0, 16 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP05)
+{
+	NAME(_ADR, 0x001c0004) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 16 },
+				Package() { 0x0000ffff, 1, 0, 17 },
+				Package() { 0x0000ffff, 2, 0, 18 },
+				Package() { 0x0000ffff, 3, 0, 19 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP06)
+{
+	NAME(_ADR, 0x001c0005) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 17 },
+				Package() { 0x0000ffff, 1, 0, 18 },
+				Package() { 0x0000ffff, 2, 0, 19 },
+				Package() { 0x0000ffff, 3, 0, 16 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP07)
+{
+	NAME(_ADR, 0x001c0006) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 18 },
+				Package() { 0x0000ffff, 1, 0, 19 },
+				Package() { 0x0000ffff, 2, 0, 16 },
+				Package() { 0x0000ffff, 3, 0, 17 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }
+			})
+
+		}
+
+	}
+}
+
+Device (RP08)
+{
+	NAME(_ADR, 0x001c0007) // FIXME: Have a macro for PCI Devices -> ACPI notation?
+	//#include "pcie_port.asl"
+	Method(_PRT)
+	{
+		If (PICM) {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, 0, 19 },
+				Package() { 0x0000ffff, 1, 0, 16 },
+				Package() { 0x0000ffff, 2, 0, 17 },
+				Package() { 0x0000ffff, 3, 0, 18 }
+			})
+		} Else {
+			Return (Package() {
+				Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
+				Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
+				Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0 },
+				Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }
+			})
+
+		}
+
+	}
+}
+
+
diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl
new file mode 100644
index 0000000..e0c336a
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel SATA Controller 0:1f.2
+
+// Note: Some BIOSes put the S-ATA code into an SSDT to make it easily
+// pluggable
+
+Device (SATA)
+{
+	Name (_ADR, 0x001f0002)
+
+	Device (PRID)
+	{
+		Name (_ADR, 0)
+
+		// Get Timing Mode
+		Method (_GTM)
+		{
+			Name(PBUF, Buffer(20) {
+				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+				0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+				0x00,0x00,0x00,0x00 })
+
+			CreateDwordField (PBUF,  0, PIO0)
+			CreateDwordField (PBUF,  4, DMA0)
+			CreateDwordField (PBUF,  8, PIO1)
+			CreateDwordField (PBUF, 12, DMA1)
+			CreateDwordField (PBUF, 16, FLAG)
+
+			// TODO fill return structure
+
+			Return (PBUF)
+		}
+
+		// Set Timing Mode
+		Method (_STM, 3)
+		{
+			CreateDwordField (Arg0,  0, PIO0)
+			CreateDwordField (Arg0,  4, DMA0)
+			CreateDwordField (Arg0,  8, PIO1)
+			CreateDwordField (Arg0, 12, DMA1)
+			CreateDwordField (Arg0, 16, FLAG)
+
+			// TODO: Do the deed
+		}
+
+		Device (DSK0)
+		{
+			Name (_ADR, 0)
+			// TODO: _RMV ?
+			// TODO: _GTF ?
+		}
+
+		Device (DSK1)
+		{
+			Name (_ADR, 1)
+
+			// TODO: _RMV ?
+			// TODO: _GTF ?
+		}
+
+	}
+}
+
diff --git a/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl b/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl
new file mode 100644
index 0000000..06bfcb6
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/sleepstates.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+Name(\_S0, Package(){0x0,0x0,0x0,0x0})
+// Name(\_S1, Package(){0x1,0x1,0x0,0x0})
+Name(\_S3, Package(){0x5,0x5,0x0,0x0})
+Name(\_S4, Package(){0x6,0x6,0x0,0x0})
+Name(\_S5, Package(){0x7,0x7,0x0,0x0})
+
diff --git a/src/southbridge/intel/bd82x6x/acpi/smbus.asl b/src/southbridge/intel/bd82x6x/acpi/smbus.asl
new file mode 100644
index 0000000..4409308
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/smbus.asl
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+// Intel SMBus Controller 0:1f.3
+
+Device (SBUS)
+{
+	Name (_ADR, 0x001f0003)
+
+#ifdef ENABLE_SMBUS_METHODS
+	OperationRegion (SMBP, PCI_Config, 0x00, 0x100)
+	Field(SMBP, DWordAcc, NoLock, Preserve)
+	{
+		Offset(0x40),
+		,	2,
+		I2CE,	1
+	}
+
+	OperationRegion (SMBI, SystemIO, SMBUS_IO_BASE, 0x20)
+	Field (SMBI, ByteAcc, NoLock, Preserve)
+	{
+		HSTS,	8,	// Host Status
+		,	8,
+		HCNT,	8,	// Host Control
+		HCMD,	8,	// Host Command
+		TXSA,	8,	// Transmit Slave Address
+		DAT0,	8,	// Host Data 0
+		DAT1,	8,	// Host Data 1
+		HBDB,	8,	// Host Block Data Byte
+		PECK,	8,	// Packet Error Check
+		RXSA,	8,	// Receive Slave Address
+		RXDA,	16,	// Receive Slave Data
+		AUXS,	8,	// Auxiliary Status
+		AUXC,	8,	// Auxiliary Control
+		SLPC,	8,	// SMLink Pin Control
+		SBPC,	8,	// SMBus Pin Control
+		SSTS,	8,	// Slave Status
+		SCMD,	8,	// Slave Command
+		NADR,	8,	// Notify Device Address
+		NDLB,	8,	// Notify Data Low Byte
+		NDLH,	8,	// Notify Data High Byte
+	}
+
+	// Kill all SMBus communication
+	Method (KILL, 0, Serialized)
+	{
+		Or (HCNT, 0x02, HCNT)	// Send Kill
+		Or (HSTS, 0xff, HSTS)	// Clean Status
+	}
+
+	// Check if last operation completed
+	// return	Failure = 0, Success = 1
+	Method (CMPL, 0, Serialized)
+	{
+		Store (4000, Local0)		// Timeout 200ms in 50us steps
+		While (Local0) {
+			If (And(HSTS, 0x02)) {	// Completion Status?
+				Return (1)	// Operation Completed
+			} Else {
+				Stall (50)
+				Decrement (Local0)
+				If (LEqual(Local0, 0)) {
+					KILL()
+				}
+			}
+		}
+
+		Return (0)		//  Failure
+	}
+
+
+	// Wait for SMBus to become ready
+	Method (SRDY, 0, Serialized)
+	{
+		Store (200, Local0)	// Timeout 200ms
+		While (Local0) {
+			If (And(HSTS, 0x40)) {		// IN_USE?
+				Sleep(1)		// Wait 1ms
+				Decrement(Local0)	// timeout--
+				If (LEqual(Local0, 0)) {
+					Return (1)
+				}
+			} Else {
+				Store (0, Local0)	// We're ready
+			}
+		}
+
+		Store (4000, Local0)	// Timeout 200ms (50us * 4000)
+		While (Local0) {
+			If (And (HSTS, 0x01)) {		// Host Busy?
+				Stall(50)		// Wait 50us
+				Decrement(Local0)	// timeout--
+				If (LEqual(Local0, 0)) {
+					KILL()
+				}
+			} Else {
+				Return (0)		// Success
+			}
+		}
+
+		Return (1)		// Failure
+	}
+
+	// SMBus Send Byte
+	// Arg0:	Address
+	// Arg1:	Data
+	// Return:	1 = Success, 0=Failure
+
+	Method (SSXB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0)
+		}
+
+		// Send Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Arg0, TXSA)	// Write Address
+		Store (Arg1, HCMD)	// Write Data
+
+		Store (0x48, HCNT)	// Start + Byte Data Protocol
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (1)		// Success
+		}
+
+		Return (0)
+	}
+
+
+	// SMBus Receive Byte
+	// Arg0:	Address
+	// Return:	0xffff = Failure, Data (8bit) = Success
+
+	Method (SRXB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0xffff)
+		}
+
+		// Receive Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Or (Arg0, 1), TXSA)	// Write Address
+
+		Store (0x44, HCNT)	// Start
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (DAT0)		// Success
+		}
+
+		Return (0xffff)
+	}
+
+
+	// SMBus Write Byte
+	// Arg0:	Address
+	// Arg1:	Command
+	// Arg2:	Data
+	// Return:	1 = Success, 0=Failure
+
+	Method (SWRB, 3, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0)
+		}
+
+		// Send Byte
+		Store (0, I2CE)		// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Arg0, TXSA)	// Write Address
+		Store (Arg1, HCMD)	// Write Command
+		Store (Arg2, DAT0)	// Write Data
+
+		Store (0x48, HCNT)	// Start + Byte Protocol
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (1)		// Success
+		}
+
+		Return (0)
+	}
+
+
+	// SMBus Read Byte
+	// Arg0:	Address
+	// Arg1:	Command
+	// Return:	0xffff = Failure, Data (8bit) = Success
+
+	Method (SRDB, 2, Serialized)
+	{
+
+		// Is the SMBus Controller Ready?
+		If (SRDY()) {
+			Return (0xffff)
+		}
+
+		// Receive Byte
+		Store (0, I2CE)			// SMBus Enable
+		Store (0xbf, HSTS)
+		Store (Or (Arg0, 1), TXSA)	// Write Address
+		Store (Arg1, HCMD)		// Command
+
+		Store (0x48, HCNT)		// Start
+
+		If (CMPL()) {
+			Or (HSTS, 0xff, HSTS)	// Clean up
+			Return (DAT0)		// Success
+		}
+
+		Return (0xffff)
+	}
+#endif
+}
+
diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl
new file mode 100644
index 0000000..cf3e6a0
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/* Intel Cougar Point USB support */
+
+// EHCI Controller 0:1d.0
+
+Device (EHC1)
+{
+	Name(_ADR, 0x001d0000)
+
+	Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+
+	Device (HUB7)
+	{
+		Name (_ADR, 0x00000000)
+
+		// How many are there?
+		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
+		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
+		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
+		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
+		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
+		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+	}
+}
+
+// EHCI #2 Controller 0:1a.0
+
+Device (EHC2)
+{
+	Name(_ADR, 0x001a0000)
+
+	Name (_PRW, Package(){ 13, 4 }) // Power Resources for Wake
+
+	// Leave USB ports on for to allow Wake from USB
+
+	Method(_S3D,0)	// Highest D State in S3 State
+	{
+		Return (2)
+	}
+
+	Method(_S4D,0)	// Highest D State in S4 State
+	{
+		Return (2)
+	}
+
+	Device (HUB7)
+	{
+		Name (_ADR, 0x00000000)
+
+		// How many are there?
+		Device (PRT1) { Name (_ADR, 1) } // USB Port 0
+		Device (PRT2) { Name (_ADR, 2) } // USB Port 1
+		Device (PRT3) { Name (_ADR, 3) } // USB Port 2
+		Device (PRT4) { Name (_ADR, 4) } // USB Port 3
+		Device (PRT5) { Name (_ADR, 5) } // USB Port 4
+		Device (PRT6) { Name (_ADR, 6) } // USB Port 5
+	}
+}
+
diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c
new file mode 100644
index 0000000..46bf82c
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/azalia.c
@@ -0,0 +1,361 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include <delay.h>
+#include "pch.h"
+
+#define HDA_ICII_REG 0x68
+#define   HDA_ICII_BUSY (1 << 0)
+#define   HDA_ICII_VALID  (1 << 1)
+
+typedef struct southbridge_intel_bd82x6x_config config_t;
+
+static int set_bits(u32 port, u32 mask, u32 val)
+{
+	u32 reg32;
+	int count;
+
+	/* Write (val & mask) to port */
+	val &= mask;
+	reg32 = read32(port);
+	reg32 &= ~mask;
+	reg32 |= val;
+	write32(port, reg32);
+
+	/* Wait for readback of register to
+	 * match what was just written to it
+	 */
+	count = 50;
+	do {
+		/* Wait 1ms based on BKDG wait time */
+		mdelay(1);
+		reg32 = read32(port);
+		reg32 &= mask;
+	} while ((reg32 != val) && --count);
+
+	/* Timeout occurred */
+	if (!count)
+		return -1;
+	return 0;
+}
+
+static int codec_detect(u32 base)
+{
+	u8 reg8;
+
+	/* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */
+	if (set_bits(base + 0x08, 1, 1) == -1)
+		goto no_codec;
+
+	/* Write back the value once reset bit is set. */
+	write16(base + 0x0, read16(base + 0x0));
+
+	/* Read in Codec location (BAR + 0xe)[2..0]*/
+	reg8 = read8(base + 0xe);
+	reg8 &= 0x0f;
+	if (!reg8)
+		goto no_codec;
+
+	return reg8;
+
+no_codec:
+	/* Codec Not found */
+	/* Put HDA back in reset (BAR + 0x8) [0] */
+	set_bits(base + 0x08, 1, 0);
+	printk(BIOS_DEBUG, "Azalia: No codec!\n");
+	return 0;
+}
+
+const u32 * cim_verb_data = NULL;
+u32 cim_verb_data_size = 0;
+
+static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb)
+{
+	int idx=0;
+
+	while (idx < (cim_verb_data_size / sizeof(u32))) {
+		u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32
+		if (cim_verb_data[idx] != viddid) {
+			idx += verb_size + 3; // skip verb + header
+			continue;
+		}
+		*verb = &cim_verb_data[idx+3];
+		return verb_size;
+	}
+
+	/* Not all codecs need to load another verb */
+	return 0;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate it is ready
+ *  no response would imply that the codec is non-operative
+ */
+
+static int wait_for_ready(u32 base)
+{
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+
+	while(timeout--) {
+		u32 reg32 = read32(base +  HDA_ICII_REG);
+		if (!(reg32 & HDA_ICII_BUSY))
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+/**
+ *  Wait 50usec for the codec to indicate that it accepted
+ *  the previous command.  No response would imply that the code
+ *  is non-operative
+ */
+
+static int wait_for_valid(u32 base)
+{
+	u32 reg32;
+
+	/* Send the verb to the codec */
+	reg32 = read32(base + HDA_ICII_REG);
+	reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID;
+	write32(base + HDA_ICII_REG, reg32);
+
+	/* Use a 50 usec timeout - the Linux kernel uses the
+	 * same duration */
+
+	int timeout = 50;
+	while(timeout--) {
+		reg32 = read32(base + HDA_ICII_REG);
+		if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
+			HDA_ICII_VALID)
+			return 0;
+		udelay(1);
+	}
+
+	return -1;
+}
+
+static void codec_init(struct device *dev, u32 base, int addr)
+{
+	u32 reg32;
+	const u32 *verb;
+	u32 verb_size;
+	int i;
+
+	printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr);
+
+	/* 1 */
+	if (wait_for_ready(base) == -1) {
+		printk(BIOS_DEBUG, "  codec not ready.\n");
+		return;
+	}
+
+	reg32 = (addr << 28) | 0x000f0000;
+	write32(base + 0x60, reg32);
+
+	if (wait_for_valid(base) == -1) {
+		printk(BIOS_DEBUG, "  codec not valid.\n");
+		return;
+	}
+
+	reg32 = read32(base + 0x64);
+
+	/* 2 */
+	printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32);
+	verb_size = find_verb(dev, reg32, &verb);
+
+	if (!verb_size) {
+		printk(BIOS_DEBUG, "Azalia: No verb!\n");
+		return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size);
+
+	/* 3 */
+	for (i = 0; i < verb_size; i++) {
+		if (wait_for_ready(base) == -1)
+			return;
+
+		write32(base + 0x60, verb[i]);
+
+		if (wait_for_valid(base) == -1)
+			return;
+	}
+	printk(BIOS_DEBUG, "Azalia: verb loaded.\n");
+}
+
+static void codecs_init(struct device *dev, u32 base, u32 codec_mask)
+{
+	int i;
+	for (i = 3; i >= 0; i--) {
+		if (codec_mask & (1 << i))
+			codec_init(dev, base, i);
+	}
+}
+
+static void azalia_init(struct device *dev)
+{
+	u32 base;
+	struct resource *res;
+	u32 codec_mask;
+	u8 reg8;
+	u16 reg16;
+	u32 reg32;
+
+	/* Find base address */
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!res)
+		return;
+
+	// NOTE this will break as soon as the Azalia get's a bar above
+	// 4G. Is there anything we can do about it?
+	base = (u32)res->base;
+	printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base);
+
+	if (RCBA32(0x2030) & (1 << 31)) {
+		reg32 = pci_mmio_read_config32(dev, 0x120);
+		reg32 &= 0xf8ffff01;
+		reg32 |= (1 << 24); // 25 for server
+		reg32 |= RCBA32(0x2030) & 0xfe;
+		pci_mmio_write_config32(dev, 0x120, reg32);
+
+		reg16 = pci_mmio_read_config16(dev, 0x78);
+		reg16 &= ~(1 << 11);
+		pci_mmio_write_config16(dev, 0x78, reg16);
+	} else
+		printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n");
+
+	reg32 = pci_mmio_read_config32(dev, 0x114);
+	reg32 &= ~0xfe;
+	pci_mmio_write_config32(dev, 0x114, reg32);
+
+	// Set VCi enable bit
+	if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) |
+						(1 << 25) | (1 << 26))) {
+		reg32 = pci_mmio_read_config32(dev, 0x120);
+		reg32 |= (1 << 31);
+		pci_mmio_write_config32(dev, 0x120, reg32);
+	}
+
+	// Enable HDMI codec:
+	reg32 = pci_read_config32(dev, 0xc4);
+	reg32 |= (1 << 1);
+	pci_write_config32(dev, 0xc4, reg32);
+
+	reg8 = pci_read_config8(dev, 0x43);
+	reg8 |= (1 << 6);
+	pci_write_config8(dev, 0x43, reg8);
+
+	/* Additional programming steps */
+	reg32 = pci_read_config32(dev, 0xc4);
+	reg32 |= (1 << 13) | (1 << 10);
+	pci_write_config32(dev, 0xc4, reg32);
+
+	reg32 = pci_read_config32(dev, 0xd0);
+	reg32 &= ~(1 << 31);
+	pci_write_config32(dev, 0xd0, reg32);
+
+	/* Additional programming steps */
+	reg32 = pci_read_config32(dev, 0xc4);
+	reg32 |= (1 << 13);
+	pci_write_config32(dev, 0xc4, reg32);
+
+	reg32 = pci_read_config32(dev, 0xc4);
+	reg32 |= (1 << 10);
+	pci_write_config32(dev, 0xc4, reg32);
+
+	reg32 = pci_read_config32(dev, 0xd0);
+	reg32 &= ~(1 << 31);
+	pci_write_config32(dev, 0xd0, reg32);
+
+	/* Set Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
+
+	pci_write_config8(dev, 0x3c, 0x0a); // unused?
+
+	/* Codec Initialization Programming Sequence */
+	reg32 = read32(base + 0x08);
+	reg32 |= (1 << 0);
+	write32(base + 0x08, reg32);
+
+	//
+	reg8 = pci_read_config8(dev, 0x40); // Audio Control
+	reg8 |= 1; // Select Azalia mode. This needs to be controlled via devicetree.cb
+	pci_write_config8(dev, 0x40, reg8);
+
+	reg8 = pci_read_config8(dev, 0x4d); // Docking Status
+	reg8 &= ~(1 << 7); // Docking not supported
+	pci_write_config8(dev, 0x4d, reg8);
+
+	codec_mask = codec_detect(base);
+
+	if (codec_mask) {
+		printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask);
+		codecs_init(dev, base, codec_mask);
+	}
+
+	/* Enable dynamic clock gating */
+	reg8 = pci_read_config8(dev, 0x43);
+	reg8 &= ~0x7;
+	reg8 |= (1 << 2) | (1 << 0);
+	pci_write_config8(dev, 0x43, reg8);
+}
+
+static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations azalia_pci_ops = {
+	.set_subsystem    = azalia_set_subsystem,
+};
+
+static struct device_operations azalia_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= azalia_init,
+	.scan_bus		= 0,
+	.ops_pci		= &azalia_pci_ops,
+};
+
+static const struct pci_driver azalia __pci_driver = {
+	.ops	= &azalia_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c20,
+};
+
diff --git a/src/southbridge/intel/bd82x6x/bootblock.c b/src/southbridge/intel/bd82x6x/bootblock.c
new file mode 100644
index 0000000..bc8f32c
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/bootblock.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "pch.h"
+
+static void store_initial_timestamp(void)
+{
+	/* On Cougar Point we have two 32bit scratchpad registers available:
+	 * D0:F0  0xdc (SKPAD)
+	 * D31:F2 0xd0 (SATA SP)
+	 */
+	tsc_t tsc = rdtsc();
+	pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo);
+	pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi);
+}
+
+/*
+ * Enable Prefetching and Caching. 
+ */
+static void enable_spi_prefetch(void)
+{
+	u8 reg8;
+	device_t dev;
+
+	dev = PCI_DEV(0, 0x1f, 0);
+
+	reg8 = pci_read_config8(dev, 0xdc);
+	reg8 &= ~(3 << 2);
+	reg8 |= (2 << 2); /* Prefetching and Caching Enabled */
+	pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void enable_port80_on_lpc(void)
+{
+	device_t dev = PCI_DEV(0, 0x1f, 0);
+
+	/* Enable port 80 POST on LPC */
+	pci_write_config32(dev, RCBA, DEFAULT_RCBA | 1);
+#if 0
+	RCBA32(GCS) &= (~0x04);
+#else
+	volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS);
+	u32 reg32 = *gcs;
+	reg32 = reg32 & ~0x04;
+	*gcs = reg32;
+	post_code(0x01);
+#endif
+}
+
+static void bootblock_southbridge_init(void)
+{
+#if CONFIG_COLLECT_TIMESTAMPS
+	store_initial_timestamp();
+#endif
+	enable_spi_prefetch();
+	enable_port80_on_lpc();
+}
diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
new file mode 100644
index 0000000..2786d72
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
+#define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H
+
+struct southbridge_intel_bd82x6x_config {
+	/**
+	 * Interrupt Routing configuration
+	 * If bit7 is 1, the interrupt is disabled.
+	 */
+	uint8_t pirqa_routing;
+	uint8_t pirqb_routing;
+	uint8_t pirqc_routing;
+	uint8_t pirqd_routing;
+	uint8_t pirqe_routing;
+	uint8_t pirqf_routing;
+	uint8_t pirqg_routing;
+	uint8_t pirqh_routing;
+
+	/**
+	 * GPI Routing configuration
+	 *
+	 * Only the lower two bits have a meaning:
+	 * 00: No effect
+	 * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+	 * 10: SCI (if corresponding GPIO_EN bit is also set)
+	 * 11: reserved
+	 */
+	uint8_t gpi0_routing;
+	uint8_t gpi1_routing;
+	uint8_t gpi2_routing;
+	uint8_t gpi3_routing;
+	uint8_t gpi4_routing;
+	uint8_t gpi5_routing;
+	uint8_t gpi6_routing;
+	uint8_t gpi7_routing;
+	uint8_t gpi8_routing;
+	uint8_t gpi9_routing;
+	uint8_t gpi10_routing;
+	uint8_t gpi11_routing;
+	uint8_t gpi12_routing;
+	uint8_t gpi13_routing;
+	uint8_t gpi14_routing;
+	uint8_t gpi15_routing;
+
+	uint32_t gpe0_en;
+	uint16_t alt_gp_smi_en;
+
+	/* IDE configuration */
+	uint32_t ide_legacy_combined;
+	uint32_t sata_ahci;
+	uint8_t sata_port_map;
+
+	uint32_t gen1_dec;
+	uint32_t gen2_dec;
+	uint32_t gen3_dec;
+	uint32_t gen4_dec;
+};
+
+extern struct chip_operations southbridge_intel_bd82x6x_ops;
+
+#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H */
diff --git a/src/southbridge/intel/bd82x6x/early_me.c b/src/southbridge/intel/bd82x6x/early_me.c
new file mode 100644
index 0000000..5b266cc
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/early_me.c
@@ -0,0 +1,201 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include "me.h"
+#include "pch.h"
+
+static const char *me_ack_values[] = {
+	[ME_HFS_ACK_NO_DID]	= "No DID Ack received",
+	[ME_HFS_ACK_RESET]	= "Non-power cycle reset",
+	[ME_HFS_ACK_PWR_CYCLE]	= "Power cycle reset",
+	[ME_HFS_ACK_S3]		= "Go to S3",
+	[ME_HFS_ACK_S4]		= "Go to S4",
+	[ME_HFS_ACK_S5]		= "Go to S5",
+	[ME_HFS_ACK_GBL_RESET]	= "Global Reset",
+	[ME_HFS_ACK_CONTINUE]	= "Continue to boot"
+};
+
+static inline void pci_read_dword_ptr(void *ptr, int offset)
+{
+	u32 dword = pci_read_config32(PCH_ME_DEV, offset);
+	memcpy(ptr, &dword, sizeof(dword));
+}
+
+static inline void pci_write_dword_ptr(void *ptr, int offset)
+{
+	u32 dword = 0;
+	memcpy(&dword, ptr, sizeof(dword));
+	pci_write_config32(PCH_ME_DEV, offset, dword);
+}
+
+void intel_early_me_status(void)
+{
+	struct me_hfs hfs;
+	struct me_gmes gmes;
+
+	pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+	pci_read_dword_ptr(&gmes, PCI_ME_GMES);
+
+	intel_me_status(&hfs, &gmes);
+}
+
+int intel_early_me_init(void)
+{
+	int count;
+	struct me_uma uma;
+	struct me_hfs hfs;
+
+	printk(BIOS_INFO, "Intel ME early init\n");
+
+	/* Wait for ME UMA SIZE VALID bit to be set */
+	for (count = ME_RETRY; count > 0; --count) {
+		pci_read_dword_ptr(&uma, PCI_ME_UMA);
+		if (uma.valid)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!count) {
+		printk(BIOS_ERR, "ERROR: ME is not ready!\n");
+		return -1;
+	}
+
+	/* Check for valid firmware */
+	pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+	if (hfs.fpt_bad) {
+		printk(BIOS_WARNING, "WARNING: ME has bad firmware\n");
+		return -1;
+	}
+
+	printk(BIOS_INFO, "Intel ME firmware is ready\n");
+	return 0;
+}
+
+int intel_early_me_uma_size(void)
+{
+	struct me_uma uma;
+
+	pci_read_dword_ptr(&uma, PCI_ME_UMA);
+	if (uma.valid) {
+		printk(BIOS_DEBUG, "ME: Requested %uMB UMA\n", uma.size);
+		return uma.size;
+	}
+
+	printk(BIOS_DEBUG, "ME: Invalid UMA size\n");
+	return 0;
+}
+
+static inline void set_global_reset(int enable)
+{
+	u32 etr3 = pci_read_config32(PCH_LPC_DEV, ETR3);
+
+	/* Clear CF9 Without Resume Well Reset Enable */
+	etr3 &= ~ETR3_CWORWRE;
+
+	/* CF9GR indicates a Global Reset */
+	if (enable)
+		etr3 |= ETR3_CF9GR;
+	else
+		etr3 &= ~ETR3_CF9GR;
+
+	pci_write_config32(PCH_LPC_DEV, ETR3, etr3);
+}
+
+int intel_early_me_init_done(u8 status)
+{
+	u8 reset;
+	int count;
+	u32 mebase_l, mebase_h;
+	struct me_hfs hfs;
+	struct me_did did = {
+		.init_done = ME_INIT_DONE,
+		.status = status
+	};
+
+	/* MEBASE from MESEG_BASE[35:20] */
+	mebase_l = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_L);
+	mebase_h = pci_read_config32(PCI_CPU_DEVICE, PCI_CPU_MEBASE_H) & 0xf;
+	did.uma_base = (mebase_l >> 20) | (mebase_h << 12);
+
+	/* Send message to ME */
+	printk(BIOS_DEBUG, "ME: Sending Init Done with status: %d, "
+	       "UMA base: 0x%04x\n", status, did.uma_base);
+
+	pci_write_dword_ptr(&did, PCI_ME_H_GS);
+
+	/* Must wait for ME acknowledgement */
+	for (count = ME_RETRY; count > 0; --count) {
+		pci_read_dword_ptr(&hfs, PCI_ME_HFS);
+		if (hfs.bios_msg_ack)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!count) {
+		printk(BIOS_ERR, "ERROR: ME failed to respond\n");
+		return -1;
+	}
+
+	/* Return the requested BIOS action */
+	printk(BIOS_NOTICE, "ME: Requested BIOS Action: %s\n",
+	       me_ack_values[hfs.ack_data]);
+
+	/* Check status after acknowledgement */
+	intel_early_me_status();
+
+	reset = 0;
+	switch (hfs.ack_data) {
+	case ME_HFS_ACK_CONTINUE:
+		/* Continue to boot */
+		return 0;
+	case ME_HFS_ACK_RESET:
+		/* Non-power cycle reset */
+		set_global_reset(0);
+		reset = 0x06;
+		break;
+	case ME_HFS_ACK_PWR_CYCLE:
+		/* Power cycle reset */
+		set_global_reset(0);
+		reset = 0x0e;
+		break;
+	case ME_HFS_ACK_GBL_RESET:
+		/* Global reset */
+		set_global_reset(1);
+		reset = 0x0e;
+		break;
+	case ME_HFS_ACK_S3:
+	case ME_HFS_ACK_S4:
+	case ME_HFS_ACK_S5:
+		break;
+	}
+
+	/* Perform the requested reset */
+	if (reset) {
+		outb(reset, 0xcf9);
+		hlt();
+	}
+	return -1;
+}
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
new file mode 100644
index 0000000..b13369a
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include "pch.h"
+#include "smbus.h"
+
+void enable_smbus(void)
+{
+	device_t dev;
+
+	/* Set the SMBus device statically. */
+	dev = PCI_DEV(0x0, 0x1f, 0x3);
+
+	/* Check to make sure we've got the right device. */
+	if (pci_read_config16(dev, 0x0) != 0x8086) {
+		die("SMBus controller not found!");
+	}
+
+	/* Set SMBus I/O base. */
+	pci_write_config32(dev, SMB_BASE,
+			   SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+	/* Set SMBus enable. */
+	pci_write_config8(dev, HOSTC, HST_EN);
+
+	/* Set SMBus I/O space enable. */
+	pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+	/* Disable interrupt generation. */
+	outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+	/* Clear any lingering errors, so transactions can run. */
+	outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+	print_debug("SMBus controller enabled.\n");
+}
+
+int smbus_read_byte(unsigned device, unsigned address)
+{
+	return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}
+
diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c
new file mode 100644
index 0000000..95906e3
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/early_usb.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include "pch.h"
+
+#define PCH_EHCI1_TEMP_BAR0 0xe8000000
+#define PCH_EHCI2_TEMP_BAR0 0xe8000400
+
+/*
+ * Setup USB controller MMIO BAR to prevent the
+ * reference code from resetting the controller.
+ *
+ * The BAR will be re-assigned during device
+ * enumeration so these are only temporary.
+ */
+void enable_usb_bar(void)
+{
+	device_t usb0 = PCH_EHCI1_DEV;
+	device_t usb1 = PCH_EHCI2_DEV;
+	u32 cmd;
+
+	/* USB Controller 1 */
+	pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+			   PCH_EHCI1_TEMP_BAR0);
+	cmd = pci_read_config32(usb0, PCI_COMMAND);
+	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config32(usb0, PCI_COMMAND, cmd);
+
+	/* USB Controller 1 */
+	pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+			   PCH_EHCI1_TEMP_BAR0);
+	cmd = pci_read_config32(usb1, PCI_COMMAND);
+	cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config32(usb1, PCI_COMMAND, cmd);
+}
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c
new file mode 100644
index 0000000..ed1ebf7
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/finalize.c
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <northbridge/intel/sandybridge/pcie_config.c>
+#include "pch.h"
+
+void intel_pch_finalize_smm(void)
+{
+	/* Set SPI opcode menu */
+	RCBA16(0x3894) = SPI_OPPREFIX;
+	RCBA16(0x3896) = SPI_OPTYPE;
+	RCBA32(0x3898) = SPI_OPMENU_LOWER;
+	RCBA32(0x389c) = SPI_OPMENU_UPPER;
+
+	/* Lock SPIBAR */
+	RCBA32_OR(0x3804, (1 << 15));
+
+	/* TCLOCKDN: TC Lockdown */
+	RCBA32_OR(0x0050, (1 << 31));
+
+	/* BIOS Interface Lockdown */
+	RCBA32_OR(0x3410, (1 << 0));
+
+	/* Function Disable SUS Well Lockdown */
+	RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7));
+
+	/* Global SMI Lock */
+	pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4);
+
+	/* GEN_PMCON Lock */
+	pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2));
+
+	/* R/WO registers */
+	RCBA32(0x21a4) = RCBA32(0x21a4);
+	pcie_write_config32(PCI_DEV(0, 27, 0), 0x74,
+		    pcie_read_config32(PCI_DEV(0, 27, 0), 0x74));
+}
diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c
new file mode 100644
index 0000000..598726a
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/gpio.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#include "pch.h"
+#include "gpio.h"
+
+void setup_pch_gpios(const struct pch_gpio_map *gpio)
+{
+	u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+
+	/* GPIO Set 1 */
+	if (gpio->set1.level)
+		outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL);
+	if (gpio->set1.mode)
+		outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+	if (gpio->set1.direction)
+		outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL);
+	if (gpio->set1.reset)
+		outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+	if (gpio->set1.invert)
+		outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV);
+	if (gpio->set1.blink)
+		outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+	/* GPIO Set 2 */
+	if (gpio->set2.level)
+		outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2);
+	if (gpio->set2.mode)
+		outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+	if (gpio->set2.direction)
+		outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+	if (gpio->set2.reset)
+		outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+	/* GPIO Set 3 */
+	if (gpio->set3.level)
+		outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3);
+	if (gpio->set3.mode)
+		outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+	if (gpio->set3.direction)
+		outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+	if (gpio->set3.reset)
+		outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}
diff --git a/src/southbridge/intel/bd82x6x/gpio.h b/src/southbridge/intel/bd82x6x/gpio.h
new file mode 100644
index 0000000..214947f
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/gpio.h
@@ -0,0 +1,153 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef INTEL_BD82X6X_GPIO_H
+#define INTEL_BD82X6X_GPIO_H
+
+#define GPIO_MODE_NATIVE	0
+#define GPIO_MODE_GPIO		1
+#define GPIO_MODE_NONE		1
+
+#define GPIO_DIR_OUTPUT		0
+#define GPIO_DIR_INPUT		1
+
+#define GPIO_NO_INVERT		0
+#define GPIO_INVERT		1
+
+#define GPIO_LEVEL_LOW		0
+#define GPIO_LEVEL_HIGH		1
+
+#define GPIO_NO_BLINK		0
+#define GPIO_BLINK		1
+
+#define GPIO_RESET_PWROK	0
+#define GPIO_RESET_RSMRST	1
+
+struct pch_gpio_set1 {
+	u32 gpio0 : 1;
+	u32 gpio1 : 1;
+	u32 gpio2 : 1;
+	u32 gpio3 : 1;
+	u32 gpio4 : 1;
+	u32 gpio5 : 1;
+	u32 gpio6 : 1;
+	u32 gpio7 : 1;
+	u32 gpio8 : 1;
+	u32 gpio9 : 1;
+	u32 gpio10 : 1;
+	u32 gpio11 : 1;
+	u32 gpio12 : 1;
+	u32 gpio13 : 1;
+	u32 gpio14 : 1;
+	u32 gpio15 : 1;
+	u32 gpio16 : 1;
+	u32 gpio17 : 1;
+	u32 gpio18 : 1;
+	u32 gpio19 : 1;
+	u32 gpio20 : 1;
+	u32 gpio21 : 1;
+	u32 gpio22 : 1;
+	u32 gpio23 : 1;
+	u32 gpio24 : 1;
+	u32 gpio25 : 1;
+	u32 gpio26 : 1;
+	u32 gpio27 : 1;
+	u32 gpio28 : 1;
+	u32 gpio29 : 1;
+	u32 gpio30 : 1;
+	u32 gpio31 : 1;
+} __attribute__ ((packed));
+
+struct pch_gpio_set2 {
+	u32 gpio32 : 1;
+	u32 gpio33 : 1;
+	u32 gpio34 : 1;
+	u32 gpio35 : 1;
+	u32 gpio36 : 1;
+	u32 gpio37 : 1;
+	u32 gpio38 : 1;
+	u32 gpio39 : 1;
+	u32 gpio40 : 1;
+	u32 gpio41 : 1;
+	u32 gpio42 : 1;
+	u32 gpio43 : 1;
+	u32 gpio44 : 1;
+	u32 gpio45 : 1;
+	u32 gpio46 : 1;
+	u32 gpio47 : 1;
+	u32 gpio48 : 1;
+	u32 gpio49 : 1;
+	u32 gpio50 : 1;
+	u32 gpio51 : 1;
+	u32 gpio52 : 1;
+	u32 gpio53 : 1;
+	u32 gpio54 : 1;
+	u32 gpio55 : 1;
+	u32 gpio56 : 1;
+	u32 gpio57 : 1;
+	u32 gpio58 : 1;
+	u32 gpio59 : 1;
+	u32 gpio60 : 1;
+	u32 gpio61 : 1;
+	u32 gpio62 : 1;
+	u32 gpio63 : 1;
+} __attribute__ ((packed));
+
+struct pch_gpio_set3 {
+	u32 gpio64 : 1;
+	u32 gpio65 : 1;
+	u32 gpio66 : 1;
+	u32 gpio67 : 1;
+	u32 gpio68 : 1;
+	u32 gpio69 : 1;
+	u32 gpio70 : 1;
+	u32 gpio71 : 1;
+	u32 gpio72 : 1;
+	u32 gpio73 : 1;
+	u32 gpio74 : 1;
+	u32 gpio75 : 1;
+} __attribute__ ((packed));
+
+struct pch_gpio_map {
+	struct {
+		const struct pch_gpio_set1 *mode;
+		const struct pch_gpio_set1 *direction;
+		const struct pch_gpio_set1 *level;
+		const struct pch_gpio_set1 *reset;
+		const struct pch_gpio_set1 *invert;
+		const struct pch_gpio_set1 *blink;
+	} set1;
+	struct {
+		const struct pch_gpio_set2 *mode;
+		const struct pch_gpio_set2 *direction;
+		const struct pch_gpio_set2 *level;
+		const struct pch_gpio_set2 *reset;
+	} set2;
+	struct {
+		const struct pch_gpio_set3 *mode;
+		const struct pch_gpio_set3 *direction;
+		const struct pch_gpio_set3 *level;
+		const struct pch_gpio_set3 *reset;
+	} set3;
+};
+
+/* Configure GPIOs with mainboard provided settings */
+void setup_pch_gpios(const struct pch_gpio_map *gpio);
+
+#endif
diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
new file mode 100644
index 0000000..2752992
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -0,0 +1,671 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <pc80/mc146818rtc.h>
+#include <pc80/isa-dma.h>
+#include <pc80/i8259.h>
+#include <arch/io.h>
+#include <arch/ioapic.h>
+#include <arch/acpi.h>
+#include <cpu/cpu.h>
+#include "pch.h"
+
+#define NMI_OFF	0
+
+#define ENABLE_ACPI_MODE_IN_COREBOOT	0
+#define TEST_SMM_FLASH_LOCKDOWN		0
+
+typedef struct southbridge_intel_bd82x6x_config config_t;
+
+static void pch_enable_apic(struct device *dev)
+{
+	int i;
+	u32 reg32;
+	volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
+	volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
+
+	/* Enable ACPI I/O and power management.
+	 * Set SCI IRQ to IRQ9
+	 */
+	pci_write_config8(dev, ACPI_CNTL, 0x80);
+
+	*ioapic_index = 0;
+	*ioapic_data = (1 << 25);
+
+	/* affirm full set of redirection table entries ("write once") */
+	*ioapic_index = 1;
+	reg32 = *ioapic_data;
+	*ioapic_index = 1;
+	*ioapic_data = reg32;
+
+	*ioapic_index = 0;
+	reg32 = *ioapic_data;
+	printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f);
+	if (reg32 != (1 << 25))
+		die("APIC Error\n");
+
+	printk(BIOS_SPEW, "Dumping IOAPIC registers\n");
+	for (i=0; i<3; i++) {
+		*ioapic_index = i;
+		printk(BIOS_SPEW, "  reg 0x%04x:", i);
+		reg32 = *ioapic_data;
+		printk(BIOS_SPEW, " 0x%08x\n", reg32);
+	}
+
+	*ioapic_index = 3; /* Select Boot Configuration register. */
+	*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
+}
+
+static void pch_enable_serial_irqs(struct device *dev)
+{
+	/* Set packet length and toggle silent mode bit for one frame. */
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0));
+	pci_write_config8(dev, SERIRQ_CNTL,
+			  (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0));
+}
+
+/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control
+ * 0x00 - 0000 = Reserved
+ * 0x01 - 0001 = Reserved
+ * 0x02 - 0010 = Reserved
+ * 0x03 - 0011 = IRQ3
+ * 0x04 - 0100 = IRQ4
+ * 0x05 - 0101 = IRQ5
+ * 0x06 - 0110 = IRQ6
+ * 0x07 - 0111 = IRQ7
+ * 0x08 - 1000 = Reserved
+ * 0x09 - 1001 = IRQ9
+ * 0x0A - 1010 = IRQ10
+ * 0x0B - 1011 = IRQ11
+ * 0x0C - 1100 = IRQ12
+ * 0x0D - 1101 = Reserved
+ * 0x0E - 1110 = IRQ14
+ * 0x0F - 1111 = IRQ15
+ * PIRQ[n]_ROUT[7] - PIRQ Routing Control
+ * 0x80 - The PIRQ is not routed.
+ */
+
+static void pch_pirq_init(device_t dev)
+{
+	device_t irq_dev;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing);
+	pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
+	pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
+	pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
+
+	pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing);
+	pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing);
+	pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing);
+	pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing);
+
+	/* Eric Biederman once said we should let the OS do this.
+	 * I am not so sure anymore he was right.
+	 */
+
+	for(irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
+		u8 int_pin=0, int_line=0;
+
+		if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
+			continue;
+
+		int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
+
+		switch (int_pin) {
+		case 1: /* INTA# */ int_line = config->pirqa_routing; break;
+		case 2: /* INTB# */ int_line = config->pirqb_routing; break;
+		case 3: /* INTC# */ int_line = config->pirqc_routing; break;
+		case 4: /* INTD# */ int_line = config->pirqd_routing; break;
+		}
+
+		if (!int_line)
+			continue;
+
+		pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line);
+	}
+}
+
+static void pch_gpi_routing(device_t dev)
+{
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+	u32 reg32 = 0;
+
+	/* An array would be much nicer here, or some
+	 * other method of doing this.
+	 */
+	reg32 |= (config->gpi0_routing & 0x03) << 0;
+	reg32 |= (config->gpi1_routing & 0x03) << 2;
+	reg32 |= (config->gpi2_routing & 0x03) << 4;
+	reg32 |= (config->gpi3_routing & 0x03) << 6;
+	reg32 |= (config->gpi4_routing & 0x03) << 8;
+	reg32 |= (config->gpi5_routing & 0x03) << 10;
+	reg32 |= (config->gpi6_routing & 0x03) << 12;
+	reg32 |= (config->gpi7_routing & 0x03) << 14;
+	reg32 |= (config->gpi8_routing & 0x03) << 16;
+	reg32 |= (config->gpi9_routing & 0x03) << 18;
+	reg32 |= (config->gpi10_routing & 0x03) << 20;
+	reg32 |= (config->gpi11_routing & 0x03) << 22;
+	reg32 |= (config->gpi12_routing & 0x03) << 24;
+	reg32 |= (config->gpi13_routing & 0x03) << 26;
+	reg32 |= (config->gpi14_routing & 0x03) << 28;
+	reg32 |= (config->gpi15_routing & 0x03) << 30;
+
+	pci_write_config32(dev, 0xb8, reg32);
+}
+
+static void pch_power_options(device_t dev)
+{
+	u8 reg8;
+	u16 reg16, pmbase;
+	u32 reg32;
+	const char *state;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	int pwr_on=CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	int nmi_option;
+
+	/* Which state do we want to goto after g3 (power restored)?
+	 * 0 == S0 Full On
+	 * 1 == S5 Soft Off
+	 *
+	 * If the option is not existent (Laptops), use Kconfig setting.
+	 */
+	get_option(&pwr_on, "power_on_after_fail");
+
+	reg16 = pci_read_config16(dev, GEN_PMCON_3);
+	reg16 &= 0xfffe;
+	switch (pwr_on) {
+	case MAINBOARD_POWER_OFF:
+		reg16 |= 1;
+		state = "off";
+		break;
+	case MAINBOARD_POWER_ON:
+		reg16 &= ~1;
+		state = "on";
+		break;
+	case MAINBOARD_POWER_KEEP:
+		reg16 &= ~1;
+		state = "state keep";
+		break;
+	default:
+		state = "undefined";
+	}
+
+	reg16 &= ~(3 << 4);	/* SLP_S4# Assertion Stretch 4s */
+	reg16 |= (1 << 3);	/* SLP_S4# Assertion Stretch Enable */
+
+	reg16 &= ~(1 << 10);
+	reg16 |= (1 << 11);	/* SLP_S3# Min Assertion Width 50ms */
+
+	reg16 |= (1 << 12);	/* Disable SLP stretch after SUS well */
+
+	pci_write_config16(dev, GEN_PMCON_3, reg16);
+	printk(BIOS_INFO, "Set power %s after power failure.\n", state);
+
+	/* Set up NMI on errors. */
+	reg8 = inb(0x61);
+	reg8 &= 0x0f;		/* Higher Nibble must be 0 */
+	reg8 &= ~(1 << 3);	/* IOCHK# NMI Enable */
+	// reg8 &= ~(1 << 2);	/* PCI SERR# Enable */
+	reg8 |= (1 << 2); /* PCI SERR# Disable for now */
+	outb(reg8, 0x61);
+
+	reg8 = inb(0x70);
+	nmi_option = NMI_OFF;
+	get_option(&nmi_option, "nmi");
+	if (nmi_option) {
+		printk(BIOS_INFO, "NMI sources enabled.\n");
+		reg8 &= ~(1 << 7);	/* Set NMI. */
+	} else {
+		printk(BIOS_INFO, "NMI sources disabled.\n");
+		reg8 |= ( 1 << 7);	/* Can't mask NMI from PCI-E and NMI_NOW */
+	}
+	outb(reg8, 0x70);
+
+	/* Enable CPU_SLP# and Intel Speedstep, set SMI# rate down */
+	reg16 = pci_read_config16(dev, GEN_PMCON_1);
+	reg16 &= ~(3 << 0);	// SMI# rate 1 minute
+	reg16 &= ~(1 << 10);	// Disable BIOS_PCI_EXP_EN for native PME
+#if DEBUG_PERIODIC_SMIS
+	/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
+	 * periodic SMIs.
+	 */
+	reg16 |= (3 << 0); // Periodic SMI every 8s
+#endif
+	pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+	// Set the board's GPI routing.
+	pch_gpi_routing(dev);
+
+	pmbase = pci_read_config16(dev, 0x40) & 0xfffe;
+
+	outl(config->gpe0_en, pmbase + GPE0_EN);
+	outw(config->alt_gp_smi_en, pmbase + ALT_GP_SMI_EN);
+
+	/* Set up power management block and determine sleep mode */
+	reg32 = inl(pmbase + 0x04); // PM1_CNT
+	reg32 &= ~(7 << 10);	// SLP_TYP
+	reg32 |= (1 << 0);	// SCI_EN
+	outl(reg32, pmbase + 0x04);
+
+	/* Clear magic status bits to prevent unexpected wake */
+	reg32 = RCBA32(0x3310);
+	reg32 |= (1 << 4)|(1 << 5)|(1 << 0);
+	RCBA32(0x3310) = reg32;
+
+	reg32 = RCBA32(0x3f02);
+	reg32 &= ~0xf;
+	RCBA32(0x3f02) = reg32;
+}
+
+static void pch_rtc_init(struct device *dev)
+{
+	u8 reg8;
+	int rtc_failed;
+
+	reg8 = pci_read_config8(dev, GEN_PMCON_3);
+	rtc_failed = reg8 & RTC_BATTERY_DEAD;
+	if (rtc_failed) {
+		reg8 &= ~RTC_BATTERY_DEAD;
+		pci_write_config8(dev, GEN_PMCON_3, reg8);
+	}
+	printk(BIOS_DEBUG, "rtc_failed = 0x%x\n", rtc_failed);
+
+	rtc_init(rtc_failed);
+}
+
+static void pch_pm_init(struct device *dev)
+{
+	pci_write_config8(dev, 0xa9, 0x47);
+	RCBA32_AND_OR(0x2238, ~0UL, (1 << 6)|(1 << 0));
+	RCBA32_AND_OR(0x228c, ~0UL, (1 << 0));
+	RCBA16_AND_OR(0x1100, ~0UL, (1 << 13)|(1 << 14));
+	RCBA16_AND_OR(0x0900, ~0UL, (1 << 14));
+	RCBA32(0x2304) = 0xc0388400;
+	RCBA32_AND_OR(0x2314, ~0UL, (1 << 5)|(1 << 18));
+	RCBA32_AND_OR(0x2320, ~0UL, (1 << 15)|(1 << 1));
+	RCBA32_AND_OR(0x3314, ~0x1f, 0xf);
+	RCBA32(0x3318) = 0x050f0000;
+	RCBA32(0x3324) = 0x04000000;
+	RCBA32_AND_OR(0x3340, ~0UL, 0xfffff);
+	RCBA32_AND_OR(0x3344, ~0UL, (1 << 1));
+	RCBA32(0x3360) = 0x0001c000;
+	RCBA32(0x3368) = 0x00061100;
+	RCBA32(0x3378) = 0x7f8fdfff;
+	RCBA32(0x337c) = 0x000003fc;
+	RCBA32(0x3388) = 0x00001000;
+	RCBA32(0x3390) = 0x0001c000;
+	RCBA32(0x33a0) = 0x00000800;
+	RCBA32(0x33b0) = 0x00001000;
+	RCBA32(0x33c0) = 0x00093900;
+	RCBA32(0x33cc) = 0x24653002;
+	RCBA32(0x33d0) = 0x062108fe;
+	RCBA32_AND_OR(0x33d4, 0xf000f000, 0x00670060);
+	RCBA32(0x3a28) = 0x01010000;
+	RCBA32(0x3a2c) = 0x01010404;
+	RCBA32(0x3a80) = 0x01041041;
+	RCBA32_AND_OR(0x3a84, ~0x0000ffff, 0x00001001);
+	RCBA32_AND_OR(0x3a84, ~0UL, (1 << 24)); /* SATA 2/3 disabled */
+	RCBA32_AND_OR(0x3a88, ~0UL, (1 << 0));  /* SATA 4/5 disabled */
+	RCBA32(0x3a6c) = 0x00000001;
+	RCBA32_AND_OR(0x2344, 0x00ffff00, 0xff00000c);
+	RCBA32_AND_OR(0x80c, ~(0xff << 20), 0x11 << 20);
+	RCBA32(0x33c8) = 0;
+	RCBA32_AND_OR(0x21b0, ~0UL, 0xf);
+}
+
+static void enable_hpet(void)
+{
+	u32 reg32;
+
+	/* Move HPET to default address 0xfed00000 and enable it */
+	reg32 = RCBA32(HPTC);
+	reg32 |= (1 << 7); // HPET Address Enable
+	reg32 &= ~(3 << 0);
+	RCBA32(HPTC) = reg32;
+}
+
+static void enable_clock_gating(device_t dev)
+{
+	u32 reg32;
+	u16 reg16;
+
+	RCBA32_AND_OR(0x2234, ~0UL, 0xf);
+
+	reg16 = pci_read_config16(dev, GEN_PMCON_1);
+	reg16 |= (1 << 2) | (1 << 11);
+	pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+	pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
+	pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
+	pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
+	pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
+
+	reg32 = RCBA32(CG);
+	reg32 |= (1 << 31);
+	reg32 |= (1 << 29) | (1 << 28);
+	reg32 |= (1 << 27) | (1 << 26) | (1 << 25) | (1 << 24);
+	reg32 |= (1 << 16);
+	reg32 |= (1 << 17);
+	reg32 |= (1 << 18);
+	reg32 |= (1 << 22);
+	reg32 |= (1 << 23);
+	reg32 &= ~(1 << 20);
+	reg32 |= (1 << 19);
+	reg32 |= (1 << 0);
+	reg32 |= (0xf << 1);
+	RCBA32(CG) = reg32;
+
+	RCBA32_OR(0x38c0, 0x7);
+	RCBA32_OR(0x36d4, 0x6680c004);
+	RCBA32_OR(0x3564, 0x3);
+}
+
+#if CONFIG_HAVE_SMI_HANDLER
+static void pch_lock_smm(struct device *dev)
+{
+#if TEST_SMM_FLASH_LOCKDOWN
+	u8 reg8;
+#endif
+
+#if ENABLE_ACPI_MODE_IN_COREBOOT
+	printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n");
+	outb(0xe1, 0xb2); // Enable ACPI mode
+	printk(BIOS_DEBUG, "done.\n");
+#else
+	printk(BIOS_DEBUG, "Disabling ACPI via APMC:\n");
+	outb(0x1e, 0xb2); // Disable ACPI mode
+	printk(BIOS_DEBUG, "done.\n");
+#endif
+	/* Don't allow evil boot loaders, kernels, or
+	 * userspace applications to deceive us:
+	 */
+	smm_lock();
+
+#if TEST_SMM_FLASH_LOCKDOWN
+	/* Now try this: */
+	printk(BIOS_DEBUG, "Locking BIOS to RO... ");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+	reg8 &= ~(1 << 0);			/* clear BIOSWE */
+	pci_write_config8(dev, 0xdc, reg8);
+	reg8 |= (1 << 1);			/* set BLE */
+	pci_write_config8(dev, 0xdc, reg8);
+	printk(BIOS_DEBUG, "ok.\n");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+
+	printk(BIOS_DEBUG, "Writing:\n");
+	*(volatile u8 *)0xfff00000 = 0x00;
+	printk(BIOS_DEBUG, "Testing:\n");
+	reg8 |= (1 << 0);			/* set BIOSWE */
+	pci_write_config8(dev, 0xdc, reg8);
+
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	printk(BIOS_DEBUG, " BLE: %s; BWE: %s\n", (reg8&2)?"on":"off",
+			(reg8&1)?"rw":"ro");
+	printk(BIOS_DEBUG, "Done.\n");
+#endif
+}
+#endif
+
+static void pch_disable_smm_only_flashing(struct device *dev)
+{
+	u8 reg8;
+
+	printk(BIOS_SPEW, "Enabling BIOS updates outside of SMM... ");
+	reg8 = pci_read_config8(dev, 0xdc);	/* BIOS_CNTL */
+	reg8 &= ~(1 << 5);
+	pci_write_config8(dev, 0xdc, reg8);
+}
+
+static void pch_fixups(struct device *dev)
+{
+	u8 gen_pmcon_2;
+
+	/* Indicate DRAM init done for MRC S3 to know it can resume */
+	gen_pmcon_2 = pci_read_config8(dev, GEN_PMCON_2);
+	gen_pmcon_2 |= (1 << 7);
+	pci_write_config8(dev, GEN_PMCON_2, gen_pmcon_2);
+
+	/*
+	 * Enable DMI ASPM in the PCH
+	 */
+	RCBA32_AND_OR(0x2304, ~(1 << 10), 0);
+	RCBA32_OR(0x21a4, (1 << 11)|(1 << 10));
+	RCBA32_OR(0x21a8, 0x3);
+}
+
+static void pch_decode_init(struct device *dev)
+{
+	config_t *config = dev->chip_info;
+
+	printk(BIOS_DEBUG, "pch_decode_init\n");
+
+	pci_write_config32(dev, LPC_GEN1_DEC, config->gen1_dec);
+	pci_write_config32(dev, LPC_GEN2_DEC, config->gen2_dec);
+	pci_write_config32(dev, LPC_GEN3_DEC, config->gen3_dec);
+	pci_write_config32(dev, LPC_GEN4_DEC, config->gen4_dec);
+}
+
+static void lpc_init(struct device *dev)
+{
+	printk(BIOS_DEBUG, "pch: lpc_init\n");
+
+	/* Set the value for PCI command register. */
+	pci_write_config16(dev, PCI_COMMAND, 0x000f);
+
+	/* IO APIC initialization. */
+	pch_enable_apic(dev);
+
+	pch_enable_serial_irqs(dev);
+
+	/* Setup the PIRQ. */
+	pch_pirq_init(dev);
+
+	/* Setup power options. */
+	pch_power_options(dev);
+
+	/* Initialize power management */
+	pch_pm_init(dev);
+
+	/* Set the state of the GPIO lines. */
+	//gpio_init(dev);
+
+	/* Initialize the real time clock. */
+	pch_rtc_init(dev);
+
+	/* Initialize ISA DMA. */
+	isa_dma_init();
+
+	/* Initialize the High Precision Event Timers, if present. */
+	enable_hpet();
+
+	/* Initialize Clock Gating */
+	enable_clock_gating(dev);
+
+	setup_i8259();
+
+	/* The OS should do this? */
+	/* Interrupt 9 should be level triggered (SCI) */
+	i8259_configure_irq_trigger(9, 1);
+
+	pch_disable_smm_only_flashing(dev);
+
+#if CONFIG_HAVE_SMI_HANDLER
+	pch_lock_smm(dev);
+#endif
+
+	pch_fixups(dev);
+}
+
+static void pch_lpc_read_resources(device_t dev)
+{
+	struct resource *res;
+
+	/* Get the normal PCI resources of this device. */
+	pci_dev_read_resources(dev);
+
+	/* Add an extra subtractive resource for both memory and I/O. */
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
+	res->base = 0;
+	res->size = 0x1000;
+	res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
+	res->base = 0xff800000;
+	res->size = 0x00800000; /* 8 MB for flash */
+	res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
+		     IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+
+	res = new_resource(dev, 3); /* IOAPIC */
+	res->base = IO_APIC_ADDR;
+	res->size = 0x00001000;
+	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
+}
+
+static void pch_lpc_enable_resources(device_t dev)
+{
+	pch_decode_init(dev);
+	return pci_dev_enable_resources(dev);
+}
+
+static void pch_lpc_enable(device_t dev)
+{
+	/* Enable PCH Display Port */
+	RCBA16(DISPBDF) = 0x0010;
+	RCBA32_OR(FD2, PCH_ENABLE_DBDF);
+
+	pch_enable(dev);
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pch_lpc_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pch_lpc_enable_resources,
+	.init			= lpc_init,
+	.enable			= pch_lpc_enable,
+	.scan_bus		= scan_static_bus,
+	.ops_pci		= &pci_ops,
+};
+
+
+/* IDs for LPC device of Intel 6 series Chipset and
+ * Intel C200 Series Chipset according to specification
+ * update from August 2011
+ */
+
+static const struct pci_driver q67_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c4e,
+};
+static const struct pci_driver q65_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c4c,
+};
+static const struct pci_driver b65_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c50,
+};
+static const struct pci_driver h67_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c4a,
+};
+static const struct pci_driver z68_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c46,
+};
+static const struct pci_driver h61_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c5c,
+};
+static const struct pci_driver c202_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c52,
+};
+static const struct pci_driver c204_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c54,
+};
+static const struct pci_driver c206_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c56,
+};
+static const struct pci_driver qm67_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c4f,
+};
+static const struct pci_driver um67_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c47,
+};
+static const struct pci_driver hm67_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c4b,
+};
+static const struct pci_driver hm65_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c49,
+};
+static const struct pci_driver qs67_lpc __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c4d,
+};
diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c
new file mode 100644
index 0000000..dabf3a7
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/me.c
@@ -0,0 +1,745 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+/*
+ * This is a ramstage driver for the Intel Management Engine found in the
+ * 6-series chipset.  It handles the required boot-time messages over the
+ * MMIO-based Management Engine Interface to tell the ME that the BIOS is
+ * finished with POST.  Additional messages are defined for debug but are
+ * not used unless the console loglevel is high enough.
+ */
+
+#include <arch/acpi.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include <string.h>
+#include <delay.h>
+
+#ifdef __SMM__
+# include <arch/romcc_io.h>
+# include <northbridge/intel/sandybridge/pcie_config.c>
+#else
+# include <device/device.h>
+# include <device/pci.h>
+#endif
+
+#include "me.h"
+#include "pch.h"
+
+#if CONFIG_CHROMEOS
+#include <vendorcode/google/chromeos/gnvs.h>
+#endif
+
+#ifndef __SMM__
+/* Path that the BIOS should take based on ME state */
+static const char *me_bios_path_values[] = {
+	[ME_NORMAL_BIOS_PATH]		= "Normal",
+	[ME_S3WAKE_BIOS_PATH]		= "S3 Wake",
+	[ME_ERROR_BIOS_PATH]		= "Error",
+	[ME_RECOVERY_BIOS_PATH]		= "Recovery",
+	[ME_DISABLE_BIOS_PATH]		= "Disable",
+	[ME_FIRMWARE_UPDATE_BIOS_PATH]	= "Firmware Update",
+};
+#endif
+
+/* MMIO base address for MEI interface */
+static u32 mei_base_address;
+
+#if CONFIG_DEBUG_INTEL_ME
+static void mei_dump(void *ptr, int dword, int offset, const char *type)
+{
+	struct mei_csr *csr;
+
+	printk(BIOS_SPEW, "%-9s[%02x] : ", type, offset);
+
+	switch (offset) {
+	case MEI_H_CSR:
+	case MEI_ME_CSR_HA:
+		csr = ptr;
+		if (!csr) {
+			printk(BIOS_SPEW, "ERROR: 0x%08x\n", dword);
+			break;
+		}
+		printk(BIOS_SPEW, "cbd=%u cbrp=%02u cbwp=%02u ready=%u "
+		       "reset=%u ig=%u is=%u ie=%u\n", csr->buffer_depth,
+		       csr->buffer_read_ptr, csr->buffer_write_ptr,
+		       csr->ready, csr->reset, csr->interrupt_generate,
+		       csr->interrupt_status, csr->interrupt_enable);
+		break;
+	case MEI_ME_CB_RW:
+	case MEI_H_CB_WW:
+		printk(BIOS_SPEW, "CB: 0x%08x\n", dword);
+		break;
+	default:
+		printk(BIOS_SPEW, "0x%08x\n", offset);
+		break;
+	}
+}
+#else
+# define mei_dump(ptr,dword,offset,type) do {} while (0)
+#endif
+
+/*
+ * ME/MEI access helpers using memcpy to avoid aliasing.
+ */
+
+static inline void mei_read_dword_ptr(void *ptr, int offset)
+{
+	u32 dword = read32(mei_base_address + offset);
+	memcpy(ptr, &dword, sizeof(dword));
+	mei_dump(ptr, dword, offset, "READ");
+}
+
+static inline void mei_write_dword_ptr(void *ptr, int offset)
+{
+	u32 dword = 0;
+	memcpy(&dword, ptr, sizeof(dword));
+	write32(mei_base_address + offset, dword);
+	mei_dump(ptr, dword, offset, "WRITE");
+}
+
+#ifndef __SMM__
+static inline void pci_read_dword_ptr(device_t dev, void *ptr, int offset)
+{
+	u32 dword = pci_read_config32(dev, offset);
+	memcpy(ptr, &dword, sizeof(dword));
+	mei_dump(ptr, dword, offset, "PCI READ");
+}
+#endif
+
+static inline void read_host_csr(struct mei_csr *csr)
+{
+	mei_read_dword_ptr(csr, MEI_H_CSR);
+}
+
+static inline void write_host_csr(struct mei_csr *csr)
+{
+	mei_write_dword_ptr(csr, MEI_H_CSR);
+}
+
+static inline void read_me_csr(struct mei_csr *csr)
+{
+	mei_read_dword_ptr(csr, MEI_ME_CSR_HA);
+}
+
+static inline void write_cb(u32 dword)
+{
+	write32(mei_base_address + MEI_H_CB_WW, dword);
+	mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
+}
+
+static inline u32 read_cb(void)
+{
+	u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
+	mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
+	return dword;
+}
+
+/* Wait for ME ready bit to be asserted */
+static int mei_wait_for_me_ready(void)
+{
+	struct mei_csr me;
+	unsigned try = ME_RETRY;
+
+	while (try--) {
+		read_me_csr(&me);
+		if (me.ready)
+			return 0;
+		udelay(ME_DELAY);
+	}
+
+	printk(BIOS_ERR, "ME: failed to become ready\n");
+	return -1;
+}
+
+static void mei_reset(void)
+{
+	struct mei_csr host;
+
+	if (mei_wait_for_me_ready() < 0)
+		return;
+
+	/* Reset host and ME circular buffers for next message */
+	read_host_csr(&host);
+	host.reset = 1;
+	host.interrupt_generate = 1;
+	write_host_csr(&host);
+
+	if (mei_wait_for_me_ready() < 0)
+		return;
+
+	/* Re-init and indicate host is ready */
+	read_host_csr(&host);
+	host.interrupt_generate = 1;
+	host.ready = 1;
+	host.reset = 0;
+	write_host_csr(&host);
+}
+
+static int mei_send_msg(struct mei_header *mei, struct mkhi_header *mkhi,
+			void *req_data)
+{
+	struct mei_csr host;
+	unsigned ndata, n;
+	u32 *data;
+
+	/* Number of dwords to write, ignoring MKHI */
+	ndata = mei->length >> 2;
+
+	/* Pad non-dword aligned request message length */
+	if (mei->length & 3)
+		ndata++;
+	if (!ndata) {
+		printk(BIOS_DEBUG, "ME: request does not include MKHI\n");
+		return -1;
+	}
+	ndata++; /* Add MEI header */
+
+	/*
+	 * Make sure there is still room left in the circular buffer.
+	 * Reset the buffer pointers if the requested message will not fit.
+	 */
+	read_host_csr(&host);
+	if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
+		printk(BIOS_ERR, "ME: circular buffer full, resetting...\n");
+		mei_reset();
+		read_host_csr(&host);
+	}
+
+	/*
+	 * This implementation does not handle splitting large messages
+	 * across multiple transactions.  Ensure the requested length
+	 * will fit in the available circular buffer depth.
+	 */
+	if ((host.buffer_depth - host.buffer_write_ptr) < ndata) {
+		printk(BIOS_ERR, "ME: message (%u) too large for buffer (%u)\n",
+		       ndata + 2, host.buffer_depth);
+		return -1;
+	}
+
+	/* Write MEI header */
+	mei_write_dword_ptr(mei, MEI_H_CB_WW);
+	ndata--;
+
+	/* Write MKHI header */
+	mei_write_dword_ptr(mkhi, MEI_H_CB_WW);
+	ndata--;
+
+	/* Write message data */
+	data = req_data;
+	for (n = 0; n < ndata; ++n)
+		write_cb(*data++);
+
+	/* Generate interrupt to the ME */
+	read_host_csr(&host);
+	host.interrupt_generate = 1;
+	write_host_csr(&host);
+
+	/* Make sure ME is ready after sending request data */
+	return mei_wait_for_me_ready();
+}
+
+static int mei_recv_msg(struct mei_header *mei, struct mkhi_header *mkhi,
+			void *rsp_data, int rsp_bytes)
+{
+	struct mei_header mei_rsp;
+	struct mkhi_header mkhi_rsp;
+	struct mei_csr me, host;
+	unsigned ndata, n;
+	unsigned expected;
+	u32 *data;
+
+	/* Total number of dwords to read from circular buffer */
+	expected = (rsp_bytes + sizeof(mei_rsp) + sizeof(mkhi_rsp)) >> 2;
+	if (rsp_bytes & 3)
+		expected++;
+
+	/*
+	 * The interrupt status bit does not appear to indicate that the
+	 * message has actually been received.  Instead we wait until the
+	 * expected number of dwords are present in the circular buffer.
+	 */
+	for (n = ME_RETRY; n; --n) {
+		read_me_csr(&me);
+		if ((me.buffer_write_ptr - me.buffer_read_ptr) >= expected)
+			break;
+		udelay(ME_DELAY);
+	}
+	if (!n) {
+		printk(BIOS_ERR, "ME: timeout waiting for data: expected "
+		       "%u, available %u\n", expected,
+		       me.buffer_write_ptr - me.buffer_read_ptr);
+		return -1;
+	}
+
+	/* Read and verify MEI response header from the ME */
+	mei_read_dword_ptr(&mei_rsp, MEI_ME_CB_RW);
+	if (!mei_rsp.is_complete) {
+		printk(BIOS_ERR, "ME: response is not complete\n");
+		return -1;
+	}
+
+	/* Handle non-dword responses and expect at least MKHI header */
+	ndata = mei_rsp.length >> 2;
+	if (mei_rsp.length & 3)
+		ndata++;
+	if (ndata != (expected - 1)) {
+		printk(BIOS_ERR, "ME: response is missing data\n");
+		return -1;
+	}
+
+	/* Read and verify MKHI response header from the ME */
+	mei_read_dword_ptr(&mkhi_rsp, MEI_ME_CB_RW);
+	if (!mkhi_rsp.is_response ||
+	    mkhi->group_id != mkhi_rsp.group_id ||
+	    mkhi->command != mkhi_rsp.command) {
+		printk(BIOS_ERR, "ME: invalid response, group %u ?= %u, "
+		       "command %u ?= %u, is_response %u\n", mkhi->group_id,
+		       mkhi_rsp.group_id, mkhi->command, mkhi_rsp.command,
+		       mkhi_rsp.is_response);
+		return -1;
+	}
+	ndata--; /* MKHI header has been read */
+
+	/* Make sure caller passed a buffer with enough space */
+	if (ndata != (rsp_bytes >> 2)) {
+		printk(BIOS_ERR, "ME: not enough room in response buffer: "
+		       "%u != %u\n", ndata, rsp_bytes >> 2);
+		return -1;
+	}
+
+	/* Read response data from the circular buffer */
+	data = rsp_data;
+	for (n = 0; n < ndata; ++n)
+		*data++ = read_cb();
+
+	/* Tell the ME that we have consumed the response */
+	read_host_csr(&host);
+	host.interrupt_status = 1;
+	host.interrupt_generate = 1;
+	write_host_csr(&host);
+
+	return mei_wait_for_me_ready();
+}
+
+static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi,
+			       void *req_data, void *rsp_data, int rsp_bytes)
+{
+	if (mei_send_msg(mei, mkhi, req_data) < 0)
+		return -1;
+	if (mei_recv_msg(mei, mkhi, rsp_data, rsp_bytes) < 0)
+		return -1;
+	return 0;
+}
+
+/* Send END OF POST message to the ME */
+int mkhi_end_of_post(void)
+{
+	struct mkhi_header mkhi = {
+		.group_id	= MKHI_GROUP_ID_GEN,
+		.command	= MKHI_END_OF_POST,
+	};
+	struct mei_header mei = {
+		.is_complete	= 1,
+		.host_address	= MEI_HOST_ADDRESS,
+		.client_address	= MEI_ADDRESS_MKHI,
+		.length		= sizeof(mkhi),
+	};
+
+	/* Send request and wait for response */
+	if (mei_sendrecv(&mei, &mkhi, NULL, NULL, 0) < 0) {
+		printk(BIOS_ERR, "ME: END OF POST message failed\n");
+		return -1;
+	}
+
+	printk(BIOS_INFO, "ME: END OF POST message successful\n");
+	return 0;
+}
+
+/* Get ME firmware version */
+int mkhi_get_fw_version(void)
+{
+	struct me_fw_version version;
+	struct mkhi_header mkhi = {
+		.group_id	= MKHI_GROUP_ID_GEN,
+		.command	= MKHI_GET_FW_VERSION,
+	};
+	struct mei_header mei = {
+		.is_complete	= 1,
+		.host_address	= MEI_HOST_ADDRESS,
+		.client_address	= MEI_ADDRESS_MKHI,
+		.length		= sizeof(mkhi),
+	};
+
+	/* Send request and wait for response */
+	if (mei_sendrecv(&mei, &mkhi, NULL, &version, sizeof(version)) < 0) {
+		printk(BIOS_ERR, "ME: GET FW VERSION message failed\n");
+		return -1;
+	}
+
+	printk(BIOS_INFO, "ME: Firmware Version %u.%u.%u.%u (code) "
+	       "%u.%u.%u.%u (recovery)\n",
+	       version.code_major, version.code_minor,
+	       version.code_build_number, version.code_hot_fix,
+	       version.recovery_major, version.recovery_minor,
+	       version.recovery_build_number, version.recovery_hot_fix);
+
+	return 0;
+}
+
+static inline void print_cap(const char *name, int state)
+{
+	printk(BIOS_DEBUG, "ME Capability: %-30s : %sabled\n",
+	       name, state ? "en" : "dis");
+}
+
+/* Get ME Firmware Capabilities */
+int mkhi_get_fwcaps(void)
+{
+	u32 rule_id = 0;
+	struct me_fwcaps cap;
+	struct mkhi_header mkhi = {
+		.group_id	= MKHI_GROUP_ID_FWCAPS,
+		.command	= MKHI_FWCAPS_GET_RULE,
+	};
+	struct mei_header mei = {
+		.is_complete	= 1,
+		.host_address	= MEI_HOST_ADDRESS,
+		.client_address	= MEI_ADDRESS_MKHI,
+		.length		= sizeof(mkhi) + sizeof(rule_id),
+	};
+
+	/* Send request and wait for response */
+	if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap, sizeof(cap)) < 0) {
+		printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
+		return -1;
+	}
+
+	print_cap("Full Network Manageability", cap.cap_full_network);
+	print_cap("Regular Network Manageability", cap.cap_full_network);
+	print_cap("Manageability", cap.cap_manageability);
+	print_cap("Anti-Theft Technology", cap.cap_anti_theft);
+	print_cap("Capability Licensing Service", cap.cap_licensing);
+	print_cap("Virtualization Engine", cap.cap_virtualization);
+	print_cap("Power Sharing Technology", cap.cap_power_sharing);
+	print_cap("ICC Over Clocking", cap.cap_icc_over_clocking);
+	print_cap("Protected Audio Video Path", cap.cap_pavp);
+	print_cap("IPv6", cap.cap_ipv6);
+	print_cap("KVM Remote Control", cap.cap_kvm);
+	print_cap("Oubreak Containment Heuristic", cap.cap_och);
+	print_cap("Virtual LAN", cap.cap_vlan);
+	print_cap("Cipher Transport Layer", cap.cap_tls);
+	print_cap("Wireless LAN", cap.cap_wlan);
+
+	return 0;
+}
+
+/* Tell ME to issue a global reset */
+int mkhi_global_reset(void)
+{
+	struct me_global_reset reset = {
+		.request_origin	= GLOBAL_RESET_BIOS_POST,
+		.reset_type	= CBM_RR_GLOBAL_RESET,
+	};
+	struct mkhi_header mkhi = {
+		.group_id	= MKHI_GROUP_ID_CBM,
+		.command	= MKHI_GLOBAL_RESET,
+	};
+	struct mei_header mei = {
+		.is_complete	= 1,
+		.length		= sizeof(mkhi) + sizeof(reset),
+		.host_address	= MEI_HOST_ADDRESS,
+		.client_address	= MEI_ADDRESS_MKHI,
+	};
+
+	printk(BIOS_NOTICE, "ME: Requesting global reset\n");
+
+	/* Send request and wait for response */
+	if (mei_sendrecv(&mei, &mkhi, &reset, NULL, 0) < 0) {
+		/* No response means reset will happen shortly... */
+		hlt();
+	}
+
+	/* If the ME responded it rejected the reset request */
+	printk(BIOS_ERR, "ME: Global Reset failed\n");
+	return -1;
+}
+
+#ifdef __SMM__
+
+void intel_me_finalize_smm(void)
+{
+	struct me_hfs hfs;
+	u32 reg32;
+
+	mei_base_address =
+		pcie_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
+
+	/* S3 path will have hidden this device already */
+	if (!mei_base_address || mei_base_address == 0xfffffff0)
+		return;
+
+	/* Make sure ME is in a mode that expects EOP */
+	reg32 = pcie_read_config32(PCH_ME_DEV, PCI_ME_HFS);
+	memcpy(&hfs, &reg32, sizeof(u32));
+
+	/* Abort and leave device alone if not normal mode */
+	if (hfs.fpt_bad ||
+	    hfs.working_state != ME_HFS_CWS_NORMAL ||
+	    hfs.operation_mode != ME_HFS_MODE_NORMAL)
+		return;
+
+	/* Try to send EOP command so ME stops accepting other commands */
+	mkhi_end_of_post();
+
+	/* Make sure IO is disabled */
+	reg32 = pcie_read_config32(PCH_ME_DEV, PCI_COMMAND);
+	reg32 &= ~(PCI_COMMAND_MASTER |
+		   PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
+	pcie_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32);
+
+	/* Hide the PCI device */
+	RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+}
+
+#else /* !__SMM__ */
+
+/* Determine the path that we should take based on ME status */
+static me_bios_path intel_me_path(device_t dev)
+{
+	me_bios_path path = ME_DISABLE_BIOS_PATH;
+	struct me_hfs hfs;
+	struct me_gmes gmes;
+
+#if CONFIG_HAVE_ACPI_RESUME
+	/* S3 wake skips all MKHI messages */
+	if (acpi_slp_type == 3) {
+		return ME_S3WAKE_BIOS_PATH;
+	}
+#endif
+
+	pci_read_dword_ptr(dev, &hfs, PCI_ME_HFS);
+	pci_read_dword_ptr(dev, &gmes, PCI_ME_GMES);
+
+	/* Check and dump status */
+	intel_me_status(&hfs, &gmes);
+
+	/* Check for valid firmware */
+	if (hfs.fpt_bad)
+		return ME_ERROR_BIOS_PATH;
+
+	/* Check Current Working State */
+	switch (hfs.working_state) {
+	case ME_HFS_CWS_NORMAL:
+		path = ME_NORMAL_BIOS_PATH;
+		break;
+	case ME_HFS_CWS_REC:
+		path = ME_RECOVERY_BIOS_PATH;
+		break;
+	default:
+		path = ME_DISABLE_BIOS_PATH;
+		break;
+	}
+
+	/* Check Current Operation Mode */
+	switch (hfs.operation_mode) {
+	case ME_HFS_MODE_NORMAL:
+		break;
+	case ME_HFS_MODE_DEBUG:
+	case ME_HFS_MODE_DIS:
+	case ME_HFS_MODE_OVER_JMPR:
+	case ME_HFS_MODE_OVER_MEI:
+	default:
+		path = ME_DISABLE_BIOS_PATH;
+		break;
+	}
+
+	/* Check for any error code */
+	if (hfs.error_code)
+		path = ME_ERROR_BIOS_PATH;
+
+	return path;
+}
+
+/* Prepare ME for MEI messages */
+static int intel_mei_setup(device_t dev)
+{
+	struct resource *res;
+	struct mei_csr host;
+	u32 reg32;
+
+	/* Find the MMIO base for the ME interface */
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
+	if (!res || res->base == 0 || res->size == 0) {
+		printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
+		return -1;
+	}
+	mei_base_address = res->base;
+
+	/* Ensure Memory and Bus Master bits are set */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Clean up status for next message */
+	read_host_csr(&host);
+	host.interrupt_generate = 1;
+	host.ready = 1;
+	host.reset = 0;
+	write_host_csr(&host);
+
+	return 0;
+}
+
+/* Read the Extend register hash of ME firmware */
+static int intel_me_extend_valid(device_t dev)
+{
+	struct me_heres status;
+	u32 extend[] = {0};
+	int i, count = 0;
+
+	pci_read_dword_ptr(dev, &status, PCI_ME_HERES);
+	if (!status.extend_feature_present) {
+		printk(BIOS_ERR, "ME: Extend Feature not present\n");
+		return -1;
+	}
+
+	if (!status.extend_reg_valid) {
+		printk(BIOS_ERR, "ME: Extend Register not valid\n");
+		return -1;
+	}
+
+	switch (status.extend_reg_algorithm) {
+	case PCI_ME_EXT_SHA1:
+		count = 5;
+		printk(BIOS_DEBUG, "ME: Extend SHA-1: ");
+		break;
+	case PCI_ME_EXT_SHA256:
+		count = 8;
+		printk(BIOS_DEBUG, "ME: Extend SHA-256: ");
+		break;
+	default:
+		printk(BIOS_ERR, "ME: Extend Algorithm %d unknown\n",
+		       status.extend_reg_algorithm);
+		return -1;
+	}
+
+	for (i = 0; i < count; ++i) {
+		extend[i] = pci_read_config32(dev, PCI_ME_HER(i));
+		printk(BIOS_DEBUG, "%08x", extend[i]);
+	}
+	printk(BIOS_DEBUG, "\n");
+
+#if CONFIG_CHROMEOS
+	/* Save hash in NVS for the OS to verify */
+	chromeos_set_me_hash(extend, count);
+#endif
+
+	return 0;
+}
+
+/* Hide the ME virtual PCI devices */
+static void intel_me_hide(device_t dev)
+{
+	dev->enabled = 0;
+	pch_enable(dev);
+}
+
+/* Check whether ME is present and do basic init */
+static void intel_me_init(device_t dev)
+{
+	me_bios_path path = intel_me_path(dev);
+
+	/* Do initial setup and determine the BIOS path */
+	printk(BIOS_NOTICE, "ME: BIOS path: %s\n", me_bios_path_values[path]);
+
+	switch (path) {
+	case ME_S3WAKE_BIOS_PATH:
+		intel_me_hide(dev);
+		break;
+
+	case ME_NORMAL_BIOS_PATH:
+		/* Validate the extend register */
+		if (intel_me_extend_valid(dev) < 0)
+			break; /* TODO: force recovery mode */
+
+		/* Prepare MEI MMIO interface */
+		if (intel_mei_setup(dev) < 0)
+			break;
+
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+		/* Print ME firmware version */
+		mkhi_get_fw_version();
+		/* Print ME firmware capabilities */
+		mkhi_get_fwcaps();
+#endif
+
+		/*
+		 * Leave the ME unlocked in this path.
+		 * It will be locked via SMI command later.
+		 */
+		break;
+
+	case ME_ERROR_BIOS_PATH:
+	case ME_RECOVERY_BIOS_PATH:
+	case ME_DISABLE_BIOS_PATH:
+	case ME_FIRMWARE_UPDATE_BIOS_PATH:
+		/*
+		 * TODO(dlaurie) Force recovery mode if ME is unhappy?
+		 */
+		break;
+	}
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+			   pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+			   ((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= intel_me_init,
+	.scan_bus		= scan_static_bus,
+	.ops_pci		= &pci_ops,
+};
+
+static const struct pci_driver intel_me __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c3a,
+};
+
+#endif /* !__SMM__ */
diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h
new file mode 100644
index 0000000..f16f83f
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/me.h
@@ -0,0 +1,279 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _INTEL_ME_H
+#define _INTEL_ME_H
+
+#define ME_RETRY		100000	/* 1 second */
+#define ME_DELAY		10	/* 10 us */
+
+/*
+ * Management Engine PCI registers
+ */
+
+#define PCI_CPU_DEVICE		PCI_DEV(0,0,0)
+#define PCI_CPU_MEBASE_L	0x70	/* Set by MRC */
+#define PCI_CPU_MEBASE_H	0x74	/* Set by MRC */
+
+#define PCI_ME_HFS		0x40
+#define  ME_HFS_CWS_RESET	0
+#define  ME_HFS_CWS_INIT	1
+#define  ME_HFS_CWS_REC		2
+#define  ME_HFS_CWS_NORMAL	5
+#define  ME_HFS_CWS_WAIT	6
+#define  ME_HFS_CWS_TRANS	7
+#define  ME_HFS_CWS_INVALID	8
+#define  ME_HFS_STATE_PREBOOT	0
+#define  ME_HFS_STATE_M0_UMA	1
+#define  ME_HFS_STATE_M3	4
+#define  ME_HFS_STATE_M0	5
+#define  ME_HFS_STATE_BRINGUP	6
+#define  ME_HFS_STATE_ERROR	7
+#define  ME_HFS_ERROR_NONE	0
+#define  ME_HFS_ERROR_UNCAT	1
+#define  ME_HFS_ERROR_IMAGE	3
+#define  ME_HFS_ERROR_DEBUG	4
+#define  ME_HFS_MODE_NORMAL	0
+#define  ME_HFS_MODE_DEBUG	2
+#define  ME_HFS_MODE_DIS	3
+#define  ME_HFS_MODE_OVER_JMPR	4
+#define  ME_HFS_MODE_OVER_MEI	5
+#define  ME_HFS_BIOS_DRAM_ACK	1
+#define  ME_HFS_ACK_NO_DID	0
+#define  ME_HFS_ACK_RESET	1
+#define  ME_HFS_ACK_PWR_CYCLE	2
+#define  ME_HFS_ACK_S3		3
+#define  ME_HFS_ACK_S4		4
+#define  ME_HFS_ACK_S5		5
+#define  ME_HFS_ACK_GBL_RESET	6
+#define  ME_HFS_ACK_CONTINUE	7
+
+struct me_hfs {
+	u32 working_state: 4;
+	u32 mfg_mode: 1;
+	u32 fpt_bad: 1;
+	u32 operation_state: 3;
+	u32 fw_init_complete: 1;
+	u32 ft_bup_ld_flr: 1;
+	u32 update_in_progress: 1;
+	u32 error_code: 4;
+	u32 operation_mode: 4;
+	u32 reserved: 4;
+	u32 boot_options_present: 1;
+	u32 ack_data: 3;
+	u32 bios_msg_ack: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_UMA		0x44
+
+struct me_uma {
+	u32 size: 6;
+	u32 reserved_1: 10;
+	u32 valid: 1;
+	u32 reserved_0: 14;
+	u32 set_to_one: 1;
+} __attribute__ ((packed));
+
+#define PCI_ME_H_GS		0x4c
+#define  ME_INIT_DONE		1
+#define  ME_INIT_STATUS_SUCCESS	0
+#define  ME_INIT_STATUS_NOMEM	1
+#define  ME_INIT_STATUS_ERROR	2
+
+struct me_did {
+	u32 uma_base: 16;
+	u32 reserved: 8;
+	u32 status: 4;
+	u32 init_done: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_GMES		0x48
+#define  ME_GMES_PHASE_ROM	0
+#define  ME_GMES_PHASE_BUP	1
+#define  ME_GMES_PHASE_UKERNEL	2
+#define  ME_GMES_PHASE_POLICY	3
+#define  ME_GMES_PHASE_MODULE	4
+#define  ME_GMES_PHASE_UNKNOWN	5
+#define  ME_GMES_PHASE_HOST	6
+
+struct me_gmes {
+	u32 reserved: 16;
+	u32 current_state: 8;
+	u32 current_pmevent: 4;
+	u32 progress_code: 4;
+} __attribute__ ((packed));
+
+#define PCI_ME_HERES		0xbc
+#define  PCI_ME_EXT_SHA1	0x00
+#define  PCI_ME_EXT_SHA256	0x02
+#define PCI_ME_HER(x)		(0xc0+(4*(x)))
+
+struct me_heres {
+	u32 extend_reg_algorithm: 4;
+	u32 reserved: 26;
+	u32 extend_feature_present: 1;
+	u32 extend_reg_valid: 1;
+} __attribute__ ((packed));
+
+/*
+ * Management Engine MEI registers
+ */
+
+#define MEI_H_CB_WW		0x00
+#define MEI_H_CSR		0x04
+#define MEI_ME_CB_RW		0x08
+#define MEI_ME_CSR_HA		0x0c
+
+struct mei_csr {
+	u32 interrupt_enable: 1;
+	u32 interrupt_status: 1;
+	u32 interrupt_generate: 1;
+	u32 ready: 1;
+	u32 reset: 1;
+	u32 reserved: 3;
+	u32 buffer_read_ptr: 8;
+	u32 buffer_write_ptr: 8;
+	u32 buffer_depth: 8;
+} __attribute__ ((packed));
+
+#define MEI_ADDRESS_CORE	0x01
+#define MEI_ADDRESS_AMT		0x02
+#define MEI_ADDRESS_RESERVED	0x03
+#define MEI_ADDRESS_WDT		0x04
+#define MEI_ADDRESS_MKHI	0x07
+#define MEI_ADDRESS_ICC		0x08
+#define MEI_ADDRESS_THERMAL	0x09
+
+#define MEI_HOST_ADDRESS	0
+
+struct mei_header {
+	u32 client_address: 8;
+	u32 host_address: 8;
+	u32 length: 9;
+	u32 reserved: 6;
+	u32 is_complete: 1;
+} __attribute__ ((packed));
+
+#define MKHI_GROUP_ID_CBM	0x00
+#define MKHI_GROUP_ID_FWCAPS	0x03
+#define MKHI_GROUP_ID_HMRFPO	0x05
+#define MKHI_GROUP_ID_MDES	0x08
+#define MKHI_GROUP_ID_GEN	0xff
+
+#define MKHI_GLOBAL_RESET	0x0b
+
+#define MKHI_FWCAPS_GET_RULE	0x02
+
+#define MKHI_MDES_ENABLE	0x09
+
+#define MKHI_GET_FW_VERSION	0x02
+#define MKHI_END_OF_POST	0x0c
+#define MKHI_FEATURE_OVERRIDE	0x14
+
+struct mkhi_header {
+	u32 group_id: 8;
+	u32 command: 7;
+	u32 is_response: 1;
+	u32 reserved: 8;
+	u32 result: 8;
+} __attribute__ ((packed));
+
+struct me_fw_version {
+	u16 code_minor;
+	u16 code_major;
+	u16 code_build_number;
+	u16 code_hot_fix;
+	u16 recovery_minor;
+	u16 recovery_major;
+	u16 recovery_build_number;
+	u16 recovery_hot_fix;
+} __attribute__ ((packed));
+
+struct me_fwcaps {
+	u32 id;
+	u8 length;
+	u32 cap_full_network : 1;
+	u32 cap_standard_network: 1;
+	u32 cap_manageability: 1;
+	u32 cap_reserved_0: 2;
+	u32 cap_anti_theft: 1;
+	u32 cap_licensing: 1;
+	u32 cap_virtualization: 1;
+	u32 cap_reserved_1: 2;
+	u32 cap_power_sharing: 1;
+	u32 cap_icc_over_clocking: 1;
+	u32 cap_pavp: 1;
+	u32 cap_reserved_2: 4;
+	u32 cap_ipv6: 1;
+	u32 cap_kvm: 1;
+	u32 cap_och: 1;
+	u32 cap_vlan: 1;
+	u32 cap_tls: 1;
+	u32 cap_reserved_3: 1;
+	u32 cap_wlan: 1;
+	u32 cap_reserved_4: 8;
+	u8 reserved[3];
+} __attribute__ ((packed));
+
+#define CBM_RR_GLOBAL_RESET	0x01
+
+#define GLOBAL_RESET_BIOS_MRC	0x01
+#define GLOBAL_RESET_BIOS_POST	0x02
+#define GLOBAL_RESET_MEBX	0x03
+
+struct me_global_reset {
+	u8 request_origin;
+	u8 reset_type;
+} __attribute__ ((packed));
+
+typedef enum {
+	ME_NORMAL_BIOS_PATH,
+	ME_S3WAKE_BIOS_PATH,
+	ME_ERROR_BIOS_PATH,
+	ME_RECOVERY_BIOS_PATH,
+	ME_DISABLE_BIOS_PATH,
+	ME_FIRMWARE_UPDATE_BIOS_PATH,
+} me_bios_path;
+
+/* Defined in me_status.c for both romstage and ramstage */
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes);
+
+#ifdef __PRE_RAM__
+void intel_early_me_status(void);
+int intel_early_me_init(void);
+int intel_early_me_uma_size(void);
+int intel_early_me_init_done(u8 status);
+#else
+/* ME Kernel Host Interface Messages */
+int mkhi_end_of_post(void);
+int mkhi_global_reset(void);
+int mkhi_get_fwcaps(void);
+int mkhi_get_fw_version(void);
+int mkhi_hmrfpo_status(void);
+int mkhi_hmrfpo_lock(void);
+int mkhi_hmrfpo_enable(void);
+#endif
+
+#ifdef __SMM__
+void intel_me_finalize_smm(void);
+#endif
+
+#endif /* _INTEL_ME_H */
diff --git a/src/southbridge/intel/bd82x6x/me_status.c b/src/southbridge/intel/bd82x6x/me_status.c
new file mode 100644
index 0000000..b2f38d6
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/me_status.c
@@ -0,0 +1,213 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <console/console.h>
+#include "me.h"
+
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+/* HFS1[3:0] Current Working State Values */
+static const char *me_cws_values[] = {
+	[ME_HFS_CWS_RESET]	= "Reset",
+	[ME_HFS_CWS_INIT]	= "Initializing",
+	[ME_HFS_CWS_REC]	= "Recovery",
+	[ME_HFS_CWS_NORMAL]	= "Normal",
+	[ME_HFS_CWS_WAIT]	= "Platform Disable Wait",
+	[ME_HFS_CWS_TRANS]	= "OP State Transition",
+	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In"
+};
+
+/* HFS1[8:6] Current Operation State Values */
+static const char *me_opstate_values[] = {
+	[ME_HFS_STATE_PREBOOT]	= "Preboot",
+	[ME_HFS_STATE_M0_UMA]	= "M0 with UMA",
+	[ME_HFS_STATE_M3]	= "M3 without UMA",
+	[ME_HFS_STATE_M0]	= "M0 without UMA",
+	[ME_HFS_STATE_BRINGUP]	= "Bring up",
+	[ME_HFS_STATE_ERROR]	= "M0 without UMA but with error"
+};
+
+/* HFS[19:16] Current Operation Mode Values */
+static const char *me_opmode_values[] = {
+	[ME_HFS_MODE_NORMAL]	= "Normal",
+	[ME_HFS_MODE_DEBUG]	= "Debug",
+	[ME_HFS_MODE_DIS]	= "Soft Temporary Disable",
+	[ME_HFS_MODE_OVER_JMPR]	= "Security Override via Jumper",
+	[ME_HFS_MODE_OVER_MEI]	= "Security Override via MEI Message"
+};
+
+/* HFS[15:12] Error Code Values */
+static const char *me_error_values[] = {
+	[ME_HFS_ERROR_NONE]	= "No Error",
+	[ME_HFS_ERROR_UNCAT]	= "Uncategorized Failure",
+	[ME_HFS_ERROR_IMAGE]	= "Image Failure",
+	[ME_HFS_ERROR_DEBUG]	= "Debug Failure"
+};
+
+/* GMES[31:28] ME Progress Code */
+static const char *me_progress_values[] = {
+	[ME_GMES_PHASE_ROM]	= "ROM Phase",
+	[ME_GMES_PHASE_BUP]	= "BUP Phase",
+	[ME_GMES_PHASE_UKERNEL]	= "uKernel Phase",
+	[ME_GMES_PHASE_POLICY]	= "Policy Module",
+	[ME_GMES_PHASE_MODULE]	= "Module Loading",
+	[ME_GMES_PHASE_UNKNOWN]	= "Unknown",
+	[ME_GMES_PHASE_HOST]	= "Host Communication"
+};
+
+/* GMES[27:24] Power Management Event */
+static const char *me_pmevent_values[] = {
+	[0x00] = "Clean Moff->Mx wake",
+	[0x01] = "Moff->Mx wake after an error",
+	[0x02] = "Clean global reset",
+	[0x03] = "Global reset after an error",
+	[0x04] = "Clean Intel ME reset",
+	[0x05] = "Intel ME reset due to exception",
+	[0x06] = "Pseudo-global reset",
+	[0x07] = "S0/M0->Sx/M3",
+	[0x08] = "Sx/M3->S0/M0",
+	[0x09] = "Non-power cycle reset",
+	[0x0a] = "Power cycle reset through M3",
+	[0x0b] = "Power cycle reset through Moff",
+	[0x0c] = "Sx/Mx->Sx/Moff"
+};
+
+/* Progress Code 0 states */
+static const char *me_progress_rom_values[] = {
+	[0x00] = "BEGIN",
+	[0x06] = "DISABLE"
+};
+
+/* Progress Code 1 states */
+static const char *me_progress_bup_values[] = {
+	[0x00] = "Initialization starts",
+	[0x01] = "Disable the host wake event",
+	[0x04] = "Flow determination start process",
+	[0x08] = "Error reading/matching the VSCC table in the descriptor",
+	[0x0a] = "Check to see if straps say ME DISABLED",
+	[0x0b] = "Timeout waiting for PWROK",
+	[0x0d] = "Possibly handle BUP manufacturing override strap",
+	[0x11] = "Bringup in M3",
+	[0x12] = "Bringup in M0",
+	[0x13] = "Flow detection error",
+	[0x15] = "M3 clock switching error",
+	[0x18] = "M3 kernel load",
+	[0x1c] = "T34 missing - cannot program ICC",
+	[0x1f] = "Waiting for DID BIOS message",
+	[0x20] = "Waiting for DID BIOS message failure",
+	[0x21] = "DID reported an error",
+	[0x22] = "Enabling UMA",
+	[0x23] = "Enabling UMA error",
+	[0x24] = "Sending DID Ack to BIOS",
+	[0x25] = "Sending DID Ack to BIOS error",
+	[0x26] = "Switching clocks in M0",
+	[0x27] = "Switching clocks in M0 error",
+	[0x28] = "ME in temp disable",
+	[0x32] = "M0 kernel load",
+};
+
+/* Progress Code 3 states */
+static const char *me_progress_policy_values[] = {
+	[0x00] = "Entery into Policy Module",
+	[0x03] = "Received S3 entry",
+	[0x04] = "Received S4 entry",
+	[0x05] = "Received S5 entry",
+	[0x06] = "Received UPD entry",
+	[0x07] = "Received PCR entry",
+	[0x08] = "Received NPCR entry",
+	[0x09] = "Received host wake",
+	[0x0a] = "Received AC<>DC switch",
+	[0x0b] = "Received DRAM Init Done",
+	[0x0c] = "VSCC Data not found for flash device",
+	[0x0d] = "VSCC Table is not valid",
+	[0x0e] = "Flash Partition Boundary is outside address space",
+	[0x0f] = "ME cannot access the chipset descriptor region",
+	[0x10] = "Required VSCC values for flash parts do not match",
+};
+#endif
+
+void intel_me_status(struct me_hfs *hfs, struct me_gmes *gmes)
+{
+#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG)
+	/* Check Current States */
+	printk(BIOS_DEBUG, "ME: FW Partition Table      : %s\n",
+	       hfs->fpt_bad ? "BAD" : "OK");
+	printk(BIOS_DEBUG, "ME: Bringup Loader Failure  : %s\n",
+	       hfs->ft_bup_ld_flr ? "YES" : "NO");
+	printk(BIOS_DEBUG, "ME: Firmware Init Complete  : %s\n",
+	       hfs->fw_init_complete ? "YES" : "NO");
+	printk(BIOS_DEBUG, "ME: Manufacturing Mode      : %s\n",
+	       hfs->mfg_mode ? "YES" : "NO");
+	printk(BIOS_DEBUG, "ME: Boot Options Present    : %s\n",
+	       hfs->boot_options_present ? "YES" : "NO");
+	printk(BIOS_DEBUG, "ME: Update In Progress      : %s\n",
+	       hfs->update_in_progress ? "YES" : "NO");
+	printk(BIOS_DEBUG, "ME: Current Working State   : %s\n",
+	       me_cws_values[hfs->working_state]);
+	printk(BIOS_DEBUG, "ME: Current Operation State : %s\n",
+	       me_opstate_values[hfs->operation_state]);
+	printk(BIOS_DEBUG, "ME: Current Operation Mode  : %s\n",
+	       me_opmode_values[hfs->operation_mode]);
+	printk(BIOS_DEBUG, "ME: Error Code              : %s\n",
+	       me_error_values[hfs->error_code]);
+	printk(BIOS_DEBUG, "ME: Progress Phase          : %s\n",
+	       me_progress_values[gmes->progress_code]);
+	printk(BIOS_DEBUG, "ME: Power Management Event  : %s\n",
+	       me_pmevent_values[gmes->current_pmevent]);
+
+	printk(BIOS_DEBUG, "ME: Progress Phase State    : ");
+	switch (gmes->progress_code) {
+	case ME_GMES_PHASE_ROM:		/* ROM Phase */
+		printk(BIOS_DEBUG, "%s",
+		       me_progress_rom_values[gmes->current_state]);
+		break;
+
+	case ME_GMES_PHASE_BUP:		/* Bringup Phase */
+		if (gmes->current_state < ARRAY_SIZE(me_progress_bup_values)
+		    && me_progress_bup_values[gmes->current_state])
+			printk(BIOS_DEBUG, "%s",
+			       me_progress_bup_values[gmes->current_state]);
+		else
+			printk(BIOS_DEBUG, "0x%02x", gmes->current_state);
+		break;
+
+	case ME_GMES_PHASE_POLICY:	/* Policy Module Phase */
+		if (gmes->current_state < ARRAY_SIZE(me_progress_policy_values)
+		    && me_progress_policy_values[gmes->current_state])
+			printk(BIOS_DEBUG, "%s",
+			       me_progress_policy_values[gmes->current_state]);
+		else
+			printk(BIOS_DEBUG, "0x%02x", gmes->current_state);
+		break;
+
+	case ME_GMES_PHASE_HOST:	/* Host Communication Phase */
+		if (!gmes->current_state)
+			printk(BIOS_DEBUG, "Host communication established");
+		else
+			printk(BIOS_DEBUG, "0x%02x", gmes->current_state);
+		break;
+
+	default:
+		printk(BIOS_DEBUG, "Unknown 0x%02x", gmes->current_state);
+	}
+	printk(BIOS_DEBUG, "\n");
+#endif
+}
diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h
new file mode 100644
index 0000000..3928804
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/nvs.h
@@ -0,0 +1,139 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "vendorcode/google/chromeos/gnvs.h"
+typedef struct {
+	/* Miscellaneous */
+	u16	osys; /* 0x00 - Operating System */
+	u8	smif; /* 0x02 - SMI function call ("TRAP") */
+	u8	prm0; /* 0x03 - SMI function call parameter */
+	u8	prm1; /* 0x04 - SMI function call parameter */
+	u8	scif; /* 0x05 - SCI function call (via _L00) */
+	u8	prm2; /* 0x06 - SCI function call parameter */
+	u8	prm3; /* 0x07 - SCI function call parameter */
+	u8	lckf; /* 0x08 - Global Lock function for EC */
+	u8	prm4; /* 0x09 - Lock function parameter */
+	u8	prm5; /* 0x0a - Lock function parameter */
+	u32	p80d; /* 0x0b - Debug port (IO 0x80) value */
+	u8	lids; /* 0x0f - LID state (open = 1) */
+	u8	pwrs; /* 0x10 - Power state (AC = 1) */
+	/* Thermal policy */
+	u8	tlvl; /* 0x11 - Throttle Level Limit */
+	u8	flvl; /* 0x12 - Current FAN Level */
+	u8	tcrt; /* 0x13 - Critical Threshold */
+	u8	tpsv; /* 0x14 - Passive Threshold */
+	u8	tmax; /* 0x15 - CPU Tj_max */
+	u8	f0of; /* 0x16 - FAN 0 OFF Threshold */
+	u8	f0on; /* 0x17 - FAN 0 ON Threshold */
+	u8	f0pw; /* 0x18 - FAN 0 PWM value */
+	u8	f1of; /* 0x19 - FAN 1 OFF Threshold */
+	u8	f1on; /* 0x1a - FAN 1 ON Threshold */
+	u8	f1pw; /* 0x1b - FAN 1 PWM value */
+	u8	f2of; /* 0x1c - FAN 2 OFF Threshold */
+	u8	f2on; /* 0x1d - FAN 2 ON Threshold */
+	u8	f2pw; /* 0x1e - FAN 2 PWM value */
+	u8	f3of; /* 0x1f - FAN 3 OFF Threshold */
+	u8	f3on; /* 0x20 - FAN 3 ON Threshold */
+	u8	f3pw; /* 0x21 - FAN 3 PWM value */
+	u8	f4of; /* 0x22 - FAN 4 OFF Threshold */
+	u8	f4on; /* 0x23 - FAN 4 ON Threshold */
+	u8	f4pw; /* 0x24 - FAN 4 PWM value */
+	u8	rsvd3[3];
+	/* Processor Identification */
+	u8	apic; /* 0x28 - APIC enabled */
+	u8	mpen; /* 0x29 - MP capable/enabled */
+	u8	pcp0; /* 0x2a - PDC CPU/CORE 0 */
+	u8	pcp1; /* 0x2b - PDC CPU/CORE 1 */
+	u8	ppcm; /* 0x2c - Max. PPC state */
+	u8      pcnt; /* 0x2d - Processor Count */
+	u8	rsvd4[4];
+	/* Super I/O & CMOS config */
+	u8	natp; /* 0x32 - SIO type */
+	u8	s5u0; /* 0x33 - Enable USB0 in S5 */
+	u8	s5u1; /* 0x34 - Enable USB1 in S5 */
+	u8	s3u0; /* 0x35 - Enable USB0 in S3 */
+	u8	s3u1; /* 0x36 - Enable USB1 in S3 */
+	u8	s33g; /* 0x37 - Enable S3 in 3G */
+	u32	cmem; /* 0x38 - CBMEM TOC */
+	/* Integrated Graphics Device */
+	u8	igds; /* 0x3c - IGD state */
+	u8	tlst; /* 0x3d - Display Toggle List Pointer */
+	u8	cadl; /* 0x3e - currently attached devices */
+	u8	padl; /* 0x3f - previously attached devices */
+	u16	cste; /* 0x40 - current display state */
+	u16	nste; /* 0x42 - next display state */
+	u16	sste; /* 0x44 - set display state */
+	u8	ndid; /* 0x46 - number of device ids */
+	u32	did[5]; /* 0x47 - 5b device id 1..5 */
+	u8	rsvd5[0x9];
+	/* Backlight Control */
+	u8	blcs; /* 0x64 - Backlight Control possible */
+	u8	brtl;
+	u8	odds;
+	u8	rsvd6[0x7];
+	/* Ambient Light Sensors*/
+	u8	alse; /* 0x6e - ALS enable */
+	u8	alaf;
+	u8	llow;
+	u8	lhih;
+	u8	rsvd7[0x6];
+	/* EMA */
+	u8	emae; /* 0x78 - EMA enable */
+	u16	emap;
+	u16	emal;
+	u8	rsvd8[0x5];
+	/* MEF */
+	u8	mefe; /* 0x82 - MEF enable */
+	u8	rsvd9[0x9];
+	/* TPM support */
+	u8	tpmp; /* 0x8c - TPM */
+	u8	tpme;
+	u8	rsvd10[8];
+	/* SATA */
+	u8	gtf0[7]; /* 0x96 - GTF task file buffer for port 0 */
+	u8	gtf1[7];
+	u8	gtf2[7];
+	u8	idem;
+	u8	idet;
+	u8	rsvd11[7];
+	/* IGD OpRegion (not implemented yet) */
+	u32	aslb; /* 0xb4 - IGD OpRegion Base Address */
+	u8	ibtt;
+	u8	ipat;
+	u8	itvf;
+	u8	itvm;
+	u8	ipsc;
+	u8	iblc;
+	u8	ibia;
+	u8	issc;
+	u8	i409;
+	u8	i509;
+	u8	i609;
+	u8	i709;
+	u8	idmm;
+	u8	idms;
+	u8	if1e;
+	u8	hvco;
+	u32	nxd[8];
+	u8	rsvd12[8];
+	/* ChromeOS specific (starts at 0xf0)*/
+	chromeos_acpi_t chromeos;
+} __attribute__((packed)) global_nvs_t;
+
diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c
new file mode 100644
index 0000000..31755b1
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/pch.c
@@ -0,0 +1,234 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include "pch.h"
+
+static int pch_revision_id = -1;
+
+int pch_silicon_revision(void)
+{
+	if (pch_revision_id < 0)
+		pch_revision_id = pci_read_config8(
+			dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+			PCI_REVISION_ID);
+	return pch_revision_id;
+}
+
+/* Set bit in Function Disble register to hide this device */
+static void pch_hide_devfn(unsigned devfn)
+{
+	switch (devfn) {
+	case PCI_DEVFN(22, 0): /* MEI #1 */
+		RCBA32_OR(FD2, PCH_DISABLE_MEI1);
+		break;
+	case PCI_DEVFN(22, 1): /* MEI #2 */
+		RCBA32_OR(FD2, PCH_DISABLE_MEI2);
+		break;
+	case PCI_DEVFN(22, 2): /* IDE-R */
+		RCBA32_OR(FD2, PCH_DISABLE_IDER);
+		break;
+	case PCI_DEVFN(22, 3): /* KT */
+		RCBA32_OR(FD2, PCH_DISABLE_KT);
+		break;
+	case PCI_DEVFN(25, 0): /* Gigabit Ethernet */
+		RCBA32_OR(BUC, PCH_DISABLE_GBE);
+		break;
+	case PCI_DEVFN(26, 0): /* EHCI #2 */
+		RCBA32_OR(FD, PCH_DISABLE_EHCI2);
+		break;
+	case PCI_DEVFN(27, 0): /* HD Audio Controller */
+		RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO);
+		break;
+	case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */
+	case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */
+	case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */
+	case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */
+	case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */
+	case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */
+	case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */
+	case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */
+		RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(devfn)));
+		break;
+	case PCI_DEVFN(29, 0): /* EHCI #1 */
+		RCBA32_OR(FD, PCH_DISABLE_EHCI1);
+		break;
+	case PCI_DEVFN(30, 0): /* PCI-to-PCI Bridge */
+		RCBA32_OR(FD, PCH_DISABLE_P2P);
+		break;
+	case PCI_DEVFN(31, 0): /* LPC */
+		RCBA32_OR(FD, PCH_DISABLE_LPC);
+		break;
+	case PCI_DEVFN(31, 2): /* SATA #1 */
+		RCBA32_OR(FD, PCH_DISABLE_SATA1);
+		break;
+	case PCI_DEVFN(31, 3): /* SMBUS */
+		RCBA32_OR(FD, PCH_DISABLE_SMBUS);
+		break;
+	case PCI_DEVFN(31, 5): /* SATA #22 */
+		RCBA32_OR(FD, PCH_DISABLE_SATA2);
+		break;
+	case PCI_DEVFN(31, 6): /* Thermal Subsystem */
+		RCBA32_OR(FD, PCH_DISABLE_THERMAL);
+		break;
+	}
+}
+
+#define IOBP_RETRY 1000
+static inline int iobp_poll(void)
+{
+	unsigned try = IOBP_RETRY;
+	u32 data;
+
+	while (try--) {
+		data = RCBA32(IOBPS);
+		if ((data & 1) == 0)
+			return 1;
+		udelay(10);
+	}
+
+	printk(BIOS_ERR, "IOBP timeout\n");
+	return 0;
+}
+
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
+{
+	u32 data;
+
+	/* Set the address */
+	RCBA32(IOBPIRI) = address;
+
+	/* READ OPCODE */
+	if (pch_silicon_revision() >= PCH_STEP_B0)
+		RCBA32(IOBPS) = IOBPS_RW_BX;
+	else
+		RCBA32(IOBPS) = IOBPS_READ_AX;
+	if (!iobp_poll())
+		return;
+
+	/* Read IOBP data */
+	data = RCBA32(IOBPD);
+	if (!iobp_poll())
+		return;
+
+	/* Check for successful transaction */
+	if ((RCBA32(IOBPS) & 0x6) != 0) {
+		printk(BIOS_ERR, "IOBP read 0x%08x failed\n", address);
+		return;
+	}
+
+	/* Update the data */
+	data &= andvalue;
+	data |= orvalue;
+
+	/* WRITE OPCODE */
+	if (pch_silicon_revision() >= PCH_STEP_B0)
+		RCBA32(IOBPS) = IOBPS_RW_BX;
+	else
+		RCBA32(IOBPS) = IOBPS_WRITE_AX;
+	if (!iobp_poll())
+		return;
+
+	/* Write IOBP data */
+	RCBA32(IOBPD) = data;
+	if (!iobp_poll())
+		return;
+}
+
+/* Check if any port in set X to X+3 is enabled */
+static int pch_pcie_check_set_enabled(device_t dev)
+{
+	device_t port;
+	int port_func;
+	int dev_func = PCI_FUNC(dev->path.pci.devfn);
+
+	printk(BIOS_DEBUG, "%s: check set enabled\n", dev_path(dev));
+
+	/* Go through static device tree list of devices
+	 * because enumeration is still in progress */
+	for (port = all_devices; port; port = port->next) {
+		/* Only care about PCIe root ports */
+		if (PCI_SLOT(port->path.pci.devfn) !=
+		    PCI_SLOT(dev->path.pci.devfn))
+			continue;
+
+		/* Check if port is in range and enabled */
+		port_func = PCI_FUNC(port->path.pci.devfn);
+		if (port_func >= dev_func &&
+		    port_func < (dev_func + 4) &&
+		    port->enabled)
+			return 1;
+	}
+
+	/* None of the ports in this set are enabled */
+	return 0;
+}
+
+void pch_enable(device_t dev)
+{
+	u32 reg32;
+
+	if (!dev->enabled) {
+		printk(BIOS_DEBUG, "%s: Disabling device\n",  dev_path(dev));
+
+		/*
+		 * PCIE Power Savings for stepping B1+:
+		 *
+		 * If PCIe 0-3 disabled set Function 0 0xE2[0] = 1
+		 * If PCIe 4-7 disabled set Function 4 0xE2[0] = 1
+		 *
+		 * This check is done here instead of pcie driver
+		 * because the pcie driver enable() handler is not
+		 * called unless the device is enabled.
+		 */
+		if (pch_silicon_revision() >= PCH_STEP_B1 &&
+		    PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT &&
+		    (PCI_FUNC(dev->path.pci.devfn) == 0 ||
+		     PCI_FUNC(dev->path.pci.devfn) == 4)) {
+			if (!pch_pcie_check_set_enabled(dev)) {
+				u8 reg8 = pci_read_config8(dev, 0xe2);
+				reg8 |= 1;
+				pci_write_config8(dev, 0xe2, reg8);
+			}
+		}
+
+		/* Ensure memory, io, and bus master are all disabled */
+		reg32 = pci_read_config32(dev, PCI_COMMAND);
+		reg32 &= ~(PCI_COMMAND_MASTER |
+			   PCI_COMMAND_MEMORY | PCI_COMMAND_IO	);
+		pci_write_config32(dev, PCI_COMMAND, reg32);
+
+		/* Hide this device if possible */
+		pch_hide_devfn(dev->path.pci.devfn);
+	} else {
+		/* Enable SERR */
+		reg32 = pci_read_config32(dev, PCI_COMMAND);
+		reg32 |= PCI_COMMAND_SERR;
+		pci_write_config32(dev, PCI_COMMAND, reg32);
+	}
+}
+
+struct chip_operations southbridge_intel_bd82x6x_ops = {
+	CHIP_NAME("Intel Series 6 (Cougar Point PCH) Southbridge")
+	.enable_dev = pch_enable,
+};
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h
new file mode 100644
index 0000000..b9255c3
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/pch.h
@@ -0,0 +1,514 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
+#define SOUTHBRIDGE_INTEL_BD82X6X_PCH_H
+
+/* PCH stepping values for LPC device */
+#define PCH_STEP_A0	0
+#define PCH_STEP_A1	1
+#define PCH_STEP_B0	2
+#define PCH_STEP_B1	3
+#define PCH_STEP_B2	4
+#define PCH_STEP_B3	5
+
+/*
+ * It does not matter where we put the SMBus I/O base, as long as we
+ * keep it consistent and don't interfere with other devices.  Stage2
+ * will relocate this anyways.
+ * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * again. But handling static BARs is a generic problem that should be
+ * solved in the device allocator.
+ */
+#define SMBUS_IO_BASE		0x0400
+#define SMBUS_SLAVE_ADDR	0x24
+/* TODO Make sure these don't get changed by stage2 */
+#define DEFAULT_GPIOBASE	0x0480
+#define DEFAULT_PMBASE		0x0500
+
+#define HPET_ADDR		0xfed00000
+#define DEFAULT_RCBA		0xfed1c000
+
+#ifndef __ACPI__
+#define DEBUG_PERIODIC_SMIS 0
+
+#if defined (__SMM__) && !defined(__ASSEMBLER__)
+void intel_pch_finalize_smm(void);
+#endif
+
+#if !defined(__ASSEMBLER__) && !defined(__ROMCC__)
+#if !defined(__PRE_RAM__) && !defined(__SMM__)
+#include "chip.h"
+int pch_silicon_revision(void);
+void pch_enable(device_t dev);
+void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
+#else
+void enable_smbus(void);
+void enable_usb_bar(void);
+int smbus_read_byte(unsigned device, unsigned address);
+#endif
+#endif
+
+#define MAINBOARD_POWER_OFF	0
+#define MAINBOARD_POWER_ON	1
+#define MAINBOARD_POWER_KEEP	2
+
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
+#endif
+
+/* PCI Configuration Space (D30:F0): PCI2PCI */
+#define PSTS	0x06
+#define SMLT	0x1b
+#define SECSTS	0x1e
+#define INTR	0x3c
+#define BCTRL	0x3e
+#define   SBR	(1 << 6)
+#define   SEE	(1 << 1)
+#define   PERE	(1 << 0)
+
+#define PCH_EHCI1_DEV		PCI_DEV(0, 0x1d, 0)
+#define PCH_EHCI2_DEV		PCI_DEV(0, 0x1a, 0)
+#define PCH_ME_DEV		PCI_DEV(0, 0x16, 0)
+#define PCH_PCIE_DEV_SLOT	28
+
+/* PCI Configuration Space (D31:F0): LPC */
+#define PCH_LPC_DEV		PCI_DEV(0, 0x1f, 0)
+#define SERIRQ_CNTL		0x64
+
+#define GEN_PMCON_1		0xa0
+#define GEN_PMCON_2		0xa2
+#define GEN_PMCON_3		0xa4
+#define ETR3			0xac
+#define  ETR3_CWORWRE		(1 << 18)
+#define  ETR3_CF9GR		(1 << 20)
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD	(1 << 2)
+#define RTC_POWER_FAILED	(1 << 1)
+#define SLEEP_AFTER_POWER_FAIL	(1 << 0)
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+#define BIOS_CNTL		0xDC
+#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
+#define GPIO_ROUT		0xb8
+
+#define PIRQA_ROUT		0x60
+#define PIRQB_ROUT		0x61
+#define PIRQC_ROUT		0x62
+#define PIRQD_ROUT		0x63
+#define PIRQE_ROUT		0x68
+#define PIRQF_ROUT		0x69
+#define PIRQG_ROUT		0x6A
+#define PIRQH_ROUT		0x6B
+
+#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define LPC_EN			0x82 /* LPC IF Enables Register */
+#define  CNF2_LPC_EN		(1 << 13) /* 0x4e/0x4f */
+#define  CNF1_LPC_EN		(1 << 12) /* 0x2e/0x2f */
+#define  MC_LPC_EN		(1 << 11) /* 0x62/0x66 */
+#define  KBC_LPC_EN		(1 << 10) /* 0x60/0x64 */
+#define  GAMEH_LPC_EN		(1 << 9)  /* 0x208/0x20f */
+#define  GAMEL_LPC_EN		(1 << 8)  /* 0x200/0x207 */
+#define  FDD_LPC_EN		(1 << 3)  /* LPC_IO_DEC[12] */
+#define  LPT_LPC_EN		(1 << 2)  /* LPC_IO_DEC[9:8] */
+#define  COMB_LPC_EN		(1 << 1)  /* LPC_IO_DEC[6:4] */
+#define  COMA_LPC_EN		(1 << 0)  /* LPC_IO_DEC[3:2] */
+#define LPC_GEN1_DEC		0x84 /* LPC IF Generic Decode Range 1 */
+#define LPC_GEN2_DEC		0x88 /* LPC IF Generic Decode Range 2 */
+#define LPC_GEN3_DEC		0x8c /* LPC IF Generic Decode Range 3 */
+#define LPC_GEN4_DEC		0x90 /* LPC IF Generic Decode Range 4 */
+
+/* PCI Configuration Space (D31:F1): IDE */
+#define PCH_IDE_DEV		PCI_DEV(0, 0x1f, 1)
+#define PCH_SATA_DEV		PCI_DEV(0, 0x1f, 2)
+#define PCH_SATA2_DEV		PCI_DEV(0, 0x1f, 5)
+#define INTR_LN			0x3c
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define   IDE_DECODE_ENABLE	(1 << 15)
+#define   IDE_SITRE		(1 << 14)
+#define   IDE_ISP_5_CLOCKS	(0 << 12)
+#define   IDE_ISP_4_CLOCKS	(1 << 12)
+#define   IDE_ISP_3_CLOCKS	(2 << 12)
+#define   IDE_RCT_4_CLOCKS	(0 <<  8)
+#define   IDE_RCT_3_CLOCKS	(1 <<  8)
+#define   IDE_RCT_2_CLOCKS	(2 <<  8)
+#define   IDE_RCT_1_CLOCKS	(3 <<  8)
+#define   IDE_DTE1		(1 <<  7)
+#define   IDE_PPE1		(1 <<  6)
+#define   IDE_IE1		(1 <<  5)
+#define   IDE_TIME1		(1 <<  4)
+#define   IDE_DTE0		(1 <<  3)
+#define   IDE_PPE0		(1 <<  2)
+#define   IDE_IE0		(1 <<  1)
+#define   IDE_TIME0		(1 <<  0)
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+
+#define IDE_SDMA_CNT		0x48	/* Synchronous DMA control */
+#define   IDE_SSDE1		(1 <<  3)
+#define   IDE_SSDE0		(1 <<  2)
+#define   IDE_PSDE1		(1 <<  1)
+#define   IDE_PSDE0		(1 <<  0)
+
+#define IDE_SDMA_TIM		0x4a
+
+#define IDE_CONFIG		0x54	/* IDE I/O Configuration Register */
+#define   SIG_MODE_SEC_NORMAL	(0 << 18)
+#define   SIG_MODE_SEC_TRISTATE	(1 << 18)
+#define   SIG_MODE_SEC_DRIVELOW	(2 << 18)
+#define   SIG_MODE_PRI_NORMAL	(0 << 16)
+#define   SIG_MODE_PRI_TRISTATE	(1 << 16)
+#define   SIG_MODE_PRI_DRIVELOW	(2 << 16)
+#define   FAST_SCB1		(1 << 15)
+#define   FAST_SCB0		(1 << 14)
+#define   FAST_PCB1		(1 << 13)
+#define   FAST_PCB0		(1 << 12)
+#define   SCB1			(1 <<  3)
+#define   SCB0			(1 <<  2)
+#define   PCB1			(1 <<  1)
+#define   PCB0			(1 <<  0)
+
+#define SATA_SP			0xd0 /* Scratchpad */
+
+/* PCI Configuration Space (D31:F3): SMBus */
+#define PCH_SMBUS_DEV		PCI_DEV(0, 0x1f, 3)
+#define SMB_BASE		0x20
+#define HOSTC			0x40
+#define SMB_RCV_SLVA		0x09
+
+/* HOSTC bits */
+#define I2C_EN			(1 << 2)
+#define SMB_SMI_EN		(1 << 1)
+#define HST_EN			(1 << 0)
+
+/* SMBus I/O bits. */
+#define SMBHSTSTAT		0x0
+#define SMBHSTCTL		0x2
+#define SMBHSTCMD		0x3
+#define SMBXMITADD		0x4
+#define SMBHSTDAT0		0x5
+#define SMBHSTDAT1		0x6
+#define SMBBLKDAT		0x7
+#define SMBTRNSADD		0x9
+#define SMBSLVDATA		0xa
+#define SMLINK_PIN_CTL		0xe
+#define SMBUS_PIN_CTL		0xf
+
+#define SMBUS_TIMEOUT		(10 * 1000 * 100)
+
+
+/* Southbridge IO BARs */
+
+#define GPIOBASE		0x48
+
+#define PMBASE		0x40
+
+/* Root Complex Register Block */
+#define RCBA		0xf0
+
+#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
+#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
+#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
+
+#define RCBA_AND_OR(bits, x, and, or) \
+        RCBA##bits(x) = ((RCBA##bits(x) & (and)) | (or))
+#define RCBA8_AND_OR(x, and, or)  RCBA_AND_OR(8, x, and, or)
+#define RCBA16_AND_OR(x, and, or) RCBA_AND_OR(16, x, and, or)
+#define RCBA32_AND_OR(x, and, or) RCBA_AND_OR(32, x, and, or)
+#define RCBA32_OR(x, or) RCBA_AND_OR(32, x, ~0UL, or)
+
+#define VCH		0x0000	/* 32bit */
+#define VCAP1		0x0004	/* 32bit */
+#define VCAP2		0x0008	/* 32bit */
+#define PVC		0x000c	/* 16bit */
+#define PVS		0x000e	/* 16bit */
+
+#define V0CAP		0x0010	/* 32bit */
+#define V0CTL		0x0014	/* 32bit */
+#define V0STS		0x001a	/* 16bit */
+
+#define V1CAP		0x001c	/* 32bit */
+#define V1CTL		0x0020	/* 32bit */
+#define V1STS		0x0026	/* 16bit */
+
+#define RCTCL		0x0100	/* 32bit */
+#define ESD		0x0104	/* 32bit */
+#define ULD		0x0110	/* 32bit */
+#define ULBA		0x0118	/* 64bit */
+
+#define RP1D		0x0120	/* 32bit */
+#define RP1BA		0x0128	/* 64bit */
+#define RP2D		0x0130	/* 32bit */
+#define RP2BA		0x0138	/* 64bit */
+#define RP3D		0x0140	/* 32bit */
+#define RP3BA		0x0148	/* 64bit */
+#define RP4D		0x0150	/* 32bit */
+#define RP4BA		0x0158	/* 64bit */
+#define HDD		0x0160	/* 32bit */
+#define HDBA		0x0168	/* 64bit */
+#define RP5D		0x0170	/* 32bit */
+#define RP5BA		0x0178	/* 64bit */
+#define RP6D		0x0180	/* 32bit */
+#define RP6BA		0x0188	/* 64bit */
+
+#define RPC		0x0224	/* 32bit */
+#define RPFN		0x0238	/* 32bit */
+
+#define TRSR		0x1e00	/*  8bit */
+#define TRCR		0x1e10	/* 64bit */
+#define TWDR		0x1e18	/* 64bit */
+
+#define IOTR0		0x1e80	/* 64bit */
+#define IOTR1		0x1e88	/* 64bit */
+#define IOTR2		0x1e90	/* 64bit */
+#define IOTR3		0x1e98	/* 64bit */
+
+#define TCTL		0x3000	/*  8bit */
+
+#define NOINT		0
+#define INTA		1
+#define INTB		2
+#define INTC		3
+#define INTD		4
+
+#define DIR_IDR		12	/* Interrupt D Pin Offset */
+#define DIR_ICR		8	/* Interrupt C Pin Offset */
+#define DIR_IBR		4	/* Interrupt B Pin Offset */
+#define DIR_IAR		0	/* Interrupt A Pin Offset */
+
+#define PIRQA		0
+#define PIRQB		1
+#define PIRQC		2
+#define PIRQD		3
+#define PIRQE		4
+#define PIRQF		5
+#define PIRQG		6
+#define PIRQH		7
+
+/* IO Buffer Programming */
+#define IOBPIRI		0x2330
+#define IOBPD		0x2334
+#define IOBPS		0x2338
+#define  IOBPS_RW_BX    ((1 << 9)|(1 << 10))
+#define  IOBPS_WRITE_AX	((1 << 9)|(1 << 10))
+#define  IOBPS_READ_AX	((1 << 8)|(1 << 9)|(1 << 10))
+
+#define D31IP		0x3100	/* 32bit */
+#define D31IP_TTIP	24	/* Thermal Throttle Pin */
+#define D31IP_SIP2	20	/* SATA Pin 2 */
+#define D31IP_SMIP	12	/* SMBUS Pin */
+#define D31IP_SIP	8	/* SATA Pin */
+#define D30IP		0x3104	/* 32bit */
+#define D30IP_PIP	0	/* PCI Bridge Pin */
+#define D29IP		0x3108	/* 32bit */
+#define D29IP_E1P	0	/* EHCI #1 Pin */
+#define D28IP		0x310c	/* 32bit */
+#define D28IP_P8IP	28	/* PCI Express Port 8 */
+#define D28IP_P7IP	24	/* PCI Express Port 7 */
+#define D28IP_P6IP	20	/* PCI Express Port 6 */
+#define D28IP_P5IP	16	/* PCI Express Port 5 */
+#define D28IP_P4IP	12	/* PCI Express Port 4 */
+#define D28IP_P3IP	8	/* PCI Express Port 3 */
+#define D28IP_P2IP	4	/* PCI Express Port 2 */
+#define D28IP_P1IP	0	/* PCI Express Port 1 */
+#define D27IP		0x3110	/* 32bit */
+#define D27IP_ZIP	0	/* HD Audio Pin */
+#define D26IP		0x3114	/* 32bit */
+#define D26IP_E2P	0	/* EHCI #2 Pin */
+#define D25IP		0x3118	/* 32bit */
+#define D25IP_LIP	0	/* GbE LAN Pin */
+#define D22IP		0x3124	/* 32bit */
+#define D22IP_KTIP	12	/* KT Pin */
+#define D22IP_IDERIP	8	/* IDE-R Pin */
+#define D22IP_MEI2IP	4	/* MEI #2 Pin */
+#define D22IP_MEI1IP	0	/* MEI #1 Pin */
+#define D31IR		0x3140	/* 16bit */
+#define D30IR		0x3142	/* 16bit */
+#define D29IR		0x3144	/* 16bit */
+#define D28IR		0x3146	/* 16bit */
+#define D27IR		0x3148	/* 16bit */
+#define D26IR		0x314c	/* 16bit */
+#define D25IR		0x3150	/* 16bit */
+#define D22IR		0x315c	/* 16bit */
+#define OIC		0x31ff	/*  8bit */
+
+#define DIR_ROUTE(x,a,b,c,d) \
+  RCBA32(x) = (((d) << DIR_IDR) | ((c) << DIR_ICR) | \
+               ((b) << DIR_IBR) | ((a) << DIR_IAR))
+
+#define RC		0x3400	/* 32bit */
+#define HPTC		0x3404	/* 32bit */
+#define GCS		0x3410	/* 32bit */
+#define BUC		0x3414	/* 32bit */
+#define PCH_DISABLE_GBE		(1 << 5)
+#define FD		0x3418	/* 32bit */
+#define DISPBDF		0x3424  /* 16bit */
+#define FD2		0x3428	/* 32bit */
+#define CG		0x341c	/* 32bit */
+
+/* Function Disable 1 RCBA 0x3418 */
+#define PCH_DISABLE_ALWAYS	((1 << 0)|(1 << 26)|(1 << 27))
+#define PCH_DISABLE_P2P		(1 << 1)
+#define PCH_DISABLE_SATA1	(1 << 2)
+#define PCH_DISABLE_SMBUS	(1 << 3)
+#define PCH_DISABLE_HD_AUDIO	(1 << 4)
+#define PCH_DISABLE_EHCI2	(1 << 13)
+#define PCH_DISABLE_LPC		(1 << 14)
+#define PCH_DISABLE_EHCI1	(1 << 15)
+#define PCH_DISABLE_PCIE(x)	(1 << (16 + x))
+#define PCH_DISABLE_THERMAL	(1 << 24)
+#define PCH_DISABLE_SATA2	(1 << 25)
+
+/* Function Disable 2 RCBA 0x3428 */
+#define PCH_DISABLE_KT		(1 << 4)
+#define PCH_DISABLE_IDER	(1 << 3)
+#define PCH_DISABLE_MEI2	(1 << 2)
+#define PCH_DISABLE_MEI1	(1 << 1)
+#define PCH_ENABLE_DBDF		(1 << 0)
+
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL	0x00
+#define GP_IO_SEL	0x04
+#define GP_LVL		0x0c
+#define GPO_BLINK	0x18
+#define GPI_INV		0x2c
+#define GPIO_USE_SEL2	0x30
+#define GP_IO_SEL2	0x34
+#define GP_LVL2		0x38
+#define GPIO_USE_SEL3	0x40
+#define GP_IO_SEL3	0x44
+#define GP_LVL3		0x48
+#define GP_RST_SEL1	0x60
+#define GP_RST_SEL2	0x64
+#define GP_RST_SEL3	0x68
+
+/* ICH7 PMBASE */
+#define PM1_STS		0x00
+#define   WAK_STS	(1 << 15)
+#define   PCIEXPWAK_STS	(1 << 14)
+#define   PRBTNOR_STS	(1 << 11)
+#define   RTC_STS	(1 << 10)
+#define   PWRBTN_STS	(1 << 8)
+#define   GBL_STS	(1 << 5)
+#define   BM_STS	(1 << 4)
+#define   TMROF_STS	(1 << 0)
+#define PM1_EN		0x02
+#define   PCIEXPWAK_DIS	(1 << 14)
+#define   RTC_EN	(1 << 10)
+#define   PWRBTN_EN	(1 << 8)
+#define   GBL_EN	(1 << 5)
+#define   TMROF_EN	(1 << 0)
+#define PM1_CNT		0x04
+#define   SLP_EN	(1 << 13)
+#define   SLP_TYP	(7 << 10)
+#define    SLP_TYP_S0	0
+#define    SLP_TYP_S1	1
+#define    SLP_TYP_S3	5
+#define    SLP_TYP_S4	6
+#define    SLP_TYP_S5	7
+#define   GBL_RLS	(1 << 2)
+#define   BM_RLD	(1 << 1)
+#define   SCI_EN	(1 << 0)
+#define PM1_TMR		0x08
+#define PROC_CNT	0x10
+#define LV2		0x14
+#define LV3		0x15
+#define LV4		0x16
+#define PM2_CNT		0x50 // mobile only
+#define GPE0_STS	0x20
+#define   PME_B0_STS	(1 << 13)
+#define   PME_STS	(1 << 11)
+#define   BATLOW_STS	(1 << 10)
+#define   PCI_EXP_STS	(1 << 9)
+#define   RI_STS	(1 << 8)
+#define   SMB_WAK_STS	(1 << 7)
+#define   TCOSCI_STS	(1 << 6)
+#define   SWGPE_STS	(1 << 2)
+#define   HOT_PLUG_STS	(1 << 1)
+#define GPE0_EN		0x28
+#define   PME_B0_EN	(1 << 13)
+#define   PME_EN	(1 << 11)
+#define SMI_EN		0x30
+#define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
+#define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define   PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define   TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define   MCSMI_EN	 (1 << 11) // Trap microcontroller range access
+#define   BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
+#define   SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
+#define   APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
+#define   SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
+#define   BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
+#define   EOS		 (1 <<  1) // End of SMI (deassert SMI#)
+#define   GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
+#define SMI_STS		0x34
+#define ALT_GP_SMI_EN	0x38
+#define ALT_GP_SMI_STS	0x3a
+#define GPE_CNTL	0x42
+#define DEVACT_STS	0x44
+#define SS_CNT		0x50
+#define C3_RES		0x54
+
+/*
+ * SPI Opcode Menu setup for SPIBAR lockdown
+ * should support most common flash chips.
+ */
+
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x52 /* BE52: Block Erase 0x52 */
+#define SPI_OPTYPE_7 0x03 /* Write, address required */
+
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+			  (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
+
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) |  \
+		    (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) |	  \
+		    (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+
+#endif /* __ACPI__ */
+#endif				/* SOUTHBRIDGE_INTEL_BD82X6X_PCH_H */
diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c
new file mode 100644
index 0000000..845a6fe
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/pci.c
@@ -0,0 +1,145 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+
+static void pci_init(struct device *dev)
+{
+	u16 reg16;
+	u8 reg8;
+
+	printk(BIOS_DEBUG, "PCI init.\n");
+	/* Enable Bus Master */
+	reg16 = pci_read_config16(dev, PCI_COMMAND);
+	reg16 |= PCI_COMMAND_MASTER;
+	pci_write_config16(dev, PCI_COMMAND, reg16);
+
+	/* This device has no interrupt */
+	pci_write_config8(dev, INTR, 0xff);
+
+	/* disable parity error response and SERR */
+	reg16 = pci_read_config16(dev, BCTRL);
+	reg16 &= ~(1 << 0);
+	reg16 &= ~(1 << 1);
+	pci_write_config16(dev, BCTRL, reg16);
+
+	/* Master Latency Count must be set to 0x04! */
+	reg8 = pci_read_config8(dev, SMLT);
+	reg8 &= 0x07;
+	reg8 |= (0x04 << 3);
+	pci_write_config8(dev, SMLT, reg8);
+
+	/* Will this improve throughput of bus masters? */
+	pci_write_config8(dev, PCI_MIN_GNT, 0x06);
+
+	/* Clear errors in status registers */
+	reg16 = pci_read_config16(dev, PSTS);
+	//reg16 |= 0xf900;
+	pci_write_config16(dev, PSTS, reg16);
+
+	reg16 = pci_read_config16(dev, SECSTS);
+	// reg16 |= 0xf900;
+	pci_write_config16(dev, SECSTS, reg16);
+}
+
+#undef PCI_BRIDGE_UPDATE_COMMAND
+static void ich_pci_dev_enable_resources(struct device *dev)
+{
+	const struct pci_operations *ops;
+	uint16_t command;
+
+	/* Set the subsystem vendor and device id for mainboard devices */
+	ops = ops_pci(dev);
+	if (dev->on_mainboard && ops && ops->set_subsystem) {
+		printk(BIOS_DEBUG, "%s subsystem <- %02x/%02x\n",
+			dev_path(dev),
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+		ops->set_subsystem(dev,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID,
+			CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID);
+	}
+
+	command = pci_read_config16(dev, PCI_COMMAND);
+	command |= dev->command;
+#ifdef PCI_BRIDGE_UPDATE_COMMAND
+	/* If we write to PCI_COMMAND, on some systems
+	 * this will cause the ROM and APICs not being visible
+	 * anymore.
+	 */
+	printk(BIOS_DEBUG, "%s cmd <- %02x\n", dev_path(dev), command);
+	pci_write_config16(dev, PCI_COMMAND, command);
+#else
+	printk(BIOS_DEBUG, "%s cmd <- %02x (NOT WRITTEN!)\n", dev_path(dev), command);
+#endif
+}
+
+static void ich_pci_bus_enable_resources(struct device *dev)
+{
+	uint16_t ctrl;
+	/* enable IO in command register if there is VGA card
+	 * connected with (even it does not claim IO resource)
+	 */
+	if (dev->link_list->bridge_ctrl & PCI_BRIDGE_CTL_VGA)
+		dev->command |= PCI_COMMAND_IO;
+	ctrl = pci_read_config16(dev, PCI_BRIDGE_CONTROL);
+	ctrl |= dev->link_list->bridge_ctrl;
+	ctrl |= (PCI_BRIDGE_CTL_PARITY + PCI_BRIDGE_CTL_SERR); /* error check */
+	printk(BIOS_DEBUG, "%s bridge ctrl <- %04x\n", dev_path(dev), ctrl);
+	pci_write_config16(dev, PCI_BRIDGE_CONTROL, ctrl);
+
+	/* This is the reason we need our own pci_bus_enable_resources */
+	ich_pci_dev_enable_resources(dev);
+}
+
+static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* NOTE: This is not the default position! */
+	if (!vendor || !device) {
+		pci_write_config32(dev, 0x54,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, 0x54,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= ich_pci_bus_enable_resources,
+	.init			= pci_init,
+	.scan_bus		= pci_scan_bridge,
+	.ops_pci		= &pci_ops,
+};
+
+static const struct pci_driver pch_pci __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x2448,
+};
diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c
new file mode 100644
index 0000000..f867ca9
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/pcie.c
@@ -0,0 +1,288 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pciexp.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+
+static u16 pcie_port_link_width(int port)
+{
+	u16 link_width;
+
+	link_width = pci_read_config16(
+		dev_find_slot(0, PCI_DEVFN(0x1c, port)), 0x52);
+	link_width >>= 4;
+	link_width &= 0x3f;
+	return link_width;
+}
+
+static void pch_pcie_pm_early(struct device *dev)
+{
+	u16 link_width_p0, link_width_p4;
+	u8 slot_power_limit = 10; /* 10W for x1 */
+	u32 reg32;
+	u8 reg8;
+
+	link_width_p0 = pcie_port_link_width(0);
+	link_width_p4 = pcie_port_link_width(4);
+
+	/* Enable dynamic clock gating where needed */
+	reg8 = pci_read_config8(dev, 0xe1);
+	switch (PCI_FUNC(dev->path.pci.devfn)) {
+	case 0: /* Port 0 */
+		if (link_width_p0 == 4)
+			slot_power_limit = 40; /* 40W for x4 */
+		else if (link_width_p0 == 2)
+			slot_power_limit = 20; /* 20W for x2 */
+	case 4: /* Port 4 */
+		if (link_width_p4 == 4)
+			slot_power_limit = 40; /* 40W for x4 */
+		else if (link_width_p4 == 2)
+			slot_power_limit = 20; /* 20W for x2 */
+		reg8 |= 0x3f;
+		break;
+	case 1: /* Port 1 only if Port 0 is x1 */
+		if (link_width_p0 == 1)
+			reg8 |= 0x3;
+		break;
+	case 2: /* Port 2 only if Port 0 is x1 or x2 */
+	case 3: /* Port 3 only if Port 0 is x1 or x2 */
+		if (link_width_p0 <= 2)
+			reg8 |= 0x3;
+		break;
+	case 5: /* Port 5 only if Port 4 is x1 */
+		if (link_width_p4 == 1)
+			reg8 |= 0x3;
+		break;
+	case 6: /* Port 7 only if Port 4 is x1 or x2 */
+	case 7: /* Port 7 only if Port 4 is x1 or x2 */
+		if (link_width_p4 <= 2)
+			reg8 |= 0x3;
+		break;
+	}
+	pci_write_config8(dev, 0xe1, reg8);
+
+	/* Set 0xE8[0] = 1 */
+	reg32 = pci_read_config32(dev, 0xe8);
+	reg32 |= 1;
+	pci_write_config32(dev, 0xe8, reg32);
+
+	/* Adjust Common Clock exit latency */
+	reg32 = pci_read_config32(dev, 0xd8);
+	reg32 &= ~(1 << 17);
+	reg32 |= (1 << 16) | (1 << 15);
+	reg32 &= ~(1 << 31); /* Disable PME# SCI for native PME handling */
+	pci_write_config32(dev, 0xd8, reg32);
+
+	/* Adjust ASPM L1 exit latency */
+	reg32 = pci_read_config32(dev, 0x4c);
+	reg32 &= ~((1 << 17) | (1 << 16) | (1 << 15));
+	if (RCBA32(0x2320) & (1 << 16)) {
+		/* If RCBA+2320[15]=1 set ASPM L1 to 8-16us */
+		reg32 |= (1 << 17);
+	} else {
+		/* Else set ASPM L1 to 2-4us */
+		reg32 |= (1 << 16);
+	}
+	pci_write_config32(dev, 0x4c, reg32);
+
+	/* Set slot power limit as configured above */
+	reg32 = pci_read_config32(dev, 0x54);
+	reg32 &= ~((1 << 15) | (1 << 16)); /* 16:15 = Slot power scale */
+	reg32 &= ~(0xff << 7);             /* 14:7  = Slot power limit */
+	reg32 |= (slot_power_limit << 7);
+	pci_write_config32(dev, 0x54, reg32);
+}
+
+static void pch_pcie_pm_late(struct device *dev)
+{
+	enum aspm_type apmc;
+	u32 reg32;
+
+	/* Set 0x314 = 0x743a361b */
+	pci_mmio_write_config32(dev, 0x314, 0x743a361b);
+
+	/* Set 0x318[31:16] = 0x1414 */
+	reg32 = pci_mmio_read_config32(dev, 0x318);
+	reg32 &= 0x0000ffff;
+	reg32 |= 0x14140000;
+	pci_mmio_write_config32(dev, 0x318, reg32);
+
+	/* Set 0x324[5] = 1 */
+	reg32 = pci_mmio_read_config32(dev, 0x324);
+	reg32 |= (1 << 5);
+	pci_mmio_write_config32(dev, 0x324, reg32);
+
+	/* Set 0x330[7:0] = 0x40 */
+	reg32 = pci_mmio_read_config32(dev, 0x330);
+	reg32 &= ~(0xff);
+	reg32 |= 0x40;
+	pci_mmio_write_config32(dev, 0x330, reg32);
+
+	/* Set 0x33C[24:0] = 0x854c74 */
+	reg32 = pci_mmio_read_config32(dev, 0x33c);
+	reg32 &= 0xff000000;
+	reg32 |= 0x00854c74;
+	pci_mmio_write_config32(dev, 0x33c, reg32);
+
+	/* No IO-APIC, Disable EOI forwarding */
+	reg32 = pci_read_config32(dev, 0xd4);
+	reg32 |= (1 << 1);
+	pci_write_config32(dev, 0xd4, reg32);
+
+	/* Get configured ASPM state */
+	apmc = pci_read_config32(dev, 0x50) & 3;
+
+	/* If both L0s and L1 enabled then set root port 0xE8[1]=1 */
+	if (apmc == PCIE_ASPM_BOTH) {
+		reg32 = pci_read_config32(dev, 0xe8);
+		reg32 |= (1 << 1);
+		pci_write_config32(dev, 0xe8, reg32);
+	}
+}
+
+static void pci_init(struct device *dev)
+{
+	u16 reg16;
+	u32 reg32;
+
+	printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
+
+	/* Enable Bus Master */
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	/* Set Cache Line Size to 0x10 */
+	// This has no effect but the OS might expect it
+	pci_write_config8(dev, 0x0c, 0x10);
+
+	reg16 = pci_read_config16(dev, 0x3e);
+	reg16 &= ~(1 << 0); /* disable parity error response */
+	// reg16 &= ~(1 << 1); /* disable SERR */
+	reg16 |= (1 << 2); /* ISA enable */
+	pci_write_config16(dev, 0x3e, reg16);
+
+#ifdef EVEN_MORE_DEBUG
+	reg32 = pci_read_config32(dev, 0x20);
+	printk(BIOS_SPEW, "    MBL    = 0x%08x\n", reg32);
+	reg32 = pci_read_config32(dev, 0x24);
+	printk(BIOS_SPEW, "    PMBL   = 0x%08x\n", reg32);
+	reg32 = pci_read_config32(dev, 0x28);
+	printk(BIOS_SPEW, "    PMBU32 = 0x%08x\n", reg32);
+	reg32 = pci_read_config32(dev, 0x2c);
+	printk(BIOS_SPEW, "    PMLU32 = 0x%08x\n", reg32);
+#endif
+
+	/* Clear errors in status registers */
+	reg16 = pci_read_config16(dev, 0x06);
+	//reg16 |= 0xf900;
+	pci_write_config16(dev, 0x06, reg16);
+
+	reg16 = pci_read_config16(dev, 0x1e);
+	//reg16 |= 0xf900;
+	pci_write_config16(dev, 0x1e, reg16);
+
+	/* Power Management init after enumeration */
+	pch_pcie_pm_late(dev);
+}
+
+static void pch_pcie_enable(device_t dev)
+{
+	/* Power Management init before enumeration */
+	pch_pcie_pm_early(dev);
+}
+
+static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	/* NOTE: This is not the default position! */
+	if (!vendor || !device) {
+		pci_write_config32(dev, 0x94,
+				pci_read_config32(dev, 0));
+	} else {
+		pci_write_config32(dev, 0x94,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations pci_ops = {
+	.set_subsystem = pcie_set_subsystem,
+};
+
+static struct device_operations device_ops = {
+	.read_resources		= pci_bus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_bus_enable_resources,
+	.init			= pci_init,
+	.enable			= pch_pcie_enable,
+	.scan_bus		= pciexp_scan_bridge,
+	.ops_pci		= &pci_ops,
+};
+
+static const struct pci_driver pch_pcie_port1 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c10,	/* D28:F0 */
+};
+
+static const struct pci_driver pch_pcie_port2 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c12,	/* D28:F1 */
+};
+
+static const struct pci_driver pch_pcie_port3 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c14,	/* D28:F2 */
+};
+
+static const struct pci_driver pch_pcie_port4 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c16,	/* D28:F3 */
+};
+
+static const struct pci_driver pch_pcie_port5 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c18,	/* D28:F4 */
+};
+
+static const struct pci_driver pch_pcie_port6 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c1a,	/* D28:F5 */
+};
+
+static const struct pci_driver pch_pcie_port7 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c1c,	/* D28:F6 */
+};
+
+static const struct pci_driver pch_pcie_port8 __pci_driver = {
+	.ops	= &device_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c1e,	/* D28:F7 */
+};
diff --git a/src/southbridge/intel/bd82x6x/reset.c b/src/southbridge/intel/bd82x6x/reset.c
new file mode 100644
index 0000000..29b69ff
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/reset.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <reset.h>
+
+void soft_reset(void)
+{
+        outb(0x04, 0xcf9);
+}
+
+#if 0
+void hard_reset(void)
+{
+	/* Try rebooting through port 0xcf9. */
+	outb((1 << 2) | (1 << 1), 0xcf9);
+}
+#endif
+
+void hard_reset(void)
+{
+        outb(0x02, 0xcf9);
+        outb(0x06, 0xcf9);
+}
diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c
new file mode 100644
index 0000000..d7e00ab
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/sata.c
@@ -0,0 +1,241 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+
+typedef struct southbridge_intel_bd82x6x_config config_t;
+
+static void sata_init(struct device *dev)
+{
+	u32 reg32;
+	u16 reg16;
+	/* Get the chip configuration */
+	config_t *config = dev->chip_info;
+
+	printk(BIOS_DEBUG, "pch_sata: initializing...\n");
+
+	if (config == NULL) {
+		printk(BIOS_ERR, "pch_sata: error: device not in devicetree.cb!\n");
+		return;
+	}
+
+	/* SATA configuration */
+
+	/* Enable BARs */
+	pci_write_config16(dev, PCI_COMMAND, 0x0007);
+
+	if (config->ide_legacy_combined) {
+		printk(BIOS_DEBUG, "SATA controller in combined mode.\n");
+		/* Combine IDE - SATA configuration */
+		pci_write_config16(dev, 0x90, 0x0000);
+
+		/* No AHCI: clear AHCI base */
+		pci_write_config32(dev, 0x24, 0x00000000);
+		/* And without AHCI BAR no memory decoding */
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 &= ~PCI_COMMAND_MEMORY;
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+
+		pci_write_config8(dev, 0x09, 0x80);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0200);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* Port enable */
+		reg16 = pci_read_config16(dev, 0x92);
+		reg16 &= ~0x3f;
+		reg16 |= config->sata_port_map;
+		pci_write_config16(dev, 0x92, reg16);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94,
+			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
+	} else if(config->sata_ahci) {
+		u32 abar;
+
+		printk(BIOS_DEBUG, "SATA controller in AHCI mode.\n");
+		/* Set Sata Controller Mode. */
+		pci_write_config16(dev, 0x90, 0x0060 |
+				   ((config->sata_port_map ^ 0x3f) << 8));
+
+		/* Set Interrupt Line */
+		/* Interrupt Pin is set by D31IP.PIP */
+		pci_write_config8(dev, INTR_LN, 0x0a);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_PSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0001);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* for AHCI, Port Enable is managed in memory mapped space */
+		reg16 = pci_read_config16(dev, 0x92);
+		reg16 &= ~0x3f; /* 6 ports SKU + ORM */
+		reg16 |= 0x8000 | config->sata_port_map;
+		pci_write_config16(dev, 0x92, reg16);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94,
+			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
+
+		/* Initialize AHCI memory-mapped space */
+		abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+		printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
+		/* CAP (HBA Capabilities) : enable power management */
+		reg32 = read32(abar + 0x00);
+		reg32 |= 0x0c006000;  // set PSC+SSC+SALP+SSS
+		reg32 &= ~0x00020060; // clear SXS+EMS+PMS
+		write32(abar + 0x00, reg32);
+		/* PI (Ports implemented) */
+		write32(abar + 0x0c, config->sata_port_map);
+		(void) read32(abar + 0x0c); /* Read back 1 */
+		(void) read32(abar + 0x0c); /* Read back 2 */
+		/* CAP2 (HBA Capabilities Extended)*/
+		reg32 = read32(abar + 0x24);
+		reg32 &= ~0x00000002;
+		write32(abar + 0x24, reg32);
+		/* VSP (Vendor Specific Register */
+		reg32 = read32(abar + 0xa0);
+		reg32 &= ~0x00000005;
+		write32(abar + 0xa0, reg32);
+	} else {
+		printk(BIOS_DEBUG, "SATA controller in plain mode.\n");
+		/* Set Sata Controller Mode. No Mapping(?) */
+		pci_write_config16(dev, 0x90, 0x0000);
+
+		/* No AHCI: clear AHCI base */
+		pci_write_config32(dev, 0x24, 0x00000000);
+
+		/* And without AHCI BAR no memory decoding */
+		reg16 = pci_read_config16(dev, PCI_COMMAND);
+		reg16 &= ~PCI_COMMAND_MEMORY;
+		pci_write_config16(dev, PCI_COMMAND, reg16);
+
+		/* Native mode capable on both primary and secondary (0xa)
+		 * or'ed with enabled (0x50) = 0xf
+		 */
+		pci_write_config8(dev, 0x09, 0x8f);
+
+		/* Set Interrupt Line */
+		/* Interrupt Pin is set by D31IP.PIP */
+		pci_write_config8(dev, INTR_LN, 0xff);
+
+		/* Set timings */
+		pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE |
+				IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS |
+				IDE_PPE0 | IDE_IE0 | IDE_TIME0);
+		pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE |
+				IDE_SITRE | IDE_ISP_3_CLOCKS |
+				IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0);
+
+		/* Sync DMA */
+		pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0);
+		pci_write_config16(dev, IDE_SDMA_TIM, 0x0201);
+
+		/* Set IDE I/O Configuration */
+		reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0;
+		pci_write_config32(dev, IDE_CONFIG, reg32);
+
+		/* Port enable */
+		reg16 = pci_read_config16(dev, 0x92);
+		reg16 &= ~0x3f;
+		reg16 |= config->sata_port_map;
+		pci_write_config16(dev, 0x92, reg16);
+
+		/* SATA Initialization register */
+		pci_write_config32(dev, 0x94,
+			   ((config->sata_port_map ^ 0x3f) << 24) | 0x183);
+	}
+}
+
+static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations sata_pci_ops = {
+	.set_subsystem    = sata_set_subsystem,
+};
+
+static struct device_operations sata_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= sata_init,
+	.scan_bus		= 0,
+	.ops_pci		= &sata_pci_ops,
+};
+
+/* Non-AHCI and Non-RAID Mode */
+static const struct pci_driver pch_sata_normal_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c00,
+};
+static const struct pci_driver pch_sata_mobile_normal_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c01,
+};
+
+/* AHCI Mode */
+static const struct pci_driver pch_sata_ahci_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c02,
+};
+static const struct pci_driver pch_sata_mobile_ahci_driver __pci_driver = {
+	.ops	= &sata_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c03,
+};
+
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
new file mode 100644
index 0000000..bd17532a6
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -0,0 +1,107 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/smbus.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <arch/io.h>
+#include "pch.h"
+#include "smbus.h"
+
+static void pch_smbus_init(device_t dev)
+{
+	struct resource *res;
+	u16 reg16;
+
+	/* Enable clock gating */
+	reg16 = pci_read_config32(dev, 0x80);
+	reg16 &= ~((1 << 8)|(1 << 10)|(1 << 12)|(1 << 14));
+	pci_write_config32(dev, 0x80, reg16);
+
+	/* Set Receive Slave Address */
+	res = find_resource(dev, PCI_BASE_ADDRESS_4);
+	if (res)
+		outb(SMBUS_SLAVE_ADDR, res->base + SMB_RCV_SLVA);
+}
+
+static int lsmbus_read_byte(device_t dev, u8 address)
+{
+	u16 device;
+	struct resource *res;
+	struct bus *pbus;
+
+	device = dev->path.i2c.device;
+	pbus = get_pbus_smbus(dev);
+	res = find_resource(pbus->dev, 0x20);
+
+	return do_smbus_read_byte(res->base, device, address);
+}
+
+static struct smbus_bus_operations lops_smbus_bus = {
+	.read_byte	= lsmbus_read_byte,
+};
+
+static void smbus_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+}
+
+static struct pci_operations smbus_pci_ops = {
+	.set_subsystem    = smbus_set_subsystem,
+};
+
+static void smbus_read_resources(device_t dev)
+{
+	struct resource *res = new_resource(dev, PCI_BASE_ADDRESS_4);
+	res->base = SMBUS_IO_BASE;
+	res->size = 32;
+	res->limit = res->base + res->size - 1;
+	res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE |
+		     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+	/* Also add MMIO resource */
+	res = pci_get_resource(dev, PCI_BASE_ADDRESS_0);
+}
+
+static struct device_operations smbus_ops = {
+	.read_resources		= smbus_read_resources,
+	.set_resources		= pci_dev_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.scan_bus		= scan_static_bus,
+	.init			= pch_smbus_init,
+	.ops_smbus_bus		= &lops_smbus_bus,
+	.ops_pci		= &smbus_pci_ops,
+};
+
+static const struct pci_driver pch_smbus __pci_driver = {
+	.ops	= &smbus_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c22,
+};
diff --git a/src/southbridge/intel/bd82x6x/smbus.h b/src/southbridge/intel/bd82x6x/smbus.h
new file mode 100644
index 0000000..f2f7f60
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/smbus.h
@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com>
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/smbus_def.h>
+#include "pch.h"
+
+static void smbus_delay(void)
+{
+	inb(0x80);
+}
+
+static int smbus_wait_until_ready(u16 smbus_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_base + SMBHSTSTAT);
+	} while (byte & 1);
+	return loops ? 0 : -1;
+}
+
+static int smbus_wait_until_done(u16 smbus_base)
+{
+	unsigned loops = SMBUS_TIMEOUT;
+	unsigned char byte;
+	do {
+		smbus_delay();
+		if (--loops == 0)
+			break;
+		byte = inb(smbus_base + SMBHSTSTAT);
+	} while ((byte & 1) || (byte & ~((1 << 6) | (1 << 0))) == 0);
+	return loops ? 0 : -1;
+}
+
+static int do_smbus_read_byte(unsigned smbus_base, unsigned device, unsigned address)
+{
+	unsigned char global_status_register;
+	unsigned char byte;
+
+	if (smbus_wait_until_ready(smbus_base) < 0) {
+		return SMBUS_WAIT_UNTIL_READY_TIMEOUT;
+	}
+	/* Setup transaction */
+	/* Disable interrupts */
+	outb(inb(smbus_base + SMBHSTCTL) & (~1), smbus_base + SMBHSTCTL);
+	/* Set the device I'm talking too */
+	outb(((device & 0x7f) << 1) | 1, smbus_base + SMBXMITADD);
+	/* Set the command/address... */
+	outb(address & 0xff, smbus_base + SMBHSTCMD);
+	/* Set up for a byte data read */
+	outb((inb(smbus_base + SMBHSTCTL) & 0xe3) | (0x2 << 2),
+	     (smbus_base + SMBHSTCTL));
+	/* Clear any lingering errors, so the transaction will run */
+	outb(inb(smbus_base + SMBHSTSTAT), smbus_base + SMBHSTSTAT);
+
+	/* Clear the data byte... */
+	outb(0, smbus_base + SMBHSTDAT0);
+
+	/* Start the command */
+	outb((inb(smbus_base + SMBHSTCTL) | 0x40),
+	     smbus_base + SMBHSTCTL);
+
+	/* Poll for transaction completion */
+	if (smbus_wait_until_done(smbus_base) < 0) {
+		return SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
+	}
+
+	global_status_register = inb(smbus_base + SMBHSTSTAT);
+
+	/* Ignore the "In Use" status... */
+	global_status_register &= ~(3 << 5);
+
+	/* Read results of transaction */
+	byte = inb(smbus_base + SMBHSTDAT0);
+	if (global_status_register != (1 << 1)) {
+		return SMBUS_ERROR;
+	}
+	return byte;
+}
+
diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c
new file mode 100644
index 0000000..e5715bd
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/smi.c
@@ -0,0 +1,403 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <console/console.h>
+#include <arch/io.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <string.h>
+#include "pch.h"
+
+#if CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE
+#include "northbridge/intel/sandybridge/sandybridge.h"
+#endif
+
+extern unsigned char _binary_smm_start;
+extern unsigned char _binary_smm_size;
+
+/* While we read PMBASE dynamically in case it changed, let's
+ * initialize it with a sane value
+ */
+static u16 pmbase = DEFAULT_PMBASE;
+
+/**
+ * @brief read and clear PM1_STS
+ * @return PM1_STS register
+ */
+static u16 reset_pm1_status(void)
+{
+	u16 reg16;
+
+	reg16 = inw(pmbase + PM1_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outw(reg16, pmbase + PM1_STS);
+
+	return reg16;
+}
+
+static void dump_pm1_status(u16 pm1_sts)
+{
+	printk(BIOS_DEBUG, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_DEBUG, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_DEBUG, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_DEBUG, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_DEBUG, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_DEBUG, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_DEBUG, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_DEBUG, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_DEBUG, "TMROF ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+/**
+ * @brief read and clear SMI_STS
+ * @return SMI_STS register
+ */
+static u32 reset_smi_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + SMI_STS);
+
+	return reg32;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 25)) printk(BIOS_DEBUG, "EL_SMI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear GPE0_STS
+ * @return GPE0_STS register
+ */
+static u32 reset_gpe0_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + GPE0_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + GPE0_STS);
+
+	return reg32;
+}
+
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+	int i;
+	printk(BIOS_DEBUG, "GPE0_STS: ");
+	for (i=31; i<= 16; i--) {
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+	}
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "EL_SCI/BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "HOT_PLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear ALT_GP_SMI_STS
+ * @return ALT_GP_SMI_STS register
+ */
+static u16 reset_alt_gp_smi_status(void)
+{
+	u16 reg16;
+
+	reg16 = inl(pmbase + ALT_GP_SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg16, pmbase + ALT_GP_SMI_STS);
+
+	return reg16;
+}
+
+static void dump_alt_gp_smi_status(u16 alt_gp_smi_sts)
+{
+	int i;
+	printk(BIOS_DEBUG, "ALT_GP_SMI_STS: ");
+	for (i=15; i<= 0; i--) {
+		if (alt_gp_smi_sts & (1 << i)) printk(BIOS_DEBUG, "GPI%d ", (i-16));
+	}
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief read and clear TCOx_STS
+ * @return TCOx_STS registers
+ */
+static u32 reset_tco_status(void)
+{
+	u32 tcobase = pmbase + 0x60;
+	u32 reg32;
+
+	reg32 = inl(tcobase + 0x04);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
+	if (reg32 & (1 << 18))
+		outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+
+	return reg32;
+}
+
+
+static void dump_tco_status(u32 tco_sts)
+{
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+
+/**
+ * @brief Set the EOS bit
+ */
+static void smi_set_eos(void)
+{
+	u8 reg8;
+
+	reg8 = inb(pmbase + SMI_EN);
+	reg8 |= EOS;
+	outb(reg8, pmbase + SMI_EN);
+}
+
+extern uint8_t smm_relocation_start, smm_relocation_end;
+
+static void smm_relocate(void)
+{
+	u32 smi_en;
+	u16 pm1_en;
+	u32 gpe0_en;
+
+	printk(BIOS_DEBUG, "Initializing SMM handler...");
+
+	pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
+							PMBASE) & 0xff80;
+
+	printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase);
+
+	smi_en = inl(pmbase + SMI_EN);
+	if (smi_en & APMC_EN) {
+		printk(BIOS_INFO, "SMI# handler already enabled?\n");
+		return;
+	}
+
+	/* copy the SMM relocation code */
+	memcpy((void *)0x38000, &smm_relocation_start,
+			&smm_relocation_end - &smm_relocation_start);
+
+	printk(BIOS_DEBUG, "\n");
+	dump_smi_status(reset_smi_status());
+	dump_pm1_status(reset_pm1_status());
+	dump_gpe0_status(reset_gpe0_status());
+	dump_alt_gp_smi_status(reset_alt_gp_smi_status());
+	dump_tco_status(reset_tco_status());
+
+	/* Disable GPE0 PME_B0 */
+	gpe0_en = inl(pmbase + GPE0_EN);
+	gpe0_en &= ~PME_B0_EN;
+	outl(gpe0_en, pmbase + GPE0_EN);
+
+	/* Enable SMI generation:
+	 *  - on TCO events
+	 *  - on APMC writes (io 0xb2)
+	 *  - on writes to SLP_EN (sleep states)
+	 *  - on writes to GBL_RLS (bios commands)
+	 * No SMIs:
+	 *  - on microcontroller writes (io 0x62/0x66)
+	 */
+
+	smi_en = 0; /* reset SMI enables */
+
+#if 0
+	smi_en |= LEGACY_USB2_EN | LEGACY_USB_EN;
+#endif
+	smi_en |= TCO_EN;
+	smi_en |= APMC_EN;
+#if DEBUG_PERIODIC_SMIS
+	/* Set DEBUG_PERIODIC_SMIS in pch.h to debug using
+	 * periodic SMIs.
+	 */
+	smi_en |= PERIODIC_EN;
+#endif
+	smi_en |= SLP_SMI_EN;
+#if 0
+	smi_en |= BIOS_EN;
+#endif
+
+	/* The following need to be on for SMIs to happen */
+	smi_en |= EOS | GBL_SMI_EN;
+
+	outl(smi_en, pmbase + SMI_EN);
+
+	pm1_en = 0;
+	pm1_en |= PWRBTN_EN;
+	pm1_en |= GBL_EN;
+	outw(pm1_en, pmbase + PM1_EN);
+
+	/**
+	 * There are several methods of raising a controlled SMI# via
+	 * software, among them:
+	 *  - Writes to io 0xb2 (APMC)
+	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
+	 *
+	 * Using the local apic is a bit more tricky. According to
+	 * AMD Family 11 Processor BKDG no destination shorthand must be
+	 * used.
+	 * The whole SMM initialization is quite a bit hardware specific, so
+	 * I'm not too worried about the better of the methods at the moment
+	 */
+
+	/* raise an SMI interrupt */
+	printk(BIOS_SPEW, "  ... raise SMI#\n");
+	outb(0x00, 0xb2);
+}
+
+static int smm_handler_copied = 0;
+
+static void smm_install(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0));
+	u32 smm_base = 0xa0000;
+	struct ied_header ied = {
+		.signature = "INTEL RSVD",
+		.size = IED_SIZE,
+		.reserved = {0},
+	};
+
+	/* The first CPU running this gets to copy the SMM handler. But not all
+	 * of them.
+	 */
+	if (smm_handler_copied)
+		return;
+	smm_handler_copied = 1;
+
+	/* enable the SMM memory window */
+	pci_write_config8(dev, SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);
+
+#if CONFIG_SMM_TSEG
+	smm_base = pci_read_config32(dev, TSEG) & ~1;
+#endif
+
+	/* copy the real SMM handler */
+	printk(BIOS_DEBUG, "Installing SMM handler to 0x%08x\n", smm_base);
+	memcpy((void *)smm_base, &_binary_smm_start, (size_t)&_binary_smm_size);
+
+	/* copy the IED header into place */
+	if (CONFIG_SMM_TSEG_SIZE > IED_SIZE) {
+		/* Top of TSEG region */
+		smm_base += CONFIG_SMM_TSEG_SIZE - IED_SIZE;
+		printk(BIOS_DEBUG, "Installing IED header to 0x%08x\n",
+		       smm_base);
+		memcpy((void *)smm_base, &ied, sizeof(ied));
+	}
+	wbinvd();
+
+	/* close the SMM memory window and enable normal SMM */
+	pci_write_config8(dev, SMRAM, G_SMRAME | C_BASE_SEG);
+}
+
+void smm_init(void)
+{
+	/* Put SMM code to 0xa0000 */
+	smm_install();
+
+	/* Put relocation code to 0x38000 and relocate SMBASE */
+	smm_relocate();
+
+	/* We're done. Make sure SMIs can happen! */
+	smi_set_eos();
+}
+
+void smm_lock(void)
+{
+	/* LOCK the SMM memory window and enable normal SMM.
+	 * After running this function, only a full reset can
+	 * make the SMM registers writable again.
+	 */
+	printk(BIOS_DEBUG, "Locking SMM.\n");
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM,
+			D_LCK | G_SMRAME | C_BASE_SEG);
+}
+
+void smm_setup_structures(void *gnvs, void *tcg, void *smi1)
+{
+	/* The GDT or coreboot table is going to live here. But a long time
+	 * after we relocated the GNVS, so this is not troublesome.
+	 */
+	*(u32 *)0x500 = (u32)gnvs;
+	*(u32 *)0x504 = (u32)tcg;
+	*(u32 *)0x508 = (u32)smi1;
+	outb(0xea, 0xb2);
+}
diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c
new file mode 100644
index 0000000..be678f4
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/smihandler.c
@@ -0,0 +1,716 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <arch/hlt.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/smm.h>
+#include <device/pci_def.h>
+#include "pch.h"
+
+#define APM_CNT		0xb2
+#define   CST_CONTROL	0x85
+#define   PST_CONTROL	0x80
+#define   ACPI_DISABLE	0x1e
+#define   ACPI_ENABLE	0xe1
+#define   GNVS_UPDATE   0xea
+#define APM_STS		0xb3
+
+#include "nvs.h"
+
+/* While we read PMBASE dynamically in case it changed, let's
+ * initialize it with a sane value
+ */
+u16 pmbase = DEFAULT_PMBASE;
+u8 smm_initialized = 0;
+
+/* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located
+ * by coreboot.
+ */
+global_nvs_t *gnvs = (global_nvs_t *)0x0;
+void *tcg = (void *)0x0;
+void *smi1 = (void *)0x0;
+
+#if CONFIG_SMM_TSEG
+static u32 tseg_base = 0;
+static inline void tseg_fixup(void **ptr)
+{
+	/* Adjust pointer with TSEG base */
+	if (*ptr)
+		*ptr = (void *)(((u8*)*ptr) + tseg_base);
+}
+#else
+#define tseg_fixup(x) do {} while(0)
+#endif
+
+/**
+ * @brief read and clear PM1_STS
+ * @return PM1_STS register
+ */
+static u16 reset_pm1_status(void)
+{
+	u16 reg16;
+
+	reg16 = inw(pmbase + PM1_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outw(reg16, pmbase + PM1_STS);
+
+	return reg16;
+}
+
+static void dump_pm1_status(u16 pm1_sts)
+{
+	printk(BIOS_SPEW, "PM1_STS: ");
+	if (pm1_sts & (1 << 15)) printk(BIOS_SPEW, "WAK ");
+	if (pm1_sts & (1 << 14)) printk(BIOS_SPEW, "PCIEXPWAK ");
+	if (pm1_sts & (1 << 11)) printk(BIOS_SPEW, "PRBTNOR ");
+	if (pm1_sts & (1 << 10)) printk(BIOS_SPEW, "RTC ");
+	if (pm1_sts & (1 <<  8)) printk(BIOS_SPEW, "PWRBTN ");
+	if (pm1_sts & (1 <<  5)) printk(BIOS_SPEW, "GBL ");
+	if (pm1_sts & (1 <<  4)) printk(BIOS_SPEW, "BM ");
+	if (pm1_sts & (1 <<  0)) printk(BIOS_SPEW, "TMROF ");
+	printk(BIOS_SPEW, "\n");
+	int reg16 = inw(pmbase + PM1_EN);
+	printk(BIOS_SPEW, "PM1_EN: %x\n", reg16);
+}
+
+/**
+ * @brief read and clear SMI_STS
+ * @return SMI_STS register
+ */
+static u32 reset_smi_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + SMI_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + SMI_STS);
+
+	return reg32;
+}
+
+static void dump_smi_status(u32 smi_sts)
+{
+	printk(BIOS_DEBUG, "SMI_STS: ");
+	if (smi_sts & (1 << 26)) printk(BIOS_DEBUG, "SPI ");
+	if (smi_sts & (1 << 21)) printk(BIOS_DEBUG, "MONITOR ");
+	if (smi_sts & (1 << 20)) printk(BIOS_DEBUG, "PCI_EXP_SMI ");
+	if (smi_sts & (1 << 18)) printk(BIOS_DEBUG, "INTEL_USB2 ");
+	if (smi_sts & (1 << 17)) printk(BIOS_DEBUG, "LEGACY_USB2 ");
+	if (smi_sts & (1 << 16)) printk(BIOS_DEBUG, "SMBUS_SMI ");
+	if (smi_sts & (1 << 15)) printk(BIOS_DEBUG, "SERIRQ_SMI ");
+	if (smi_sts & (1 << 14)) printk(BIOS_DEBUG, "PERIODIC ");
+	if (smi_sts & (1 << 13)) printk(BIOS_DEBUG, "TCO ");
+	if (smi_sts & (1 << 12)) printk(BIOS_DEBUG, "DEVMON ");
+	if (smi_sts & (1 << 11)) printk(BIOS_DEBUG, "MCSMI ");
+	if (smi_sts & (1 << 10)) printk(BIOS_DEBUG, "GPI ");
+	if (smi_sts & (1 <<  9)) printk(BIOS_DEBUG, "GPE0 ");
+	if (smi_sts & (1 <<  8)) printk(BIOS_DEBUG, "PM1 ");
+	if (smi_sts & (1 <<  6)) printk(BIOS_DEBUG, "SWSMI_TMR ");
+	if (smi_sts & (1 <<  5)) printk(BIOS_DEBUG, "APM ");
+	if (smi_sts & (1 <<  4)) printk(BIOS_DEBUG, "SLP_SMI ");
+	if (smi_sts & (1 <<  3)) printk(BIOS_DEBUG, "LEGACY_USB ");
+	if (smi_sts & (1 <<  2)) printk(BIOS_DEBUG, "BIOS ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear GPE0_STS
+ * @return GPE0_STS register
+ */
+static u32 reset_gpe0_status(void)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + GPE0_STS);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32, pmbase + GPE0_STS);
+
+	return reg32;
+}
+
+static void dump_gpe0_status(u32 gpe0_sts)
+{
+	int i;
+	printk(BIOS_DEBUG, "GPE0_STS: ");
+	for (i=31; i<= 16; i--) {
+		if (gpe0_sts & (1 << i)) printk(BIOS_DEBUG, "GPIO%d ", (i-16));
+	}
+	if (gpe0_sts & (1 << 14)) printk(BIOS_DEBUG, "USB4 ");
+	if (gpe0_sts & (1 << 13)) printk(BIOS_DEBUG, "PME_B0 ");
+	if (gpe0_sts & (1 << 12)) printk(BIOS_DEBUG, "USB3 ");
+	if (gpe0_sts & (1 << 11)) printk(BIOS_DEBUG, "PME ");
+	if (gpe0_sts & (1 << 10)) printk(BIOS_DEBUG, "BATLOW ");
+	if (gpe0_sts & (1 <<  9)) printk(BIOS_DEBUG, "PCI_EXP ");
+	if (gpe0_sts & (1 <<  8)) printk(BIOS_DEBUG, "RI ");
+	if (gpe0_sts & (1 <<  7)) printk(BIOS_DEBUG, "SMB_WAK ");
+	if (gpe0_sts & (1 <<  6)) printk(BIOS_DEBUG, "TCO_SCI ");
+	if (gpe0_sts & (1 <<  5)) printk(BIOS_DEBUG, "AC97 ");
+	if (gpe0_sts & (1 <<  4)) printk(BIOS_DEBUG, "USB2 ");
+	if (gpe0_sts & (1 <<  3)) printk(BIOS_DEBUG, "USB1 ");
+	if (gpe0_sts & (1 <<  2)) printk(BIOS_DEBUG, "SWGPE ");
+	if (gpe0_sts & (1 <<  1)) printk(BIOS_DEBUG, "HOTPLUG ");
+	if (gpe0_sts & (1 <<  0)) printk(BIOS_DEBUG, "THRM ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+
+/**
+ * @brief read and clear TCOx_STS
+ * @return TCOx_STS registers
+ */
+static u32 reset_tco_status(void)
+{
+	u32 tcobase = pmbase + 0x60;
+	u32 reg32;
+
+	reg32 = inl(tcobase + 0x04);
+	/* set status bits are cleared by writing 1 to them */
+	outl(reg32 & ~(1<<18), tcobase + 0x04); //  Don't clear BOOT_STS before SECOND_TO_STS
+	if (reg32 & (1 << 18))
+		outl(reg32 & (1<<18), tcobase + 0x04); // clear BOOT_STS
+
+	return reg32;
+}
+
+
+static void dump_tco_status(u32 tco_sts)
+{
+	printk(BIOS_DEBUG, "TCO_STS: ");
+	if (tco_sts & (1 << 20)) printk(BIOS_DEBUG, "SMLINK_SLV ");
+	if (tco_sts & (1 << 18)) printk(BIOS_DEBUG, "BOOT ");
+	if (tco_sts & (1 << 17)) printk(BIOS_DEBUG, "SECOND_TO ");
+	if (tco_sts & (1 << 16)) printk(BIOS_DEBUG, "INTRD_DET ");
+	if (tco_sts & (1 << 12)) printk(BIOS_DEBUG, "DMISERR ");
+	if (tco_sts & (1 << 10)) printk(BIOS_DEBUG, "DMISMI ");
+	if (tco_sts & (1 <<  9)) printk(BIOS_DEBUG, "DMISCI ");
+	if (tco_sts & (1 <<  8)) printk(BIOS_DEBUG, "BIOSWR ");
+	if (tco_sts & (1 <<  7)) printk(BIOS_DEBUG, "NEWCENTURY ");
+	if (tco_sts & (1 <<  3)) printk(BIOS_DEBUG, "TIMEOUT ");
+	if (tco_sts & (1 <<  2)) printk(BIOS_DEBUG, "TCO_INT ");
+	if (tco_sts & (1 <<  1)) printk(BIOS_DEBUG, "SW_TCO ");
+	if (tco_sts & (1 <<  0)) printk(BIOS_DEBUG, "NMI2SMI ");
+	printk(BIOS_DEBUG, "\n");
+}
+
+/* We are using PCIe accesses for now
+ *  1. the chipset can do it
+ *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
+ */
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/pcie_config.c>
+
+int southbridge_io_trap_handler(int smif)
+{
+	switch (smif) {
+	case 0x32:
+		printk(BIOS_DEBUG, "OS Init\n");
+		/* gnvs->smif:
+		 *  On success, the IO Trap Handler returns 0
+		 *  On failure, the IO Trap Handler returns a value != 0
+		 */
+		gnvs->smif = 0;
+		return 1; /* IO trap handled */
+	}
+
+	/* Not handled */
+	return 0;
+}
+
+/**
+ * @brief Set the EOS bit
+ */
+void southbridge_smi_set_eos(void)
+{
+	u8 reg8;
+
+	reg8 = inb(pmbase + SMI_EN);
+	reg8 |= EOS;
+	outb(reg8, pmbase + SMI_EN);
+}
+
+static void busmaster_disable_on_bus(int bus)
+{
+        int slot, func;
+        unsigned int val;
+        unsigned char hdr;
+
+        for (slot = 0; slot < 0x20; slot++) {
+                for (func = 0; func < 8; func++) {
+                        u32 reg32;
+                        device_t dev = PCI_DEV(bus, slot, func);
+
+                        val = pci_read_config32(dev, PCI_VENDOR_ID);
+
+                        if (val == 0xffffffff || val == 0x00000000 ||
+                            val == 0x0000ffff || val == 0xffff0000)
+                                continue;
+
+                        /* Disable Bus Mastering for this one device */
+                        reg32 = pci_read_config32(dev, PCI_COMMAND);
+                        reg32 &= ~PCI_COMMAND_MASTER;
+                        pci_write_config32(dev, PCI_COMMAND, reg32);
+
+                        /* If this is a bridge, then follow it. */
+                        hdr = pci_read_config8(dev, PCI_HEADER_TYPE);
+                        hdr &= 0x7f;
+                        if (hdr == PCI_HEADER_TYPE_BRIDGE ||
+                            hdr == PCI_HEADER_TYPE_CARDBUS) {
+                                unsigned int buses;
+                                buses = pci_read_config32(dev, PCI_PRIMARY_BUS);
+                                busmaster_disable_on_bus((buses >> 8) & 0xff);
+                        }
+                }
+        }
+}
+
+/*
+ * Drive GPIO 60 low to gate memory reset in S3.
+ *
+ * Intel reference designs all use GPIO 60 but it is
+ * not a requirement and boards could use a different pin.
+ */
+static void southbridge_gate_memory_reset(void)
+{
+	u32 reg32;
+	u16 gpiobase;
+
+	gpiobase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc;
+	if (!gpiobase)
+		return;
+
+	/* Make sure it is set as GPIO */
+	reg32 = inl(gpiobase + GPIO_USE_SEL2);
+	if (!(reg32 & (1 << 28))) {
+		reg32 |= (1 << 28);
+		outl(reg32, gpiobase + GPIO_USE_SEL2);
+	}
+
+	/* Make sure it is set as output */
+	reg32 = inl(gpiobase + GP_IO_SEL2);
+	if (reg32 & (1 << 28)) {
+		reg32 &= ~(1 << 28);
+		outl(reg32, gpiobase + GP_IO_SEL2);
+	}
+
+	/* Drive the output low */
+	reg32 = inl(gpiobase + GP_LVL2);
+	reg32 &= ~(1 << 28);
+	outl(reg32, gpiobase + GP_LVL2);
+}
+
+static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u8 reg8;
+	u32 reg32;
+	u8 slp_typ;
+	/* FIXME: the power state on boot should be read from
+	 * CMOS or even better from GNVS. Right now it's hard
+	 * coded at compile time.
+	 */
+	u8 s5pwr = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+	void (*mainboard_sleep)(u8 slp_typ) = mainboard_smi_sleep;
+
+	/* First, disable further SMIs */
+	reg8 = inb(pmbase + SMI_EN);
+	reg8 &= ~SLP_SMI_EN;
+	outb(reg8, pmbase + SMI_EN);
+
+	/* Figure out SLP_TYP */
+	reg32 = inl(pmbase + PM1_CNT);
+	printk(BIOS_SPEW, "SMI#: SLP = 0x%08x\n", reg32);
+	slp_typ = (reg32 >> 10) & 7;
+
+	/* Do any mainboard sleep handling */
+	tseg_fixup((void **)&mainboard_sleep);
+	if (mainboard_sleep)
+		mainboard_sleep(slp_typ);
+
+	/* Next, do the deed.
+	 */
+
+	switch (slp_typ) {
+	case 0: printk(BIOS_DEBUG, "SMI#: Entering S0 (On)\n"); break;
+	case 1: printk(BIOS_DEBUG, "SMI#: Entering S1 (Assert STPCLK#)\n"); break;
+	case 5:
+		printk(BIOS_DEBUG, "SMI#: Entering S3 (Suspend-To-RAM)\n");
+
+		/* Gate memory reset */
+		southbridge_gate_memory_reset();
+
+		/* Invalidate the cache before going to S3 */
+		wbinvd();
+		break;
+	case 6: printk(BIOS_DEBUG, "SMI#: Entering S4 (Suspend-To-Disk)\n"); break;
+	case 7:
+		printk(BIOS_DEBUG, "SMI#: Entering S5 (Soft Power off)\n");
+
+		outl(0, pmbase + GPE0_EN);
+
+		/* Should we keep the power state after a power loss?
+		 * In case the setting is "ON" or "OFF" we don't have
+		 * to do anything. But if it's "KEEP" we have to switch
+		 * to "OFF" before entering S5.
+		 */
+		if (s5pwr == MAINBOARD_POWER_KEEP) {
+			reg8 = pcie_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+			reg8 |= 1;
+			pcie_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+		}
+
+		/* also iterates over all bridges on bus 0 */
+		busmaster_disable_on_bus(0);
+		break;
+	default: printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break;
+	}
+
+	/* Write back to the SLP register to cause the originally intended
+	 * event again. We need to set BIT13 (SLP_EN) though to make the
+	 * sleep happen.
+	 */
+	outl(reg32 | SLP_EN, pmbase + PM1_CNT);
+
+	/* Make sure to stop executing code here for S3/S4/S5 */
+	if (slp_typ > 1)
+		hlt();
+
+	/* In most sleep states, the code flow of this function ends at
+	 * the line above. However, if we entered sleep state S1 and wake
+	 * up again, we will continue to execute code in this function.
+	 */
+	reg32 = inl(pmbase + PM1_CNT);
+	if (reg32 & SCI_EN) {
+		/* The OS is not an ACPI OS, so we set the state to S0 */
+		reg32 &= ~(SLP_EN | SLP_TYP);
+		outl(reg32, pmbase + PM1_CNT);
+	}
+}
+
+static void southbridge_smi_apmc(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u32 pmctrl;
+	u8 reg8;
+	void (*mainboard_apmc)(u8 apmc) = mainboard_smi_apmc;
+
+	/* Emulate B2 register as the FADT / Linux expects it */
+
+	reg8 = inb(APM_CNT);
+	switch (reg8) {
+	case CST_CONTROL:
+		/* Calling this function seems to cause
+		 * some kind of race condition in Linux
+		 * and causes a kernel oops
+		 */
+		printk(BIOS_DEBUG, "C-state control\n");
+		break;
+	case PST_CONTROL:
+		/* Calling this function seems to cause
+		 * some kind of race condition in Linux
+		 * and causes a kernel oops
+		 */
+		printk(BIOS_DEBUG, "P-state control\n");
+		break;
+	case ACPI_DISABLE:
+		pmctrl = inl(pmbase + PM1_CNT);
+		pmctrl &= ~SCI_EN;
+		outl(pmctrl, pmbase + PM1_CNT);
+		printk(BIOS_DEBUG, "SMI#: ACPI disabled.\n");
+		break;
+	case ACPI_ENABLE:
+		pmctrl = inl(pmbase + PM1_CNT);
+		pmctrl |= SCI_EN;
+		outl(pmctrl, pmbase + PM1_CNT);
+		printk(BIOS_DEBUG, "SMI#: ACPI enabled.\n");
+		break;
+	case GNVS_UPDATE:
+		if (smm_initialized) {
+			printk(BIOS_DEBUG, "SMI#: SMM structures already initialized!\n");
+			return;
+		}
+		gnvs = *(global_nvs_t **)0x500;
+		tcg  = *(void **)0x504;
+		smi1 = *(void **)0x508;
+		smm_initialized = 1;
+		printk(BIOS_DEBUG, "SMI#: Setting up structures to %p, %p, %p\n", gnvs, tcg, smi1);
+		break;
+	}
+
+	tseg_fixup((void **)&mainboard_apmc);
+	if (mainboard_apmc)
+		mainboard_apmc(reg8);
+}
+
+static void southbridge_smi_pm1(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u16 pm1_sts;
+
+	pm1_sts = reset_pm1_status();
+	dump_pm1_status(pm1_sts);
+
+	/* While OSPM is not active, poweroff immediately
+	 * on a power button event.
+	 */
+	if (pm1_sts & PWRBTN_STS) {
+		// power button pressed
+		u32 reg32;
+		reg32 = (7 << 10) | (1 << 13);
+		outl(reg32, pmbase + PM1_CNT);
+	}
+}
+
+static void southbridge_smi_gpe0(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u32 gpe0_sts;
+
+	gpe0_sts = reset_gpe0_status();
+	dump_gpe0_status(gpe0_sts);
+}
+
+static void southbridge_smi_gpi(unsigned int node, smm_state_save_area_t *state_save)
+{
+	void (*mainboard_gpi)(u16 gpi_sts) = mainboard_smi_gpi;
+	u16 reg16;
+	reg16 = inw(pmbase + ALT_GP_SMI_STS);
+	outw(reg16, pmbase + ALT_GP_SMI_STS);
+
+	reg16 &= inw(pmbase + ALT_GP_SMI_EN);
+
+	tseg_fixup((void **)&mainboard_gpi);
+	if (mainboard_gpi) {
+		mainboard_gpi(reg16);
+	} else {
+		if (reg16)
+			printk(BIOS_DEBUG, "GPI (mask %04x)\n",reg16);
+	}
+
+	outw(reg16, pmbase + ALT_GP_SMI_STS);
+}
+
+static void southbridge_smi_mc(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + SMI_EN);
+
+	/* Are periodic SMIs enabled? */
+	if ((reg32 & MCSMI_EN) == 0)
+		return;
+
+	printk(BIOS_DEBUG, "Microcontroller SMI.\n");
+}
+
+
+
+static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u32 tco_sts;
+
+	tco_sts = reset_tco_status();
+
+	/* Any TCO event? */
+	if (!tco_sts)
+		return;
+
+	if (tco_sts & (1 << 8)) { // BIOSWR
+		u8 bios_cntl;
+
+		bios_cntl = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
+
+		if (bios_cntl & 1) {
+			/* BWE is RW, so the SMI was caused by a
+			 * write to BWE, not by a write to the BIOS
+			 */
+
+			/* This is the place where we notice someone
+			 * is trying to tinker with the BIOS. We are
+			 * trying to be nice and just ignore it. A more
+			 * resolute answer would be to power down the
+			 * box.
+			 */
+			printk(BIOS_DEBUG, "Switching back to RO\n");
+			pcie_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1));
+		} /* No else for now? */
+	} else if (tco_sts & (1 << 3)) { /* TIMEOUT */
+		/* Handle TCO timeout */
+		printk(BIOS_DEBUG, "TCO Timeout.\n");
+	} else if (!tco_sts) {
+		dump_tco_status(tco_sts);
+	}
+}
+
+static void southbridge_smi_periodic(unsigned int node, smm_state_save_area_t *state_save)
+{
+	u32 reg32;
+
+	reg32 = inl(pmbase + SMI_EN);
+
+	/* Are periodic SMIs enabled? */
+	if ((reg32 & PERIODIC_EN) == 0)
+		return;
+
+	printk(BIOS_DEBUG, "Periodic SMI.\n");
+}
+
+static void southbridge_smi_monitor(unsigned int node, smm_state_save_area_t *state_save)
+{
+#define IOTRAP(x) (trap_sts & (1 << x))
+	u32 trap_sts, trap_cycle;
+	u32 data, mask = 0;
+	int i;
+
+	trap_sts = RCBA32(0x1e00); // TRSR - Trap Status Register
+	RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
+
+	trap_cycle = RCBA32(0x1e10);
+	for (i=16; i<20; i++) {
+		if (trap_cycle & (1 << i))
+			mask |= (0xff << ((i - 16) << 2));
+	}
+
+
+	/* IOTRAP(3) SMI function call */
+	if (IOTRAP(3)) {
+		if (gnvs && gnvs->smif)
+			io_trap_handler(gnvs->smif); // call function smif
+		return;
+	}
+
+	/* IOTRAP(2) currently unused
+	 * IOTRAP(1) currently unused */
+
+	/* IOTRAP(0) SMIC */
+	if (IOTRAP(0)) {
+		if (!(trap_cycle & (1 << 24))) { // It's a write
+			printk(BIOS_DEBUG, "SMI1 command\n");
+			data = RCBA32(0x1e18);
+			data &= mask;
+			// if (smi1)
+			// 	southbridge_smi_command(data);
+			// return;
+		}
+		// Fall through to debug
+	}
+
+	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n", trap_cycle & 0xfffc);
+	for (i=0; i < 4; i++) if(IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
+	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
+	printk(BIOS_DEBUG, "  read/write: %s\n", (trap_cycle & (1 << 24)) ? "read" : "write");
+
+	if (!(trap_cycle & (1 << 24))) {
+		/* Write Cycle */
+		data = RCBA32(0x1e18);
+		printk(BIOS_DEBUG, "  iotrap written data = 0x%08x\n", data);
+	}
+#undef IOTRAP
+}
+
+typedef void (*smi_handler_t)(unsigned int node,
+		smm_state_save_area_t *state_save);
+
+static smi_handler_t southbridge_smi[32] = {
+	NULL,			  //  [0] reserved
+	NULL,			  //  [1] reserved
+	NULL,			  //  [2] BIOS_STS
+	NULL,			  //  [3] LEGACY_USB_STS
+	southbridge_smi_sleep,	  //  [4] SLP_SMI_STS
+	southbridge_smi_apmc,	  //  [5] APM_STS
+	NULL,			  //  [6] SWSMI_TMR_STS
+	NULL,			  //  [7] reserved
+	southbridge_smi_pm1,	  //  [8] PM1_STS
+	southbridge_smi_gpe0,	  //  [9] GPE0_STS
+	southbridge_smi_gpi,	  // [10] GPI_STS
+	southbridge_smi_mc,	  // [11] MCSMI_STS
+	NULL,			  // [12] DEVMON_STS
+	southbridge_smi_tco,	  // [13] TCO_STS
+	southbridge_smi_periodic, // [14] PERIODIC_STS
+	NULL,			  // [15] SERIRQ_SMI_STS
+	NULL,			  // [16] SMBUS_SMI_STS
+	NULL,			  // [17] LEGACY_USB2_STS
+	NULL,			  // [18] INTEL_USB2_STS
+	NULL,			  // [19] reserved
+	NULL,			  // [20] PCI_EXP_SMI_STS
+	southbridge_smi_monitor,  // [21] MONITOR_STS
+	NULL,			  // [22] reserved
+	NULL,			  // [23] reserved
+	NULL,			  // [24] reserved
+	NULL,			  // [25] EL_SMI_STS
+	NULL,			  // [26] SPI_STS
+	NULL,			  // [27] reserved
+	NULL,			  // [28] reserved
+	NULL,			  // [29] reserved
+	NULL,			  // [30] reserved
+	NULL			  // [31] reserved
+};
+
+/**
+ * @brief Interrupt handler for SMI#
+ *
+ * @param smm_revision revision of the smm state save map
+ */
+
+void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)
+{
+	int i, dump = 0;
+	u32 smi_sts;
+
+	/* Update global variable pmbase */
+	pmbase = pcie_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
+
+#if CONFIG_SMM_TSEG
+	/* Update global variable TSEG base */
+	tseg_base = pcie_read_config32(PCI_DEV(0, 0, 0), TSEG) & ~1;
+#endif
+
+	/* We need to clear the SMI status registers, or we won't see what's
+	 * happening in the following calls.
+	 */
+	smi_sts = reset_smi_status();
+
+	/* Call SMI sub handler for each of the status bits */
+	for (i = 0; i < 31; i++) {
+		if (smi_sts & (1 << i)) {
+			if (southbridge_smi[i]) {
+#if CONFIG_SMM_TSEG
+				smi_handler_t handler = (smi_handler_t)
+					((u8*)southbridge_smi[i] + tseg_base);
+				if (handler)
+					handler(node, state_save);
+#else
+				southbridge_smi[i](node, state_save);
+#endif
+			} else {
+				printk(BIOS_DEBUG, "SMI_STS[%d] occured, but no "
+						"handler available.\n", i);
+				dump = 1;
+			}
+		}
+	}
+
+	if(dump) {
+		dump_smi_status(smi_sts);
+	}
+
+}
diff --git a/src/southbridge/intel/bd82x6x/usb_debug.c b/src/southbridge/intel/bd82x6x/usb_debug.c
new file mode 100644
index 0000000..4258a03
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/usb_debug.c
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <console/console.h>
+#include <usbdebug.h>
+#include <device/pci_def.h>
+#include "pch.h"
+
+/* Required for successful build, but currently empty. */
+void set_debug_port(unsigned int port)
+{
+	/* Not needed, the ICH* southbridges hardcode physical USB port 1. */
+}
+
+void enable_usbdebug(unsigned int port)
+{
+	u32 dbgctl;
+	device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */
+
+	/* Set the EHCI BAR address. */
+	pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR);
+
+	/* Enable access to the EHCI memory space registers. */
+	pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY);
+
+	/* Force ownership of the Debug Port to the EHCI controller. */
+	printk(BIOS_DEBUG, "Enabling OWNER_CNT\n");
+	dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET);
+	dbgctl |= (1 << 30);
+	write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl);
+}
+
diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c
new file mode 100644
index 0000000..5ebd70e
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/usb_ehci.c
@@ -0,0 +1,114 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "pch.h"
+#include <usbdebug.h>
+#include <arch/io.h>
+
+static void usb_ehci_init(struct device *dev)
+{
+	u32 reg32;
+
+	/* Disable Wake on Disconnect in RMH */
+	reg32 = RCBA32(0x35b0);
+	reg32 |= 0x22;
+	RCBA32(0x35b0) = reg32;
+
+	printk(BIOS_DEBUG, "EHCI: Setting up controller.. ");
+	reg32 = pci_read_config32(dev, PCI_COMMAND);
+	reg32 |= PCI_COMMAND_MASTER;
+	//reg32 |= PCI_COMMAND_SERR;
+	pci_write_config32(dev, PCI_COMMAND, reg32);
+
+	printk(BIOS_DEBUG, "done.\n");
+}
+
+static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
+{
+	u8 access_cntl;
+
+	access_cntl = pci_read_config8(dev, 0x80);
+
+	/* Enable writes to protected registers. */
+	pci_write_config8(dev, 0x80, access_cntl | 1);
+
+	if (!vendor || !device) {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				pci_read_config32(dev, PCI_VENDOR_ID));
+	} else {
+		pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
+				((device & 0xffff) << 16) | (vendor & 0xffff));
+	}
+
+	/* Restore protection. */
+	pci_write_config8(dev, 0x80, access_cntl);
+}
+
+static void usb_ehci_set_resources(struct device *dev)
+{
+#if CONFIG_USBDEBUG
+	struct resource *res;
+	u32 base;
+	u32 usb_debug;
+
+	usb_debug = get_ehci_debug();
+	set_ehci_debug(0);
+#endif
+	pci_dev_set_resources(dev);
+
+#if CONFIG_USBDEBUG
+	res = find_resource(dev, 0x10);
+	set_ehci_debug(usb_debug);
+	if (!res) return;
+	base = res->base;
+	set_ehci_base(base);
+	report_resource_stored(dev, res, "");
+#endif
+}
+
+
+
+static struct pci_operations lops_pci = {
+	.set_subsystem	= &usb_ehci_set_subsystem,
+};
+
+static struct device_operations usb_ehci_ops = {
+	.read_resources		= pci_dev_read_resources,
+	.set_resources		= usb_ehci_set_resources,
+	.enable_resources	= pci_dev_enable_resources,
+	.init			= usb_ehci_init,
+	.scan_bus		= 0,
+	.ops_pci		= &lops_pci,
+};
+
+static const struct pci_driver pch_usb_ehci1 __pci_driver = {
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c26,
+};
+static const struct pci_driver pch_usb_ehci2 __pci_driver = {
+	.ops	= &usb_ehci_ops,
+	.vendor	= PCI_VENDOR_ID_INTEL,
+	.device	= 0x1c2d,
+};
diff --git a/src/southbridge/intel/bd82x6x/watchdog.c b/src/southbridge/intel/bd82x6x/watchdog.c
new file mode 100644
index 0000000..362e896
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/watchdog.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <watchdog.h>
+
+  //
+  //  Disable PCH Watchdog timer at SB_RCBA+0x3410
+  //
+  //  Mmio32((MmPci32(0, 0, 0x1F, 0, 0xF0) & ~BIT0), 0x3410) |= 0x20;
+  //
+void watchdog_off(void)
+{
+	device_t dev;
+	unsigned long value, base;
+
+	/* Turn off the ICH7 watchdog. */
+	dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0));
+
+	/* Enable I/O space. */
+	value = pci_read_config16(dev, 0x04);
+	value |= (1 << 10);
+	pci_write_config16(dev, 0x04, value);
+
+	/* Get TCO base. */
+	base = (pci_read_config32(dev, 0x40) & 0x0fffe) + 0x60;
+
+	/* Disable the watchdog timer. */
+	value = inw(base + 0x08);
+	value |= 1 << 11;
+	outw(value, base + 0x08);
+
+	/* Clear TCO timeout status. */
+	outw(0x0008, base + 0x04);
+	outw(0x0002, base + 0x06);
+
+	printk(BIOS_DEBUG, "PCH watchdog disabled\n");
+}
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 9b0bb1f..80aa6cf 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -46,7 +46,6 @@
 void enable_smbus(void);
 int smbus_read_byte(unsigned device, unsigned address);
 #endif
-void enable_usbdebug(unsigned int port);
 #endif
 
 #define MAINBOARD_POWER_OFF	0
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 7feb76a..68b3d97 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -27,6 +27,7 @@
 #include <pc80/i8259.h>
 #include <arch/io.h>
 #include <arch/ioapic.h>
+#include <arch/acpi.h>
 #include <cpu/cpu.h>
 #include "i82801gx.h"
 
@@ -169,8 +170,6 @@
 	pci_write_config32(dev, 0xb8, reg32);
 }
 
-extern u8 acpi_slp_type;
-
 static void i82801gx_power_options(device_t dev)
 {
 	u8 reg8;
diff --git a/src/southbridge/nvidia/ck804/ck804.h b/src/southbridge/nvidia/ck804/ck804.h
index e7bf021..3e8b1f2 100644
--- a/src/southbridge/nvidia/ck804/ck804.h
+++ b/src/southbridge/nvidia/ck804/ck804.h
@@ -24,7 +24,6 @@
 #include "chip.h"
 
 void ck804_enable(device_t dev);
-void enable_usbdebug(unsigned int port);
 
 extern struct pci_operations ck804_pci_ops;
 
diff --git a/src/southbridge/nvidia/mcp55/mcp55.h b/src/southbridge/nvidia/mcp55/mcp55.h
index 3173c50..aa52886 100644
--- a/src/southbridge/nvidia/mcp55/mcp55.h
+++ b/src/southbridge/nvidia/mcp55/mcp55.h
@@ -35,7 +35,6 @@
 #else
 #if !defined(__ROMCC__)
 void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn);
-void enable_usbdebug(unsigned int port);
 #endif
 #endif
 
diff --git a/src/southbridge/sis/sis966/sis966.h b/src/southbridge/sis/sis966/sis966.h
index d6624b3..2c7c7b8 100644
--- a/src/southbridge/sis/sis966/sis966.h
+++ b/src/southbridge/sis/sis966/sis966.h
@@ -39,8 +39,4 @@
 void sis966_enable(device_t dev);
 #endif
 
-#if defined(__PRE_RAM__) && !defined(__ROMCC__)
-void enable_usbdebug(unsigned int port);
-#endif
-
 #endif /* SIS966_H */
diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c
index 61f4989..3e2f215 100644
--- a/src/southbridge/via/vt8237r/lpc.c
+++ b/src/southbridge/via/vt8237r/lpc.c
@@ -32,6 +32,7 @@
 #include <pc80/keyboard.h>
 #include <pc80/i8259.h>
 #include <stdlib.h>
+#include <arch/acpi.h>
 #include "vt8237r.h"
 #include "chip.h"
 
@@ -147,9 +148,6 @@
  * This avoids having to handle any System Management Interrupts (SMIs).
  */
 
-extern u8 acpi_slp_type;
-
-
 static void setup_pm(device_t dev)
 {
 	u16 tmp;
diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig
index cb0c571..cc7592f 100644
--- a/src/superio/ite/Kconfig
+++ b/src/superio/ite/Kconfig
@@ -18,6 +18,8 @@
 ##
 
 
+config SUPERIO_ITE_IT8500
+	bool
 config SUPERIO_ITE_IT8661F
 	bool
 config SUPERIO_ITE_IT8671F
@@ -36,3 +38,5 @@
 	default n
 config SUPERIO_ITE_IT8718F
 	bool
+config SUPERIO_ITE_IT8772F
+	bool
diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc
index 21f7707..7fe5f2a 100644
--- a/src/superio/ite/Makefile.inc
+++ b/src/superio/ite/Makefile.inc
@@ -17,6 +17,7 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
+subdirs-y += it8500
 subdirs-y += it8661f
 subdirs-y += it8671f
 subdirs-y += it8673f
@@ -24,3 +25,4 @@
 subdirs-y += it8712f
 subdirs-y += it8716f
 subdirs-y += it8718f
+subdirs-y += it8772f
diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc
new file mode 100644
index 0000000..d001c61
--- /dev/null
+++ b/src/superio/ite/it8772f/Makefile.inc
@@ -0,0 +1,21 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c
diff --git a/src/superio/ite/it8772f/acpi/superio.asl b/src/superio/ite/it8772f/acpi/superio.asl
new file mode 100644
index 0000000..5bb45fa
--- /dev/null
+++ b/src/superio/ite/it8772f/acpi/superio.asl
@@ -0,0 +1,299 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+	Name (_ADR, 0x2E)
+	OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
+	Field (SIOA, ByteAcc, NoLock, Preserve)
+	{
+		SI2E, 8,
+		SI2F, 8,
+	}
+
+	IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x02),
+		SCNT, 8,	/* Configure Control */
+		Offset (0x07),
+		SLDN, 8,	/* Logical Device Number */
+		Offset (0x30),
+		SACT, 8,	/* Activate */
+		Offset (0x60),
+		IO0H, 8,	/* Base Address 0 MSB */
+		IO0L, 8,	/* Base Address 0 LSB */
+		Offset (0x62),
+		IO1H, 8,	/* Base Address 1 MSB */
+		IO1L, 8,	/* Base Address 1 LSB */
+		Offset (0x70),
+		IQ00, 8,	/* Interrupt Select */
+	}
+
+	Name (SFDC, 0)		/* Floppy Disk Controller */
+	Name (SSP1, 1)		/* Serial Port 1 */
+	Name (SENV, 4)		/* Environment Controller */
+	Name (SKBC, 5)		/* Keyboard */
+	Name (SKBM, 6)		/* Mouse */
+	Name (SGPI, 7)		/* GPIO */
+	Name (SINF, 10)		/* Consumer IR */
+
+	Method (ENTR, 0, NotSerialized)
+	{
+		Store (0x87, SI2E)
+		Store (0x01, SI2E)
+		Store (0x55, SI2E)
+		Store (0x55, SI2E)
+	}
+
+	Method (EXIT, 0, NotSerialized)
+	{
+		Store (0x02, SCNT)
+	}
+
+	/* Parse activate register for an LDN */
+	Method (ISEN, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (SACT, Local0)
+		EXIT ()
+
+		/* Check if it exists */
+		If (LEqual (Local0, 0xFF))
+		{
+			Return (0x00)
+		}
+
+		/* Check if activated */
+		If (LEqual (Local0, One))
+		{
+			Return (0x0F)
+		}
+		Else
+		{
+			Return (0x0D)
+		}
+	}
+
+	/* Enable an LDN via the activate register */
+	Method (SENA, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (One, SACT)
+		EXIT ()
+	}
+
+	/* Disable an LDN via the activate register */
+	Method (SDIS, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (Zero, SACT)
+		EXIT ()
+	}
+
+#ifdef SIO_ENABLE_ENVC
+	Device (ENVC) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 10)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (SENV))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
+			IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_ENVC_IO0, SIO_ENVC_IO0, 0x08, 0x08)
+			IO (Decode16, SIO_ENVC_IO1, SIO_ENVC_IO1, 0x04, 0x04)
+		})
+
+		OperationRegion (ECAP, SystemIO, SIO_ENVC_IO0, 0x07)
+		Field (ECAP, ByteAcc, NoLock, Preserve)
+		{
+			Offset (0x05),
+			ECAI, 8,  // Address Index Register
+			ECAD, 8,  // Address Data Register
+		}
+
+		// Registers for thermal zone implementations
+		IndexField (ECAI, ECAD, ByteAcc, NoLock, Preserve)
+		{
+			Offset (0x29),
+			TIN1, 8,  // TMPIN1 Reading
+			TIN2, 8,  // TMPIN2 Reading
+			TIN3, 8,  // TMPIN3 Reading
+			Offset (0x6b),
+			F2PS, 8,  // FAN2 PWM Setting
+			Offset (0x73),
+			F3PS, 8,  // FAN3 PWM Setting
+		}
+	}
+#endif
+
+#ifdef SIO_ENABLE_GPIO
+	Device (GPIO) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 11)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (0x0F)
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
+			IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_GPIO_IO0, SIO_GPIO_IO0, 0x01, 0x01)
+			IO (Decode16, SIO_GPIO_IO1, SIO_GPIO_IO1, 0x08, 0x08)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_COM1
+	Device (COM1) {
+		Name (_HID, EISAID ("PNP0501"))
+		Name (_UID, 1)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (SSP1))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+			IRQNoFlags () {4}
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, 0x03F8, 0x03F8, 0x08, 0x08)
+			IRQNoFlags () {4}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_PS2K
+	Device (PS2K)		// Keyboard
+	{
+		Name (_HID, EISAID("PNP0303"))
+		Name (_CID, EISAID("PNP030B"))
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (SKBC))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+			IRQNoFlags () {1}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+			IRQNoFlags () {1}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_PS2M
+	Device (PS2M)		// Mouse
+	{
+		Name (_HID, EISAID("PNP0F13"))
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (SKBM))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IRQNoFlags () {12}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IRQNoFlags () {12}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_FDC0
+	Device (FDC0)		// Floppy controller
+	{
+		Name (_HID, EISAID ("PNP0700"))
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (SFDC))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+			IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
+			IRQNoFlags () {6}
+			DMA (Compatibility, NotBusMaster, Transfer8) {2}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x03F0, 0x03F0, 0x01, 0x06)
+			IO (Decode16, 0x03F7, 0x03F7, 0x01, 0x01)
+			IRQNoFlags () {6}
+			DMA (Compatibility, NotBusMaster, Transfer8) {2}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_INFR
+	Device (INFR)		// Infrared controller
+	{
+		Name (_HID, EISAID ("PNP0510"))
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (SINF))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
+			IRQNoFlags () { SIO_INFR_IRQ }
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IO (Decode16, SIO_INFR_IO0, SIO_INFR_IO0, 0x08, 0x08)
+			IRQNoFlags () { SIO_INFR_IRQ }
+		})
+	}
+#endif
+}
diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h
new file mode 100644
index 0000000..e91f6fa
--- /dev/null
+++ b/src/superio/ite/it8772f/chip.h
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_ITE_IT8772F_CHIP_H
+#define SUPERIO_ITE_IT8772F_CHIP_H
+
+#include <device/device.h>
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+extern struct chip_operations superio_ite_it8772f_ops;
+
+struct superio_ite_it8772f_config {
+	struct pc_keyboard keyboard;
+
+	/* GPIO SimpleIO register values via devicetree.cb */
+	u8 gpio_set1;
+	u8 gpio_set2;
+	u8 gpio_set3;
+	u8 gpio_set4;
+	u8 gpio_set5;
+	u8 gpio_set6;
+
+	u8 skip_keyboard;
+
+	/*
+	 * Enable external temperature sensor to use PECI GetTemp()
+	 * command and store in register TMPIN 1, 2, or 3.
+	 */
+	u8 peci_tmpin;
+
+	/*
+	 * Enable a FAN for sofware control.
+	 */
+	u8 fan1_enable;
+	u8 fan2_enable;
+	u8 fan3_enable;
+};
+
+#endif
diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c
new file mode 100644
index 0000000..0721060
--- /dev/null
+++ b/src/superio/ite/it8772f/early_serial.c
@@ -0,0 +1,131 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+#include <device/pnp_def.h>
+#include "it8772f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE                     IT8772F_BASE
+#define SIO_INDEX                    SIO_BASE
+#define SIO_DATA                     (SIO_BASE + 1)
+
+/* Global configuration registers. */
+#define IT8772F_CONFIG_REG_CC        0x02 /* Configure Control (write-only). */
+#define IT8772F_CONFIG_REG_LDN       0x07 /* Logical Device Number. */
+#define IT8772F_CONFIG_REG_CLOCKSEL  0x23 /* Clock Selection. */
+#define IT8772F_CONFIG_REG_MFC       0x2a /* Multi-function control */
+#define IT8772F_CONFIG_REG_WATCHDOG  0x72 /* Watchdog control. */
+
+u8 it8772f_sio_read(u8 index)
+{
+	outb(index, SIO_BASE);
+	return inb(SIO_DATA);
+}
+
+void it8772f_sio_write(u8 index, u8 value)
+{
+	outb(index, SIO_BASE);
+	outb(value, SIO_DATA);
+}
+
+static void it8772f_enter_conf(void)
+{
+	u16 port = SIO_BASE;
+
+	outb(0x87, port);
+	outb(0x01, port);
+	outb(0x55, port);
+	outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void it8772f_exit_conf(void)
+{
+	it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02);
+}
+
+/* Select 24MHz CLKIN (48MHz is the default). */
+void it8772f_24mhz_clkin(void)
+{
+	it8772f_enter_conf();
+	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, 0x00);
+	it8772f_sio_write(IT8772F_CONFIG_REG_CLOCKSEL, 0x1);
+	it8772f_exit_conf();
+}
+
+/*
+ * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off.
+ *
+ * Enable 3VSBSW#. (For System Suspend-to-RAM)
+ * 0: 3VSBSW# will be always inactive.
+ * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#.
+ */
+void it8772f_enable_3vsbsw(void)
+{
+	it8772f_enter_conf();
+	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+	it8772f_sio_write(IT8772F_CONFIG_REG_MFC, 0x80);
+	it8772f_exit_conf();
+}
+
+void it8772f_kill_watchdog(void)
+{
+	it8772f_enter_conf();
+	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+	it8772f_sio_write(IT8772F_CONFIG_REG_WATCHDOG, 0x00);
+	it8772f_exit_conf();
+}
+
+/* Enable the serial port(s). */
+void it8772f_enable_serial(device_t dev, u16 iobase)
+{
+	it8772f_enter_conf();
+	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, dev & 0xff);
+	it8772f_sio_write(PNP_IDX_IO0, (iobase >> 8) & 0xff);
+	it8772f_sio_write(PNP_IDX_IO0+1, iobase & 0xff);
+	it8772f_sio_write(PNP_IDX_EN, 1);
+	it8772f_exit_conf();
+}
+
+/* Set AC resume to be up to the Southbridge */
+void it8772f_ac_resume_southbridge(void)
+{
+	it8772f_enter_conf();
+	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC);
+	it8772f_sio_write(0xf4, 0x60);
+	it8772f_exit_conf();
+}
+
+/* Configure a set of GPIOs */
+void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup,
+			u8 output, u8 enable)
+{
+	set--; /* Set 1 is offset 0 */
+	it8772f_enter_conf();
+	it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO);
+	if (set < 5) {
+		it8772f_sio_write(GPIO_REG_SELECT(set), select);
+		it8772f_sio_write(GPIO_REG_ENABLE(set), enable);
+		it8772f_sio_write(GPIO_REG_POLARITY(set), polarity);
+	}
+	it8772f_sio_write(GPIO_REG_OUTPUT(set), output);
+	it8772f_sio_write(GPIO_REG_PULLUP(set), pullup);
+	it8772f_exit_conf();
+}
diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h
new file mode 100644
index 0000000..1ec82e1
--- /dev/null
+++ b/src/superio/ite/it8772f/it8772f.h
@@ -0,0 +1,120 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SUPERIO_ITE_IT8772F_IT8772F_H
+#define SUPERIO_ITE_IT8772F_IT8772F_H
+
+#define IT8772F_BASE 0x2e
+
+#define IT8772F_FDC  0x00 /* Floppy disk controller */
+#define IT8772F_SP1  0x01 /* Com1 */
+#define IT8772F_EC   0x04 /* Environment controller */
+#define IT8772F_KBCK 0x05 /* Keyboard */
+#define IT8772F_KBCM 0x06 /* Mouse */
+#define IT8772F_GPIO 0x07 /* GPIO */
+#define IT8772F_IR   0x0a /* Consumer IR */
+
+/* Environmental Controller interface */
+#define IT8772F_INTERFACE_SELECT		0x0a
+#define  IT8772F_INTERFACE_PSEUDO_EOC		(1 << 7)
+#define  IT8772F_INTERFACE_SMB_ENABLE		(1 << 6)
+#define  IT8772F_INTERFACE_SEL_DISABLE		(0 << 4)
+#define  IT8772F_INTERFACE_SEL_SST_SLAVE	(1 << 4)
+#define  IT8772F_INTERFACE_SEL_PECI		(2 << 4)
+#define  IT8772F_INTERFACE_SEL_SST_HOST		(3 << 4)
+#define  IT8772F_INTERFACE_CLOCK_32MHZ		(0 << 3)
+#define  IT8772F_INTERFACE_CLOCK_24MHZ		(1 << 3)
+#define  IT8772F_INTERFACE_SPEED_TOLERANCE	(1 << 2)
+#define  IT8772F_INTERFACE_PECI_AWFCS		(1 << 0)
+#define IT8772F_FAN_TAC2_READ			0x0e
+#define IT8772F_FAN_TAC3_READ			0x0f
+#define IT8772F_FAN_MAIN_CTL			0x13
+#define  IT8772F_FAN_MAIN_CTL_TAC_SMART(x)	(1 << ((x)-1))
+#define  IT8772F_FAN_MAIN_CTL_TAC_EN(x)		(1 << ((x)+3))
+#define IT8772F_FAN_CTL_MODE			0x14
+#define  IT8772F_FAN_CTL_ON(x)			(1 << ((x)-1))
+#define  IT8772F_FAN_PWM_MIN_DUTY		(1 << 3)
+#define  IT8772F_FAN_PWM_CLOCK_48MHZ		(0 << 4)
+#define  IT8772F_FAN_PWM_CLOCK_24MHZ		(1 << 4)
+#define  IT8772F_FAN_PWM_CLOCK_8MHZ		(3 << 4)
+#define  IT8772F_FAN_PWM_CLOCK_6MHZ		(4 << 4)
+#define  IT8772F_FAN_PWM_CLOCK_3MHZ		(5 << 4)
+#define  IT8772F_FAN_PWM_CLOCK_1_5MHZ		(6 << 4)
+#define  IT8772F_FAN_PWM_CLOCK_51KHZ		(7 << 4)
+#define  IT8772F_FAN_CTL_POLARITY_LOW		(0 << 7)
+#define  IT8772F_FAN_CTL_POLARITY_HIGH		(1 << 7)
+#define IT8772F_FAN_CTL2_PWM_MODE		0x16
+#define IT8772F_FAN_CTL3_PWM_MODE		0x17
+#define  IT8772F_FAN_CTL_PWM_MODE_SOFTWARE	(0 << 7)
+#define  IT8772F_FAN_CTL_PWM_MODE_AUTOMATIC	(1 << 7)
+#define IT8772F_ADC_TEMP_CHANNEL_ENABLE		0x51
+#define IT8772F_FAN_CTL2_PWM_START		0x6b
+#define IT8772F_FAN_CTL2_AUTO_MODE		0x6c
+#define IT8772F_FAN_CTL3_PWM_START		0x73
+#define IT8772F_FAN_CTL3_AUTO_MODE		0x74
+#define  IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS	(0 << 7)
+#define  IT8772F_FAN_CTL_AUTO_SMOOTHING_EN	(1 << 7)
+#define IT8772F_EXTEMP_STATUS			0x88
+#define IT8772F_EXTEMP_ADDRESS			0x89
+#define IT8772F_EXTEMP_WRITE_LENGTH		0x8a
+#define IT8772F_EXTEMP_READ_LENGTH		0x8b
+#define IT8772F_EXTEMP_COMMAND			0x8c
+#define IT8772F_EXTEMP_WRITE_DATA_2		0x8d
+#define IT8772F_EXTEMP_CONTROL			0x8e
+#define  IT8772F_EXTEMP_CONTROL_AUTO_32HZ	(0 << 6)
+#define  IT8772F_EXTEMP_CONTROL_AUTO_16HZ	(1 << 6)
+#define  IT8772F_EXTEMP_CONTROL_AUTO_8HZ	(2 << 6)
+#define  IT8772F_EXTEMP_CONTROL_AUTO_4HZ	(3 << 6)
+#define  IT8772F_EXTEMP_CONTROL_AUTO_START	(1 << 5)
+#define  IT8772F_EXTEMP_CONTROL_AUTO_ABORT	(1 << 4)
+#define  IT8772F_EXTEMP_CONTROL_AUTO_TWO_DOMAIN	(1 << 3)
+#define  IT8772F_EXTEMP_CONTROL_CONTENTION	(1 << 2)
+#define  IT8772F_EXTEMP_CONTROL_SST_IDLE_HIGH	(1 << 1)
+#define  IT8772F_EXTEMP_CONTROL_START		(1 << 0)
+
+/* Standard PECI GetTemp */
+#define PECI_CLIENT_ADDRESS			0x30
+#define PECI_GETTEMP_COMMAND			0x01
+#define PECI_GETTEMP_WRITE_LENGTH		0x01
+#define PECI_GETTEMP_READ_LENGTH		0x02
+
+/* GPIO interface */
+#define IT8772F_GPIO_LED_BLINK1_PINMAP		0xf8
+#define IT8772F_GPIO_LED_BLINK1_CONTROL		0xf9
+
+#define GPIO_REG_SELECT(x)   (0x25 + (x))
+#define GPIO_REG_POLARITY(x) (0xb0 + (x))
+#define GPIO_REG_PULLUP(x)   (0xb8 + (x))
+#define GPIO_REG_ENABLE(x)   (0xc0 + (x))
+#define GPIO_REG_OUTPUT(x)   (0xc8 + (x))
+
+#ifndef __ROMCC__
+u8 it8772f_sio_read(u8 index);
+void it8772f_sio_write(u8 index, u8 value);
+void it8772f_enable_serial(device_t dev, u16 iobase);
+void it8772f_kill_watchdog(void);
+void it8772f_24mhz_clkin(void);
+void it8772f_enable_3vsbsw(void);
+void it8772f_ac_resume_southbridge(void);
+void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup,
+			u8 output, u8 enable);
+#endif
+
+#endif
diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c
new file mode 100644
index 0000000..1361ef2
--- /dev/null
+++ b/src/superio/ite/it8772f/superio.c
@@ -0,0 +1,250 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pnp.h>
+#include <uart8250.h>
+#include <pc80/keyboard.h>
+#include <arch/io.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "it8772f.h"
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+	u16 port = dev->path.pnp.port;
+
+	outb(0x87, port);
+	outb(0x01, port);
+	outb(0x55, port);
+	outb((port == 0x4e) ? 0xaa : 0x55, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	pnp_write_config(dev, 0x02, 0x02);
+}
+
+static inline u8 it8772f_envc_read(struct resource *res, u8 addr)
+{
+	outb(addr, res->base + 5);
+	return inb(res->base + 6);
+}
+
+static inline void it8772f_envc_write(struct resource *res, u8 addr, u8 value)
+{
+	outb(addr, res->base + 5);
+	outb(value, res->base + 6);
+}
+
+/*
+ * Setup External Temperature to read via PECI into TMPINx register
+ */
+static void it8772f_enable_peci(struct resource *res, int tmpin)
+{
+	if (tmpin < 1 || tmpin > 3)
+		return;
+
+	/* Enable PECI interface */
+	it8772f_envc_write(res, IT8772F_INTERFACE_SELECT,
+			   IT8772F_INTERFACE_SEL_PECI |
+			   IT8772F_INTERFACE_SPEED_TOLERANCE);
+
+	/* Setup External Temperature using PECI GetTemp */
+	it8772f_envc_write(res, IT8772F_EXTEMP_ADDRESS,
+			   PECI_CLIENT_ADDRESS);
+	it8772f_envc_write(res, IT8772F_EXTEMP_COMMAND,
+			   PECI_GETTEMP_COMMAND);
+	it8772f_envc_write(res, IT8772F_EXTEMP_WRITE_LENGTH,
+			   PECI_GETTEMP_WRITE_LENGTH);
+	it8772f_envc_write(res, IT8772F_EXTEMP_READ_LENGTH,
+			   PECI_GETTEMP_READ_LENGTH);
+	it8772f_envc_write(res, IT8772F_EXTEMP_CONTROL,
+			   IT8772F_EXTEMP_CONTROL_AUTO_4HZ |
+			   IT8772F_EXTEMP_CONTROL_AUTO_START);
+
+	/* External Temperature reported in TMPINx register */
+	it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE,
+			   (tmpin & 3) << 6);
+}
+
+/*
+ * Setup a FAN PWM interface for software control
+ */
+static void it8772f_enable_fan(struct resource *res, int fan)
+{
+	u8 reg;
+
+	if (fan < 1 || fan > 3)
+		return;
+
+	/* Enable 6MHz (23.43kHz PWM) active high output */
+	reg = it8772f_envc_read(res, IT8772F_FAN_CTL_MODE);
+	reg |= IT8772F_FAN_CTL_ON(fan) |
+		IT8772F_FAN_PWM_CLOCK_6MHZ |
+		IT8772F_FAN_CTL_POLARITY_HIGH;
+	it8772f_envc_write(res, IT8772F_FAN_CTL_MODE, reg);
+
+	/* Enable output in smart mode */
+	reg = it8772f_envc_read(res, IT8772F_FAN_MAIN_CTL);
+	reg |= IT8772F_FAN_MAIN_CTL_TAC_SMART(fan);
+	reg |= IT8772F_FAN_MAIN_CTL_TAC_EN(fan);
+	it8772f_envc_write(res, IT8772F_FAN_MAIN_CTL, reg);
+
+	switch (fan) {
+	case 2:
+		/* Enable software operation */
+		it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_MODE,
+				   IT8772F_FAN_CTL_PWM_MODE_SOFTWARE);
+		/* Disable Smoothing */
+		it8772f_envc_write(res, IT8772F_FAN_CTL2_AUTO_MODE,
+				   IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS);
+		/* Set a default medium fan speed */
+		it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, 0x80);
+		break;
+	case 3:
+		/* Enable software operation */
+		it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_MODE,
+				   IT8772F_FAN_CTL_PWM_MODE_SOFTWARE);
+		/* Disable Smoothing */
+		it8772f_envc_write(res, IT8772F_FAN_CTL3_AUTO_MODE,
+				   IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS);
+		/* Set a default medium fan speed */
+		it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, 0x80);
+		break;
+	}
+}
+
+static void it8772f_init(device_t dev)
+{
+	struct superio_ite_it8772f_config *conf = dev->chip_info;
+	struct resource *res;
+
+	if (!dev->enabled)
+		return;
+
+	switch (dev->path.pnp.device) {
+	case IT8772F_EC:
+		res = find_resource(dev, PNP_IDX_IO0);
+		if (!res)
+			break;
+
+		/* Enable PECI if configured */
+		it8772f_enable_peci(res, conf->peci_tmpin);
+
+		/* Enable FANx if configured */
+		if (conf->fan1_enable)
+			it8772f_enable_fan(res, 1);
+		if (conf->fan2_enable)
+			it8772f_enable_fan(res, 2);
+		if (conf->fan3_enable)
+			it8772f_enable_fan(res, 3);
+		break;
+	case IT8772F_GPIO:
+		/* Set GPIO output levels */
+		res = find_resource(dev, PNP_IDX_IO1);
+		if (res) {
+			if (conf->gpio_set1)
+				outb(conf->gpio_set1, res->base + 0);
+			if (conf->gpio_set2)
+				outb(conf->gpio_set2, res->base + 1);
+			if (conf->gpio_set3)
+				outb(conf->gpio_set3, res->base + 2);
+			if (conf->gpio_set4)
+				outb(conf->gpio_set4, res->base + 3);
+			if (conf->gpio_set5)
+				outb(conf->gpio_set5, res->base + 4);
+			if (conf->gpio_set6)
+				outb(conf->gpio_set6, res->base + 5);
+		}
+		break;
+	case IT8772F_KBCK:
+		if (!conf->skip_keyboard) {
+			set_kbc_ps2_mode();
+			pc_keyboard_init(&conf->keyboard);
+		}
+		break;
+	case IT8772F_KBCM:
+		break;
+	case IT8772F_IR:
+		break;
+	}
+}
+
+static void it8772f_pnp_set_resources(device_t dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_resources(dev);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static void it8772f_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static void it8772f_pnp_enable(device_t dev)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, !!dev->enabled);
+	pnp_exit_ext_func_mode(dev);
+}
+
+static struct device_operations ops = {
+	.read_resources		= pnp_read_resources,
+	.set_resources		= it8772f_pnp_set_resources,
+	.enable_resources	= it8772f_pnp_enable_resources,
+	.enable			= it8772f_pnp_enable,
+	.init			= it8772f_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	/* Floppy Disk Controller */
+	{ &ops, IT8772F_FDC, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	/* Serial Port 1 */
+	{ &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	/* Environmental Controller */
+	{ &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+	  {0x0ff8, 0}, {0x0ffc, 4}, },
+	/* KBC Keyboard */
+	{ &ops, IT8772F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0,
+	  {0x0fff, 0}, {0x0fff, 4}, },
+	/* KBC Mouse */
+	{ &ops, IT8772F_KBCM, PNP_IRQ0, },
+	/* 27 GPIOs */
+	{ &ops, IT8772F_GPIO, PNP_IO0 | PNP_IO1,
+	  {0x0fff, 0}, {0x0ff8, 0}, },
+	/* Infrared */
+	{ &ops, IT8772F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+		ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_ite_it8772f_ops = {
+	CHIP_NAME("ITE IT8772F Super I/O")
+	.enable_dev = enable_dev,
+};
diff --git a/src/superio/nuvoton/Kconfig b/src/superio/nuvoton/Kconfig
index 7b2d9dc..28fa1ef 100644
--- a/src/superio/nuvoton/Kconfig
+++ b/src/superio/nuvoton/Kconfig
@@ -19,3 +19,6 @@
 
 config SUPERIO_NUVOTON_WPCM450
 	bool
+
+config SUPERIO_NUVOTON_NCT6776F
+	bool
diff --git a/src/superio/nuvoton/Makefile.inc b/src/superio/nuvoton/Makefile.inc
index 2f2ea96..995cc9d 100644
--- a/src/superio/nuvoton/Makefile.inc
+++ b/src/superio/nuvoton/Makefile.inc
@@ -18,3 +18,4 @@
 ##
 
 subdirs-y += wpcm450
+subdirs-y += nct6776f
diff --git a/src/superio/nuvoton/nct6776f/Makefile.inc b/src/superio/nuvoton/nct6776f/Makefile.inc
new file mode 100644
index 0000000..7b449ed
--- /dev/null
+++ b/src/superio/nuvoton/nct6776f/Makefile.inc
@@ -0,0 +1,22 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+##
+
+ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6776F) += superio.c
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/superio/nuvoton/nct6776f/chip.h
similarity index 60%
copy from src/cpu/x86/mmx_disable.inc
copy to src/superio/nuvoton/nct6776f/chip.h
index 1a4e70f..5f7ef5b 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/superio/nuvoton/nct6776f/chip.h
@@ -1,11 +1,12 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,8 +18,17 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef SUPERIO_NUVOTON_NCT6776F_CHIP_H
+#define SUPERIO_NUVOTON_NCT6776F_CHIP_H
 
+struct chip_operations;
+extern struct chip_operations superio_nuvoton_nct6776f_ops;
+
+#include <pc80/keyboard.h>
+
+struct superio_nuvoton_nct6776f_config {
+	
+	struct pc_keyboard keyboard;
+};
+
+#endif
diff --git a/src/superio/nuvoton/nct6776f/early_init.c b/src/superio/nuvoton/nct6776f/early_init.c
new file mode 100644
index 0000000..e7b0759
--- /dev/null
+++ b/src/superio/nuvoton/nct6776f/early_init.c
@@ -0,0 +1,45 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <arch/romcc_io.h>
+
+static void pnp_enter_ext_func_mode(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0x87, port);
+	outb(0x87, port);
+}
+
+static void pnp_exit_ext_func_mode(device_t dev)
+{
+	u16 port = dev >> 8;
+	outb(0xaa, port);
+}
+
+static void inline nct6776f_enable_serial(device_t dev, u16 iobase)
+{
+	pnp_enter_ext_func_mode(dev);
+	pnp_set_logical_device(dev);
+	pnp_set_enable(dev, 0);
+	pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
+	pnp_set_enable(dev, 1);
+	pnp_exit_ext_func_mode(dev);
+}
+
diff --git a/src/cpu/x86/mmx_disable.inc b/src/superio/nuvoton/nct6776f/nct6776f.h
similarity index 64%
copy from src/cpu/x86/mmx_disable.inc
copy to src/superio/nuvoton/nct6776f/nct6776f.h
index 1a4e70f..c12cab6 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/superio/nuvoton/nct6776f/nct6776f.h
@@ -1,11 +1,12 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -17,8 +18,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef SUPERIO_NUVOTON_NCT6776F_NCT6776F_H
+#define SUPERIO_NUVOTON_NCT6776F_NCT6776F_H
 
+#define NCT6776F_SP1  0x02 /* COM1 */
+#define NCT6776F_SP2  0x03 /* COM2 */
+#define NCT6776F_KBC  0x05 /* Keyboard */
+
+#endif
diff --git a/src/superio/nuvoton/nct6776f/superio.c b/src/superio/nuvoton/nct6776f/superio.c
new file mode 100644
index 0000000..1896978
--- /dev/null
+++ b/src/superio/nuvoton/nct6776f/superio.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include <stdlib.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <pc80/keyboard.h>
+#include "chip.h"
+#include "nct6776f.h"
+
+static void init(device_t dev)
+{
+	struct superio_nuvoton_nct6776f_config *conf = dev->chip_info;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case NCT6776F_KBC:
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = pnp_set_resources,
+	.enable_resources = pnp_enable_resources,
+	.enable           = pnp_enable,
+	.init             = init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, NCT6776F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, },
+	{ &ops, NCT6776F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, },
+	{ &ops, NCT6776F_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, },
+};
+
+static void enable_dev(struct device *dev)
+{
+	pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_nuvoton_nct6776f_ops = {
+	CHIP_NAME("NUVOTON NCT6776F Super I/O")
+	.enable_dev = enable_dev,
+};
diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig
index 7378d18..85b7e39 100644
--- a/src/superio/smsc/Kconfig
+++ b/src/superio/smsc/Kconfig
@@ -37,5 +37,7 @@
 	bool
 config SUPERIO_SMSC_KBC1100
 	bool
+config SUPERIO_SMSC_MEC1308
+	bool
 config SUPERIO_SMSC_SMSCSUPERIO
 	bool
diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc
index 68d4d56..38ea5fa 100644
--- a/src/superio/smsc/Makefile.inc
+++ b/src/superio/smsc/Makefile.inc
@@ -27,4 +27,5 @@
 subdirs-y += lpc47n227
 subdirs-y += sio10n268
 subdirs-y += kbc1100
+subdirs-y += mec1308
 subdirs-y += smscsuperio
diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c
new file mode 100644
index 0000000..41e1b10
--- /dev/null
+++ b/src/superio/smsc/lpc47n207/early_serial.c
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/*
+ * This code tries to discover the SMSC LPC47N207 superio chip which can be
+ * connected over an LPC dongle. The chip could be bootstrap mapped to one of
+ * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e.
+ *
+ * Initializing the UART requires accesses to a few control registers. This
+ * structure includes the register offset and the value to write (along with
+ * the mask).
+ */
+typedef struct {
+	u8 conf_reg;
+	u8 value;
+	u8 mask;
+} uart_conf;
+
+/* All regs/values to write to initialize the LPC47N207 UART */
+static const uart_conf uart_conf_data [] = {
+	{2, (1 << 3), (1 << 3)},    /* cr02, enable Primary UART power */
+	{0xc, (1 << 6), (1 << 6)},  /* cr0c, enable Primary UART high speed */
+	{0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff},  /* cr24, base addr */
+};
+
+void try_enabling_LPC47N207_uart(void)
+{
+	device_t dev = PCH_LPC_DEV;
+	u16 saved_basic_config;
+	u16 saved_extended_config;
+	u8 reg_value;
+	const uart_conf* conf_item;
+	u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e};
+	u16 lpc_port;
+	int i, j;
+
+	/* preserve the LPC controller conffguration */
+	saved_basic_config = pci_read_config16(dev, LPC_EN);
+	saved_extended_config = pci_read_config32(dev, LPC_GEN1_DEC);
+
+	/* enable COMA mapping and all possible LPC addresses of 47N207 */
+	pci_write_config16(dev, LPC_EN,
+			   saved_basic_config |
+			   CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN);
+
+	/* map full 256 bytes at 0x1600 to the LPC bus */
+	pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601);
+
+	/* Set COM1/COM2 decode range */
+	pci_write_config16(dev, LPC_IO_DEC, 0x0010);
+
+#define CONFIG_ENABLE    0x55
+#define CONFIG_DISABLE   0xaa
+
+	for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) {
+		lpc_port = lpc_ports[j];
+
+		/* enable CONFIG mode */
+		outb(CONFIG_ENABLE, lpc_port);
+		reg_value=inb(lpc_port);
+		if (reg_value != CONFIG_ENABLE) {
+			continue; /* There is no LPC device at this address */
+		}
+
+		do {
+			/*
+			 * Registers 12 and 13 hold config address, look for a
+			 * match.
+			 */
+			outb(0x12, lpc_port);
+			reg_value=inb(lpc_port + 1);
+			if (reg_value != (lpc_port & 0xff))
+			    break;
+
+			outb(0x13, lpc_port);
+			reg_value=inb(lpc_port + 1);
+			if (reg_value != (lpc_port >> 8))
+				break;
+
+			/* This must be the SMSC LPC 47N207, enable the UART. */
+			for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) {
+				u8 reg, value, mask;
+
+				conf_item = uart_conf_data + i;
+
+				reg = conf_item->conf_reg;
+				value = conf_item->value;
+				mask = conf_item->mask;
+
+				outb(reg, lpc_port);
+				reg_value = inb(lpc_port + 1);
+				reg_value &= ~mask;
+				reg_value |= (value & mask);
+				outb(reg_value, lpc_port + 1);
+			}
+			/* Keep COMA UART enable bit on */
+			saved_basic_config |=  COMA_LPC_EN;
+		} while (0);
+		outb(CONFIG_DISABLE, lpc_port);
+	}
+
+	/* Restore PCH config state. */
+	pci_write_config16(dev, LPC_EN, saved_basic_config);
+	pci_write_config32(dev, LPC_GEN1_DEC, saved_extended_config);
+
+}
diff --git a/src/cpu/x86/mmx_disable.inc b/src/superio/smsc/lpc47n207/lpc47n207.h
similarity index 68%
copy from src/cpu/x86/mmx_disable.inc
copy to src/superio/smsc/lpc47n207/lpc47n207.h
index 1a4e70f..69689a4 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/superio/smsc/lpc47n207/lpc47n207.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -14,11 +14,12 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H
+#define SUPERIO_SMSC_LPC47N207_LPC47N207_H
 
+extern void try_enabling_LPC47N207_uart(void);
+
+#endif
diff --git a/src/superio/smsc/mec1308/Makefile.inc b/src/superio/smsc/mec1308/Makefile.inc
new file mode 100644
index 0000000..b2b7baa
--- /dev/null
+++ b/src/superio/smsc/mec1308/Makefile.inc
@@ -0,0 +1,20 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+
+ramstage-$(CONFIG_SUPERIO_SMSC_MEC1308) += superio.c
diff --git a/src/superio/smsc/mec1308/acpi/superio.asl b/src/superio/smsc/mec1308/acpi/superio.asl
new file mode 100644
index 0000000..96f2ef8
--- /dev/null
+++ b/src/superio/smsc/mec1308/acpi/superio.asl
@@ -0,0 +1,261 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+// Scope is \_SB.PCI0.LPCB
+
+Device (SIO) {
+	OperationRegion (SIOA, SystemIO, 0x2E, 0x02)
+	Field (SIOA, ByteAcc, NoLock, Preserve)
+	{
+		SI2E, 8,
+		SI2F, 8,
+	}
+
+	IndexField (SI2E, SI2F, ByteAcc, NoLock, Preserve)
+	{
+		Offset (0x07),
+		SLDN, 8,	/* Logical Device Number */
+		Offset (0x30),
+		SACT, 8,	/* Activate */
+		Offset (0x60),
+		IO0H, 8,	/* Base Address 0 MSB */
+		IO0L, 8,	/* Base Address 0 LSB */
+		Offset (0x62),
+		IO1H, 8,	/* Base Address 1 MSB */
+		IO1L, 8,	/* Base Address 1 LSB */
+		Offset (0x70),
+		IQ00, 8,	/* Interrupt Select */
+	}
+
+	Name (LPM1, 1)		/* ACPI PM1 */
+	Name (LEC1, 2)		/* EC 1 */
+	Name (LEC2, 3)		/* EC 2 */
+	Name (LSP1, 4)		/* Serial Port */
+	Name (LKBC, 7)		/* Keyboard */
+	Name (LEC0, 8)		/* EC 0 */
+	Name (LMBX, 9)		/* Mailbox */
+
+	Method (ENTR, 0, NotSerialized)
+	{
+		Store (0x55, SI2E)
+	}
+
+	Method (EXIT, 0, NotSerialized)
+	{
+		Store (0xaa, SI2E)
+	}
+
+	/* Parse activate register for an LDN */
+	Method (ISEN, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (SACT, Local0)
+		EXIT ()
+
+		/* Check if it exists */
+		If (LEqual (Local0, 0xFF))
+		{
+			Return (0x00)
+		}
+
+		/* Check if activated */
+		If (LEqual (Local0, One))
+		{
+			Return (0x0F)
+		}
+		Else
+		{
+			Return (0x0D)
+		}
+	}
+
+	/* Enable an LDN via the activate register */
+	Method (SENA, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (One, SACT)
+		EXIT ()
+	}
+
+	/* Disable an LDN via the activate register */
+	Method (SDIS, 1, NotSerialized)
+	{
+		ENTR ()
+		Store (Arg0, SLDN)
+		Store (Zero, SACT)
+		EXIT ()
+	}
+
+#ifdef SIO_ENABLE_SPM1
+	Device (SPM1) {
+		Name (_HID, EISAID ("PNP0C02"))
+		Name (_UID, 1)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LPM1))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SPM1_IO0, SIO_SPM1_IO0, 0x08, 0x08)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SEC1
+	Device (SEC1) {
+		Name (_HID, EISAID ("PNP0C09"))
+		Name (_UID, 2)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LEC1))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC1_IO0, SIO_SEC1_IO0, 0x04, 0x04)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SEC2
+	Device (SEC2) {
+		Name (_HID, EISAID ("PNP0C09"))
+		Name (_UID, 3)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LEC2))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC2_IO0, SIO_SEC2_IO0, 0x04, 0x04)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SSP1
+	Device (SSP1) {
+		Name (_HID, EISAID ("PNP0501"))
+		Name (_UID, 4)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LSP1))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08)
+			IRQNoFlags () {SIO_SSP1_IRQ}
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SSP1_IO0, SIO_SSP1_IO0, 0x08, 0x08)
+			IRQNoFlags () {SIO_SSP1_IRQ}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SKBC
+	Device (SKBC)		// Keyboard
+	{
+		Name (_HID, EISAID("PNP0303"))
+		Name (_CID, EISAID("PNP030B"))
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LKBC))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+			IRQNoFlags () {1}
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IO (Decode16, 0x60, 0x60, 0x01, 0x01)
+			IO (Decode16, 0x64, 0x64, 0x01, 0x01)
+			IRQNoFlags () {1}
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SEC0
+	Device (SEC0) {
+		Name (_HID, EISAID ("PNP0C09"))
+		Name (_UID, 8)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LEC0))
+		}
+
+		Name (_CRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04)
+		})
+
+		Name (_PRS, ResourceTemplate ()
+		{
+			IO (Decode16, SIO_SEC0_IO0, SIO_SEC0_IO0, 0x04, 0x04)
+		})
+	}
+#endif
+
+#ifdef SIO_ENABLE_SMBX
+	Device (SMBX)		// Mailbox
+	{
+		Name (_HID, EISAID("PNP0C02"))
+		Name (_UID, 9)
+
+		Method (_STA, 0, NotSerialized) {
+			Return (ISEN (LMBX))
+		}
+
+		Name (_CRS, ResourceTemplate()
+		{
+			IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34)
+		})
+
+		Name (_PRS, ResourceTemplate()
+		{
+			IO (Decode16, SIO_SMBX_IO0, SIO_SMBX_IO0, 0x34, 0x34)
+		})
+	}
+#endif
+}
diff --git a/src/cpu/x86/mmx_disable.inc b/src/superio/smsc/mec1308/chip.h
similarity index 68%
copy from src/cpu/x86/mmx_disable.inc
copy to src/superio/smsc/mec1308/chip.h
index 1a4e70f..04e829d 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/superio/smsc/mec1308/chip.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,18 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#ifndef SUPERIO_SMSC_MEC1308_CHIP_H
+#define SUPERIO_SMSC_MEC1308_CHIP_H
 
+#include <pc80/keyboard.h>
+#include <uart8250.h>
+
+struct chip_operations;
+extern struct chip_operations superio_smsc_mec1308_ops;
+
+struct superio_smsc_mec1308_config {
+	
+	struct pc_keyboard keyboard;
+};
+
+#endif
diff --git a/src/cpu/x86/mmx_disable.inc b/src/superio/smsc/mec1308/mec1308.h
similarity index 74%
copy from src/cpu/x86/mmx_disable.inc
copy to src/superio/smsc/mec1308/mec1308.h
index 1a4e70f..2b61234 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/superio/smsc/mec1308/mec1308.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,11 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+#define MEC1308_PM1   1
+#define MEC1308_EC1   2
+#define MEC1308_EC2   3
+#define MEC1308_UART  4
+#define MEC1308_KBC   7
+#define MEC1308_EC0   8
+#define MEC1308_MBX   9
 
diff --git a/src/cpu/x86/mmx_disable.inc b/src/superio/smsc/mec1308/mec1308_early_init.c
similarity index 78%
rename from src/cpu/x86/mmx_disable.inc
rename to src/superio/smsc/mec1308/mec1308_early_init.c
index 1a4e70f..60d43a7 100644
--- a/src/cpu/x86/mmx_disable.inc
+++ b/src/superio/smsc/mec1308/mec1308_early_init.c
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2002 Eric Biederman <ebiederm@xmission.com>
+ * Copyright (C) 2011 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,8 +17,13 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
-	/*
-	 * Execute the EMMS (Empty MMX Technology State) instruction.
-	 */
-	emms
+/* Pre-RAM driver for the SMSC MEC1308 EC chip */
+
+#include <arch/romcc_io.h>
+#include "mec1308.h"
+
+static inline void mec1308_early_init(unsigned port)
+{
+
+}
 
diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c
new file mode 100644
index 0000000..dfa155f
--- /dev/null
+++ b/src/superio/smsc/mec1308/superio.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* RAM driver for the SMSC KBC1100 Super I/O chip */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console/console.h>
+#include <device/smbus.h>
+#include <string.h>
+#include <bitops.h>
+#include <pc80/keyboard.h>
+#include <stdlib.h>
+#include "chip.h"
+#include "mec1308.h"
+#if CONFIG_HAVE_ACPI_RESUME
+#include <arch/acpi.h>
+#endif
+
+static void pnp_enter_conf_state(device_t dev)
+{
+	outb(0x55, dev->path.pnp.port);
+}
+
+static void pnp_exit_conf_state(device_t dev)
+{
+	outb(0xaa, dev->path.pnp.port);
+}
+
+static void mec1308_pnp_set_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void mec1308_pnp_enable_resources(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_enable_resources(dev);
+	pnp_exit_conf_state(dev);
+}
+
+static void mec1308_pnp_enable(device_t dev)
+{
+	pnp_enter_conf_state(dev);
+	pnp_set_logical_device(dev);
+
+	if(dev->enabled) {
+		pnp_set_enable(dev, 1);
+	}
+	else {
+		pnp_set_enable(dev, 0);
+	}
+	pnp_exit_conf_state(dev);
+}
+
+static void mec1308_init(device_t dev)
+{
+	struct superio_smsc_mec1308_config *conf = dev->chip_info;
+
+	if (!dev->enabled)
+		return;
+
+	switch(dev->path.pnp.device) {
+	case MEC1308_KBC:
+#if CONFIG_HAVE_ACPI_RESUME
+		if (acpi_slp_type == 3)
+			return;
+#endif
+		pc_keyboard_init(&conf->keyboard);
+		break;
+	}
+}
+
+static struct device_operations ops = {
+	.read_resources   = pnp_read_resources,
+	.set_resources    = mec1308_pnp_set_resources,
+	.enable_resources = mec1308_pnp_enable_resources,
+	.enable           = mec1308_pnp_enable,
+	.init             = mec1308_init,
+};
+
+static struct pnp_info pnp_dev_info[] = {
+	{ &ops, MEC1308_PM1,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_EC1,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_EC2,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_UART, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, },
+	{ &ops, MEC1308_KBC,  PNP_IRQ0, { 0, 0 } /* IO Fixed at 0x60/0x64 */ },
+	{ &ops, MEC1308_EC0,  PNP_IO0, { 0x7ff, 0 } },
+	{ &ops, MEC1308_MBX,  PNP_IO0, { 0x7ff, 0 } },
+};
+
+static void enable_dev(device_t dev)
+{
+	pnp_enable_devices(dev, &pnp_ops,
+			   ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+}
+
+struct chip_operations superio_smsc_mec1308_ops = {
+	CHIP_NAME("SMSC MEC1308 EC SuperIO Interface")
+	.enable_dev = enable_dev
+};
+
diff --git a/src/vendorcode/Kconfig b/src/vendorcode/Kconfig
new file mode 100644
index 0000000..18a2068
--- /dev/null
+++ b/src/vendorcode/Kconfig
@@ -0,0 +1 @@
+source src/vendorcode/google/Kconfig
diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc
index de64572..e6d6bb1 100644
--- a/src/vendorcode/Makefile.inc
+++ b/src/vendorcode/Makefile.inc
@@ -1 +1,2 @@
 subdirs-y += amd
+subdirs-y += google
diff --git a/src/vendorcode/google/Kconfig b/src/vendorcode/google/Kconfig
new file mode 100644
index 0000000..d3f8590
--- /dev/null
+++ b/src/vendorcode/google/Kconfig
@@ -0,0 +1,19 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+source src/vendorcode/google/chromeos/Kconfig
diff --git a/src/vendorcode/google/Makefile.inc b/src/vendorcode/google/Makefile.inc
new file mode 100644
index 0000000..20d40a8
--- /dev/null
+++ b/src/vendorcode/google/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+subdirs-$(CONFIG_CHROMEOS) += chromeos
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
new file mode 100644
index 0000000..4f5a907
--- /dev/null
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -0,0 +1,55 @@
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+#
+config CHROMEOS
+	bool
+	default n
+	select TPM
+	select CACHE_ROM
+	help
+	  Enable ChromeOS specific features like the GPIO sub table in
+	  the coreboot table. NOTE: Enabling this option on an unsupported
+	  board will most likely break your build.
+
+config VBNV_OFFSET
+	hex
+	default 0x26
+	help
+	  CMOS offset for VbNv data. This value must match cmos.layout
+	  in the mainboard directory, minus 14 bytes for the RTC.
+
+config VBNV_SIZE
+	hex
+	default 0x10
+	help
+	  CMOS storage size for VbNv data. This value must match cmos.layout
+	  in the mainboard directory.
+
+config CHROMEOS_RAMOOPS
+	bool "Reserve space for Chrome OS ramoops"
+	default y
+
+config CHROMEOS_RAMOOPS_RAM_START
+	hex "Physical address of preserved RAM"
+	default 0x00f00000
+	depends on CHROMEOS_RAMOOPS
+
+config CHROMEOS_RAMOOPS_RAM_SIZE
+	hex "Size of preserved RAM"
+	default 0x00100000
+	depends on CHROMEOS_RAMOOPS
diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc
new file mode 100644
index 0000000..c1b1cce
--- /dev/null
+++ b/src/vendorcode/google/chromeos/Makefile.inc
@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+romstage-y += chromeos.c
+ramstage-y += chromeos.c
+romstage-y += vbnv.c
+ramstage-y += vbnv.c
+romstage-y += vboot.c
+ramstage-y += gnvs.c
diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl
new file mode 100644
index 0000000..dc4a0bf
--- /dev/null
+++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* This is the ChromeOS specific ACPI information needed by
+ * the mainboard's chromeos.asl
+ */
+
+VBT0,   32,	// 0x000 - Boot Reason
+VBT1,   32,	// 0x004 - Active Main Firmware
+VBT2,   32,	// 0x008 - Active EC Firmware
+VBT3,   16,	// 0x00c - CHSW
+VBT4, 2048,	// 0x00e - HWID
+VBT5,  512,	// 0x10e - FWID
+VBT6,  512,	// 0x14e - FRID
+VBT7,   32,	// 0x18e - active main firmware type
+VBT8,   32,	// 0x192 - Recovery Reason
+VBT9,   32,	// 0x196 - FMAP base address
+CHVD, 24576,	// 0x19a - VDAT space filled by verified boot
+VBTA,	32,	// 0xd9a - pointer to smbios FWID
+MEHH,  256,	// 0xd9e - Management Engine Hash
+		// 0xdbe
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
new file mode 100644
index 0000000..c1c3b38
--- /dev/null
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "chromeos.h"
+#include <arch/coreboot_tables.h>
+#include <console/console.h>
+
+int developer_mode_enabled(void)
+{
+	return get_developer_mode_switch();
+}
+
+int recovery_mode_enabled(void)
+{
+	/* TODO(reinauer): get information from VbInit.
+	 * the recovery mode switch is not the only reason to go
+	 * to recovery mode.
+	 */
+	return get_recovery_mode_switch() || get_recovery_mode_from_vbnv();
+}
+
diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h
new file mode 100644
index 0000000..ec0f3b7
--- /dev/null
+++ b/src/vendorcode/google/chromeos/chromeos.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __CHROMEOS_H__
+#define __CHROMEOS_H__
+
+/* functions implemented per mainboard: */
+int get_developer_mode_switch(void);
+int get_recovery_mode_switch(void);
+#ifdef __PRE_RAM__
+void save_chromeos_gpios(void);
+#endif
+
+/* functions implemented in vbnv.c: */
+int get_recovery_mode_from_vbnv(void);
+
+/* functions implemented in chromeos.c: */
+int developer_mode_enabled(void);
+int recovery_mode_enabled(void);
+
+/* functions implemented in vboot.c */
+void init_chromeos(int bootmode);
+
+#endif
diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c
new file mode 100644
index 0000000..46eba8a
--- /dev/null
+++ b/src/vendorcode/google/chromeos/gnvs.c
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include "gnvs.h"
+#if CONFIG_ADD_FDT
+#include <fdt/fdt.h>
+#include <fdt/libfdt.h>
+#include <fdt/libfdt_env.h>
+#endif
+
+chromeos_acpi_t *vboot_data;
+static u32 me_hash_saved[8];
+
+void chromeos_init_vboot(chromeos_acpi_t *chromeos)
+{
+	vboot_data = chromeos;
+
+	/* Copy saved ME hash into NVS */
+	memcpy(vboot_data->mehh, me_hash_saved, sizeof(vboot_data->mehh));
+}
+
+void chromeos_set_vboot_data_ptr(void *blob)
+{
+#if CONFIG_ADD_FDT
+	int node_offset, addr_cell_len;
+	const u32 *cell;
+	uintptr_t table_addr = (uintptr_t)vboot_data;
+	u32 table_addr32;
+	u64 table_addr64;
+	void *table_ptr;
+
+	cell = fdt_getprop(blob, 0, "#address-cells", NULL);
+	if (cell && *cell == 2) {
+		addr_cell_len = 8;
+		table_addr64 = cpu_to_fdt64(table_addr);
+		table_ptr = &table_addr64;
+	} else {
+		addr_cell_len = 4;
+		table_addr32 = cpu_to_fdt32(table_addr);
+		table_ptr = &table_addr32;
+	}
+
+	node_offset = fdt_path_offset(blob, "/chromeos-config");
+	if (node_offset < 0) {
+		printk(BIOS_ERR,
+			"Couldn't find /chromeos-config in the fdt.\n");
+		return;
+	}
+
+	if (fdt_setprop(blob, node_offset, "gnvs-vboot-table",
+			table_ptr, addr_cell_len) < 0) {
+		printk(BIOS_ERR, "Couldn't set gnvs-vboot-table.\n");
+	}
+#else
+	printk(BIOS_ERR, "No fdt, can't set gnvs-vboot-table.\n");
+#endif
+}
+
+void chromeos_set_me_hash(u32 *hash, int len)
+{
+	if ((len*sizeof(u32)) > sizeof(vboot_data->mehh))
+		return;
+
+	/* Copy to NVS or save until it is ready */
+	if (vboot_data)
+		memcpy(vboot_data->mehh, hash, len*sizeof(u32));
+	else
+		memcpy(me_hash_saved, hash, len*sizeof(u32));
+}
diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h
new file mode 100644
index 0000000..36922ba
--- /dev/null
+++ b/src/vendorcode/google/chromeos/gnvs.h
@@ -0,0 +1,69 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H
+#define __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H
+
+#define BOOT_REASON_OTHER	0
+#define BOOT_REASON_S3DIAG	9
+
+#define CHSW_RECOVERY_X86	(1 << 1)
+#define CHSW_RECOVERY_EC	(1 << 2)
+#define CHSW_DEVELOPER_SWITCH	(1 << 5)
+#define CHSW_FIRMWARE_WP_DIS	(1 << 9)
+
+#define ACTIVE_MAINFW_RECOVERY	0
+#define ACTIVE_MAINFW_RW_A	1
+#define ACTIVE_MAINFW_RW_B	2
+
+#define ACTIVE_MAINFW_TYPE_RECOVERY	0
+#define ACTIVE_MAINFW_TYPE_NORMAL	1
+#define ACTIVE_MAINFW_TYPE_DEVELOPER	2
+
+#define RECOVERY_REASON_NONE	0
+#define RECOVERY_REASON_ME	1
+// TODO(reinauer) other recovery reasons?
+
+#define ACTIVE_ECFW_RO		0
+#define ACTIVE_ECFW_RW		1
+
+typedef struct {
+	/* ChromeOS specific */
+	u32	vbt0;		// 00 boot reason
+	u32	vbt1;		// 04 active main firmware
+	u32	vbt2;		// 08 active ec firmware
+	u16	vbt3;		// 0c CHSW
+	u8	vbt4[256];	// 0e HWID
+	u8	vbt5[64];	// 10e FWID
+	u8	vbt6[64];	// 14e FRID - 275
+	u32	vbt7;		// 18e active main firmware type
+	u32	vbt8;		// 192 recovery reason
+	u32	vbt9;		// 196 fmap base address
+	u8	vdat[3072];	// 19a
+	u32	vbt10;		// d9a smbios bios version
+	u32	mehh[8];	// d9e management engine hash
+				// dbe
+} __attribute__((packed)) chromeos_acpi_t;
+
+extern chromeos_acpi_t *vboot_data;
+void chromeos_init_vboot(chromeos_acpi_t *chromeos);
+void chromeos_set_vboot_data_ptr(void *);
+void chromeos_set_me_hash(u32*, int);
+
+#endif
diff --git a/src/vendorcode/google/chromeos/vbnv.c b/src/vendorcode/google/chromeos/vbnv.c
new file mode 100644
index 0000000..2129461
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vbnv.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <pc80/mc146818rtc.h>
+#include <cpu/x86/car.h>
+#include "chromeos.h"
+
+#define VBNV_BLOCK_SIZE 16	/* Size of NV storage block in bytes */
+
+/* Constants for NV storage.  We use this rather than structs and
+ * bitfields so the data format is consistent across platforms and
+ * compilers.
+ */
+#define HEADER_OFFSET                0
+#define HEADER_MASK                     0xC0
+#define HEADER_SIGNATURE                0x40
+#define HEADER_FIRMWARE_SETTINGS_RESET  0x20
+#define HEADER_KERNEL_SETTINGS_RESET    0x10
+
+#define BOOT_OFFSET                  1
+#define BOOT_DEBUG_RESET_MODE           0x80
+#define BOOT_TRY_B_COUNT_MASK           0x0F
+
+#define RECOVERY_OFFSET              2
+#define LOCALIZATION_OFFSET          3
+
+#define DEV_FLAGS_OFFSET             4
+#define DEV_BOOT_USB_MASK               0x01
+
+#define FIRMWARE_FLAGS_OFFSET        5
+#define FIRMWARE_TEST_ERR_FUNC_MASK     0x38
+#define FIRMWARE_TEST_ERR_FUNC_SHIFT    3
+#define FIRMWARE_TEST_ERR_NUM_MASK      0x07
+
+#define KERNEL_FIELD_OFFSET         11
+#define CRC_OFFSET                  15
+
+static int vbnv_initialized CAR_GLOBAL;
+uint8_t vbnv[CONFIG_VBNV_SIZE] CAR_GLOBAL;
+
+/* Return CRC-8 of the data, using x^8 + x^2 + x + 1 polynomial.  A
+ * table-based algorithm would be faster, but for only 15 bytes isn't
+ * worth the code size.
+ */
+
+static uint8_t crc8(const uint8_t * data, int len)
+{
+	unsigned crc = 0;
+	int i, j;
+
+	for (j = len; j; j--, data++) {
+		crc ^= (*data << 8);
+		for (i = 8; i; i--) {
+			if (crc & 0x8000)
+				crc ^= (0x1070 << 3);
+			crc <<= 1;
+		}
+	}
+
+	return (uint8_t) (crc >> 8);
+}
+
+static void vbnv_setup(void)
+{
+	int i;
+
+	for (i = 0; i < CONFIG_VBNV_SIZE; i++)
+		vbnv[i] = cmos_read(CONFIG_VBNV_OFFSET + 14 + i);
+
+	/* Check data for consistency */
+	if ((HEADER_SIGNATURE != (vbnv[HEADER_OFFSET] & HEADER_MASK))
+	    || (crc8(vbnv, CRC_OFFSET) != vbnv[CRC_OFFSET])) {
+
+		/* Data is inconsistent (bad CRC or header),
+		 * so reset to defaults
+		 */
+		memset(vbnv, 0, VBNV_BLOCK_SIZE);
+		vbnv[HEADER_OFFSET] =
+		    (HEADER_SIGNATURE | HEADER_FIRMWARE_SETTINGS_RESET |
+		     HEADER_KERNEL_SETTINGS_RESET);
+	}
+	vbnv_initialized = 1;
+}
+
+int get_recovery_mode_from_vbnv(void)
+{
+	if (!vbnv_initialized)
+		vbnv_setup();
+	return vbnv[RECOVERY_OFFSET];
+}
diff --git a/src/vendorcode/google/chromeos/vboot.c b/src/vendorcode/google/chromeos/vboot.c
new file mode 100644
index 0000000..5bdb7a2
--- /dev/null
+++ b/src/vendorcode/google/chromeos/vboot.c
@@ -0,0 +1,236 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <pc80/tpm.h>
+#include <reset.h>
+#include "chromeos.h"
+
+//#define EXTRA_LOGGING
+#define UBOOT_DOES_TPM_STARTUP
+
+#define TPM_LARGE_ENOUGH_COMMAND_SIZE 256	/* saves space in the firmware */
+
+#define TPM_SUCCESS               ((u32)0x00000000)
+
+#define TPM_E_IOERROR             ((u32)0x0000001f)
+#define TPM_E_COMMUNICATION_ERROR ((u32)0x00005004)
+#define TPM_E_NON_FATAL           ((u32)0x00000800)
+#define TPM_E_INVALID_POSTINIT    ((u32)0x00000026)
+
+#define TPM_E_NEEDS_SELFTEST     ((u32)(TPM_E_NON_FATAL + 1))
+#define TPM_E_DOING_SELFTEST     ((u32)(TPM_E_NON_FATAL + 2))
+
+static const struct {
+	u8 buffer[12];
+} tpm_resume_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x2 }
+};
+
+static const struct {
+	u8 buffer[12];
+} tpm_startup_cmd = {
+	{0x0, 0xc1, 0x0, 0x0, 0x0, 0xc, 0x0, 0x0, 0x0, 0x99, 0x0, 0x1 }
+};
+
+static const struct {
+	u8 buffer[10];
+} tpm_continueselftest_cmd = {
+	{ 0x0, 0xc1, 0x0, 0x0, 0x0, 0xa, 0x0, 0x0, 0x0, 0x53 }
+};
+
+static inline void FromTpmUint32(const u8 * buffer, u32 * x)
+{
+	*x = ((buffer[0] << 24) |
+	      (buffer[1] << 16) | (buffer[2] << 8) | buffer[3]);
+}
+
+static inline int TpmCommandSize(const u8 * buffer)
+{
+	u32 size;
+	FromTpmUint32(buffer + sizeof(u16), &size);
+	return (int)size;
+}
+
+/* Gets the code field of a TPM command. */
+static inline int TpmCommandCode(const u8 * buffer)
+{
+	u32 code;
+	FromTpmUint32(buffer + sizeof(u16) + sizeof(u32), &code);
+	return code;
+}
+
+/* Gets the return code field of a TPM result. */
+static inline int TpmReturnCode(const u8 * buffer)
+{
+	return TpmCommandCode(buffer);
+}
+
+/* Like TlclSendReceive below, but do not retry if NEEDS_SELFTEST or
+ * DOING_SELFTEST errors are returned.
+ */
+static u32 TlclSendReceiveNoRetry(const u8 * request,
+				  u8 * response, int max_length)
+{
+	size_t response_length = max_length;
+	u32 result;
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: command: %x%x %x%x%x%x %x%x%x%x\n",
+	       request[0], request[1],
+	       request[2], request[3], request[4], request[5],
+	       request[6], request[7], request[8], request[9]);
+#endif
+
+	result = TPM_SUCCESS;
+	if (tis_sendrecv
+	    (request, TpmCommandSize(request), response, &response_length))
+		result = TPM_E_IOERROR;
+
+	if (0 != result) {
+		/* Communication with TPM failed, so response is garbage */
+		printk(BIOS_DEBUG,
+		       "TPM: command 0x%x send/receive failed: 0x%x\n",
+		       TpmCommandCode(request), result);
+		return TPM_E_COMMUNICATION_ERROR;
+	}
+	/* Otherwise, use the result code from the response */
+	result = TpmReturnCode(response);
+
+/* TODO: add paranoia about returned response_length vs. max_length
+ * (and possibly expected length from the response header).  See
+ * crosbug.com/17017 */
+
+#ifdef EXTRA_LOGGING
+	printk(BIOS_DEBUG, "TPM: response: %x%x %x%x%x%x %x%x%x%x\n",
+	       response[0], response[1],
+	       response[2], response[3], response[4], response[5],
+	       response[6], response[7], response[8], response[9]);
+#endif
+
+	printk(BIOS_DEBUG, "TPM: command 0x%x returned 0x%x\n",
+	       TpmCommandCode(request), result);
+
+	return result;
+}
+
+static inline u32 TlclContinueSelfTest(void)
+{
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+	printk(BIOS_DEBUG, "TPM: Continue self test\n");
+	/* Call the No Retry version of SendReceive to avoid recursion. */
+	return TlclSendReceiveNoRetry(tpm_continueselftest_cmd.buffer,
+				      response, sizeof(response));
+}
+
+/* Sends a TPM command and gets a response.  Returns 0 if success or the TPM
+ * error code if error. In the firmware, waits for the self test to complete
+ * if needed. In the host, reports the first error without retries. */
+static u32 TlclSendReceive(const u8 * request, u8 * response, int max_length)
+{
+	u32 result = TlclSendReceiveNoRetry(request, response, max_length);
+	/* When compiling for the firmware, hide command failures due to the self
+	 * test not having run or completed. */
+	/* If the command fails because the self test has not completed, try it
+	 * again after attempting to ensure that the self test has completed. */
+	if (result == TPM_E_NEEDS_SELFTEST || result == TPM_E_DOING_SELFTEST) {
+		result = TlclContinueSelfTest();
+		if (result != TPM_SUCCESS) {
+			return result;
+		}
+#if defined(TPM_BLOCKING_CONTINUESELFTEST) || defined(VB_RECOVERY_MODE)
+		/* Retry only once */
+		result = TlclSendReceiveNoRetry(request, response, max_length);
+#else
+		/* This needs serious testing.  The TPM specification says:
+		 * "iii. The caller MUST wait for the actions of
+		 * TPM_ContinueSelfTest to complete before reissuing the
+		 * command C1."  But, if ContinueSelfTest is non-blocking, how
+		 * do we know that the actions have completed other than trying
+		 * again? */
+		do {
+			result =
+			    TlclSendReceiveNoRetry(request, response,
+						   max_length);
+		} while (result == TPM_E_DOING_SELFTEST);
+#endif
+	}
+
+	return result;
+}
+
+static void init_vboot(int bootmode)
+{
+	u32 result;
+	u8 response[TPM_LARGE_ENOUGH_COMMAND_SIZE];
+
+#ifdef UBOOT_DOES_TPM_STARTUP
+	/* Doing TPM startup when we're not coming in on the S3 resume path
+	 * saves us roughly 20ms in boot time only. This does not seem to
+	 * be worth an API change to vboot_reference-firmware right now, so
+	 * let's keep the code around, but just bail out early:
+	 */
+	if (bootmode != 2)
+		return;
+#endif
+
+	printk(BIOS_DEBUG, "Verified boot TPM initialization.\n");
+
+	printk(BIOS_SPEW, "TPM: Init\n");
+	if (tis_init())
+		return;
+
+	printk(BIOS_SPEW, "TPM: Open\n");
+	if (tis_open())
+		return;
+
+
+	if (bootmode == 2) {
+		/* S3 Resume */
+		printk(BIOS_SPEW, "TPM: Resume\n");
+		result = TlclSendReceive(tpm_resume_cmd.buffer,
+					response, sizeof(response));
+		if (result == TPM_E_INVALID_POSTINIT) {
+			/* We're on a platform where the TPM maintains power
+			 * in S3, so it's already initialized.
+			 */
+			printk(BIOS_DEBUG, "TPM: Already initialized.\n");
+			return;
+		}
+	} else {
+		printk(BIOS_SPEW, "TPM: Startup\n");
+		result = TlclSendReceive(tpm_startup_cmd.buffer,
+					response, sizeof(response));
+	}
+
+	if (result == TPM_SUCCESS) {
+		printk(BIOS_SPEW, "TPM: OK.\n");
+		return;
+	}
+
+	printk(BIOS_ERR, "TPM: Error code 0x%x. Hard reset!\n", result);
+	hard_reset();
+}
+
+void init_chromeos(int bootmode)
+{
+	init_vboot(bootmode);
+}
diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c
index baa92ff..a9f96fa 100644
--- a/util/cbfstool/cbfs-mkpayload.c
+++ b/util/cbfstool/cbfs-mkpayload.c
@@ -161,7 +161,10 @@
 			continue;
 		}
 
-		segs[segments].type = PAYLOAD_SEGMENT_DATA;
+		if (phdr[i].p_flags & PF_X)
+			segs[segments].type = PAYLOAD_SEGMENT_CODE;
+		else
+			segs[segments].type = PAYLOAD_SEGMENT_DATA;
 		segs[segments].load_addr = (unsigned int)htonl(phdr[i].p_paddr);
 		segs[segments].mem_len = (unsigned int)htonl(phdr[i].p_memsz);
 		segs[segments].compression = htonl(algo);
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 4c28c29..f017b2e 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -81,8 +81,10 @@
 		base = strtoul(argv[6], NULL, 0);
 	}
 	cbfsfile = create_cbfs_file(cbfsname, filedata, &filesize, type, &base);
-	if (add_file_to_cbfs(cbfsfile, filesize, base))
+	if (add_file_to_cbfs(cbfsfile, filesize, base)) {
+		printf("Adding file '%s' failed.\n", filename);
 		return 1;
+	}
 	if (writerom(romname, rom, romsize))
 		return 1;
 	return 0;
@@ -130,8 +132,10 @@
 	cbfsfile =
 	    create_cbfs_file(cbfsname, payload, &filesize,
 			     CBFS_COMPONENT_PAYLOAD, &base);
-	if (add_file_to_cbfs(cbfsfile, filesize, base))
+	if (add_file_to_cbfs(cbfsfile, filesize, base)) {
+		printf("Adding payload '%s' failed.\n", filename);
 		return 1;
+	}
 	if (writerom(romname, rom, romsize))
 		return 1;
 	return 0;
@@ -180,8 +184,10 @@
 	    create_cbfs_file(cbfsname, stage, &filesize,
 			     CBFS_COMPONENT_STAGE, &base);
 
-	if (add_file_to_cbfs(cbfsfile, filesize, base))
+	if (add_file_to_cbfs(cbfsfile, filesize, base)) {
+		printf("Adding stage '%s' failed.\n", filename);
 		return 1;
+	}
 	if (writerom(romname, rom, romsize))
 		return 1;
 	return 0;
diff --git a/util/cbmem/cbmem.py b/util/cbmem/cbmem.py
new file mode 100755
index 0000000..3e8476d
--- /dev/null
+++ b/util/cbmem/cbmem.py
@@ -0,0 +1,204 @@
+#!/usr/bin/python
+#
+# cbmem.py - Linux space CBMEM contents parser
+#
+# Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+#
+'''
+Parse and display CBMEM contents.
+
+This module is meant to run on systems with coreboot based firmware.
+
+When started, it determines the amount of DRAM installed on the system, and
+then scans the top area of DRAM (right above the available memory size)
+looking for the CBMEM base signature at locations aligned at 0x20000
+boundaries.
+
+Once it finds the CBMEM signature, the utility parses the contents, reporting
+the section IDs/sizes and also reporting the contents of the tiemstamp and
+console sections.
+'''
+
+import mmap
+import re
+import struct
+import sys
+import time
+
+# These definitions follow src/include/cbmem.h
+CBMEM_MAGIC = 0x434f5245
+CBMEM_MAX_ENTRIES = 16
+
+CBMEM_ENTRY_FORMAT = '@LLQQ'
+CONSOLE_HEADER_FORMAT = '@LL'
+TIMESTAMP_HEADER_FORMAT = '@QLL'
+TIMESTAMP_ENTRY_FORMAT = '@LQ'
+
+mf_fileno = 0  # File number of the file providing access to memory.
+
+def align_up(base, alignment):
+    '''Increment to the alignment boundary.
+
+    Return the next integer larger than 'base' and divisible by 'alignment'.
+    '''
+
+    return base + alignment - base % alignment
+
+def normalize_timer(value, freq):
+    '''Convert timer reading into microseconds.
+
+    Get the free running clock counter value, divide it by the clock frequency
+    and multiply by 1 million to get reading in microseconds.
+
+    Then convert the value into an ASCII string with groups of three digits
+    separated by commas.
+
+    Inputs:
+      value: int, the clock reading
+      freq: float, the clock frequency
+
+    Returns:
+      A string presenting 'value' in microseconds.
+    '''
+
+    result = []
+    value = int(value * 1000000.0 / freq)
+    svalue = '%d' % value
+    vlength = len(svalue)
+    remainder = vlength % 3
+    if remainder:
+        result.append(svalue[0:remainder])
+    while remainder < vlength:
+        result.append(svalue[remainder:remainder+3])
+        remainder = remainder + 3
+    return ','.join(result)
+
+def get_cpu_freq():
+    '''Retrieve CPU frequency from sysfs.
+
+    Use /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the source.
+    '''
+    freq_str = open('/sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq'
+                    ).read()
+    # Convert reading into Hertz
+    return float(freq_str) * 1000.0
+
+def get_mem_size():
+    '''Retrieve amount of memory available to the CPU from /proc/meminfo.'''
+    mult = {
+        'kB': 1024
+        }
+    meminfo = open('/proc/meminfo').read()
+    m = re.search('MemTotal:.*\n', meminfo)
+    mem_string = re.search('MemTotal:.*\n', meminfo).group(0)
+    (_, size, mult_name) = mem_string.split()
+    return int(size) * mult[mult_name]
+
+def parse_mem_at(addr, format):
+    '''Read and parse a memory location.
+
+    This function reads memory at the passed in address, parses it according
+    to the passed in format specification and returns a list of values.
+
+    The first value in the list is the size of data matching the format
+    expression, and the rest of the elements of the list are the actual values
+    retrieved using the format.
+    '''
+
+    size = struct.calcsize(format)
+    delta = addr % 4096   # mmap requires the offset to be page size aligned.
+    mm = mmap.mmap(mf_fileno, size + delta,
+                   mmap.MAP_PRIVATE, offset=(addr - delta))
+    buf = mm.read(size + delta)
+    mm.close()
+    rv = [size,] + list(struct.unpack(format, buf[delta:size + delta + 1]))
+    return rv
+
+def dprint(text):
+    '''Debug print function.
+
+    Edit it to get the debug output.
+    '''
+
+    if False:
+        print text
+
+def process_timers(base):
+    '''Scan the array of timestamps found in CBMEM at address base.
+
+    For each timestamp print the timer ID and the value in microseconds.
+    '''
+
+    (step, base_time, max_entr, entr) = parse_mem_at(
+        base, TIMESTAMP_HEADER_FORMAT)
+
+    print('\ntime base %d, total entries %d' % (base_time, entr))
+    clock_freq = get_cpu_freq()
+    base = base + step
+    for i in range(entr):
+        (step, timer_id, timer_value) = parse_mem_at(
+            base, TIMESTAMP_ENTRY_FORMAT)
+        print '%d:%s ' % (timer_id, normalize_timer(timer_value, clock_freq)),
+        base = base + step
+    print
+
+def process_console(base):
+    '''Dump the console log buffer contents found at address base.'''
+
+    (step, size, cursor) = parse_mem_at(base, CONSOLE_HEADER_FORMAT)
+    print 'cursor at %d\n' % cursor
+
+    cons_string_format = '%ds' % min(cursor, size)
+    (_, cons_text) = parse_mem_at(base + step, cons_string_format)
+    print cons_text
+    print '\n'
+
+mem_alignment = 1024 * 1024 * 1024 # 1 GBytes
+table_alignment = 128 * 1024
+
+mem_size = get_mem_size()
+
+# start at memory address aligned at 128K.
+offset = align_up(mem_size, table_alignment)
+
+dprint('mem_size %x offset %x' %(mem_size, offset))
+mf = open("/dev/mem")
+mf_fileno = mf.fileno()
+
+while offset % mem_alignment: # do not cross the 1G boundary while searching
+    (step, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if magic == CBMEM_MAGIC:
+        offset = offset + step
+        break
+    offset += table_alignment
+else:
+    print 'Did not find the CBMEM'
+    sys.exit(0)
+
+for i in (range(1, CBMEM_MAX_ENTRIES)):
+    (_, magic, mid, base, size) = parse_mem_at(offset, CBMEM_ENTRY_FORMAT)
+    if mid == 0:
+        break
+
+    print '%x, %x, %x' % (mid, base, size)
+    if mid == 0x54494d45:
+        process_timers(base)
+    if mid == 0x434f4e53:
+        process_console(base)
+
+    offset = offset + step
+
+mf.close()
diff --git a/util/ifdtool/Makefile b/util/ifdtool/Makefile
new file mode 100644
index 0000000..b5ac8b2
--- /dev/null
+++ b/util/ifdtool/Makefile
@@ -0,0 +1,53 @@
+#
+# Makefile for ifdtool utility
+#
+# Copyright (C) 2011 by Google Inc
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published b
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+#
+
+PROGRAM = ifdtool
+
+CC      = gcc
+INSTALL = /usr/bin/install
+PREFIX  = /usr/local
+CFLAGS  = -O2 -g -Wall -W
+LDFLAGS = 
+
+OBJS = ifdtool.o
+
+all: dep $(PROGRAM)
+
+$(PROGRAM): $(OBJS)
+	$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
+
+clean:
+	rm -f $(PROGRAM) *.o *~
+
+distclean: clean
+	rm -f .dependencies
+
+dep:
+	@$(CC) $(CFLAGS) -MM *.c > .dependencies
+
+install: $(PROGRAM)
+	mkdir -p $(DESTDIR)$(PREFIX)/bin
+	$(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin
+	mkdir -p $(DESTDIR)$(PREFIX)/share/man/man8
+	$(INSTALL) $(PROGRAM).8 $(DESTDIR)$(PREFIX)/share/man/man8
+
+.PHONY: all clean distclean dep 
+
+-include .dependencies
+
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
new file mode 100644
index 0000000..67fbbb5
--- /dev/null
+++ b/util/ifdtool/ifdtool.c
@@ -0,0 +1,551 @@
+/*
+ * ifdtool - dump Intel Firmware Descriptor information
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <unistd.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <getopt.h>
+#include <fcntl.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include "ifdtool.h"
+
+static fdbar_t *find_fd(char *image, int size)
+{
+	int i, found = 0;
+
+	/* Scan for FD signature */
+	for (i = 0; i < (size - 4); i += 4) {
+		if (*(uint32_t *) (image + i) == 0x0FF0A55A) {
+			found = 1;
+			break;	// signature found.
+		}
+	}
+
+	if (!found) {
+		printf("No Flash Descriptor found in this image\n");
+		return NULL;
+	}
+
+	printf("Found Flash Descriptor signature at 0x%08x\n", i);
+
+	return (fdbar_t *) (image + i);
+}
+
+typedef struct {
+	int base, limit, size;
+} region_t;
+
+static region_t get_region(frba_t *frba, int region_type)
+{
+	region_t region;
+	region.base = 0, region.limit = 0, region.size = 0;
+
+	switch (region_type) {
+	case 0:
+		region.base = (frba->flreg0 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg0 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 1:
+		region.base = (frba->flreg1 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg1 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 2:
+		region.base = (frba->flreg2 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg2 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 3:
+		region.base = (frba->flreg3 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg3 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	case 4:
+		region.base = (frba->flreg4 & 0x00000fff) << 12;
+		region.limit = ((frba->flreg4 & 0x0fff0000) >> 4) | 0xfff;
+		break;
+	default:
+		fprintf(stderr, "Invalid region type.\n");
+		exit (EXIT_FAILURE);
+	}
+
+	region.size = region.limit - region.base + 1;
+
+	return region;
+}
+
+static const char *region_name(int region_type)
+{
+	static const char *regions[5] = {
+		"Flash Descriptor",
+		"BIOS",
+		"Intel ME",
+		"GbE",
+		"Platform Data"
+	};
+
+	if (region_type < 0 || region_type > 4) {
+		fprintf(stderr, "Invalid region type.\n");
+		exit (EXIT_FAILURE);
+	}
+
+	return regions[region_type];
+}
+
+static const char *region_filename(int region_type)
+{
+	static const char *region_filenames[5] = {
+		"flashregion_0_flashdescriptor.bin",
+		"flashregion_1_bios.bin",
+		"flashregion_2_intel_me.bin",
+		"flashregion_3_gbe.bin",
+		"flashregion_4_platform_data.bin"
+	};
+
+	if (region_type < 0 || region_type > 4) {
+		fprintf(stderr, "Invalid region type.\n");
+		exit (EXIT_FAILURE);
+	}
+
+	return region_filenames[region_type];
+}
+
+static void dump_frba(frba_t * frba)
+{
+	printf("\nFound Region Section\n");
+	printf("FLREG0:    0x%08x\n", frba->flreg0);
+	printf("FLREG1:    0x%08x\n", frba->flreg1);
+	printf("FLREG2:    0x%08x\n", frba->flreg2);
+	printf("FLREG3:    0x%08x\n", frba->flreg3);
+	printf("FLREG4:    0x%08x\n", frba->flreg4);
+}
+
+static void decode_spi_frequency(unsigned int freq)
+{
+	switch (freq) {
+	case SPI_FREQUENCY_20MHZ:
+		printf("20MHz");
+		break;
+	case SPI_FREQUENCY_33MHZ:
+		printf("33MHz");
+		break;
+	case SPI_FREQUENCY_50MHZ:
+		printf("50MHz");
+		break;
+	default:
+		printf("unknown<%x>MHz", freq);
+	}
+}
+
+static void dump_fcba(fcba_t * fcba)
+{
+	printf("\nFound Component Section\n");
+	printf("FLCOMP     0x%08x\n", fcba->flcomp);
+	printf("  Read ID/Read Status Clock Frequency: ");
+	decode_spi_frequency((fcba->flcomp >> 27) & 7);
+	printf("\n  Write/Erase Clock Frequency:         ");
+	decode_spi_frequency((fcba->flcomp >> 24) & 7);
+	printf("\n  Fast Read Clock Frequency:           ");
+	decode_spi_frequency((fcba->flcomp >> 21) & 7);
+	printf("\n");
+	printf("FLILL      0x%08x\n", fcba->flill);
+	printf("FLPB       0x%08x\n", fcba->flpb);
+}
+
+static void dump_fpsba(fpsba_t * fpsba)
+{
+	printf("\nFound PCH Strap Section\n");
+	printf("PCHSTRP0:  0x%08x\n", fpsba->pchstrp0);
+	printf("PCHSTRP1:  0x%08x\n", fpsba->pchstrp1);
+	printf("PCHSTRP2:  0x%08x\n", fpsba->pchstrp2);
+	printf("PCHSTRP3:  0x%08x\n", fpsba->pchstrp3);
+	printf("PCHSTRP4:  0x%08x\n", fpsba->pchstrp4);
+	printf("PCHSTRP5:  0x%08x\n", fpsba->pchstrp5);
+	printf("PCHSTRP6:  0x%08x\n", fpsba->pchstrp6);
+	printf("PCHSTRP7:  0x%08x\n", fpsba->pchstrp7);
+	printf("PCHSTRP8:  0x%08x\n", fpsba->pchstrp8);
+	printf("PCHSTRP9:  0x%08x\n", fpsba->pchstrp9);
+	printf("PCHSTRP10: 0x%08x\n", fpsba->pchstrp10);
+	printf("PCHSTRP11: 0x%08x\n", fpsba->pchstrp11);
+	printf("PCHSTRP12: 0x%08x\n", fpsba->pchstrp12);
+	printf("PCHSTRP13: 0x%08x\n", fpsba->pchstrp13);
+	printf("PCHSTRP14: 0x%08x\n", fpsba->pchstrp14);
+	printf("PCHSTRP15: 0x%08x\n", fpsba->pchstrp15);
+}
+
+static void dump_fmba(fmba_t * fmba)
+{
+	printf("\nFound Master Section\n");
+	printf("FLMSTR1:   0x%08x\n", fmba->flmstr1);
+	printf("FLMSTR2:   0x%08x\n", fmba->flmstr2);
+	printf("FLMSTR3:   0x%08x\n", fmba->flmstr3);
+}
+
+static void dump_fmsba(fmsba_t * fmsba)
+{
+	printf("\nFound Processor Strap Section\n");
+	printf("????:      0x%08x\n", fmsba->data[0]);
+	printf("????:      0x%08x\n", fmsba->data[1]);
+	printf("????:      0x%08x\n", fmsba->data[2]);
+	printf("????:      0x%08x\n", fmsba->data[3]);
+}
+
+static void dump_fd(char *image, int size)
+{
+	fdbar_t *fdb = find_fd(image, size);
+	if (!fdb)
+		exit(EXIT_FAILURE);
+
+	printf("FLMAP0:    0x%08x\n", fdb->flmap0);
+	printf("  NR:      %d\n", (fdb->flmap0 >> 24) & 7);
+	printf("  FRBA:    0x%x\n", ((fdb->flmap0 >> 16) & 0xff) << 4);
+	printf("  NC:      %d\n", ((fdb->flmap0 >> 8) & 3) + 1);
+	printf("  FCBA:    0x%x\n", ((fdb->flmap0) & 0xff) << 4);
+
+	printf("FLMAP1:    0x%08x\n", fdb->flmap1);
+	printf("  ISL:     0x%02x\n", (fdb->flmap1 >> 24) & 0xff);
+	printf("  FPSBA:   0x%x\n", ((fdb->flmap1 >> 16) & 0xff) << 4);
+	printf("  NM:      %d\n", (fdb->flmap1 >> 8) & 3);
+	printf("  FMBA:    0x%x\n", ((fdb->flmap1) & 0xff) << 4);
+
+	printf("FLMAP2:    0x%08x\n", fdb->flmap2);
+	printf("  PSL:     0x%04x\n", (fdb->flmap2 >> 8) & 0xffff);
+	printf("  FMSBA:   0x%x\n", ((fdb->flmap2) & 0xff) << 4);
+
+	printf("FLUMAP1:   0x%08x\n", fdb->flumap1);
+
+	dump_frba((frba_t *)
+			(image + (((fdb->flmap0 >> 16) & 0xff) << 4)));
+	dump_fcba((fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4)));
+	dump_fpsba((fpsba_t *)
+			(image + (((fdb->flmap1 >> 16) & 0xff) << 4)));
+	dump_fmba((fmba_t *) (image + (((fdb->flmap1) & 0xff) << 4)));
+	dump_fmsba((fmsba_t *) (image + (((fdb->flmap2) & 0xff) << 4)));
+}
+
+static void write_regions(char *image, int size)
+{
+	int i;
+
+	fdbar_t *fdb = find_fd(image, size);
+	if (!fdb)
+		exit(EXIT_FAILURE);
+
+	frba_t *frba =
+	    (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+
+	for (i = 0; i<5; i++) {
+		region_t region = get_region(frba, i);
+		printf("Flash Region %d (%s): %08x - %08x %s\n",
+		       i, region_name(i), region.base, region.limit,
+		       region.size < 1 ? "(unused)" : "");
+		if (region.size > 0) {
+			int region_fd;
+			region_fd = open(region_filename(i),
+					 O_WRONLY | O_CREAT | O_TRUNC,
+					 S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
+			if (write(region_fd, image + region.base, region.size) != region.size)
+				printf("Error while writing.");
+			close(region_fd);
+		}
+	}
+}
+
+static void write_image(char *filename, char *image, int size)
+{
+	char new_filename[FILENAME_MAX]; // allow long file names
+	int new_fd;
+
+	strncpy(new_filename, filename, FILENAME_MAX);
+	strncat(new_filename, ".new", FILENAME_MAX - strlen(filename));
+
+	printf("Writing new image to %s\n", new_filename);
+
+	// Now write out new image
+	new_fd = open(new_filename,
+			 O_WRONLY | O_CREAT | O_TRUNC,
+			 S_IRUSR | S_IWUSR | S_IRGRP | S_IROTH);
+	if (write(new_fd, image, size) != size)
+		printf("Error while writing.");
+	close(new_fd);
+}
+
+static void set_spi_frequency(char *filename, char *image, int size,
+			      enum spi_frequency freq)
+{
+	fdbar_t *fdb = find_fd(image, size);
+	fcba_t *fcba = (fcba_t *) (image + (((fdb->flmap0) & 0xff) << 4));
+
+	/* clear bits 21-29 */
+	fcba->flcomp &= ~0x3fe00000;
+	/* Read ID and Read Status Clock Frequency */
+	fcba->flcomp |= freq << 27;
+	/* Write and Erase Clock Frequency */
+	fcba->flcomp |= freq << 24;
+	/* Fast Read Clock Frequency */
+	fcba->flcomp |= freq << 21;
+
+	write_image(filename, image, size);
+}
+
+void inject_region(char *filename, char *image, int size, int region_type,
+		   char *region_fname)
+{
+	fdbar_t *fdb = find_fd(image, size);
+	if (!fdb)
+		exit(EXIT_FAILURE);
+	frba_t *frba =
+	    (frba_t *) (image + (((fdb->flmap0 >> 16) & 0xff) << 4));
+
+	region_t region = get_region(frba, region_type);
+	if (region.size <= 0xfff) {
+		fprintf(stderr, "Region %s is disabled in target. Not injecting.\n",
+				region_name(region_type));
+		exit(EXIT_FAILURE);
+	}
+
+	int region_fd = open(region_fname, O_RDONLY);
+	if (region_fd == -1) {
+		perror("Could not open file");
+		exit(EXIT_FAILURE);
+	}
+	struct stat buf;
+	if (fstat(region_fd, &buf) == -1) {
+		perror("Could not stat file");
+		exit(EXIT_FAILURE);
+	}
+	int region_size = buf.st_size;
+
+	printf("File %s is %d bytes\n", region_fname, region_size);
+
+	if ( (region_size > region.size) || ((region_type != 1) &&
+		(region_size > region.size))) {
+		fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)"
+				" bytes. Not injecting.\n",
+				region_name(region_type), region.size,
+				region.size, region_size, region_size);
+		exit(EXIT_FAILURE);
+	}
+
+	int offset = 0;
+	if ((region_type == 1) && (region_size < region.size)) {
+		fprintf(stderr, "Region %s is %d(0x%x) bytes. File is %d(0x%x)"
+				" bytes. Padding before injecting.\n",
+				region_name(region_type), region.size,
+				region.size, region_size, region_size);
+		offset = region.size - region_size;
+		memset(image + region.base, 0xff, offset);
+	}
+
+	if (read(region_fd, image + region.base + offset, region_size)
+							!= region_size) {
+		perror("Could not read file");
+		exit(EXIT_FAILURE);
+	}
+
+	close(region_fd);
+
+	printf("Adding %s as the %s section of %s\n",
+	       region_fname, region_name(region_type), filename);
+	write_image(filename, image, size);
+}
+
+static void print_version(void)
+{
+	printf("ifdtool v%s -- ", IFDTOOL_VERSION);
+	printf("Copyright (C) 2011 Google Inc.\n\n");
+	printf
+	    ("This program is free software: you can redistribute it and/or modify\n"
+	     "it under the terms of the GNU General Public License as published by\n"
+	     "the Free Software Foundation, version 2 of the License.\n\n"
+	     "This program is distributed in the hope that it will be useful,\n"
+	     "but WITHOUT ANY WARRANTY; without even the implied warranty of\n"
+	     "MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the\n"
+	     "GNU General Public License for more details.\n\n"
+	     "You should have received a copy of the GNU General Public License\n"
+	     "along with this program.  If not, see <http://www.gnu.org/licenses/>.\n\n");
+}
+
+static void print_usage(const char *name)
+{
+	printf("usage: %s [-vhdix?] <filename>\n", name);
+	printf("\n"
+	       "   -d | --dump:                      dump intel firmware descriptor\n"
+	       "   -x | --extract:                   extract intel fd modules\n"
+	       "   -i | --inject <region>:<module>   inject file <module> into region <region>\n"
+	       "   -s | --spifreq <20|33|50>         set the SPI frequency\n"
+	       "   -v | --version:                   print the version\n"
+	       "   -h | --help:                      print this help\n\n"
+	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform\n"
+	       "\n");
+}
+
+int main(int argc, char *argv[])
+{
+	int opt, option_index = 0;
+	int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0;
+	char *region_type_string = NULL, *region_fname = NULL;
+	int region_type = -1, inputfreq = 0;
+	enum spi_frequency spifreq = SPI_FREQUENCY_20MHZ;
+
+	static struct option long_options[] = {
+		{"dump", 0, NULL, 'd'},
+		{"extract", 0, NULL, 'x'},
+		{"inject", 1, NULL, 'i'},
+		{"spifreq", 1, NULL, 's'},
+		{"version", 0, NULL, 'v'},
+		{"help", 0, NULL, 'h'},
+		{0, 0, 0, 0}
+	};
+
+	while ((opt = getopt_long(argc, argv, "dxi:s:vh?",
+				  long_options, &option_index)) != EOF) {
+		switch (opt) {
+		case 'd':
+			mode_dump = 1;
+			break;
+		case 'x':
+			mode_extract = 1;
+			break;
+		case 'i':
+			// separate type and file name
+			region_type_string = strdup(optarg);
+			region_fname = strchr(region_type_string, ':');
+			if (!region_fname) {
+				print_usage(argv[0]);
+				exit(EXIT_FAILURE);
+			}
+			region_fname[0] = '\0';
+			region_fname++;
+			// Descriptor, BIOS, ME, GbE, Platform
+			// valid type?
+			if (!strcasecmp("Descriptor", region_type_string))
+				region_type = 0;
+			else if (!strcasecmp("BIOS", region_type_string))
+				region_type = 1;
+			else if (!strcasecmp("ME", region_type_string))
+				region_type = 2;
+			else if (!strcasecmp("GbE", region_type_string))
+				region_type = 3;
+			else if (!strcasecmp("Platform", region_type_string))
+				region_type = 4;
+			if (region_type == -1) {
+				fprintf(stderr, "No such region type: '%s'\n\n",
+					region_type_string);
+				print_usage(argv[0]);
+				exit(EXIT_FAILURE);
+			}
+			mode_inject = 1;
+			break;
+		case 's':
+			// Parse the requested SPI frequency
+			inputfreq = strtol(optarg, NULL, 0);
+			switch (inputfreq) {
+			case 20:
+				spifreq = SPI_FREQUENCY_20MHZ;
+				break;
+			case 33:
+				spifreq = SPI_FREQUENCY_33MHZ;
+				break;
+			case 50:
+				spifreq = SPI_FREQUENCY_50MHZ;
+				break;
+			default:
+				fprintf(stderr, "Invalid SPI Frequency: %d\n",
+					inputfreq);
+				print_usage(argv[0]);
+				exit(EXIT_FAILURE);
+			}
+			mode_spifreq = 1;
+			break;
+		case 'v':
+			print_version();
+			exit(EXIT_SUCCESS);
+			break;
+		case 'h':
+		case '?':
+		default:
+			print_usage(argv[0]);
+			exit(EXIT_SUCCESS);
+			break;
+		}
+	}
+
+	if ((mode_dump + mode_extract + mode_inject + mode_spifreq) > 1) {
+		fprintf(stderr, "Only one mode allowed.\n\n");
+		print_usage(argv[0]);
+		exit(EXIT_FAILURE);
+	}
+
+	if ((mode_dump + mode_extract + mode_inject + mode_spifreq) == 0) {
+		fprintf(stderr, "You need to specify a mode.\n\n");
+		print_usage(argv[0]);
+		exit(EXIT_FAILURE);
+	}
+
+	if (optind + 1 != argc) {
+		fprintf(stderr, "You need to specify a file.\n\n");
+		print_usage(argv[0]);
+		exit(EXIT_FAILURE);
+	}
+
+	char *filename = argv[optind];
+	int bios_fd = open(filename, O_RDONLY);
+	if (bios_fd == -1) {
+		perror("Could not open file");
+		exit(EXIT_FAILURE);
+	}
+	struct stat buf;
+	if (fstat(bios_fd, &buf) == -1) {
+		perror("Could not stat file");
+		exit(EXIT_FAILURE);
+	}
+	int size = buf.st_size;
+
+	printf("File %s is %d bytes\n", filename, size);
+
+	char *image = malloc(size);
+	if (!image) {
+		printf("Out of memory.\n");
+		exit(EXIT_FAILURE);
+	}
+
+	if (read(bios_fd, image, size) != size) {
+		perror("Could not read file");
+		exit(EXIT_FAILURE);
+	}
+
+	close(bios_fd);
+
+	if (mode_dump)
+		dump_fd(image, size);
+
+	if (mode_extract)
+		write_regions(image, size);
+
+	if (mode_inject)
+		inject_region(filename, image, size, region_type,
+				region_fname);
+
+	if (mode_spifreq)
+		set_spi_frequency(filename, image, size, spifreq);
+
+	free(image);
+
+	return 0;
+}
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
new file mode 100644
index 0000000..9bf3794
--- /dev/null
+++ b/util/ifdtool/ifdtool.h
@@ -0,0 +1,87 @@
+/*
+ * ifdtool - dump intel firmware descriptors
+ *
+ * Copyright (C) 2011 Google Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <stdint.h>
+#define IFDTOOL_VERSION "1.0"
+
+enum spi_frequency {
+	SPI_FREQUENCY_20MHZ = 0,
+	SPI_FREQUENCY_33MHZ = 1,
+	SPI_FREQUENCY_50MHZ = 4,
+};
+
+// flash descriptor
+typedef struct {
+	uint32_t flvalsig;
+	uint32_t flmap0;
+	uint32_t flmap1;
+	uint32_t flmap2;
+	uint8_t  reserved[0xefc - 0x20];
+	uint32_t flumap1;
+} __attribute__((packed)) fdbar_t;
+
+// regions
+typedef struct {
+	uint32_t flreg0;
+	uint32_t flreg1;
+	uint32_t flreg2;
+	uint32_t flreg3;
+	uint32_t flreg4;
+} __attribute__((packed)) frba_t;
+
+// component section
+typedef struct {
+	uint32_t flcomp;
+	uint32_t flill;
+	uint32_t flpb;
+} __attribute__((packed)) fcba_t;
+
+// pch strap
+typedef struct {
+	uint32_t pchstrp0;
+	uint32_t pchstrp1;
+	uint32_t pchstrp2;
+	uint32_t pchstrp3;
+	uint32_t pchstrp4;
+	uint32_t pchstrp5;
+	uint32_t pchstrp6;
+	uint32_t pchstrp7;
+	uint32_t pchstrp8;
+	uint32_t pchstrp9;
+	uint32_t pchstrp10;
+	uint32_t pchstrp11;
+	uint32_t pchstrp12;
+	uint32_t pchstrp13;
+	uint32_t pchstrp14;
+	uint32_t pchstrp15;
+} __attribute__((packed)) fpsba_t;
+
+// master
+typedef struct {
+	uint32_t flmstr1;
+	uint32_t flmstr2;
+	uint32_t flmstr3;
+} __attribute__((packed)) fmba_t;
+
+// processor strap
+typedef struct {
+	uint32_t data[8];
+} __attribute__((packed)) fmsba_t;
+
+
diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c
index e79380a..0ab8c07 100644
--- a/util/inteltool/cpu.c
+++ b/util/inteltool/cpu.c
@@ -32,7 +32,7 @@
 {
 	uint32_t ret;
 
-#if defined(__DARWIN__) && !defined(__LP64__)
+#if 1 || defined(__DARWIN__) && !defined(__LP64__)
 	asm volatile (
 		"pushl %%ebx\n"
 		"cpuid\n"
@@ -61,8 +61,10 @@
 	}
 
 	if (read(fd_msr, buf, 8) == 8) {
-		msr.lo = *(uint32_t *)buf;
-		msr.hi = *(uint32_t *)(buf + 4);
+		msr.lo = buf[0] | (buf[1] << 8) |
+			 (buf[2] << 16) | (buf[3] << 24);
+		msr.hi = buf[4] | (buf[5] << 8) |
+			 (buf[6] << 16) | (buf[7] << 24);
 
 		return msr;
 	}
diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c
index a416106..79d6051 100644
--- a/util/inteltool/inteltool.c
+++ b/util/inteltool/inteltool.c
@@ -21,6 +21,7 @@
 
 #include <stdio.h>
 #include <stdlib.h>
+#include <inttypes.h>
 #include <getopt.h>
 #include <fcntl.h>
 #include <sys/mman.h>
@@ -93,7 +94,8 @@
 		    fd_mem, (off_t) phys_addr);
 
 	if (virt_addr == MAP_FAILED) {
-		printf("Error mapping physical memory 0x%08lx[0x%x]\n", phys_addr, len);
+		printf("Error mapping physical memory 0x%08" PRIx64 "[0x%x]\n",
+			phys_addr, len);
 		return NULL;
 	}
 
diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c
index 946b8a9..df39fcc 100644
--- a/util/kconfig/confdata.c
+++ b/util/kconfig/confdata.c
@@ -674,6 +674,33 @@
 	return res;
 }
 
+/*
+ * Return malloced string the contents of which are a concatenation of the
+ * directory name of the first argument and the second argument.
+ */
+static char* get_tmp_file_name(const char* base, const char *tmp_name)
+{
+        char *file_name, *p;
+        /* for sure a few bytes longer than needed */
+        int file_name_size = strlen(base) + sizeof(file_name) + 10;
+
+        file_name = malloc(file_name_size);
+        if (!file_name) {
+                fprintf(stderr, "%s:%d: failed to allocate %d bytes\n",
+                        __FILE__, __LINE__, file_name_size);
+               return 0;
+        }
+
+        strcpy(file_name, base);
+        p = strrchr(file_name, '/');
+        if (p)
+                strcpy(p + 1, tmp_name);
+        else
+                strcpy(file_name, tmp_name);
+
+        return file_name;
+}
+
 int conf_write_autoconf(void)
 {
 	struct symbol *sym;
@@ -682,9 +709,19 @@
 	FILE *out, *out_h;
 	time_t now;
 	int i, l;
+	char *tmp_conf, *tmp_conf_h;
 
 	sym_clear_all_valid();
 
+	name = getenv("KCONFIG_AUTOHEADER");
+	if (!name)
+		name = "include/linux/autoconf.h";
+
+	tmp_conf = get_tmp_file_name(name, ".tmpconfig");
+	tmp_conf_h = get_tmp_file_name(name, ".tmpconfig.h");
+	if (!tmp_conf || !tmp_conf_h)
+		return 1;
+
 	file_write_dep("build/auto.conf.cmd");
 
 #if 0
@@ -692,11 +729,11 @@
 		return 1;
 #endif
 
-	out = fopen(".tmpconfig", "w");
+	out = fopen(tmp_conf, "w");
 	if (!out)
 		return 1;
 
-	out_h = fopen(".tmpconfig.h", "w");
+	out_h = fopen(tmp_conf_h, "w");
 	if (!out_h) {
 		fclose(out);
 		return 1;
@@ -787,11 +824,8 @@
 	fclose(out);
 	fclose(out_h);
 
-	name = getenv("KCONFIG_AUTOHEADER");
-	if (!name)
-		name = "include/linux/autoconf.h";
 	UNLINK_IF_NECESSARY(name);
-	if (rename(".tmpconfig.h", name))
+	if (rename(tmp_conf_h, name))
 		return 1;
 	name = getenv("KCONFIG_AUTOCONFIG");
 	if (!name)
@@ -801,9 +835,11 @@
 	 * and this marks the successful completion of the previous steps.
 	 */
 	UNLINK_IF_NECESSARY(name);
-	if (rename(".tmpconfig", name))
+	if (rename(tmp_conf, name))
 		return 1;
 
+	free(tmp_conf_h);
+	free(tmp_conf);
 	return 0;
 }
 
diff --git a/util/nvramtool/cbfs.h b/util/nvramtool/cbfs.h
index 5f9db8d..768b204 100644
--- a/util/nvramtool/cbfs.h
+++ b/util/nvramtool/cbfs.h
@@ -172,7 +172,6 @@
 #define CBFS_NAME(_c) (((char *) (_c)) + sizeof(struct cbfs_file))
 #define CBFS_SUBHEADER(_p) ( (void *) ((((u8 *) (_p)) + ntohl((_p)->offset))) )
 
-void * cbfs_get_file(const char *name);
 struct cbfs_file *cbfs_find(const char *name);
 void *cbfs_find_file(const char *name, unsigned int type, unsigned int *len);
 
diff --git a/util/nvramtool/cli/nvramtool.c b/util/nvramtool/cli/nvramtool.c
index bc929da..f5d8caa 100644
--- a/util/nvramtool/cli/nvramtool.c
+++ b/util/nvramtool/cli/nvramtool.c
@@ -143,7 +143,8 @@
 		
 		if (fd_stat.st_size < 128) {
 			lseek(fd, 127, SEEK_SET);
-			write(fd, "\0", 1);
+			if (write(fd, "\0", 1) != 1)
+				fprintf(stderr, "Write failed.\n");
 			fsync(fd);
 		}
 		
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index c3448f3..dab04db 100755
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -131,6 +131,13 @@
 
 	struct stat st;
 	char *chip_h = malloc(strlen(path)+12);
+	sprintf(chip_h, "src/%s", path);
+	if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) {
+		fprintf(stderr, "ERROR: Chip component %s does not exist.\n",
+				path);
+		exit(1);
+	}
+
 	sprintf(chip_h, "src/%s/chip.h", path);
 	if ((stat(chip_h, &st) == -1) && (errno == ENOENT))
 		new_chip->chiph_exists = 0;
diff --git a/util/superiotool/ite.c b/util/superiotool/ite.c
index 0e43614..6318f38 100644
--- a/util/superiotool/ite.c
+++ b/util/superiotool/ite.c
@@ -708,6 +708,8 @@
 		{EOT}}},
 	{0x8761, "IT8761E", {
 		{EOT}}},
+	{0x8772, "IT8772F", {
+		{EOT}}},
 	{0x8780, "IT8780F", {
 		{EOT}}},
 	{EOT}
diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c
index 260f3bb2..0f355c5 100644
--- a/util/superiotool/smsc.c
+++ b/util/superiotool/smsc.c
@@ -685,9 +685,11 @@
 		{EOT}}},
 	{0x83, "SCH5514D", {	/* From sensors-detect */
 		{EOT}}},
+#if 0
 	{0x85, "SCH5317", {	/* From sensors-detect */
 		/* The SCH5317 can have either 0x85 or 0x8c as device ID. */
 		{EOT}}},
+#endif
 	{0x86, "SCH5127", {	/* From sensors-detect */
 		{EOT}}},
 	{0x89, "SCH5027", {	/* From sensors-detect (no public datasheet) */
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
index 19103c7..941c6ac 100644
--- a/util/xcompile/xcompile
+++ b/util/xcompile/xcompile
@@ -41,7 +41,8 @@
 # This should be a loop over all supported architectures
 TARCH=i386
 TWIDTH=32
-for gccprefixes in `pwd`/util/crossgcc/xgcc/bin/${TARCH}-elf- ${TARCH}-elf- ""; do
+for gccprefixes in `pwd`/util/crossgcc/xgcc/bin/${TARCH}-elf- ${CROSS_COMPILE} \
+		${TARCH}-elf- ""; do
 	if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then
 		continue
 	fi
@@ -78,11 +79,17 @@
 testcc "$CC" "$CFLAGS-Wa,--divide " && CFLAGS="$CFLAGS-Wa,--divide "
 testcc "$CC" "$CFLAGS-fno-stack-protector " && CFLAGS="$CFLAGS-fno-stack-protector "
 testcc "$CC" "$CFLAGS-Wl,--build-id=none " && CFLAGS="$CFLAGS-Wl,--build-id=none "
+# Use bfd linker instead of gold if available:
+testcc "$CC" "$CFLAGS-fuse-ld=bfd " && CFLAGS="$CFLAGS-fuse-ld=bfd " && LINKER_SUFFIX='.bfd'
+# Prevent SSE instructions sneaking in:
+testcc "$CC" "$CFLAGS-mno-sse " && CFLAGS="$CFLAGS-mno-sse "
 
-if which gcc 2>/dev/null >/dev/null; then
-	HOSTCC=gcc
-else
-	HOSTCC=cc
+if [ -z "${HOSTCC}" ]; then
+	if which gcc 2>/dev/null >/dev/null; then
+		HOSTCC=gcc
+	else
+		HOSTCC=cc
+	fi
 fi
 
 cat << EOF
@@ -90,7 +97,7 @@
 AS:=${GCCPREFIX}as ${ASFLAGS}
 CC:=${GCCPREFIX}gcc ${CFLAGS}
 AR:=${GCCPREFIX}ar
-LD:=${GCCPREFIX}ld ${LDFLAGS}
+LD:=${GCCPREFIX}ld${LINKER_SUFFIX} ${LDFLAGS}
 STRIP:=${GCCPREFIX}strip
 NM:=${GCCPREFIX}nm
 OBJCOPY:=${GCCPREFIX}objcopy