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chromium / chromiumos / third_party / coreboot / refs/heads/chromeos-2016.05
commit1d54f693ae7435bb1e29347620000b03b318880b[log] [tgz]
authorRonak Kanabar <ronak.kanabar@intel.com>Wed Mar 31 16:57:20 2021
committerCommit Bot <commit-bot@chromium.org>Mon Apr 19 20:23:38 2021
tree6f330d8ab058fc6ce4a1d5654eebd0ef20700096
parentb12a6685d4511daf943fa338e8cb04c6ab2f753d [diff]
UPSTREAM: vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2117_00

The headers added are generated as per FSP v2117_00.
Previous FSP version was v2081_02.
Changes Include:
- Adjust Reserved UPD Offset in FspmUpd.h and FspsUpd.h
- Remove FivrFaults and FivrEfficiency Upds from FspmUpd.h
- Few UPDs description update in FspmUpd.h and FspsUpd.h

BUG=b:184129128
BRANCH=None
TEST=Build and boot ADLRVP

Change-Id: Ib069e9bc36621f38a1c8486079e13393167d83a0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Original-Commit-Id: 369405090fc73e60f2e26f7bc1c5a8acc8305a5e
Original-Change-Id: I068552084b1ef3e5c4fba7a46240d116c92c7b5b
Original-Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/51977
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Original-Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2836445
2 files changed
tree: 6f330d8ab058fc6ce4a1d5654eebd0ef20700096
  1. .checkpatch.conf
  2. .clang-format
  3. .editorconfig
  4. .gitignore
  5. .gitmodules
  6. .gitreview
  7. AUTHORS
  8. COPYING
  9. Documentation/
  10. LICENSES/
  11. MAINTAINERS
  12. Makefile
  13. Makefile.inc
  14. PRESUBMIT.cfg
  15. README.md
  16. configs/
  17. gnat.adc
  18. payloads/
  19. src/
  20. tests/
  21. toolchain.inc
  22. util/
README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of “unusual” things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that‘s worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you’re feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.