commit | 44521a6e234e9062d8689f2d75c27ba997c9bbde | [log] [tgz] |
---|---|---|
author | Alexis Savery <asavery@chromium.org> | Wed Aug 30 20:11:34 2023 |
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | Tue Sep 19 21:28:37 2023 |
tree | 1252727e2b7fbb5eee3701b8563d194bb1d1d298 | |
parent | 97b0ad87ce5362542b160f47787b96ab6199d044 [diff] |
UPSTREAM: google/puff: Enable ASPM of RTL8111H With kernel 5.15, puff hangs during power idle tests because the NIC does not enter ASPM L1.2. We add "enable_aspm_l1_2" in devicetree for RTL8111H to enable ASPM L1.2. BUG=b:268859220, b:279618219 TEST=emerge and run power.Idle Cq-Depend: chromium:4864243 (cherry picked from commit 8ba64cd608e4e88e8ca34e04132cc0f39a1af5a2) Original-Change-Id: I129dfd79e8112191453be513b2e3a260429b3030 Original-Signed-off-by: Alexis Savery <asavery@chromium.org> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/77570 Original-Reviewed-by: Sam McNally <sammc@google.com> Original-Reviewed-by: Martin L Roth <gaumless@gmail.com> Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> GitOrigin-RevId: 8ba64cd608e4e88e8ca34e04132cc0f39a1af5a2 Change-Id: Ib35442ab4710c240093b76cfe712fe8c0fa56655 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/4851427 Reviewed-by: Jonathon Murphy <jpmurphy@google.com> Tested-by: ChromeOS Prod (Robot) <chromeos-ci-prod@chromeos-bot.iam.gserviceaccount.com> Commit-Queue: Jonathon Murphy <jpmurphy@google.com> (cherry picked from commit e89b44dcefd06314a395bfd1507839ae1084b9c0) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/4864239 Tested-by: Alexis Savery <asavery@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Commit-Queue: Alexis Savery <asavery@chromium.org>
coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.
With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.
coreboot was formerly known as LinuxBIOS.
After the basic initialization of the hardware has been performed, any desired “payload” can be started by coreboot.
See https://www.coreboot.org/Payloads for a list of supported payloads.
coreboot supports a wide range of chipsets, devices, and mainboards.
For details please consult:
ANY_TOOLCHAIN
Kconfig option if you’re feeling lucky (no support in this case).Optional:
make menuconfig
and make nconfig
)Please consult https://www.coreboot.org/Build_HOWTO for details.
If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.
Please see https://www.coreboot.org/QEMU for details.
Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:
You can contact us directly on the coreboot mailing list:
https://www.coreboot.org/Mailinglist
The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.
coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the “GPL (version 2, or any later version)”, and some files are licensed under the “GPL, version 2”. For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.
This makes the resulting coreboot images licensed under the GPL, version 2.