tegra124: fix and fine tune the warm boot code
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same
as PLLP. But that is incorrect, BootROM had switched it to pllp_out2
with the rate 204MHz. So actually the warm boot procedure was running at
the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz.
And the CPU complex power on sequences were different with what we used
in kernel and Coreboot. Fix up the sequence as below.
* enable CPU clk
* power on CPU complex
* remove I/O clamps
* remove CPU reset
Update the time of the CPU complex power on function for record.
* power_on_partition(PARTID_CRAIL): 528 uSec
* power_on_partition(PARTID_CONC): 0 uSec
* power_on_partition(PARTID_CE0): 4 uSec
Finally, removing the redundant routine of a flow controller event with
(20 | MSEC_EVENT | MODE_STOP).
BUG=chrome-os-partner:29394
BRANCH=none
TEST=manually test LP0 with lid switch quickly and make sure the last
write to restore register successfully
Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: https://chromium-review.googlesource.com/205901
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1)
Reviewed-on: https://chromium-review.googlesource.com/207196
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
1 file changed
